WO2019149015A1 - 电源变换电路的控制方法以及相关电源变换电路 - Google Patents

电源变换电路的控制方法以及相关电源变换电路 Download PDF

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Publication number
WO2019149015A1
WO2019149015A1 PCT/CN2018/125802 CN2018125802W WO2019149015A1 WO 2019149015 A1 WO2019149015 A1 WO 2019149015A1 CN 2018125802 W CN2018125802 W CN 2018125802W WO 2019149015 A1 WO2019149015 A1 WO 2019149015A1
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Prior art keywords
turned
circuit
power conversion
switch
transistor
Prior art date
Application number
PCT/CN2018/125802
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English (en)
French (fr)
Inventor
张彦忠
刘春阳
马征
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18903671.8A priority Critical patent/EP3734824B1/en
Publication of WO2019149015A1 publication Critical patent/WO2019149015A1/zh
Priority to US16/945,091 priority patent/US11201549B2/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/01—Resonant DC/DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33573—Full-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/4815—Resonant converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present application relates to the field of power supply technologies, and in particular, to a control method of a power conversion circuit and an associated power conversion circuit.
  • the power conversion circuit is widely used for converting power from one voltage level to another.
  • the DC-DC conversion circuit passes the source input voltage through a working process such as transformation, rectification, filtering, etc., and finally outputs The required voltage is to the load.
  • the power conversion circuit usually includes a switching circuit, a transformer, a rectification, and a filter circuit.
  • a high-frequency control operation of the switching circuit in the power conversion circuit is usually required, so the energy loss of the power conversion circuit Mainly from switching losses, conduction losses and current switching losses in switching circuits.
  • the current technology cannot achieve a combination between switching loss, conduction loss and current switching loss of the switching circuit, and the technical integration still faces severe challenges.
  • Embodiments of the present invention provide a control method of a power conversion circuit and an associated power conversion circuit to reduce switching loss, conduction loss, and current switching loss in the power conversion circuit.
  • an embodiment of the present invention provides a control method of a power conversion circuit, where the power conversion circuit includes a three-level switch circuit, a resonance circuit, a transformer, a rectifier circuit, and a filter circuit; the three-level switch The three input ends of the circuit are respectively connected to a DC voltage P, a reference voltage UREF, a DC voltage N, and an output terminal SM of the three-level switching circuit is connected to an input end of the resonant circuit, and an output end of the resonant circuit is a primary side winding of the transformer is connected, a secondary winding of the transformer is connected to an input end of the rectifier circuit, and an output end of the rectifier circuit is connected to an input end of the filter circuit;
  • the three-level switch circuit includes a switch unit UC1 and a switch unit UC4; one end of the UC1 is connected to the P, the other end is connected to the UREF, and the output end of the UC1 is X1, in the UC1
  • the first switch tube Q1 connected between the P and the X1 is included; one end of the UC4 is connected to the N, the other end is connected to the UREF, and the output end of the UC4 is X4.
  • the UC4 includes a first switching transistor Q4 connected between the DC voltage N and the X4; the three-level switching circuit further includes a second switching transistor connected between the X1 and the SM Q2, a second switching transistor Q3 connected between the X4 and the SM; and a third switching transistor S1 connected between the P and the SM, connected to the N and the SM a third switch tube S2; wherein the Q1, Q2, Q3, Q4, S1, S2 each comprise a transistor, and each of the transistors is connected in parallel with a body diode, the body diode is oriented in a transistor connected in parallel Turns on when reverse biased.
  • each switch tube Q1, Q2, Q3, Q4, S1, S2 is controlled by the control unit in order, by controlling the opening and closing of different switch tubes, so that different sizes and directions of AC voltage VS and current are output. IS.
  • the three-level switch circuit is included in the positive half cycle portion of the pulse width modulation signal and the negative half cycle portion of the pulse width modulation signal, and the following focuses on the three-level switch.
  • the control method provided by the embodiment of the present invention is described by the switching circuit operating at a positive half-cycle angle of the pulse width modulated signal.
  • the method includes the steps of: controlling all of the transistors to be turned off, the body diode of the S1, the body diode of the Q1, the The body diodes of Q2 are all turned on based on the current freewheeling action of the resonant circuit; controlling the S1 to be turned on to establish a first working state of the power conversion circuit; after the first working state lasts for T1, control The Q1 and the Q2 are turned on.
  • S1 and S2 have the property of low conduction loss
  • Q1, Q2, Q3 and Q4 have the property of low turn-off loss
  • the power conversion circuit provided by the embodiment of the present invention includes a three-level switching circuit and a resonant circuit.
  • the related transistor such as S1
  • the body diodes of Q1, Q2 are turned on based on the current freewheeling action of the resonant circuit, and the voltage across the diode is a diode voltage drop (close to 0), and then when S1 is turned on, the S1 turn-on process has zero voltage.
  • the characteristics of the switch Zero Voltage Switch, ZVS
  • Q1 and Q2 also have ZVS characteristics when Q1 and Q2 are turned on, thus reducing the switching loss of the relevant switch tube during the turn-on process.
  • control S1 is turned on before the Q1 and the Q2, when the Q1 and Q2 are turned on, the impedance of a small portion of the current is switched from the branch where S1 is located to the branch where Q1 and Q2 are located, and the impedance of the branch where Q1 and Q2 are located. It is larger than the impedance of the branch where S1 is located, so it is only necessary to switch the current of a very small part. This can avoid the rapid change of current in a short time and bring about additional electromagnetic interference (EMI) and reduce the current switching loss.
  • EMI electromagnetic interference
  • the embodiment of the present invention can simultaneously achieve the effects of reducing switching loss, conduction loss, and current switching loss in the power conversion circuit.
  • the method further includes a turn-off process of the switch.
  • the first possible turn-off process is: controlling the S1 to be turned off before the Q1 is turned off, controlling the Q1 to be turned off before the Q2 is turned off, thereby switching the first operating state to the second Working status.
  • the second possible turn-off process is: controlling the S1 to be turned off before the Q1 is turned off, and controlling the Q2 to be turned off before the Q1 is turned off, thereby switching the first working state to the second Working status.
  • the S1 has a lower conduction loss than the Q1 and Q2, and the S2 has a lower conduction loss than the Q3 and Q4; the Q1 and Q2 have a ratio S1 has a lower turn-off loss, and Q3 and Q4 have a lower turn-off loss than the S2. Therefore, during the turn-off of the switching transistor, control S1 is turned off before Q1 and Q2, and finally Q1 and Q2 are turned off. Since Q1 and Q2 have low turn-off loss, the switch during the turn-off process is realized. loss.
  • the three-level switch circuit has a circuit structure of various implementation forms.
  • the UC1 further includes a connection to the UREF. And a diode DH between the X1, the DH is used to establish the second working state when both S1 and Q1 are turned off; the UC4 further includes a connection between the UREF and the X4 Diode DB between.
  • the turn-off process of this circuit structure can be designed with reference to the first possible turn-off process.
  • the three level switch circuit has a plurality of variant configurations.
  • the transistor K1 and the transistor K2 are added to the three-level switching circuit of the first aspect, and the K1 is connected in parallel with a body diode KD1, and the KD1 direction is set to be turned on when K1 is reverse biased.
  • the K2 has a body diode KD2 connected in parallel, and the KD2 direction is set to be turned on when K1 is reverse biased.
  • the collector of K1 is connected to the connection point between DH and DB
  • the emitter of K1 is connected to the emitter of K2
  • the collector of K2 is connected to the connection point between Q2 and Q3, and then connected to SM.
  • the K1, K2 are used to establish the second working state when both S1 and Q1 are turned off.
  • the turn-off process of this circuit structure can be designed with reference to the first possible turn-off process.
  • DH and DB are replaced by a transistor Q5 and a transistor Q6, wherein the Q5 has a body diode in parallel
  • the D5, D5 direction is set to conduct when Q5 is reverse biased; the Q6 has a body diode D6 in parallel, and the D6 direction is set to be turned on when Q6 is reverse biased.
  • the collector of Q5 is connected to the output terminal X1 of UC1, the emitter of Q5 is connected to UREF, the emitter of Q6 is connected to the output terminal X4 of UC4, and the collector of Q6 is connected to UREF.
  • the Q6 is configured to establish the second working state when both S1 and Q2 are turned off.
  • the turn-off process of this circuit structure can be designed with reference to the second possible turn-off process.
  • the UC1, UC4 comprise a capacitor C connected between the X1 and the X4, DH and DB are replaced by a capacitor C.
  • One end of the capacitor C is connected to the output terminal X1 of the UC1, and one end of the capacitor C is connected to the output terminal X4 of the UC4.
  • the capacitor C is used to turn off both the S1 and the Q2.
  • the second working state is established.
  • the turn-off process of this circuit structure can be designed with reference to the second possible turn-off process.
  • the method when the three-level switching circuit operates in a negative half cycle of the pulse width modulation signal, the method further includes The following steps: controlling all of the transistors to be turned off, the body diode is turned on based on a current freewheeling action of the resonant circuit; controlling the S2 to be turned on to establish a third operating state of the power conversion circuit; After the third working state lasts for T2, the Q3 and the Q4 are controlled to be turned on.
  • the method further includes a turn-off process of the switch, and controlling the S2 before the Q4 is turned off. Turning off, the Q4 is controlled to be turned off before the Q3 is turned off, thereby switching the third operating state to the fourth operating state.
  • an embodiment of the present invention provides a power conversion circuit including a three-level switch circuit, a resonance circuit, a transformer, a rectifier circuit, and a filter circuit; three inputs of the three-level switch circuit The terminals are respectively connected to a DC voltage P, a reference voltage UREF, a DC voltage N, and an output terminal SM of the three-level switching circuit is connected to an input end of the resonant circuit, an output end of the resonant circuit and an original of the transformer a side winding connection, a secondary winding of the transformer is connected to an input end of the rectifier circuit, and an output end of the rectifier circuit is connected to an input end of the filter circuit;
  • the three-level switch circuit includes a switch unit UC1 and a switch unit UC4; one end of the UC1 is connected to the P, the other end is connected to the UREF, and the output end of the UC1 is X1, and is included in the UC1.
  • a first switch tube Q1 connected between the P and the X1; one end of the UC4 is connected to the N, the other end is connected to the UREF, and the output end of the UC4 is X4, in the UC4
  • the first switch tube Q4 connected between the DC voltage N and the X4 is included;
  • the three-level switching circuit further includes a second switching transistor Q2 connected between the X1 and the SM, a second switching transistor Q3 connected between the X4 and the SM, and a third switch S1 between the P and the SM, connected to a third switch S2 between the N and the SM; wherein the Q1, Q2, Q3, Q4, S1, S2 are A transistor is included, and each of the transistors is connected in parallel with a body diode, the body diode being oriented to be turned on when the transistor is reverse biased; and the power conversion circuit is configured to implement any of claims 1-10 The method described in the item.
  • the UC1 further includes a diode DH connected between the UREF and the X1, the DH is used to establish when both S1 and Q1 are turned off The second operating state;
  • the UC4 further includes a diode DB connected between the UREF and the X4.
  • the three-level switching circuit includes, in addition to the DH and the DB, a transistor K1 and a transistor K2 connected between the UREF and the SM, the K1, K2 is respectively connected to the body diodes KD1, KD2, the direction of which is set to be turned on when the K1 is reverse biased, and the direction of the KD2 is set to be turned on when the K2 is reverse biased.
  • the UC1 further includes a transistor Q5 connected between the UREF and the X1, the Q5 is connected to the body diode D5, and the direction of the D5 is set to Said Q5 is turned on when reverse biased; said UC4 further comprising a transistor Q6 connected between said UREF and said X4, said Q6 parallel body diode D6, said D6 being oriented in said Q6 Turns on when reverse biased.
  • the UC1, UC4 comprise a capacitance C connected between the X1 and the X4.
  • an embodiment of the present invention provides a chopper.
  • the chopper includes a three-level switching circuit and a resonant circuit, and the three-level switching circuit is specifically the three-level switching circuit described in the second aspect, and the resonant circuit is specifically described in the second aspect. Resonant circuit.
  • an embodiment of the present invention further provides a non-volatile storage medium for storing the method described in the first aspect.
  • the body diodes of the relevant transistors are based on the resonant circuit.
  • the current is continuously turned on, and the voltage across the diode is the diode voltage drop (close to 0).
  • the S1 is turned on again, the S1 is turned on, and the ZVS is characterized.
  • Q1 and Q2 are turned on, Q1 and Q2 are also the same.
  • ZVS features to reduce switching losses during turn-on.
  • S1 uses a transistor with low conduction loss
  • Q1 and Q2 use a transistor with low turn-off loss.
  • control S1 In the on state, most of the current passes through S1, so the circuit can be greatly reduced. Conduction loss. Since the control S1 is turned on before the Q1 and the Q2, when the current is switched from the path 1 to the path 2 when the current is switched from the path 1 to the path 2, only a very small portion of the circuit needs to be switched, so that short time can be avoided. Rapid changes in current bring additional EMI interference and reduce current switching losses. Finally, during the turn-off process, control S1 is turned off before Q1 and Q2, and finally Q1 and Q2 are turned off. Since Q1 and Q2 have low turn-off losses, switching losses during turn-off are reduced.
  • FIG. 1 is a schematic structural diagram of a power conversion circuit according to an embodiment of the present invention.
  • FIG. 2 is a structural diagram of a frame of another power conversion circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a power conversion circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a control unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a control method of a power conversion circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an application scenario of a power conversion circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an application scenario of a power conversion circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an application scenario of a power conversion circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of signal control and electrical changes of some transistors provided by an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of still another power conversion circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of signal control of some transistors according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of still another power conversion circuit according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of signal control of some transistors according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of still another power conversion circuit according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram of signal control of some transistors provided by an embodiment of the present invention.
  • the power conversion circuit according to the embodiment of the present invention includes an input power source 1, a voltage dividing circuit 2, a three-level switching circuit 3, a resonance circuit 4, a transformer 5, a rectifier circuit 6, and a filter circuit 7, which in turn The connection in which the three-level switching circuit 3 and the resonance circuit 4 constitute the chopper of the embodiment of the present invention.
  • the input power source 1 can be, for example, a DC power source, and the input power source 1 is connected to the voltage dividing circuit 2; the voltage dividing circuit 2 is used for dividing the input power source, and the voltage dividing circuit 2 can be composed of a plurality of voltage dividing capacitors in series, for example, The two voltage dividing capacitors C1 and C2 are connected in series; the chopper includes a three-level switching circuit 3 and a resonant circuit 4 for converting the input direct current into a sinusoidal alternating current, and providing an alternating current voltage VS and current on the output phase line. IS.
  • the three-level switch circuit is composed of a set of power switch tubes, diodes and/or capacitors, and the input of the three-level switch circuit 3 is connected to the voltage dividing circuit, specifically, the input of the three-level switch circuit 3
  • the terminals are respectively connected with three voltages provided by the voltage dividing circuit 2: a direct current voltage P, a reference voltage UREF, a direct current voltage N, and an output of the three-level switching circuit 3 is connected to an input of the resonant circuit 4;
  • the resonant circuit 4 includes an inductor, The capacitor, the inductor and the capacitor are connected in series to form a resonant cavity (for example, the resonant circuit 4 is an LLC resonant circuit), one end of the resonant cavity is connected to the midpoint of the three-level switching circuit 3, and the other end is connected to the voltage dividing circuit via the primary winding of the transformer.
  • the rectifier circuit 6 is connected by a rectifier bridge The side bridge arm is configured to rectify the input current; the output of the rectifier circuit 6 is connected to the input of the filter circuit 7, and the filter circuit 7 includes a capacitor for filtering the input current.
  • the related circuit and the connection relationship in the power conversion circuit shown in FIG. 1 are only an example of the embodiment of the present invention, and are not limited thereto.
  • the power conversion circuit can have various implementation manners. For example, referring to FIG. 1
  • the related circuit proposed by the embodiment of the present invention constitutes a three-phase power conversion circuit;
  • the phase power conversion circuit also includes an input power source 1, a voltage dividing circuit 2, a three-level switching circuit 3, a resonance circuit 4, a transformer 5, a rectifier circuit 6, and a filter circuit 7, but different circuit layouts and circuit connections in individual circuits
  • the three-level switching circuit includes three-level switching circuits 31, 32 and 33 connected in parallel, and the three-level switching circuits 31, 32 and 33 of the resonant circuits 41, 42, 43 are connected in parallel in the resonant circuit.
  • the points are respectively connected to the resonant circuits 41, 42, 43 to provide a three-phase input for the primary winding of the transformer, and the secondary winding of the transformer is output to the rectifier circuits 61, 62, 63 through the three phases, after rectification, and then unified output to Filtering is performed in the filter circuit.
  • the three level switch circuit includes two switch units UC1, UC4 controlled by a control unit (shown in FIG. 4).
  • UC1 includes a first switch transistor QI, Q1 is a transistor, a collector of Q1 is connected to P, an emitter is connected to an output terminal X1, and Q1 is connected in parallel with a body diode D1.
  • UC1 When the direction of D1 is set to be reverse biased when Q1 is reversed Conduction; optionally, UC1 also includes diode DH, the anode of DH is connected to UREF, and the cathode of DH is connected to output X1.
  • UC4 includes a first switching transistor Q4, Q4 is a transistor, an emitter of Q4 is connected to N, a collector is connected to an output terminal X1, and a Q4 is connected in parallel with a body diode D4, and a direction of D4 is set to be turned on when Q4 is reverse biased;
  • the UC4 further includes a diode DB, the cathode of the DB is connected to the UREF, and the anode of the DB is connected to the output terminal X4.
  • the second switch tube Q2 and the second switch Q3 tube controlled by the control unit are further included, the Q2 and the Q3 are both transistors; the collector of the Q2 is connected to the X1, the emitter Connect the output terminal SM of the three-level switch circuit, Q2 is connected with the body diode D2 in parallel, the direction of D2 is set to be turned on when Q2 is reverse biased; the emitter of Q3 is connected to X4, and the collector is connected to the three-level switch circuit.
  • the output terminals SM and Q3 are connected in parallel with the body diode D3, and the direction of D3 is set to be turned on when Q3 is reverse biased.
  • a third switching transistor S1 and a third switching transistor S2 controlled by the control unit are further included, and both of the S1 and S2 are transistors.
  • the collector of S1 is connected to P, the emitter is connected to SM, the emitter of S2 is connected to P, and the collector is connected to SM.
  • One end of the resonant circuit is connected to the SM, and the other end is connected to the UREF through the primary winding of the transformer to provide current freewheeling for the three-level switching circuit.
  • the voltage on the output terminal SM of the modulation signal is substantially equal to the DC voltage of the voltage input terminal P of the UC1 (+U/ 2), this corresponds to the first operating state of the three-level switching circuit; when the S1 and QI are turned off, and the Q2 remains on, the voltage at the output terminal SM is substantially equal to the reference voltage UREF ( 0), this corresponds to the second operating state of the three-level switching circuit; when the S2 is turned on, and the switching unit UC4, the transistor Q4, the Q3 is turned on, the voltage on the output terminal SM is substantially equal to a DC voltage (-U/2) of the voltage input terminal N of the UC4, which corresponds to a third operating state of the three-level switching circuit; when the S2 and Q4 are turned off, and the Q3 remains turned on, The voltage at the output SM is substantially equal to the reference voltage UREF(0), which corresponds to the
  • the S1 has lower conduction loss performance than Q1 and Q2, and S2 has lower conduction loss performance than Q3 and Q4, and Q1 and Q2 have lower shutdown loss performance than S1, Q3.
  • Q4 has a lower turn-off loss performance than S2.
  • each switch tube Q1, Q2, Q3, Q4, S1, S2 is controlled by the control unit in an orderly manner.
  • the chopper outputs alternating voltages of different sizes and directions. VS and current IS.
  • the control unit involved in the embodiment of the present invention is described below. Referring to FIG. 4, FIG. 4 is a schematic diagram of control of a different switching tube by a control unit according to an embodiment of the present invention.
  • the control unit realizes the orderly control of the switching transistors Q1, Q2, Q3, Q4, S1, S2 by outputting the pulse width modulation signals G1, G2.
  • the three-level switching circuit outputs a pulse width modulation signal G1 when operating in the positive half cycle of the pulse width modulation signal, and outputs the pulse width modulation signal G2 when the three level switching circuit operates in the negative half cycle of the pulse width modulation signal.
  • the pulse width modulation signal is generally a high frequency signal, and the pulse width modulation signal is processed into a control signal that can directly control the switching tube after being processed inside the control unit, and finally applied to control signals of different transistors (control signal 1 in the figure) 6) is a discrete logic signal that coincides with the pulse width modulated signals G1, G2, i.e., has a signal that can be equal to zero or one amplitude.
  • a delay module (delay module 1-4 in the figure) is also provided, and the relevant delay module is in the trailing edge of the pulse width modulation signals G1 and G2. It is activated and enables the output of the delay module to output the pulse width modulated signal after a predetermined time T delay.
  • the delay module when the control signal 0 of the pulse width modulation signal G1 is switched to 1, S1 will be turned on, but Q1 will be turned on after the preset time length T11, and Q2 will be turned on after the preset time length T21.
  • the method includes a three-level switching circuit operating in a positive half cycle portion of the pulse width modulation signal and a negative half cycle portion operating in the pulse width modulation signal, and the following describes control of the three-level switching circuit operating in a positive half cycle of the pulse width modulation signal Method, it is apparent that those skilled in the art can easily obtain relevant information about when the three-level switching circuit operates in the negative half cycle of the pulse width modulation signal according to the description, and therefore will not be described below.
  • the current freewheeling circuit will include the "resonant circuit-DS1-P" branch and the "resonant circuit-D2-D1- P" branch road.
  • the diodes DS1, D2, D1 will be turned on, at this time the voltage across S1 (or Q1 + Q2) is very low (only diode drop), which provides for the next time S1, or the opening of Q1, Q2 Zero Voltage Switch (ZVS) condition.
  • ZVS Zero Voltage Switch
  • S1 Since the body diode of S1 is already in the on state before the turn-on, S1 is turned on at the voltage of 0 (or close to 0), so that S1 has the ZVS characteristic, and the turn-on loss of S1 during the turn-on process is small. Referring to FIG. 7, after the turn-on, the current continues to pass through S1, and flows through the output terminal SM to the resonant circuit. Since S1 itself has a low on-voltage drop property, the conduction loss generated by S1 on the S1 is very low.
  • the three-level switch circuit establishes a first working state. At this time, S1 transmits power from the P end to the SM end, that is, the SM end can output a DC voltage to the subsequent circuit (+ U/2).
  • control switch tubes Q1 and Q2 are delayed to be turned on.
  • the opening times of Q1 and Q2 may be the same or different.
  • the delay turn-on time of Q1 and Q2 can be adjusted according to the optimal operating states of Q1, Q2, and S1, so that the conduction loss of the three-level switch circuit can be minimized.
  • the three-level switch circuit continues to be in the first working state.
  • S1, Q1, and Q2 are common (most of the S1 transmission) transmits power from the P end to the SM. End, that is, the SM terminal can output a DC voltage (+U/2) to subsequent circuits.
  • control switch S1 in this step, the control switch S1 is turned off before Q1 and Q2 are turned off.
  • the current loop includes "UREP-DH-Q2-SM", that is, the UEP level is output from the SM.
  • control switch Q2 is turned off. After Q2 is turned off, all the switches are again in the off state, waiting for the next cycle to be turned on.
  • step S105 is started before step S106; in still another possible embodiment, step S106 can also be started before step S105, that is, according to the switch unit UC1.
  • the actual circuit structure (such as the circuit structure shown in Figure 3) controls Q1 to turn off before Q2 turns off.
  • the control Q2 is turned off before the Q1 is turned off, and the embodiment of the present invention is not limited herein.
  • Figure 9 shows the timing control and electrical changes of the associated switching transistors (S1, Q1, Q2) when the three-level switching circuit operates in the positive half cycle of the pulse width modulated signal.
  • S1, Q1, Q2 the relevant switching tube
  • FIG. 9 shows the relevant signal control timing of the control unit, and the control unit periodically inputs the pulse width modulation signals GS1, GQ1, and GQ2 to S1, Q1, and Q2, respectively, when the pulse width modulation signal is converted.
  • the control signal amplitude is 1, the corresponding switch tube is turned on.
  • the amplitude of the control signal converted by the pulse width modulation signal is 0, the corresponding switch tube is turned off.
  • Figure 9 also shows the variation of the current flowing through the control of the input switch (S1, Q1, Q2) under the control of the input signal, and shows the endpoints on both sides of Q1 and Q2 under the control of the input signal (or S1 The side end) changes in voltage, that is, the voltage change between the P connection point and the SM connection point.
  • the pulse width modulation signal GS1 of S1 becomes 0, that is, the converted control signal becomes 0, so S1 is turned off, and the pulse width modulation signal of Q2 is delayed to t2 due to the delay mode, Q3 The pulse width modulated signal is delayed to t3 due to the delay mode.
  • the power between P and SM is transmitted through Q1 and Q2, so the currents IQ1 and IQ2 are correspondingly increased.
  • the voltage across Q1 and Q2 (the voltage across S1) is also small, close to zero.
  • the three-level switch circuit is in the first working state, and the SM terminal outputs the voltage U/2.
  • the pulse width modulation signal GS1 of Q1 becomes 0, that is, the converted control signal becomes 0, so Q1 is turned off, and the three-level switching circuit starts to switch the "UREP-DH-Q2-SM" loop, three electric
  • the first switching state of the flat switching circuit is switched to the second operating state, IQ2 begins to decrease, and the voltages on both sides of Q1 and Q2 (the voltage across S1) begin to increase. Since Q1 and Q2 have low turn-off loss properties, the turn-off loss of Q1 is small during this process.
  • the three-level switching circuit can perform the correlation control operation of the negative period of the pulse width modulation signal from the time t3-t4, and the description will not be repeated here.
  • the switching transistors Q1, Q2, Q3, Q4, S1, and S2 are controlled to be in an off state, and an electromotive force is generated in the inductive load in the resonant circuit, which serves as a power source.
  • the branch with the three-level switching circuit constitutes a circuit that continuously supplies current, thereby generating a current freewheeling circuit.
  • the voltages on both sides of Q1 and Q2 (the voltages on both sides of S1) begin to decrease or even reverse. Since Q1, Q2, and S1 are each connected in parallel with a reverse body diode, the current freewheeling circuit will include the "resonant circuit-DS1-P".
  • the control signal converted by the pulse width modulation signal GS1 of S1 becomes 1, so S1 is turned on, and the current IS1 flowing through S1 increases from 0.
  • the opening process of S1 has the characteristics of ZVS, and the opening loss of S1 is small.
  • the current rapidly increases through S1.
  • S1 itself has the property of low on-voltage drop, the conduction loss generated by S1 after S1 is low is very low.
  • the three-level switch circuit establishes a first working state, and S1 transmits power from the P terminal to the SM terminal, and the SM terminal can output a DC voltage to the subsequent circuit (+U/2).
  • the voltage across S1, Q1, and Q2 is small. (close to 0).
  • the control signal converted by the pulse width modulation signal GQ1 of Q1 becomes 1, so that Q1 is turned on, and the control signal converted by the pulse width modulation signal GQ2 of Q2 becomes 1, so that Q2 is turned on.
  • the voltage across Q1 and Q2 is very small (close to 0), so the turn-on process of Q1 and Q2 also has the characteristics of ZVS. Since the conduction voltage drop of Q1 and Q2 is large, only a small part of the current flows through Q1 and Q2, and IQ1 and IQ2 are small. Most of the circuits are still flowing from S1, and IS1 is large. Since S1 has a low conduction loss property, The conduction loss of the three-level switching circuit is small. At this time, the three-level switch circuit is in the first working state, and the SM terminal outputs the voltage U/2.
  • the durations of different time periods such as t1-t2, t2-t3, t3-t4, t4-t5, and t5-t6, are greater than or equal to zero, and the duration of different time periods may be based on actual conditions. The specific application situation is set.
  • the power conversion circuit provided by the embodiment of the present invention includes a chopper, which further includes a three-level switching circuit and a resonant circuit.
  • the body diodes of the associated transistors such as S1, Q1, Q2
  • the SVS has a ZVS characteristic.
  • Q1 and Q2 are turned on, Q1 and Q2 also have ZVS characteristics, thereby reducing the switching loss during the turn-on process.
  • S1 uses a transistor with low conduction loss
  • Q1 and Q2 use a transistor with low turn-off loss.
  • the circuit can be greatly reduced. Conduction loss. Since the control S1 is turned on before the Q1 and the Q2, when the current is switched from the path 1 to the path 2 when the current is switched from the path 1 to the path 2, only a very small portion of the circuit needs to be switched, so that short time can be avoided. Rapid changes in current bring additional electromagnetic interference (EMI) and reduce current switching losses.
  • EMI electromagnetic interference
  • control S1 is turned off before Q1 and Q2, and finally Q1 and Q2 are turned off. Since Q1 and Q2 have low turn-off losses, switching losses during turn-off are reduced.
  • FIG. 10 shows a possible power conversion circuit structure.
  • the power conversion circuit structure is different from the circuit structure shown in FIG. 3 in that a transistor K1 and a transistor K2 are added to the three-level switching circuit.
  • the K1 has a body diode KD1 connected in parallel, and the KD1 direction is set to be turned on when K1 is reverse biased; the K2 is connected in parallel with a body diode KD2, and the KD2 direction is set to be turned on when K1 is reverse biased.
  • the collector of K1 is connected to the connection point between DH and DB
  • the emitter of K1 is connected to the emitter of K2
  • the collector of K2 is connected to the connection point between Q2 and Q3, and then connected to SM.
  • the control unit controls the different transistors, for example, referring to FIG. 11, which shows the pulse width modulation signals (GS1, GQ1, GQ2) that the control unit inputs to S1, Q1, Q2, and GK1, respectively.
  • FIG. 11 shows the pulse width modulation signals (GS1, GQ1, GQ2) that the control unit inputs to S1, Q1, Q2, and GK1, respectively.
  • GK1 pulse width modulation signals
  • control K1 is turned on, thereby switching the first operating state of the three-level switching circuit to the second operating state.
  • K1 is also turned off.
  • FIG. 12 shows a possible power conversion circuit structure.
  • the power conversion circuit structure is different from the circuit structure shown in FIG. 3 in that a transistor Q5 and a transistor Q6 are used in the three-level switching circuit.
  • Replace DH and DB wherein Q5 has a body diode D5 in parallel, D5 direction is set to be turned on when Q5 is reverse biased; Q6 is connected in parallel with a body diode D6, D6 direction is set to be reversed in Q6 Conducted when biased.
  • the collector of Q5 is connected to the output terminal X1 of UC1, the emitter of Q5 is connected to UREF, the emitter of Q6 is connected to the output terminal X4 of UC4, and the collector of Q6 is connected to UREF.
  • control unit controls the different transistors, for example, referring to FIG. 13, which shows the pulse width modulation signals (GS1, GQ1, GQ2) that the control unit inputs to S1, Q1, Q2, and Q6, respectively. GQ6), it can be seen that in the control mode, in the turn-on phase of S1, Q1, and Q2, control S1 is turned on before Q1 and Q2 are turned on, so that the three-level switch circuit establishes the first working state; During the turn-off phase of Q1 and Q2, control S1 is turned off before Q2, and then Q2 is controlled to be turned off before Q1.
  • FIG. 13 shows the pulse width modulation signals (GS1, GQ1, GQ2) that the control unit inputs to S1, Q1, Q2, and Q6, respectively. GQ6)
  • control Q6 is turned on, so that after Q2 is turned off, the first operating state of the three-level switching circuit is switched to the second operating state.
  • Q6 is also turned off.
  • FIG. 14 shows a possible power conversion circuit structure diagram.
  • the difference between the power conversion circuit structure and the circuit structure shown in FIG. 3 includes replacing the DH with a capacitor C in the three-level switch circuit.
  • DB one end of the capacitor C is connected to the output terminal X1 of the UC1, and one end of the capacitor C is connected to the output terminal X4 of the UC4.
  • FIG. 15 shows the pulse width modulation signals (GS1, GQ1, GQ2) input by the control unit to S1, Q1, and Q2, respectively.
  • GS1, GQ1, GQ2 pulse width modulation signals

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Abstract

一种电源变换电路的控制方法以及相关电源变换电路，相关电源变换电路包括三电平开关电路（3）和谐振电路（4），所述方法包括：控制三电平开关电路（3）中所有晶体管关断，晶体管S1的体二极管（DS1）、晶体管Q1的体二极管（D1）、晶体管Q2的体二极管（D2）皆基于所述谐振电路（4）的电流续流作用导通；控制所述S1开通，以建立所述电源变换电路的第一工作状态；在所述第一工作状态持续T1时间后，控制所述Q1和所述Q2开通。本方案有利于降低电源变换电路中的开关损耗、导通损耗和电流切换损耗。

Description

电源变换电路的控制方法以及相关电源变换电路 技术领域
本申请涉及电源技术领域，尤其涉及电源变换电路的控制方法以及相关电源变换电路。
背景技术
电源变换电路广泛应用于在一电压等级到另一电压等级电能的转换，比如在DC-DC变换中，DC-DC变换电路将源输入电压通过变压、整流、滤波等工作程序，最终输出所需的电压到负载。电源变换电路通常包括开关电路、变压器、整流以及滤波电路，为了实现有序、稳定的电源变换，通常需要对电源变换电路中的开关电路进行高频的控制操作，所以，电源变换电路的能量损耗主要来自开关电路中的开关损耗、导通损耗和电流切换损耗。然而，现在技术在实现降低开关电路的开关损耗、导通损耗和电流切换损耗之间通常不能兼得，技术整合上依然面临严峻挑战。
发明内容
本发明实施例提供了电源变换电路的控制方法以及相关电源变换电路中，以期降低电源变换电路中的开关损耗、导通损耗和电流切换损耗。
第一方面，本发明实施例提供了一种电源变换电路的控制方法，其中，所述电源变换电路包括三电平开关电路、谐振电路、变压器、整流电路和滤波电路；所述三电平开关电路的三个输入端分别连接到直流电压P、参考电压UREF、直流电压N，所述三电平开关电路的输出端SM与所述谐振电路的输入端相连，所述谐振电路的输出端与所述变压器的原边绕组连接，所述变压器的副边绕组与所述整流电路的输入端相连，所述整流电路的输出端与所述滤波电路的输入端相连；
其中，所述三电平开关电路包括开关单元UC1和开关单元UC4；所述UC1的一端与所述P连接，另一端与所述UREF连接,所述UC1的输出端为X1，在所述UC1中包括连接在所述P和所述X1之间的第一开关管Q1；所述UC4的一端与所述N连接，另一端与所述UREF连接，所述UC4的输出端为X4，在所述UC4中包括连接在所述直流电压N和所述X4之间的第一开关管Q4；所述三电平开关电路还包括,连接在所述X1和所述SM之间的第二开关管Q2，连接在所述X4和所述SM之间的第二开关管Q3；以及，连接在所述P和所述SM之间的第三开关管S1，连接在所述N和所述SM之间的第三开关管S2；其中，所述Q1、Q2、Q3、Q4、S1、S2均包括晶体管，且每个所述晶体管并联体二极管，所述体二极管的方向设置为在其并联的晶体管被反向偏置时导通。
实际工作中，各个开关管Q1、Q2、Q3、Q4、S1、S2受到控制单元的有序控制，通过控制不同开关管的开通与断开，使得输出不同的大小和方向的交流电压VS和电流IS。
在本发明实施例对电源变换电路的控制过程中，包括了三电平开关电路工作于脉宽调制信号的正半周部分和工作于脉宽调制信号负半周部分，下面重点从所述三电平开关电路工作于脉宽调制信号的正半周角度来描述的本发明实施例所提供的控制方法。
当所述三电平开关电路工作于脉宽调制信号的正半周时，所述方法包括以下步骤：控制所有所述晶体管关断，所述S1的体二极管、所述Q1的体二极管、所述Q2的体二极管皆基于所述谐振电路的电流续流作用导通；控制所述S1开通，以建立所述电源变换电路的第 一工作状态；在所述第一工作状态持续T1时间后，控制所述Q1和所述Q2开通。
其中，本发明实施例中，S1、S2具有低导通损耗的性质，Q1、Q2、Q3、Q4具有低关断损耗的性质。
可以看到，本发明实施例提供的电源变换电路包括了三电平开关电路和谐振电路，在对三电平开关电路进行控制的过程中，当所有晶体管都关断时，相关晶体管(如S1、Q1、Q2)的体二极管基于所述谐振电路的电流续流作用导通，其两端的电压为二极管压降(接近于0)，之后再开通S1开通时，S1的开通过程便具备零电压开关(Zero Voltage Switch，ZVS)特性，之后在开通Q1、Q2时，Q1、Q2也同样具备ZVS特性，从而实现了降低相关开关管在开通过程中的开关损耗。另外，由于控制S1在所述Q1和所述Q2之前开通，所以待Q1和Q2开通时，在小部分电流从S1所在支路切换到Q1和Q2所在支路，Q1和Q2所在支路的阻抗大于S1所在支路的阻抗，故只需切换极小部分的电流，这样能够避免短时间内电流的快速变化带来额外的电磁干扰(Electromagnetic Interference，EMI)，降低电流切换损耗。而且，由于S1、Q1、Q2皆导通之后，大部分电流经由S1流通，而S1具有低导通损耗的性质，所以能够极大降低电路的导通损耗。也就是说，实施本发明实施例能够同时实现降低电源变换电路中的开关损耗、导通损耗和电流切换损耗的效果。
基于第一方面，在第一种可能的实施方式中，所述控制所述Q1和所述Q2开通之后，所述方法还包括开关管的关断过程。
第一种可能的关断过程为：控制所述S1在所述Q1关断之前关断，控制所述Q1在所述Q2关断之前关断，从而使所述第一工作状态切换到第二工作状态。
第二种可能的关断过程为：控制所述S1在所述Q1关断之前关断，控制所述Q2在所述Q1关断之前关断，从而使所述第一工作状态切换到第二工作状态。
在本发明实施例中，所述S1具有比所述Q1和Q2更低的导通损耗，所述S2具有比所述Q3和Q4更低的导通损耗；所述Q1和Q2具有比所述S1更低的关断损耗，所述Q3和Q4具有比所述S2更低的关断损耗。所以，在开关管的关断过程中，控制S1在Q1和Q2之前关断，最后才将Q1和Q2关断，由于Q1和Q2具有低关断损耗，从而实现了降低关断过程中的开关损耗。
基于第一方面，在第二种可能的实施方式中，所述三电平开关电路具有多种实现形式的电路结构，在一种可能的电路结构中，所述UC1还包括连接在所述UREF和所述X1之间的二极管DH，所述DH用于在所述S1和所述Q1都关断时建立所述第二工作状态；所述UC4还包括连接在所述UREF和所述X4之间的二极管DB。这种电路结构的关断过程可参考第一种可能的关断过程进行设计。
基于第一方面的第二种可能的实施方式，在可能的实施方式中，所述三电平开关电路具有多种变形结构。在一种变形结构中，在第一方面所述的三电平开关电路中增加晶体管K1和晶体管K2，所述K1并联有一个体二极管KD1，KD1方向设置为在K1被反向偏置时导通；所述K2并联有一个体二极管KD2，KD2方向设置为在K1被反向偏置时导通。其中，K1的集电极连接DH和DB之间的连接点，K1的发射极连接K2的发射极，K2的集电极连接到Q2和Q3之间的连接点，进而连接到SM。所述K1、K2用于在所述S1和所述Q1都关断时建立所述第二工作状态。这种电路结构的关断过程可参考第一种可能的关断过程进行设计。
基于第一方面的第二种可能的实施方式，在又一种变形结构中，在三电平开关电路中，采用晶体管Q5和晶体管Q6替换掉DH和DB，其中，所述Q5并联有一个体二极管D5，D5方向设置为在Q5被反向偏置时导通；所述Q6并联有一个体二极管D6，D6方向设置为在Q6被反向偏置时导通。Q5的集电极连接UC1的输出端X1，Q5的发射极连接到UREF，Q6的发射极连接UC4的输出端X4，Q6的集电极连接到UREF。所述Q6用于在所述S1和所述Q2都关断时建立所述第二工作状态。这种电路结构的关断过程可参考第二种可能的关断过程进行设计。
基于第一方面的第二种可能的实施方式，在又一种变形结构中，在三电平开关电路中，所述UC1、UC4包括连接在所述X1和所述X4之间的电容C，采用电容C替换掉DH和DB，所述电容C的一端连接UC1的输出端X1，电容C的一端连接UC4的输出端X4，所述电容C用于在所述S1和所述Q2都关断时建立所述第二工作状态。这种电路结构的关断过程可参考第二种可能的关断过程进行设计。
基于第一方面，在第三种可能的实施方式中，参照上述电路结构和控制方法的实施过程，当所述三电平开关电路工作于脉宽调制信号的负半周时，所述方法还包括以下步骤：控制所有所述晶体管关断，所述体二极管基于所述谐振电路的电流续流作用导通；控制所述S2开通，以建立所述电源变换电路的第三工作状态；在所述第三工作状态持续T2时间后，控制所述Q3和所述Q4开通。
基于第一方面的第三种可能的实施方式，在所述控制所述Q3和所述Q4开通之后，所述方法还包括开关管的关断过程，控制所述S2在所述Q4关断之前关断，控制所述Q4在所述Q3关断之前关断，从而使所述第三工作状态切换到第四工作状态。
第二方面，本发明实施例提供了一种电源变换电路，所述电源变换电路包括三电平开关电路、谐振电路、变压器、整流电路和滤波电路；所述三电平开关电路的三个输入端分别连接到直流电压P、参考电压UREF、直流电压N，所述三电平开关电路的输出端SM与所述谐振电路的输入端相连，所述谐振电路的输出端与所述变压器的原边绕组连接，所述变压器的副边绕组与所述整流电路的输入端相连，所述整流电路的输出端与所述滤波电路的输入端相连；
所述三电平开关电路包括开关单元UC1和开关单元UC4；所述UC1的一端与所述P连接，另一端与所述UREF连接,所述UC1的输出端为X1，在所述UC1中包括连接在所述P和所述X1之间的第一开关管Q1；所述UC4的一端与所述N连接，另一端与所述UREF连接，所述UC4的输出端为X4，在所述UC4中包括连接在所述直流电压N和所述X4之间的第一开关管Q4；
所述三电平开关电路还包括,连接在所述X1和所述SM之间的第二开关管Q2，连接在所述X4和所述SM之间的第二开关管Q3；以及，连接在所述P和所述SM之间的第三开关管S1，连接在所述N和所述SM之间的第三开关管S2；其中，所述Q1、Q2、Q3、Q4、S1、S2均包括晶体管，且每个所述晶体管并联体二极管，所述体二极管的方向设置为在所述晶体管被反向偏置时导通；所述电源变换电路用于，实现权利要求1-10任一项所述的方法。
基于第二方面，在可能的实施方式中，所述UC1还包括连接在所述UREF和所述X1之间的二极管DH，所述DH用于在所述S1和所述Q1都关断时建立所述第二工作状态；所述 UC4还包括连接在所述UREF和所述X4之间的二极管DB。
在可能的实施例中，所述三电平开关电路除了包括所述DH和所述DB，还包括还包括连接在所述UREF和所述SM之间的晶体管K1和晶体管K2，所述K1、K2分别并联体二极管KD1、KD2，所述KD1的方向设置为在所述K1被反向偏置时导通，所述KD2的方向设置为在所述K2被反向偏置时导通。
基于第二方面，在可能的实施方式中，在所述UC1还包括连接在所述UREF和所述X1之间的晶体管Q5，所述Q5并联体二极管D5，所述D5的方向设置为在所述Q5被反向偏置时导通；所述UC4还包括连接在所述UREF和所述X4之间的晶体管Q6，所述Q6并联体二极管D6，所述D6的方向设置为在所述Q6被反向偏置时导通。
基于第二方面，在可能的实施方式中，所述UC1、UC4包括连接在所述X1和所述X4之间的电容C。
第三方面，本发明实施例提供了一种斩波器。所述斩波器包括三电平开关电路和谐振电路，所述三电平开关电路具体为第二方面中所描述的三电平开关电路，所述谐振电路具体为第二方面中所描述的谐振电路。
第四方面，本发明实施例还提供一种非易失性存储介质，所述非易失性存储介质用于存储第一方面所描述的方法。
可以看到，本发明实施例对电源变换电路中的晶体管进行控制的过程中，当所有所述晶体管都关断时，相关晶体管(如S1、Q1、Q2)的体二极管基于所述谐振电路的电流续流作用导通，其两端的电压为二极管压降(接近于0)，之后再开通S1开通时，S1的开通过程便具备ZVS特性，之后在开通Q1、Q2时，Q1、Q2也同样具备ZVS特性，从而实现降低开通过程中的开关损耗。另外，本发明实施例中S1采用具有低导通损耗的晶体管，Q1、Q2采用具有低关断损耗的晶体管，在导通状态下，电流绝大部分经由S1通过，所以能够极大程度降低电路的导通损耗。由于控制S1在所述Q1和所述Q2之前开通，所以待Q1和Q2开通时，在电流从路径1切换到路径2的过程中，只需切换极小部分的电路，这样能够避免短时间内电流的快速变化带来额外的EMI干扰，降低电流切换损耗。最后，在关断过程中，控制S1在Q1和Q2之前关断，最后才将Q1和Q2关断，由于Q1和Q2具有低关断损耗，从而实现了降低关断过程中的开关损耗。
附图说明
图1是本发明实施例提供的一种电源变换电路的框架结构图；
图2是本发明实施例提供的又一种电源变换电路的框架结构图；
图3是本发明实施例提供的一种电源变换电路的结构示意图；
图4是本发明实施例提供的一种控制单元的逻辑示意图；
图5是本发明实施例提供的一种电源变换电路的控制方法流程示意图；
图6是本发明实施例提供的一种电源变换电路的应用场景示意图；
图7是本发明实施例提供的一种电源变换电路的应用场景示意图；
图8是本发明实施例提供的一种电源变换电路的应用场景示意图；
图9是本发明实施例提供的一些晶体管的信号控制和电性变化示意图；
图10是本发明实施例提供的又一种电源变换电路的结构示意图；
图11是本发明实施例提供的一些晶体管的信号控制示意图；
图12是本发明实施例提供的又一种电源变换电路的结构示意图；
图13是本发明实施例提供的一些晶体管的信号控制示意图；
图14是本发明实施例提供的又一种电源变换电路的结构示意图；
图15是本发明实施例提供的一些晶体管的信号控制示意图。
具体实施方式
下面结合附图描述本发明的相关实施例。
首先描述本发明实施例提供的一种电源变换电路。如图1所示，本发明实施例提出的电源变换电路包括输入电源1、分压电路2、三电平开关电路3、谐振电路4、变压器5、整流电路6、滤波电路7，这些电路依次连接，其中，三电平开关电路3和谐振电路4组成了本发明实施例的斩波器。具体的，输入电源1例如可以是直流电源，输入电源1连接于分压电路2；分压电路2用于对输入电源进行分压，分压电路2可由多个分压电容串联组成，例如可以是两个分压电容C1和C2串联组成；斩波器包括三电平开关电路3和谐振电路4，用于将输入的直流电转换成正弦的交流电，在输出相线上提供交流电压VS和电流IS。具体的，三电平开关电路由一组功率开关管、二极管及(或)电容组成，所述三电平开关电路3的输入与分压电路相连，具体的，三电平开关电路3的输入端分别连接分压电路2所提供的三种电压：直流电压P、参考电压UREF、直流电压N，三电平开关电路3的输出与谐振电路4的输入相连；所述谐振电路4包含电感、电容，电感与电容串联组成谐振腔(例如所述谐振电路4为LLC谐振电路)，谐振腔的一端连接三电平开关电路3的中点，另一端经变压器原边绕组后连接分压电路中的UREF(分压电容C1和C2的中点)；变压器5的原边绕组与谐振电路4的输出相连，变压器的副边绕组与整流电路6相连,具体的，整流电路6由整流桥(副边桥臂)组成，用于对输入电流进行整流；整流电路6的输出连接滤波电路7的输入，滤波电路7包括电容，用于对输入电流进行滤波。
需要说明的是，图1所示的电源变换电路中对的相关电路以及连接关系仅仅是本发明实施例的一种示例，而非限定。在实际应用中，所述电源变换电路可以有多种实施方式，例如，参见图2，在一种实施方式中，本发明实施例提出的上述相关电路组成了三相电源变换电路；所述三相电源变换电路同样包括输入电源1、分压电路2、三电平开关电路3、谐振电路4、变压器5、整流电路6、滤波电路7，但是个别电路中的具有不同的电路布局以及电路连接，其中三电平开关电路中包括并联的三电平开关电路31、32和33，谐振电路中包括并联的谐振电路41、42、43所述三电平开关电路31、32和33各自的中点分别连接与谐振电路41、42、43连接，为变压器的原边绕组提供三相输入，变压器的副边绕组通过三相输出到整流电路61、62、63，经过整流后，再统一输出到滤波电路中进行滤波。
在由三电平开关电路和谐振电路组成的斩波器中，分压电路所提供的三个电压(N、UREF和P)输入到所述三电平开关电路，其输出端SM对应的不同的工作状态，输出电压分别为-U/2、UREF、U/2。参见图3，在一种具体实现方式中，所述三电平开关电路包括由控制单元(在图4中示出)控制的两个开关单元UC1、UC4。开关单元UC1一端连接到正电压源的正 DC电压输入端P，另一端连接到参考电压UREF，UC1的输出端为X1；开关单元UC4一端连接到负DC电压输入端N，另一端连接到参考电压UREF，UC4的输出端为X4。具体的，UC1包括第一开关管QI，Q1为晶体管，Q1的集电极连接到P，发射极连接到输出端X1，Q1并联有体二极管D1，D1的方向设置为Q1被反向偏置时导通；可选的，UC1还包括二极管DH，DH的阳极连接到UREF，DH的阴极连接到输出端X1。UC4包括第一开关管Q4，Q4为晶体管，Q4的发射极连接到N，集电极连接到输出端X1，Q4并联有体二极管D4，D4的方向设置为Q4被反向偏置时导通；可选的，UC4还包括二极管DB，DB的阴极连接到UREF，DB的阳极连接到输出端X4。
在所示的三电平开关电路中，还包括由控制单元控制的第二开关管Q2和第二开关Q3管，所述Q2、Q3均为晶体管；所述Q2的集电极连接X1，发射极连接三电平开关电路的输出端SM，Q2并联有体二极管D2，D2的方向设置为Q2被反向偏置时导通；所述Q3的发射极连接X4，集电极连接三电平开关电路的输出端SM，Q3并联有体二极管D3，D3的方向设置为Q3被反向偏置时导通。
在所述三电平开关电路中，还包括由控制单元控制的第三开关管S1和第三开关管S2，所述S1和S2均为晶体管。所述S1的集电极连接P，发射极连接SM；所述S2的发射极连接P，集电极连接SM。所述谐振电路的一端连接SM，另一端经过变压器的原边绕组后连接到UREF，为所述三电平开关电路提供电流续流。
在所述S1开通时，以及所述开关单元UC1的晶体管Q1、所述Q2开通时，调制信号的输出端SM上的电压基本上等于所述UC1的电压输入端P的DC电压(+U/2)，这对应于所述三电平开关电路的第一工作状态；在所述S1和QI断开，且所述Q2保持导通时，输出端SM上的电压基本上等于参考电压UREF(0)，这对应于所述三电平开关电路的第二工作状态；在所述S2开通时，以及所述开关单元UC4晶体管Q4、所述Q3开通时，输出端SM上的电压基本上等于所述UC4的电压输入端N的DC电压(-U/2),这对应于三电平开关电路的第三工作状态；在所述S2和Q4断开，且所述Q3保持导通时，输出端SM上的电压基本上等于参考电压UREF(0)，这对应于所述三电平开关电路的第四工作状态。
在具体实现中，所述S1具有比Q1、Q2更低的导通损耗性能，S2具有比Q3、Q4更低的导通损耗性能，Q1、Q2具有比S1更低的关断损耗性能，Q3、Q4具有比S2更低的关断损耗性能，在第一工作状态中，由于Q1、Q2的导通压降比S1大，故大部分导通电流通过S1流过，只有一小部分导通电流通过Q1、Q2流过，S1的导通损耗较小，故该导通期间能够极大降低所述斩波器的导通损耗。同理，在第三工作状态中，由于Q3、Q4的导通压降比S2大，故大部分导通电流通过S2流过，只有一小部分导通电流通过Q3、Q4流过，S2的导通损耗较小，故该导通期间能够极大降低所述斩波器的导通损耗。
实际工作中，各个开关管Q1、Q2、Q3、Q4、S1、S2受到控制单元的有序控制，通过控制不同开关管的开通与断开，使得斩波器输出不同的大小和方向的交流电压VS和电流IS。下面描述本发明实施例所涉及的控制单元。参见图4，图4为本发明实施例所提供的控制单元对不同开关管的控制示意图。控制单元通过输出脉宽调制信号G1、G2实现对开关管Q1、Q2、Q3、Q4、S1、S2的有序控制。所述三电平开关电路工作于脉宽调制信号的正半周时，输出脉宽调制信号G1，所述三电平开关电路工作于脉宽调制信号的负半周时，输出脉 宽调制信号G2。脉宽调制信号一般是高频信号，脉宽调制信号在控制单元内部经过处理后转换为可以直接对开关管进行控制的控制信号，最终施加于不同晶体管的控制信号(图示中控制信号1-6)是与脉宽调制信号G1、G2相一致的离散逻辑信号，即具有能够等于零或1的幅度的信号。脉宽调制信号经过转化成控制信号后，施加在晶体管的控制输入端上的控制信号的幅度等于0时，该晶体管关断，当此幅度等于1时，所述晶体管开通。
另外，在Q1、Q2、Q3、Q4所在的控制支路上，还设置有延时模块(图示中延时模块1-4)，相关延时模块在脉冲宽度调制信号G1、G2的后沿期间激活，并且使得延时模块的输出端能够在预设时间T延迟之后再输出该脉宽调制信号。通过设置延时模块，脉宽调制信号G1转换的控制信号0切换到1时，S1将开通，但是Q1将在预设时间长度T11之后才开通，Q2将在预设时间长度T21之后才开通。脉宽调制信号G1转换的控制信号1切换到0时，S1将关断，但是Q1将在预设时间长度T12之后才关断，Q2将在预设时间长度T22之后才关断。同理，脉宽调制信号G2转换的控制信号0切换到1时，S2将开通，但是Q3将在预设时间长度T31之后才开通，Q4将在预设时间长度T41之后才开通。脉宽调制信号G2转换的控制信号1切换到0时，S2将关断，但是Q3将在预设时间长度T32之后才关断，Q4将在预设时间长度T42之后才关断。需要说明的是，所述T11、T12、T21、T22、T31、T32、T41、T42的时间长度可以相同也可以是各有差异的，这些预设时间长度的取值皆大于或者等于0。
基于上文所述的斩波器、电源变换电路以及控制单元，下面描述本发明实施例所提供的电源转换电路的控制方法(亦即斩波器的控制方法)。该方法包括三电平开关电路工作于脉宽调制信号的正半周部分和工作于脉宽调制信号负半周部分，下面描述所述三电平开关电路工作于脉宽调制信号的正半周时的控制方法，很显然，本领域技术人员很容易的根据所述描述得到有关于当所述三电平开关电路工作于脉宽调制信号的负半周时的相关情况，故下文将不再赘述。另外，为了便于方案描述，可预先定义电流从输出端SM流向谐振电路的方向为正方向。参见图5，该方法包括但不限于以下步骤：
S101，本步骤中，控制所有开关管Q1、Q2、Q3、Q4、S1、S2为关断的状态。
由于通电的感性负载断电时，谐振电路中的强感性负载(如线圈)内产生电动势，其充当电源与三电平开关电路的支路构成持续供给电流的回路，从而产生电流续流回路。举例来说，参见图6，由于Q1、Q2、S1均并联有一个反向的体二极管，那么电流续流回路将包括“谐振电路-DS1-P”支路以及“谐振电路-D2-D1-P”支路。也就是说，二极管DS1、D2、D1将导通，此时S1(或者Q1+Q2)两端的电压很低(仅为二极管压降)，这个为下一时刻S1、或者Q1、Q2的开通提供了零电压开关(Zero Voltage Switch，ZVS)条件。
S102，本步骤中，控制开关管S1开通。
由于开通前S1的体二极管已处于导通状态，故S1在0电压(或者接近于0电压)状态开通，从而使得S1具备ZVS特性，在开通过程中的S1的开通损耗很小。参见图7，开通后，电流继续通过S1，经过输出端SM流向谐振电路，由于S1本身具备低导通压降的属性，故S1导通后电流在S1上产生的导通损耗很低。
所述S1保持导通后，所述三电平开关电路建立第一工作状态，此时，S1将功率从P 端传输到SM端，也就是说，SM端可向后续电路输出DC电压(+U/2)。
S103，在本步骤中，在开关管S1导通一段时间后，控制开关管Q1和Q2延时开通。其中，Q1和Q2的开通时间可以相同，也可以是不同的。
在Q1和Q2均开通后，由于Q1、Q2的导通压降大，故只有一小部分电流通过Q1、Q2流通，大部分电路还是从S1流通。参见图8，大部分电流通过路径1流通，小部分电流通过路径2流通，这两部分电流在输出端SM汇合流向谐振电路。所以在这个过程中，Q1、Q2产生的导通损耗也很小。
需要说明的是，实际应用中，可根据Q1、Q2、S1的最佳工作状态调节Q1和Q2的延时开通时间，从而能够使得三电平开关电路的导通损耗降到最低。
当所述S1、Q1、Q2保持导通后，所述三电平开关电路持续处于第一工作状态，此时，S1、Q1、Q2共同(S1传输大部分)将功率从P端传输到SM端，也就是说，SM端可向后续电路输出DC电压(+U/2)。
S104，在本步骤中，控制开关管S1在Q1和Q2关断之前关断。
由于Q1、Q2延迟关断，所以此时Q1、Q2仍然保持导通状态。故S1截止时，流通S1的电流减小至零，而流通Q1、Q2的电流增大。此时，三电平开关电路仍处于第一工作状态。
S105，在本步骤中，控制开关管Q1关断。
在可能的实施例中，例如在图3所示的实施例中，当Q1关断时，此时Q2仍然处于开通状态，三电平开关电路将从第一工作状态切换至第二工作状态，此时电流回路包括“UREP-DH-Q2-SM”，也就是说，从SM输出UREP电平。
S106，在本步骤中，控制开关管Q2关断。在Q2关断之后，所有开关管即又重新处于关断的状态，等待下一周期的开启。
需要说明的是，在可能的实施例中，步骤S105在步骤S106之前启动；在又一种可能的实施例中，步骤S106也可在步骤S105之前启动，也就是说，可以根据开关单元UC1的实际电路结构(例如图3所示的电路结构)，控制Q1在Q2关断之前关断。也可根据开关单元UC1的实际电路结构(例如后文图12、图14所示的电路结构)，控制Q2在Q1关断之前关断，本发明实施例在这里不作限定。
为了更好理解本发明实施例所描述的控制方法，下面结合相关附图描述相关开关管在控制过程中的电性变化。参见图9。图9示出了三电平开关电路工作于脉宽调制信号的正半周时相关开关管(S1、Q1、Q2)的时序控制和电性变化情况。本领域技术人员将可以很容易的将该情况下的电性控制描述移置到三电平开关电路工作于脉宽调制信号的负半周的情况，所以不再赘述负半周时相关开关管(S1、Q1、Q2)的时序控制和电性变化情况。
如图9所示，图9示出了控制单元的相关信号控制时序，控制单元分别周期性地向S1、Q1、Q2输入脉宽调制信号GS1、GQ1、GQ2，当脉宽调制信号所转换的控制信号幅度为1时，对应的开关管开通，当脉宽调制信号所转换的控制信号幅度为0时，对应的开关管关断。图9还示出了相关开关管(S1、Q1、Q2)在输入信号的控制下所流通的电流的变化情况，以及示出了在输入信号的控制下Q1和Q2两侧端点(或S1两侧端点)电压的变化情况，亦即在P连接点和SM连接点之间的电压变化情况。
如图9所示，假设在时间t1之前，S1、Q1、Q2处于全导通状态，此时三电平开关电 路处于第一工作状态，SM端输出电压U/2。由于Q1、Q2的导通压降大，小部分电流通过Q1、Q2流通，IQ1、IQ2较小，大部分电路还是从S1流通，IS1较大，由于S1具有低导通损耗的性质，所以三电平开关电路的导通损耗较小。此时Q1和Q2两侧的电压(S1两侧的电压)也较小，接近于0。
在时间t1，S1的脉宽调制信号GS1变为0，亦即所转换的控制信号变为0，所以S1截止，而Q2的脉宽调制信号由于延时模式而被延时到t2，Q3的脉宽调制信号由于延时模式而被延时到t3。S1截止后，在t2之前，P与SM之间的功率通过Q1和Q2进行传输，故电流IQ1、IQ2相应增大。Q1和Q2两侧的电压(S1两侧的电压)也较小，接近于0。此时三电平开关电路处于第一工作状态，SM端输出电压U/2。
在时间t2，Q1的脉宽调制信号GS1变为0，亦即所转换的控制信号变为0，所以Q1截止，三电平开关电路开始切换“UREP-DH-Q2-SM”回路，三电平开关电路的第一开关状态被切换为第二工作状态，IQ2开始减小，Q1和Q2两侧的电压(S1两侧的电压)开始增加。由于Q1和Q2具有低关断损耗的属性，所以在这个过程中，Q1的关断损耗很小。
时间t3，Q2截止，Q1和Q2两侧的电压(S1两侧的电压)增加到最大(U/2)。需要说明的是，Q2截止后，从t3-t4这段时间内，三电平开关电路可进行脉宽调制信号的负周期的相关控制动作，这里不再展开描述。
时间t4-t5期间，负半周的相关控制动作结束后，控制所有开关管Q1、Q2、Q3、Q4、S1、S2为关断的状态，谐振电路中的强感性负载内产生电动势，其充当电源与三电平开关电路的支路构成持续供给电流的回路，从而产生电流续流回路。Q1和Q2两侧的电压(S1两侧的电压)开始减少乃至反向，由于Q1、Q2、S1均并联有一个反向的体二极管，那么电流续流回路将包括“谐振电路-DS1-P”支路以及“谐振电路-D2-D1-P”支路，电流方向为负方向。二极管DS1、D2、D1导通，此时S1、Q1和Q2两端的电压很低(仅为二极管压降)，这个为下一时刻S1的开通提供了ZVS条件。
在时间t5，S1的脉宽调制信号GS1所转换的控制信号变为1，所以S1开通，流经S1的电流IS1从0开始增加，此时由于IS1两端的电压很小(接近于0)，因此S1的开通过程具有ZVS特点，S1的开通损耗很小。开通后，电流通过S1快速增大，由于S1本身具备低导通压降的属性，故S1导通后电流在S1上产生的导通损耗很低。此时，三电平开关电路建立第一工作状态，S1将功率从P端传输到SM端，SM端可向后续电路输出DC电压(+U/2)S1、Q1和Q2两端的电压很小(接近于0)。
时间t6，Q1的脉宽调制信号GQ1所转换的控制信号变为1，所以Q1开通，Q2的脉宽调制信号GQ2所转换的控制信号变为1，所以Q2开通。在Q1和Q2开通时，Q1和Q2两端的电压很小(接近于0)，所以Q1和Q2的开通过程也具备ZVS的特点。由于Q1、Q2的导通压降大，只有小部分电流通过Q1、Q2流通，IQ1、IQ2较小，大部分电路还是从S1流通，IS1较大，由于S1具有低导通损耗的性质，所以三电平开关电路的导通损耗较小。此时三电平开关电路处于第一工作状态，SM端输出电压U/2。
需要说明的是，本发明实施例中t1-t2，t2-t3，t3-t4，t4-t5，t5-t6等等不同时间段的时长均大于或等于零，且不同时间段的时长可以根据实际的应用情况进行具体设定。
可以看出，本发明实施例所提供的电源变换电路包括斩波器，所述斩波器又包括三电 平开关电路和谐振电路，在对斩波器进行控制的过程中，当所有所述晶体管都关断时，相关晶体管(如S1、Q1、Q2)的体二极管基于所述谐振电路的电流续流作用导通，其两端的电压为二极管压降(接近于0)，之后再开通S1开通时，S1的开通过程便具备ZVS特性，之后在开通Q1、Q2时，Q1、Q2也同样具备ZVS特性，从而实现降低开通过程中的开关损耗。另外，本发明实施例中S1采用具有低导通损耗的晶体管，Q1、Q2采用具有低关断损耗的晶体管，在导通状态下，电流绝大部分经由S1通过，所以能够极大程度降低电路的导通损耗。由于控制S1在所述Q1和所述Q2之前开通，所以待Q1和Q2开通时，在电流从路径1切换到路径2的过程中，只需切换极小部分的电路，这样能够避免短时间内电流的快速变化带来额外的电磁干扰(Electromagnetic Interference，EMI)，降低电流切换损耗。最后，在关断过程中，控制S1在Q1和Q2之前关断，最后才将Q1和Q2关断，由于Q1和Q2具有低关断损耗，从而实现了降低关断过程中的开关损耗。
下文中描述本发明实施例所提供的其他电源变换电路结构，在其他电源变换电路结构中，对应的三电平开关电路具有不同的电路结构，以及一些开关管可能的不同控制方式。
参见图10，图10示出了一种可能的电源变换电路结构图，该电源变换电路结构与图3所示的电路结构的区别在于，在三电平开关电路中增加晶体管K1和晶体管K2，所述K1并联有一个体二极管KD1，KD1方向设置为在K1被反向偏置时导通；所述K2并联有一个体二极管KD2，KD2方向设置为在K1被反向偏置时导通。其中，K1的集电极连接DH和DB之间的连接点，K1的发射极连接K2的发射极，K2的集电极连接到Q2和Q3之间的连接点，进而连接到SM。
在这种电路结构中，控制单元对不同晶体管的控制方式例如可参考图11，图11示出了控制单元分别输入到S1、Q1、Q2、GK1的脉宽调制信号(GS1、GQ1、GQ2、GK1)，可以看到，在该控制方式中，在S1、Q1、Q2的开通阶段，控制S1在Q1和Q2开通之前开通，以使该三电平开关电路建立第一工作状态；在S1、Q1、Q2的关断阶段，控制S1在Q2之前关断，之后才控制Q1在Q2之前关断。在Q1关断而Q2尚未关断的期间，控制K1开通，从而使三电平开关电路的第一工作状态切换为第二工作状态。当最后Q2关断时，也将K1关断。具体的分析过程可参考图9实施例中的相关描述，这里不在赘述。
参见图12，图12示出了一种可能的电源变换电路结构图，该电源变换电路结构与图3所示的电路结构的区别在于，在三电平开关电路中，采用晶体管Q5和晶体管Q6替换掉DH和DB，其中，所述Q5并联有一个体二极管D5，D5方向设置为在Q5被反向偏置时导通；所述Q6并联有一个体二极管D6，D6方向设置为在Q6被反向偏置时导通。Q5的集电极连接UC1的输出端X1，Q5的发射极连接到UREF，Q6的发射极连接UC4的输出端X4，Q6的集电极连接到UREF。
在这种电路结构中，控制单元对不同晶体管的控制方式例如可参考图13，图13示出了控制单元分别输入到S1、Q1、Q2、Q6的脉宽调制信号(GS1、GQ1、GQ2、GQ6)，可以看到，在该控制方式中，在S1、Q1、Q2的开通阶段，控制S1在Q1和Q2开通之前开通，以使该三电平开关电路建立第一工作状态；在S1、Q1、Q2的关断阶段，控制S1在Q2之前关断，之后才控制Q2在Q1之前关断。另外，在Q2即将关断的时候，控制Q6导通，从而使得在Q2关断后，三电平开关电路的第一工作状态切换为第二工作状态。当最后Q1关断时， 也将Q6关断。具体的分析过程可参考图9实施例中的相关描述，这里不在赘述。
参见图14，图14示出了一种可能的电源变换电路结构图，该电源变换电路结构与图3所示的电路结构的区别包括，在三电平开关电路中，采用电容C替换掉DH和DB，所述电容C的一端连接UC1的输出端X1，电容C的一端连接UC4的输出端X4。
在这种电路结构中，控制单元对不同晶体管的控制方式例如可参考图15，图15示出了控制单元分别输入到S1、Q1、Q2的脉宽调制信号(GS1、GQ1、GQ2)，可以看到，在该控制方式中，在S1、Q1、Q2的开通阶段，控制S1在Q1和Q2开通之前开通，以使该三电平开关电路建立第一工作状态；在S1、Q1、Q2的关断阶段，控制S1在Q2之前关断，之后才控制Q2在Q1之前关断，在Q2关断且Q1尚未关断期间，三电平开关电路的第一工作状态切换为第二工作状态。具体的分析过程可参考图9实施例中的相关描述，这里不在赘述。
需要说明的是，在上述的实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其他实施例的相关描述。

Claims (11)

  1. 一种电源变换电路的控制方法，所述电源变换电路包括三电平开关电路、谐振电路、变压器、整流电路和滤波电路；所述三电平开关电路的三个输入端分别连接到直流电压P、参考电压UREF、直流电压N，所述三电平开关电路的输出端SM与所述谐振电路的输入端相连，所述谐振电路的输出端与所述变压器的原边绕组连接，所述变压器的副边绕组与所述整流电路的输入端相连，所述整流电路的输出端与所述滤波电路的输入端相连；
    所述三电平开关电路包括开关单元UC1和开关单元UC4；所述UC1的一端与所述P连接，另一端与所述UREF连接,所述UC1的输出端为X1，在所述UC1中包括连接在所述P和所述X1之间的第一开关管Q1；所述UC4的一端与所述N连接，另一端与所述UREF连接，所述UC4的输出端为X4，在所述UC4中包括连接在所述直流电压N和所述X4之间的第一开关管Q4；
    所述三电平开关电路还包括,连接在所述X1和所述SM之间的第二开关管Q2，连接在所述X4和所述SM之间的第二开关管Q3；以及，连接在所述P和所述SM之间的第三开关管S1，连接在所述N和所述SM之间的第三开关管S2；
    其中，所述Q1、Q2、Q3、Q4、S1、S2均包括晶体管，且每个所述晶体管并联体二极管，所述体二极管的方向设置为在其并联的晶体管被反向偏置时导通；
    其特征在于，当所述三电平开关电路工作于脉宽调制信号的正半周时，所述方法包括以下步骤：
    控制所有所述晶体管关断，所述S1的体二极管、所述Q1的体二极管、所述Q2的体二极管皆基于所述谐振电路的电流续流作用导通；
    控制所述S1开通，以建立所述电源变换电路的第一工作状态；
    在所述第一工作状态持续T1时间后，控制所述Q1和所述Q2开通。
  2. 根据权利要求1所述的方法，其特征在于，所述控制所述Q1和所述Q2开通之后，所述方法还包括：
    控制所述S1在所述Q1关断之前关断，控制所述Q1在所述Q2关断之前关断，从而使所述第一工作状态切换到第二工作状态。
  3. 根据权利要求2所述的方法，其特征在于，所述UC1还包括连接在所述UREF和所述X1之间的二极管DH，所述DH用于在所述S1和所述Q1都关断时建立所述第二工作状态；所述UC4还包括连接在所述UREF和所述X4之间的二极管DB。
  4. 根据权利要求3所述的方法，其特征在于，所述三电平开关电路包括还包括连接在所述UREF和所述SM之间的晶体管K1和晶体管K2，所述K1、K2分别并联体二极管KD1、KD2，所述KD1的方向设置为在所述K1被反向偏置时导通，所述KD2的方向设置为在所述K2被反向偏置时导通，所述K1用于在所述S1和所述Q1都关断时建立所述第二工作状态。
  5. 根据权利要求1所述的方法，其特征在于，所述控制所述Q1和所述Q2开通之后，所述方法还包括：
    控制所述S1在所述Q1关断之前关断，控制所述Q2在所述Q1关断之前关断，从而使所述第一工作状态切换到第二工作状态。
  6. 根据权利要求5所述的方法，其特征在于，所述UC1还包括连接在所述UREF和所述X1之间的晶体管Q5，所述Q5并联体二极管D5，所述D5的方向设置为在所述Q5被反向偏置时导通；所述UC4还包括连接在所述UREF和所述X4之间的晶体管Q6，所述Q6并联体二极管D6，所述D6的方向设置为在所述Q6被反向偏置时导通，所述Q6用于在所述S1和所述Q2都关断时建立所述第二工作状态。
  7. 根据权利要求5所述的方法，其特征在于，所述UC1、UC4包括连接在所述X1和所述X4之间的电容C；所述电容C用于在所述S1和所述Q2都关断时建立所述第二工作状态。
  8. 根据权利要求1至7任一项所述的方法，其特征在于，当所述三电平开关电路工作于脉宽调制信号的负半周时，所述方法还包括以下步骤：
    控制所有所述晶体管关断，所述体二极管基于所述谐振电路的电流续流作用导通；
    控制所述S2开通，以建立所述电源变换电路的第三工作状态；
    在所述第三工作状态持续T2时间后，控制所述Q3和所述Q4开通。
  9. 根据权利要求8所述的方法，其特征在于，所述控制所述Q3和所述Q4开通之后，所述方法还包括：
    控制所述S2在所述Q4关断之前关断，控制所述Q4在所述Q3关断之前关断，从而使所述第三工作状态切换到第四工作状态。
  10. 根据权利要求1至9任一项所述的方法，其特征在于，所述S1具有比所述Q1和Q2更低的导通损耗，所述S2具有比所述Q3和Q4更低的导通损耗；所述Q1和Q2具有比所述S1更低的关断损耗，所述Q3和Q4具有比所述S2更低的关断损耗。
  11. 一种电源变换电路，其特征在于，所述电源变换电路包括三电平开关电路、谐振电路、变压器、整流电路和滤波电路；所述三电平开关电路的三个输入端分别连接到直流电压P、参考电压UREF、直流电压N，所述三电平开关电路的输出端SM与所述谐振电路的输入端相连，所述谐振电路的输出端与所述变压器的原边绕组连接，所述变压器的副边绕组与所述整流电路的输入端相连，所述整流电路的输出端与所述滤波电路的输入端相连；
    所述三电平开关电路包括开关单元UC1和开关单元UC4；所述UC1的一端与所述P连接，另一端与所述UREF连接,所述UC1的输出端为X1，在所述UC1中包括连接在所 述P和所述X1之间的第一开关管Q1；所述UC4的一端与所述N连接，另一端与所述UREF连接，所述UC4的输出端为X4，在所述UC4中包括连接在所述直流电压N和所述X4之间的第一开关管Q4；
    所述三电平开关电路还包括,连接在所述X1和所述SM之间的第二开关管Q2，连接在所述X4和所述SM之间的第二开关管Q3；以及，连接在所述P和所述SM之间的第三开关管S1，连接在所述N和所述SM之间的第三开关管S2；
    其中，所述Q1、Q2、Q3、Q4、S1、S2均包括晶体管，且每个所述晶体管并联体二极管，所述体二极管的方向设置为在所述晶体管被反向偏置时导通；
    所述电源变换电路用于，实现权利要求1-10任一项所述的方法。
PCT/CN2018/125802 2018-01-31 2018-12-29 电源变换电路的控制方法以及相关电源变换电路 WO2019149015A1 (zh)

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