WO2019148559A1 - Oled显示装置 - Google Patents

Oled显示装置 Download PDF

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Publication number
WO2019148559A1
WO2019148559A1 PCT/CN2018/077262 CN2018077262W WO2019148559A1 WO 2019148559 A1 WO2019148559 A1 WO 2019148559A1 CN 2018077262 W CN2018077262 W CN 2018077262W WO 2019148559 A1 WO2019148559 A1 WO 2019148559A1
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WIPO (PCT)
Prior art keywords
signal
thin film
potential
film transistor
electrically connected
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PCT/CN2018/077262
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English (en)
French (fr)
Inventor
李双
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US15/760,722 priority Critical patent/US10339869B1/en
Publication of WO2019148559A1 publication Critical patent/WO2019148559A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an OLED display device.
  • OLED Organic Light Emitting Display
  • OLED Organic Light Emitting Display
  • the OLED display device generally includes a substrate, an anode disposed on the substrate, a hole injection layer disposed on the anode, a hole transport layer disposed on the hole injection layer, and a light-emitting layer disposed on the hole transport layer.
  • the principle of luminescence of OLED display devices is that semiconductor materials and organic luminescent materials are driven by electric fields, causing luminescence by carrier injection and recombination.
  • an OLED display device generally uses an indium tin oxide (ITO) pixel electrode and a metal electrode as anodes and cathodes of the device, respectively.
  • ITO indium tin oxide
  • electrons and holes are injected from the cathode and the anode to the electron transport layer and the holes, respectively.
  • electrons and holes migrate to the light-emitting layer through the electron transport layer and the hole transport layer, respectively, and meet in the light-emitting layer to form excitons and excite the light-emitting molecules, and the latter emits visible light through radiation relaxation.
  • a pixel driving circuit is disposed in a sub-pixel thereof, and a driving thin film transistor for driving the organic light emitting diode to emit light is disposed in the pixel driving circuit, and the aging and driving of the organic light emitting diode are used during use.
  • the threshold voltage shift of the thin film transistor may cause the display quality of the OLED display device to be degraded. Therefore, it is necessary to compensate the threshold voltage of the driving thin film transistor during use of the OLED display device, in order to compensate the threshold voltage of the driving thin film transistor, In addition to providing a normal data signal (Data) to its pixel driving circuit, it is also necessary to provide other DC signals such as an initialization voltage (Vini), as shown in FIG.
  • Data normal data signal
  • Vini initialization voltage
  • each sub-pixel in order to provide an initialization voltage to each sub-pixel in the prior art.
  • a plurality of vertical DC signal lines 12' arranged in parallel are arranged in the display area 10' of the OLED display panel, and each of the DC signal lines 12' is electrically connected to a column of sub-pixels 11'.
  • the first end of each DC signal line 12' is electrically connected to the driving circuit board 2' to obtain Taking the initialization voltage, the second end is electrically connected to a short terminal 21'.
  • the sub-pixel 11' far from the driving circuit board 2' is caused.
  • the received initialization voltage is smaller than the initialization voltage of the sub-pixel 11' near the drive circuit board 2', resulting in display unevenness.
  • An object of the present invention is to provide an OLED display device capable of reducing the influence of an IR drop of a DC signal line on display uniformity of an OLED display device and improving display quality of the OLED device.
  • the present invention provides an OLED display device, including: an OLED display panel and a first driving circuit electrically connected to the OLED display panel;
  • the OLED display panel includes: a display area and a non-display area surrounding the display area;
  • the display area includes: a plurality of sub-pixels arranged in an array; and a plurality of DC signal lines arranged in parallel and extending in a column direction of the sub-pixel arrangement, each column sub-pixel correspondingly electrically connected to a DC signal line;
  • the non-display area includes: a first DC signal output end, a second DC signal output end, a first short circuit end, and a second short circuit end, the first DC signal output end, the second short circuit end, and the first
  • the driving circuit is spaced apart from the first end of the OLED display panel, and the second DC signal output end and the first shorting end are spaced apart from the second end of the OLED display panel, and the first end of the OLED display panel is The second end of the OLED display panel is opposite ends of the OLED display panel in the column direction of the sub-pixel arrangement;
  • the first DC signal output end and the second DC signal output end are electrically connected to the first driving circuit; among two adjacent DC signal lines, one of the two DC signal lines is respectively The first DC signal output end is electrically connected to the first short circuit end, and the other ends of the other DC signal line are electrically connected to the second DC signal output end and the second short circuit end, respectively.
  • the display area further includes: a plurality of data lines arranged in parallel and electrically connected to the first driving circuit, a plurality of first scanning lines arranged in parallel, a plurality of second scanning lines arranged in parallel, and a plurality of parallel lines
  • An illuminating signal line arranged at intervals, the data line is parallel to the DC signal line, the first scan line, the second scan line and the illuminating signal line are both perpendicular to the DC signal line, and each row of sub-pixels corresponds to the electric
  • a first scan line, a second scan line and an illuminating signal line are connected, and each column of sub-pixels is electrically connected to one data line.
  • a pixel driving circuit is disposed in each of the sub-pixels, and the pixel driving circuit includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, a second capacitor, and an organic light emitting diode ;
  • the gate of the first thin film transistor is electrically connected to the first scan line corresponding to the sub-pixel, the source is electrically connected to the data line corresponding to the sub-pixel, and the drain is electrically connected to the gate of the fourth thin film transistor;
  • the gate of the second thin film transistor is electrically connected to the second scan line corresponding to the sub-pixel, the source is electrically connected to the source of the fourth thin film transistor, and the drain is electrically connected to the DC signal line corresponding to the sub-pixel ;
  • the gate of the third thin film transistor is electrically connected to the corresponding illuminating signal line of the sub-pixel, the source is connected to the high voltage of the power source, and the drain is electrically connected to the source of the fourth thin film transistor;
  • the first end of the first capacitor is electrically connected to the gate of the fourth thin film transistor, and the second end is electrically connected to the source of the fourth thin film transistor;
  • the second end of the second capacitor is electrically connected to the source of the third thin film transistor, and the drain is electrically connected to the source of the fourth thin film transistor;
  • the anode of the organic light emitting diode is electrically connected to the source of the fourth thin film transistor, and the cathode is connected to the power supply low voltage.
  • the first DC signal output end and the second DC signal output end are configured to receive an initialization voltage from the first driving circuit, and provide the initialization voltage to the DC signal line;
  • the first scan line, the second scan line, and the illuminating signal line are respectively configured to provide a first scan signal, a second scan signal, and a illuminating signal to the corresponding sub-pixels, and the data line receives the data signal from the first driving circuit. And provide it to its corresponding sub-pixel.
  • the combination of the first scan signal, the second scan signal, the illuminating signal and the data signal successively corresponds to an initialization phase, a sampling phase, a programming phase and an illuminating phase;
  • the first scan signal is a first potential
  • the second scan signal is a first potential
  • the illumination signal is a second potential
  • the data signal is a reference voltage potential
  • the first scan signal is a first potential
  • the second scan signal is a second potential
  • the illuminating signal is a first potential
  • the data signal is a reference voltage potential
  • the first scan signal is a first potential
  • the second scan signal is a second potential
  • the illumination signal is a second potential
  • the data signal is a data voltage potential
  • the first scan signal is a second potential
  • the second scan signal is a second potential
  • the illuminating signal is a first potential
  • the data signal is a reference voltage potential
  • the first potential and the second potential The potential of the potential is opposite.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all P-type thin film transistors, the first potential is a low potential, and the second potential is a high potential.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all N-type thin film transistors, the first potential is a high potential, and the second potential is a low potential.
  • the non-display area further includes: a connection trace, and the second DC signal output end is electrically connected to the first driving circuit through the connection trace.
  • the first shorting end is located between the second DC signal output end and the display area, and the second shorting end is located between the first DC signal output end and the display area.
  • the OLED display device further includes: a second driving circuit, wherein the first scan line, the second scan line, and the illuminating signal line are electrically connected to the second driving circuit to respectively receive from the second driving circuit a first scan signal, a second scan signal, and a luminescence signal.
  • the present invention also provides an OLED display device, including: an OLED display panel and a first driving circuit electrically connected to the OLED display panel;
  • the OLED display panel includes: a display area and a non-display area surrounding the display area;
  • the display area includes: a plurality of sub-pixels arranged in an array; and a plurality of DC signal lines arranged in parallel and extending in a column direction of the sub-pixel arrangement, each column sub-pixel correspondingly electrically connected to a DC signal line;
  • the non-display area includes: a first DC signal output end, a second DC signal output end, a first short circuit end, and a second short circuit end, the first DC signal output end, the second short circuit end, and the first
  • the driving circuit is spaced apart from the first end of the OLED display panel, and the second DC signal output end and the first shorting end are spaced apart from the second end of the OLED display panel, and the first end of the OLED display panel is The second end of the OLED display panel is opposite ends of the OLED display panel in the column direction of the sub-pixel arrangement;
  • the first DC signal output end and the second DC signal output end are electrically connected to the first driving circuit; among two adjacent DC signal lines, one of the two DC signal lines is respectively The first DC signal output end is electrically connected to the first short circuit end, and the other ends of the other DC signal line are electrically connected to the second DC signal output end and the second short circuit end respectively;
  • the display area further includes: a plurality of data lines arranged in parallel and electrically connected to the first driving circuit, a plurality of first scanning lines arranged in parallel, a plurality of second scanning lines arranged in parallel, and a plurality of a light-emitting signal line arranged in parallel at intervals, wherein the data line is parallel to the DC signal line, and the first scan line, the second scan line, and the illuminating signal line are both perpendicular to the DC signal line, and each row of sub-pixels Correspondingly electrically connecting a first scan line, a second scan line and a light-emitting signal line, each column of sub-pixels correspondingly electrically connected to one data line;
  • Each of the sub-pixels is provided with a pixel driving circuit, and the pixel driving circuit includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, a second capacitor, and an organic led;
  • the gate of the first thin film transistor is electrically connected to the first scan line corresponding to the sub-pixel, the source is electrically connected to the data line corresponding to the sub-pixel, and the drain is electrically connected to the gate of the fourth thin film transistor;
  • the gate of the second thin film transistor is electrically connected to the second scan line corresponding to the sub-pixel, the source is electrically connected to the source of the fourth thin film transistor, and the drain is electrically connected to the DC signal line corresponding to the sub-pixel ;
  • the gate of the third thin film transistor is electrically connected to the corresponding illuminating signal line of the sub-pixel, the source is connected to the power supply high voltage, and the drain is electrically connected to the drain of the fourth thin film transistor;
  • the first end of the first capacitor is electrically connected to the gate of the fourth thin film transistor, and the second end is electrically connected to the source of the fourth thin film transistor;
  • the second end of the second capacitor is electrically connected to the source of the third thin film transistor, and the drain is electrically connected to the source of the fourth thin film transistor;
  • the anode of the organic light emitting diode is electrically connected to the source of the fourth thin film transistor, and the cathode is connected to the low voltage of the power source;
  • the non-display area further includes: a connection trace, wherein the second DC signal output end is electrically connected to the first driving circuit through the connection trace;
  • the first shorting end is located between the second DC signal output end and the display area, and the second shorting end is located between the first DC signal output end and the display area .
  • the present invention provides an OLED display device including: an OLED display panel and a first driving circuit electrically connected to the OLED display panel, wherein a DC signal line is disposed in a display area of the OLED display panel, The first DC signal output end and the second DC signal output end respectively located at opposite ends of the OLED display panel are disposed in the non-display area, and one of the adjacent two DC signal lines is output from the first DC signal.
  • the terminal receives the signal, and the other receives the signal from the second DC signal output end, so that the impedance changes in opposite directions on the adjacent two DC signal lines during the signal transmission, so that the display unevenness of the adjacent two columns of sub-pixels can mutually Compensation to reduce the influence of the voltage drop of the DC signal line on the display uniformity of the OLED display device, and improve the display quality of the OLED device.
  • FIG. 1 is a schematic structural view of a conventional OLED display device
  • FIG. 2 is a schematic structural view of an OLED display device of the present invention.
  • FIG. 3 is a circuit diagram of a pixel driving circuit of a sub-pixel of the OLED display device of the present invention.
  • FIG. 4 is a timing chart showing the operation of the OLED display device of the present invention.
  • the present invention provides an OLED display device, including: an OLED display panel 1 and a first driving circuit 2 electrically connected to the OLED display panel 1;
  • the OLED display panel 1 includes: a display area 10 and a non-display area 20 surrounding the display area 10;
  • the display area 10 includes a plurality of sub-pixels 11 arranged in an array and a plurality of DC signal lines 12 arranged in parallel along the column direction of the sub-pixels 11. Each column of sub-pixels 11 is electrically connected to a DC.
  • the signal line 12; the non-display area 20 includes: a first DC signal output terminal 21, a second DC signal output terminal 22, a first short terminal 23 and a second short terminal 24, the first DC signal
  • the output end 21, the second shorting end 24 and the first driving circuit 2 are spaced apart from the first end of the OLED display panel 1.
  • the second DC signal output end 22 and the first shorting end 23 are spaced apart from the OLED.
  • a second end of the display panel 1 , the first end of the OLED display panel 1 and the second end of the OLED display panel 1 are two opposite to each other in the column direction of the sub-pixel 11 in the OLED display panel 1 end;
  • the first DC signal output terminal 21 and the second DC signal output terminal 22 are electrically connected to the first driving circuit 2 .
  • two ends of one of the DC signal lines 12 are electrically connected to the first DC signal output end 21 and the first short-circuit end 23, respectively, and the other DC signal line 12 is connected.
  • the two ends are electrically connected to the second DC signal output end 22 and the second short end end 24, respectively.
  • the non-display area 20 further includes: a connection line 25, The two ends of the second DC signal output end 22 are electrically connected to the first driving circuit 2 through a connecting line 25, and the connecting line 25 and the second DC signal output end 22 are used as one. The whole is produced at the same time.
  • connection trace 25 is formed on the OLED display panel 1 In the display area 20, the impedance is extremely small compared to the DC signal line 12 fabricated in the display area 10, so that when the first drive circuit 2 outputs a signal to the second DC signal output terminal 22, the connection trace 25 is passed. However, the voltage drop of the signal is extremely small, so that the second DC signal output terminal 22 coincides with the signal received by the first DC signal output terminal 21.
  • the DC signal line 12 connected to the first DC signal output terminal 21 is also connected to the first short terminal 23, and the DC signal line 12 connected to the second DC signal output terminal 22 is also connected to the The two short terminals 24 are connected, so that the signals received by the DC signal line 12 connected to the first DC signal output terminal 21 are kept consistent, and the signals received by the DC signal line 12 connected to the second DC signal output terminal 22 are also maintained. Consistently, when the first DC signal output terminal 21 and the second DC signal output terminal 22 receive the same signal, the signals received on all of the DC signal lines 12 remain the same.
  • the first shorting end 23 is located between the second DC signal output end 22 and the display area 10 and the second shorting end 24 is located at the first straight
  • the stream signal output terminal 21 is between the display area 10.
  • the display area 10 further includes: a plurality of data lines 13 arranged in parallel and electrically connected to the first driving circuit 2, and a plurality of parallel spaced intervals. a first scan line 14, a plurality of second scan lines 15 arranged in parallel, and a plurality of parallel-arranged light-emitting signal lines 16, the data lines 13 being parallel to the DC signal line 12, the first scan line 14.
  • the second scan line 15 and the illuminating signal line 16 are both perpendicular to the DC signal line 12.
  • Each row of sub-pixels 11 is electrically connected to a first scan line 14, a second scan line 15, and a illuminating signal line. 16.
  • Each column of sub-pixels 11 is electrically connected to a data line 13.
  • each of the sub-pixels 11 is provided with a pixel driving circuit
  • the pixel driving circuit includes: a first thin film transistor T1 and a second thin film transistor T2. a third thin film transistor T3, a fourth thin film transistor T4, a first capacitor C1, a second capacitor C2, and an organic light emitting diode D1; wherein a gate of the first thin film transistor T1 is electrically connected to the first corresponding to the sub-pixel 11
  • the scan line 14 is electrically connected to the data line 13 corresponding to the sub-pixel 11
  • the drain is electrically connected to the gate of the fourth thin film transistor T4.
  • the gate of the second thin film transistor T2 is electrically connected to the sub-pixel 11 .
  • the source is electrically connected to the source of the fourth thin film transistor T4, the drain is electrically connected to the corresponding DC signal line 12 of the sub-pixel 11;
  • the gate of the third thin film transistor T3 Electrically connecting the corresponding light-emitting signal line 16 of the sub-pixel 11 , the source is connected to the power supply high voltage VDD, and the drain is electrically connected to the drain of the fourth thin film transistor T4;
  • the first end of the first capacitor C1 is electrically Connecting the fourth thin film transistor T4 a gate, the second end is electrically connected to the source of the fourth thin film transistor T4;
  • the second end of the second capacitor C2 is electrically connected to the source of the third thin film transistor T3, and the drain is electrically connected
  • the source of the fourth thin film transistor T4; the anode of the organic light emitting diode D1 is electrically connected to the source of the fourth thin film transistor T4, and the cath
  • the first DC signal output terminal 21 and the second DC signal output terminal 22 are used to be from the first driving circuit. 2 receiving an initialization voltage Vini, and supplying the initialization voltage Vini to the DC signal line 12; the first scan line 14, the second scan line 15, and the illuminating signal line 16 are respectively used for corresponding sub-pixels 11
  • a first scan signal SCAN1, a second scan signal SCAN2, and an illumination signal EM are provided, and the data line 12 receives the data signal Data from the first drive circuit 2 and supplies it to its corresponding sub-pixel 11.
  • the OLED display device of the present invention further includes: a second driving circuit, the first scanning line 14, the second scanning line 15 and the illuminating signal line 16 are electrically connected to the second driving circuit to respectively receive the first scanning signal SCAN1 from the second driving circuit The second scan signal SCAN2 and the illuminating signal EM.
  • a parasitic capacitance Coled in parallel with the organic light emitting diode D1 is further formed at both ends of the organic light emitting diode D1.
  • the combination of the first scan signal SCAN1, the second scan signal SCAN2, the illuminating signal EM, and the data signal Data sequentially corresponds to an initialization phase 100 and a sampling phase. 200, programming stage 300 and lighting stage 400;
  • the first scan signal SCAN1 is at a first potential
  • the second scan signal SCAN2 is at a first potential
  • the illuminating signal EM is at a second potential
  • the data signal Data is a reference voltage potential Vref
  • first The thin film transistor T1 and the second thin film transistor T2 are turned on, the potential of the second node N2 becomes the reference voltage potential Vref, the potential of the first node N1 becomes the initialization voltage Vini, the second thin film transistor T4 is turned on, and the third thin film transistor T3 is turned off.
  • the organic light emitting diode D1 does not emit light.
  • the first scan signal SCAN1 is a first potential
  • the second scan signal SCAN2 is a second potential
  • the illumination signal EM is a first potential
  • the data signal Data is a reference voltage potential Vref
  • first The thin film transistor T1 and the third thin film transistor T3 are turned on, the second thin film transistor T2 is turned off, the drain potential of the fourth thin film transistor T4 is the power supply high voltage VDD, and the source potential is the reference voltage potential Vref and the threshold voltage of the fourth thin film transistor T4. The difference between Vth.
  • the first scan signal SCAN1 is at a first potential
  • the second scan signal SCAN2 is at a second potential
  • the illuminating signal EM is at a second potential
  • the data signal Data is a data voltage potential Vdata
  • first The thin film transistor T1 and the second thin film transistor T2 are turned on
  • the third thin film transistor T3 is turned off
  • the first node N1 writes the data signal potential Vdata
  • the source potential of the fourth thin film transistor T4 becomes (Vref-Vth) + C' (Vdata -Vref), where C' is equal to C1/(C1+C2+Coled);
  • the first scan signal SCAN1 is a second potential
  • the second scan signal SCAN2 is a second potential
  • the illuminating signal EM is a first potential
  • the data signal Data is a reference voltage potential Vref;
  • the potentials of the first potential and the second potential are opposite, the first thin film transistor T1 and the second thin film transistor T2 are turned off, the third thin film transistor T3 and the fourth thin film transistor T4 are turned on, and the organic light emitting diode D1 emits light;
  • the current flowing through the organic light emitting diode D1 is K[Vdata-Vref-C'(Vdata-Vref)] 2 , where K is a characteristic parameter of the fourth thin film transistor T4, which is determined by the fourth thin film transistor T4 itself.
  • the magnitude of the initialization potential Vini affects whether the compensation sampling can be successfully completed at the end of the phase 200, and whether the threshold voltage of the fourth thin film transistor T4 can be effectively compensated in the subsequent process, thus initializing The change in the magnitude of the potential Vini affects the final luminance of the sub-pixel.
  • one of the adjacent two DC signal lines receives the initialization voltage from the first DC signal output, and the other Receiving an initialization voltage from the second DC signal output end, so that the impedance changes in the adjacent two DC signal lines are opposite in the initial voltage transmission process, so that the initialization voltage on one DC signal line gradually increases from the first end to the second end.
  • the initialization voltage on the other DC signal line gradually decreases from the second end to the first end, so that the display unevenness of the adjacent two columns of sub-pixels can compensate each other.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may all be P-type thin film transistors.
  • the first potential is low
  • the second potential is high.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may all be N-type thin film transistors.
  • the first potential is a high potential.
  • the second potential is low.
  • the present invention provides an OLED display device including: an OLED display panel and a first driving circuit electrically connected to the OLED display panel, wherein a DC signal line is disposed in a display area of the OLED display panel, a first DC signal output end and a second DC signal output end respectively located at opposite ends of the OLED display panel are respectively disposed in the display area, and one of the adjacent two DC signal lines is outputted from the first DC signal output end
  • the signal is received, and the other receives the signal from the output end of the second DC signal, so that the impedance changes in opposite directions on the adjacent two DC signal lines during the signal transmission, so that the display unevenness of the adjacent two columns of sub-pixels can compensate each other.
  • the display quality of the OLED device is improved.

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Abstract

一种OLED显示装置，包括：OLED显示面板（1）以及与OLED显示面板（1）电性连接的第一驱动电路（2），在OLED显示面板（1）的显示区（10）内设有直流信号线（12），非显示区（20）内设有分别位于OLED显示面板（1）相对的两端的第一直流信号输出端（21）和第二直流信号输出端（22），相邻的两条直流信号线中的一条从第一直流信号输出端（21）接收信号，另一条从第二直流信号输出端（22）接收信号，使得信号传输过程中，相邻的两条直流信号线上阻抗变化方向相反，从而使得相邻的两列子像素的显示不均能够相互补偿，以减少直流信号线的电压降对OLED显示装置的显示均匀性的影响，提升OLED装置的显示品质

Description

OLED显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED显示装置。
背景技术
有机发光二极管(Organic Light Emitting Display，OLED)显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED显示器件通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层、设于空穴注入层上的空穴传输层、设于空穴传输层上的发光层、设于发光层上的电子传输层、设于电子传输层上的电子注入层及设于电子注入层上的阴极。OLED显示器件的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。具体的，OLED显示器件通常采用氧化铟锡(ITO)像素电极和金属电极分别作为器件的阳极和阴极，在一定电压驱动下，电子和空穴分别从阴极和阳极注入到电子传输层和空穴传输层，电子和空穴分别经过电子传输层和空穴传输层迁移到发光层，并在发光层中相遇，形成激子并使发光分子激发，后者经过辐射弛豫而发出可见光。
对于OLED显示装置，其子像素内会设置像素驱动电路，所述像素驱动电路中会设有用于驱动有机发光二极管发光的驱动薄膜晶体管，在使用过程中，由于有机发光二级管的老化以及驱动薄膜晶体管的阈值电压偏移，会导致OLED显示装置的显示质量下降，因此需要在OLED显示装置的使用过程中对驱动薄膜晶体管的阈值电压进行补偿，为了实现对驱动薄膜晶体管的阈值电压进行补偿，除了需要向其像素驱动电路提供普通数据信号(Data)以外，还需要提供例如初始化电压(Vini)之类的其他直流信号，如图1所示，现有技术中为了向各个子像素提供初始化电压(Vini)，需要在所述OLED显示面板的显示区10’内设置多条平行间隔排列的竖直的直流信号线12’，每一条直流信号线12’对应电性连接一列子像素11’，每一条直流信号线12’的第一端均与驱动电路板2’电性连接以获取初始化电压，第二端均与一短接端21’电性连接，此时，由于直流信号线12’本身的阻抗的影响，会使得距离所述驱动电路板2’远的子像素11’接收到的初始 化电压比所述驱动电路板2’近的子像素11’的初始化电压小，从而导致显示不均。
发明内容
本发明的目的在于提供一种OLED显示装置，能够减少直流信号线的电压降(IR drop)对OLED显示装置的显示均匀性的影响，提升OLED装置的显示品质。
为实现上述目的，本发明提供了一种OLED显示装置，包括：OLED显示面板以及与所述OLED显示面板电性连接的第一驱动电路；
所述OLED显示面板包括：显示区以及包围所述显示区的非显示区；
所述显示区包括：阵列排布的多个子像素以及多条平行间隔排列且沿所述子像素排列的列方向延伸的直流信号线，每一列子像素对应电性连接一条直流信号线；所述非显示区包括：第一直流信号输出端、第二直流信号输出端、第一短接端及第二短接端，所述第一直流信号输出端、第二短接端及第一驱动电路间隔设置于所述OLED显示面板的第一端，第二直流信号输出端和第一短接端间隔设置于所述OLED显示面板的第二端，所述OLED显示面板的第一端与所述OLED显示面板的第二端为所述OLED显示面板在所述子像素排列的列方向上相对的两端；
所述第一直流信号输出端和第二直流信号输出端均与所述第一驱动电路电性连接；在相邻的两条直流信号线中，其中一条直流信号线的两端分别与所述第一直流信号输出端和第一短接端电性连接，另一条直流信号线的两端分别与所述第二直流信号输出端和第二短接端电性连接。
所述显示区还包括：多条平行间隔排列且与第一驱动电路电性连接的数据线、多条平行间隔排列的第一扫描线、多条平行间隔排列的第二扫描线及多条平行间隔排列的发光信号线，所述数据线平行于所述直流信号线，所述第一扫描线、第二扫描线及发光信号线均与所述直流信号线垂直，每一行子像素均对应电性连接一条第一扫描线、一条第二扫描线及一条发光信号线，每一列子像素均对应电性连接一条数据线。
每一个子像素内均设有一像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第二电容及有机发光二极管；
所述第一薄膜晶体管的栅极电性连接该子像素对应的第一扫描线，源极电性连接该子像素对应的数据线，漏极电性连接第四薄膜晶体管的栅极；
所述第二薄膜晶体管的栅极电性连接该子像素对应的第二扫描线，源 极电性连接所述第四薄膜晶体管的源极，漏极电性连接该子像素对应的直流信号线；
所述第三薄膜晶体管的栅极电性连接该子像素对应的发光信号线，源极接入电源高电压，漏极电性连接所述第四薄膜晶体管的源极；
所述第一电容的第一端电性连接所述第四薄膜晶体管的栅极，第二端电性连接所述第四薄膜晶体管的源极；
所述第二电容的第二端电性连接所述第三薄膜晶体管的源极，漏极电性连接所述第四薄膜晶体管的源极；
所述有机发光二极管的阳极电性连接第四薄膜晶体管的源极，阴极接入电源低电压。
所述第一直流信号输出端和第二直流信号输出端用于从所述第一驱动电路接收初始化电压，并将所述初始化电压提供给所述直流信号线；
所述第一扫描线、第二扫描线及发光信号线分别用于向其对应的子像素提供第一扫描信号、第二扫描信号及发光信号，所述数据线从第一驱动电路接收数据信号并提供给其对应的子像素。
所述第一扫描信号、第二扫描信号、发光信号及数据信号相组合先后对应一初始化阶段、采样阶段、编程阶段及发光阶段；
在所述初始化阶段，所述第一扫描信号为第一电位，第二扫描信号为第一电位，发光信号为第二电位，所述数据信号为参考电压电位；
在所述采样阶段，所述第一扫描信号为第一电位，第二扫描信号为第二电位，发光信号为第一电位，所述数据信号为参考电压电位；
在所述编程阶段，所述第一扫描信号为第一电位，第二扫描信号为第二电位，发光信号为第二电位，所述数据信号为数据电压电位；
在所述发光阶段，所述第一扫描信号为第二电位，第二扫描信号为第二电位，发光信号为第一电位，所述数据信号为参考电压电位；所述第一电位和第二电位的电位相反。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为P型薄膜晶体管，所述第一电位为低电位，所述第二电位为高电位。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为N型薄膜晶体管，所述第一电位为高电位，所述第二电位为低电位。
所述非显示区还包括：连接走线，所述第二直流信号输出端通过所述连接走线与所述第一驱动电路电性连接。
所述第一短接端位于所述第二直流信号输出端和所述显示区之间，所述第二短接端位于所述第一直流信号输出端和所述显示区之间。
所述OLED显示装置还包括：第二驱动电路，所述第一扫描线、第二扫描线及发光信号线均与所述第二驱动电路电性连接，以分别从所述第二驱动电路接收第一扫描信号、第二扫描信号及发光信号。
本发明还提供一种OLED显示装置，包括：OLED显示面板以及与所述OLED显示面板电性连接的第一驱动电路；
所述OLED显示面板包括：显示区以及包围所述显示区的非显示区；
所述显示区包括：阵列排布的多个子像素以及多条平行间隔排列且沿所述子像素排列的列方向延伸的直流信号线，每一列子像素对应电性连接一条直流信号线；所述非显示区包括：第一直流信号输出端、第二直流信号输出端、第一短接端及第二短接端，所述第一直流信号输出端、第二短接端及第一驱动电路间隔设置于所述OLED显示面板的第一端，第二直流信号输出端和第一短接端间隔设置于所述OLED显示面板的第二端，所述OLED显示面板的第一端与所述OLED显示面板的第二端为所述OLED显示面板在所述子像素排列的列方向上相对的两端；
所述第一直流信号输出端和第二直流信号输出端均与所述第一驱动电路电性连接；在相邻的两条直流信号线中，其中一条直流信号线的两端分别与所述第一直流信号输出端和第一短接端电性连接，另一条直流信号线的两端分别与所述第二直流信号输出端和第二短接端电性连接；
其中，所述显示区还包括：多条平行间隔排列且与第一驱动电路电性连接的数据线、多条平行间隔排列的第一扫描线、多条平行间隔排列的第二扫描线及多条平行间隔排列的发光信号线，所述数据线平行于所述直流信号线，所述第一扫描线、第二扫描线及发光信号线均与所述直流信号线垂直，每一行子像素均对应电性连接一条第一扫描线、一条第二扫描线及一条发光信号线，每一列子像素均对应电性连接一条数据线；
其中，每一个子像素内均设有一像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第二电容及有机发光二极管；
所述第一薄膜晶体管的栅极电性连接该子像素对应的第一扫描线，源极电性连接该子像素对应的数据线，漏极电性连接第四薄膜晶体管的栅极；
所述第二薄膜晶体管的栅极电性连接该子像素对应的第二扫描线，源极电性连接所述第四薄膜晶体管的源极，漏极电性连接该子像素对应的直流信号线；
所述第三薄膜晶体管的栅极电性连接该子像素对应的发光信号线，源极接入电源高电压，漏极电性连接所述第四薄膜晶体管的漏极；
所述第一电容的第一端电性连接所述第四薄膜晶体管的栅极，第二端电性连接所述第四薄膜晶体管的源极；
所述第二电容的第二端电性连接所述第三薄膜晶体管的源极，漏极电性连接所述第四薄膜晶体管的源极；
所述有机发光二极管的阳极电性连接第四薄膜晶体管的源极，阴极接入电源低电压；
其中，所述非显示区还包括：连接走线，所述第二直流信号输出端通过所述连接走线与所述第一驱动电路电性连接；
其中，所述第一短接端位于所述第二直流信号输出端和所述显示区之间，所述第二短接端位于所述第一直流信号输出端和所述显示区之间。
本发明的有益效果：本发明提供一种OLED显示装置，包括：OLED显示面板以及与所述OLED显示面板电性连接的第一驱动电路，在OLED显示面板的显示区内设有直流信号线，非显示区内设有分别位于所述OLED显示面板相对的两端的第一直流信号输出端和第二直流信号输出端，相邻的两条直流信号线中的一条从第一直流信号输出端接收信号，另一条从第二直流信号输出端接收信号，使得信号传输过程中，相邻的两条直流信号线上阻抗变化方向相反，从而使得相邻的两列子像素的显示不均能够相互补偿，以减少直流信号线的电压降对OLED显示装置的显示均匀性的影响，提升OLED装置的显示品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的OLED显示装置的结构示意图；
图2为本发明的OLED显示装置的结构示意图；
图3为本发明的OLED显示装置的一个子像素的像素驱动电路的电路图；
图4为本发明的OLED显示装置的工作时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种OLED显示装置，包括：OLED显示面板1以及与所述OLED显示面板1电性连接的第一驱动电路2；
所述OLED显示面板1包括：显示区10以及包围所述显示区10的非显示区20；
所述显示区10包括：阵列排布的多个子像素11以及多条平行间隔排列且沿所述子像素11排列的列方向延伸的直流信号线12，每一列子像素11对应电性连接一条直流信号线12；所述非显示区20包括：第一直流信号输出端21、第二直流信号输出端22、第一短接端23及第二短接端24，所述第一直流信号输出端21、第二短接端24及第一驱动电路2间隔设置于所述OLED显示面板1的第一端，第二直流信号输出端22和第一短接端23间隔设置于所述OLED显示面板1的第二端，所述OLED显示面板1的第一端与所述OLED显示面板1的第二端为所述OLED显示面板1在所述子像素11排列的列方向上相对的两端；
所述第一直流信号输出端21和第二直流信号输出端22均与所述第一驱动电路2电性连接。在相邻的两条直流信号线12中，其中一条直流信号线12的两端分别与所述第一直流信号输出端21和第一短接端23电性连接，另一条直流信号线12的两端分别与所述第二直流信号输出端22和第二短接端24电性连接。
具体地，如图2所示，所述第一直流信号输出端21、第二直流信号输出端22、第一短接端23及第二短接端24均为沿所述子像素11的排列的行方向延伸的导线，且为了实现所述第二直流信号输出端22与所述第一驱动电路2之间的电性连接，所述非显示区20还包括：连接走线25，所述第二直流信号输出端22两端分别通过一连接走线25与所述第一驱动电路2电性连接，制作时，所述连接走线25与所述第二直流信号输出端22作为一个整体同时制作。
应当理解的是，虽然第一驱动电路2与第二直流信号输出端22之间还需要通过连接走线25来建立电性连接，但由于连接走线25制作于所述OLED显示面板1的非显示区20内，相比于制作于显示区10内的直流信号线12，其阻抗极小，从而虽然第一驱动电路2向第二直流信号输出端22输出信号时，经过了连接走线25，但信号的电压降极小，从而第二直流信号输出端22与第一直流信号输出端21接收到的信号一致。
具体地，在本发明中，与第一直流信号输出端21相连的直流信号线12 还与第一短接端23相连，与第二直流信号输出端22相连的直流信号线12还与第二短接端24相连，从而与第一直流信号输出端21相连的直流信号线12接收到的信号保持一致，与第二直流信号输出端22相连的直流信号线12接收到的信号也保持一致，当第一直流信号输出端21和第二直流信号输出端22接收相同的信号时，所有直流信号线12上接收的信号保持一致。
优选地，如图2所示，所述第一短接端23位于所述第二直流信号输出端22和所述显示区10之间，所述第二短接端24位于所述第一直流信号输出端21和所述显示区10之间。
具体地，请参阅图3，在本发明的优选实施例中，所述显示区10还包括：多条平行间隔排列且与第一驱动电路2电性连接的数据线13、多条平行间隔排列的第一扫描线14、多条平行间隔排列的第二扫描线15及多条平行间隔排列的发光信号线16，所述数据线13平行于所述直流信号线12，所述第一扫描线14、第二扫描线15及发光信号线16均与所述直流信号线12垂直，每一行子像素11均对应电性连接一条第一扫描线14、一条第二扫描线15及一条发光信号线16，每一列子像素11均对应电性连接一条数据线13。
具体地，如图3所示，在本发明的优选实施例中，每一个子像素11内均设有一像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第一电容C1、第二电容C2及有机发光二极管D1；其中，所述第一薄膜晶体管T1的栅极电性连接该子像素11对应的第一扫描线14，源极电性连接该子像素11对应的数据线13，漏极电性连接第四薄膜晶体管T4的栅极；所述第二薄膜晶体管T2的栅极电性连接该子像素11对应的第二扫描线15，源极电性连接所述第四薄膜晶体管T4的源极，漏极电性连接该子像素11对应的直流信号线12；所述第三薄膜晶体管T3的栅极电性连接该子像素11对应的发光信号线16，源极接入电源高电压VDD，漏极电性连接所述第四薄膜晶体管T4的漏极；所述第一电容C1的第一端电性连接所述第四薄膜晶体管T4的栅极，第二端电性连接所述第四薄膜晶体管T4的源极；所述第二电容C2的第二端电性连接所述第三薄膜晶体管T3的源极，漏极电性连接所述第四薄膜晶体管T4的源极；所述有机发光二极管D1的阳极电性连接第四薄膜晶体管T4的源极，阴极接入电源低电压VSS。
需要说明的是，如图3和图4所示，在本发明的优选实施例中，所述第一直流信号输出端21和第二直流信号输出端22用于从所述第一驱动电 路2接收初始化电压Vini，并将所述初始化电压Vini提供给所述直流信号线12；所述第一扫描线14、第二扫描线15及发光信号线16分别用于向其对应的子像素11提供第一扫描信号SCAN1、第二扫描信号SCAN2及发光信号EM，所述数据线12从第一驱动电路2接收数据信号Data并提供给其对应的子像素11。
进一步地，为了向所述第一扫描线14、第二扫描线15及发光信号线16提供第一扫描信号SCAN1、第二扫描信号SCAN2及发光信号EM，本发明的OLED显示装置还包括：第二驱动电路，所述第一扫描线14、第二扫描线15及发光信号线16均与所述第二驱动电路电性连接，以分别从所述第二驱动电路接收第一扫描信号SCAN1、第二扫描信号SCAN2及发光信号EM。
进一步地，如图3所示，在所述有机发光二极管D1的两端还形成有与所述有机发光二极管D1并联的寄生电容Coled。
具体地，如图4所示，在本发明的优选实施例中，所述第一扫描信号SCAN1、第二扫描信号SCAN2、发光信号EM及数据信号Data相组合先后对应一初始化阶段100、采样阶段200、编程阶段300及发光阶段400；
在所述初始化阶段100，所述第一扫描信号SCAN1为第一电位，第二扫描信号SCAN2为第一电位，发光信号EM为第二电位，所述数据信号Data为参考电压电位Vref，第一薄膜晶体管T1和第二薄膜晶体管T2打开，第二节点N2的电位变为参考电压电位Vref，第一节点N1的电位变为初始化电压Vini，第二薄膜晶体管T4打开，第三薄膜晶体管T3关闭，有机发光二极管D1不发光。
在所述采样阶段200，所述第一扫描信号SCAN1为第一电位，第二扫描信号SCAN2为第二电位，发光信号EM为第一电位，所述数据信号Data为参考电压电位Vref，第一薄膜晶体管T1和第三薄膜晶体管T3打开，第二薄膜晶体管T2关闭，第四薄膜晶体管T4的漏极电位为电源高电压VDD，源极电位为参考电压电位Vref与第四薄膜晶体管T4的阈值电压Vth之差。
在所述编程阶段300，所述第一扫描信号SCAN1为第一电位，第二扫描信号SCAN2为第二电位，发光信号EM为第二电位，所述数据信号Data为数据电压电位Vdata，第一薄膜晶体管T1和第二薄膜晶体管T2打开，第三薄膜晶体管T3关闭，第一节点N1写入数据信号电位Vdata，第四薄膜晶体管T4的源极电位变为(Vref-Vth)+C’(Vdata-Vref)，其中C’等于C1/(C1+C2+Coled)；
在所述发光阶段400，所述第一扫描信号SCAN1为第二电位，第二扫 描信号SCAN2为第二电位，发光信号EM为第一电位，所述数据信号Data为参考电压电位Vref；所述第一电位和第二电位的电位相反，第一薄膜晶体管T1和第二薄膜晶体管T2关闭，第三薄膜晶体管T3和第四薄膜晶体管T4打开，有机发光二极管D1发光；
其中，流过有机发光二极管D1的电流为K[Vdata-Vref-C’(Vdata-Vref)] 2，其中K为第四薄膜晶体管T4的特性参数，由第四薄膜晶体管T4本身决定。
其中，在采样阶段200，初始化电位Vini的大小会影响，采用阶段200结束时是否能够顺利完成补偿采样，以及在后续过程中是否能够对第四薄膜晶体管T4的阈值电压进行有效的补偿，因此初始化电位Vini的大小变化会对子像素最后的发光亮度产生影响，在本发明的优选实施例中，相邻的两条直流信号线中的一条从第一直流信号输出端接收初始化电压，另一条从第二直流信号输出端接收初始化电压，使得初始化电压传输过程中，相邻的两条直流信号线上阻抗变化方向相反，从而一条直流信号线上的初始化电压从第一端往第二端逐渐减小，另一条直流信号线上的初始化电压从第二端往第一端逐渐减小，进而使得相邻的两列子像素的显示不均能够相互补偿。
优选地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4可以均为P型薄膜晶体管，此时，所述第一电位为低电位，所述第二电位为高电位。
优选地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4也可以均为N型薄膜晶体管，此时，所述第一电位为高电位，所述第二电位为低电位。
综上所述，本发明提供一种OLED显示装置，包括：OLED显示面板以及与所述OLED显示面板电性连接的第一驱动电路，在OLED显示面板的显示区内设有直流信号线，非显示区内设有分别位于所述OLED显示面板相对的两端的第一直流信号输出端和第二直流信号输出端，相邻的两条直流信号线中的一条从第一直流信号输出端接收信号，另一条从第二直流信号输出端接收信号，使得信号传输过程中，相邻的两条直流信号线上阻抗变化方向相反，从而使得相邻的两列子像素的显示不均能够相互补偿，以减少直流信号线的电压降对OLED显示装置的显示均匀性的影响，提升OLED装置的显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims (16)

  1. 一种OLED显示装置，包括：OLED显示面板以及与所述OLED显示面板电性连接的第一驱动电路；
    所述OLED显示面板包括：显示区以及包围所述显示区的非显示区；
    所述显示区包括：阵列排布的多个子像素以及多条平行间隔排列且沿所述子像素排列的列方向延伸的直流信号线，每一列子像素对应电性连接一条直流信号线；所述非显示区包括：第一直流信号输出端、第二直流信号输出端、第一短接端及第二短接端，所述第一直流信号输出端、第二短接端及第一驱动电路间隔设置于所述OLED显示面板的第一端，第二直流信号输出端和第一短接端间隔设置于所述OLED显示面板的第二端，所述OLED显示面板的第一端与所述OLED显示面板的第二端为所述OLED显示面板在所述子像素排列的列方向上相对的两端；
    所述第一直流信号输出端和第二直流信号输出端均与所述第一驱动电路电性连接；在相邻的两条直流信号线中，其中一条直流信号线的两端分别与所述第一直流信号输出端和第一短接端电性连接，另一条直流信号线的两端分别与所述第二直流信号输出端和第二短接端电性连接。
  2. 如权利要求1所述的OLED显示装置，其中，所述显示区还包括：多条平行间隔排列且与第一驱动电路电性连接的数据线、多条平行间隔排列的第一扫描线、多条平行间隔排列的第二扫描线及多条平行间隔排列的发光信号线，所述数据线平行于所述直流信号线，所述第一扫描线、第二扫描线及发光信号线均与所述直流信号线垂直，每一行子像素均对应电性连接一条第一扫描线、一条第二扫描线及一条发光信号线，每一列子像素均对应电性连接一条数据线。
  3. 如权利要求2所述的OLED显示装置，其中，每一个子像素内均设有一像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第二电容及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接该子像素对应的第一扫描线，源极电性连接该子像素对应的数据线，漏极电性连接第四薄膜晶体管的栅极；
    所述第二薄膜晶体管的栅极电性连接该子像素对应的第二扫描线，源极电性连接所述第四薄膜晶体管的源极，漏极电性连接该子像素对应的直流信号线；
    所述第三薄膜晶体管的栅极电性连接该子像素对应的发光信号线，源极接入电源高电压，漏极电性连接所述第四薄膜晶体管的漏极；
    所述第一电容的第一端电性连接所述第四薄膜晶体管的栅极，第二端电性连接所述第四薄膜晶体管的源极；
    所述第二电容的第二端电性连接所述第三薄膜晶体管的源极，漏极电性连接所述第四薄膜晶体管的源极；
    所述有机发光二极管的阳极电性连接第四薄膜晶体管的源极，阴极接入电源低电压。
  4. 如权利要求3所述的OLED显示装置，其中，所述第一直流信号输出端和第二直流信号输出端用于从所述第一驱动电路接收初始化电压，并将所述初始化电压提供给所述直流信号线；
    所述第一扫描线、第二扫描线及发光信号线分别用于向其对应的子像素提供第一扫描信号、第二扫描信号及发光信号，所述数据线从第一驱动电路接收数据信号并提供给其对应的子像素。
  5. 如权利要求4所述的OLED显示装置，其中，所述第一扫描信号、第二扫描信号、发光信号及数据信号相组合先后对应一初始化阶段、采样阶段、编程阶段及发光阶段；
    在所述初始化阶段，所述第一扫描信号为第一电位，第二扫描信号为第一电位，发光信号为第二电位，所述数据信号为参考电压电位；
    在所述采样阶段，所述第一扫描信号为第一电位，第二扫描信号为第二电位，发光信号为第一电位，所述数据信号为参考电压电位；
    在所述编程阶段，所述第一扫描信号为第一电位，第二扫描信号为第二电位，发光信号为第二电位，所述数据信号为数据电压电位；
    在所述发光阶段，所述第一扫描信号为第二电位，第二扫描信号为第二电位，发光信号为第一电位，所述数据信号为参考电压电位；所述第一电位和第二电位的电位相反。
  6. 如权利要求5所述的OLED显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为P型薄膜晶体管，所述第一电位为低电位，所述第二电位为高电位。
  7. 如权利要求5所述的OLED显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为N型薄膜晶体管，所述第一电位为高电位，所述第二电位为低电位。
  8. 如权利要求1所述的OLED显示装置，其中，所述非显示区还包括：连接走线，所述第二直流信号输出端通过所述连接走线与所述第一驱动电 路电性连接。
  9. 如权利要求1所述的OLED显示装置，其中，所述第一短接端位于所述第二直流信号输出端和所述显示区之间，所述第二短接端位于所述第一直流信号输出端和所述显示区之间。
  10. 如权利要求4所述的OLED显示装置，还包括：第二驱动电路，所述第一扫描线、第二扫描线及发光信号线均与所述第二驱动电路电性连接，以分别从所述第二驱动电路接收第一扫描信号、第二扫描信号及发光信号。
  11. 一种OLED显示装置，包括：OLED显示面板以及与所述OLED显示面板电性连接的第一驱动电路；
    所述OLED显示面板包括：显示区以及包围所述显示区的非显示区；
    所述显示区包括：阵列排布的多个子像素以及多条平行间隔排列且沿所述子像素排列的列方向延伸的直流信号线，每一列子像素对应电性连接一条直流信号线；所述非显示区包括：第一直流信号输出端、第二直流信号输出端、第一短接端及第二短接端，所述第一直流信号输出端、第二短接端及第一驱动电路间隔设置于所述OLED显示面板的第一端，第二直流信号输出端和第一短接端间隔设置于所述OLED显示面板的第二端，所述OLED显示面板的第一端与所述OLED显示面板的第二端为所述OLED显示面板在所述子像素排列的列方向上相对的两端；
    所述第一直流信号输出端和第二直流信号输出端均与所述第一驱动电路电性连接；在相邻的两条直流信号线中，其中一条直流信号线的两端分别与所述第一直流信号输出端和第一短接端电性连接，另一条直流信号线的两端分别与所述第二直流信号输出端和第二短接端电性连接；
    其中，所述显示区还包括：多条平行间隔排列且与第一驱动电路电性连接的数据线、多条平行间隔排列的第一扫描线、多条平行间隔排列的第二扫描线及多条平行间隔排列的发光信号线，所述数据线平行于所述直流信号线，所述第一扫描线、第二扫描线及发光信号线均与所述直流信号线垂直，每一行子像素均对应电性连接一条第一扫描线、一条第二扫描线及一条发光信号线，每一列子像素均对应电性连接一条数据线；
    其中，每一个子像素内均设有一像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第二电容及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接该子像素对应的第一扫描线，源极电性连接该子像素对应的数据线，漏极电性连接第四薄膜晶体管的栅极；
    所述第二薄膜晶体管的栅极电性连接该子像素对应的第二扫描线，源极电性连接所述第四薄膜晶体管的源极，漏极电性连接该子像素对应的直流信号线；
    所述第三薄膜晶体管的栅极电性连接该子像素对应的发光信号线，源极接入电源高电压，漏极电性连接所述第四薄膜晶体管的漏极；
    所述第一电容的第一端电性连接所述第四薄膜晶体管的栅极，第二端电性连接所述第四薄膜晶体管的源极；
    所述第二电容的第二端电性连接所述第三薄膜晶体管的源极，漏极电性连接所述第四薄膜晶体管的源极；
    所述有机发光二极管的阳极电性连接第四薄膜晶体管的源极，阴极接入电源低电压；
    其中，所述非显示区还包括：连接走线，所述第二直流信号输出端通过所述连接走线与所述第一驱动电路电性连接；
    其中，所述第一短接端位于所述第二直流信号输出端和所述显示区之间，所述第二短接端位于所述第一直流信号输出端和所述显示区之间。
  12. 如权利要求11所述的OLED显示装置，其中，所述第一直流信号输出端和第二直流信号输出端用于从所述第一驱动电路接收初始化电压，并将所述初始化电压提供给所述直流信号线；
    所述第一扫描线、第二扫描线及发光信号线分别用于向其对应的子像素提供第一扫描信号、第二扫描信号及发光信号，所述数据线从第一驱动电路接收数据信号并提供给其对应的子像素。
  13. 如权利要求12所述的OLED显示装置，其中，所述第一扫描信号、第二扫描信号、发光信号及数据信号相组合先后对应一初始化阶段、采样阶段、编程阶段及发光阶段；
    在所述初始化阶段，所述第一扫描信号为第一电位，第二扫描信号为第一电位，发光信号为第二电位，所述数据信号为参考电压电位；
    在所述采样阶段，所述第一扫描信号为第一电位，第二扫描信号为第二电位，发光信号为第一电位，所述数据信号为参考电压电位；
    在所述编程阶段，所述第一扫描信号为第一电位，第二扫描信号为第二电位，发光信号为第二电位，所述数据信号为数据电压电位；
    在所述发光阶段，所述第一扫描信号为第二电位，第二扫描信号为第二电位，发光信号为第一电位，所述数据信号为参考电压电位；所述第一电位和第二电位的电位相反。
  14. 如权利要求13所述的OLED显示装置，其中，所述第一薄膜晶体 管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为P型薄膜晶体管，所述第一电位为低电位，所述第二电位为高电位。
  15. 如权利要求13所述的OLED显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管均为N型薄膜晶体管，所述第一电位为高电位，所述第二电位为低电位。
  16. 如权利要求12所述的OLED显示装置，还包括：第二驱动电路，所述第一扫描线、第二扫描线及发光信号线均与所述第二驱动电路电性连接，以分别从所述第二驱动电路接收第一扫描信号、第二扫描信号及发光信号。
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