WO2019147886A1 - Procédés de fabrication de substrats de puissance thermiquement conducteurs à base de céramique - Google Patents

Procédés de fabrication de substrats de puissance thermiquement conducteurs à base de céramique Download PDF

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Publication number
WO2019147886A1
WO2019147886A1 PCT/US2019/015075 US2019015075W WO2019147886A1 WO 2019147886 A1 WO2019147886 A1 WO 2019147886A1 US 2019015075 W US2019015075 W US 2019015075W WO 2019147886 A1 WO2019147886 A1 WO 2019147886A1
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WIPO (PCT)
Prior art keywords
electrically conductive
conductive layer
layer
ceramic
aluminum
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PCT/US2019/015075
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English (en)
Inventor
Yajie Chen
Yiying YAO
Shawn P. Williams
Eui Kyoon Kim
Andreas Meyer
Stefan Britting
Karsten Schmidt
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Rogers Corporation
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Publication of WO2019147886A1 publication Critical patent/WO2019147886A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
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    • C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/653—Processes involving a melting step
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    • C04B37/00—Joining burned ceramic articles with other burned ceramic articles or other articles by heating
    • C04B37/02—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
    • C04B37/021—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles in a direct manner, e.g. direct copper bonding [DCB]
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    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/009—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone characterised by the material treated
    • C—CHEMISTRY; METALLURGY
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    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/50—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials
    • C04B41/5025—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials with ceramic materials
    • C04B41/5031—Alumina
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    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/50—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials
    • C04B41/5025—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials with ceramic materials
    • C04B41/5042—Zirconium oxides or zirconates; Hafnium oxides or hafnates
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    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/50—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials
    • C04B41/5053—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials non-oxide ceramics
    • C04B41/5062—Borides, Nitrides or Silicides
    • C04B41/5066—Silicon nitride
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    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/80—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone of only ceramics
    • C04B41/81—Coating or impregnation
    • C04B41/85—Coating or impregnation with inorganic materials
    • C04B41/87—Ceramics
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C24/00—Coating starting from inorganic powder
    • C23C24/02—Coating starting from inorganic powder by application of pressure only
    • C23C24/04—Impact or kinetic deposition of particles
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
    • C04B2111/00474—Uses not provided for elsewhere in C04B2111/00
    • C04B2111/00844—Uses not provided for elsewhere in C04B2111/00 for electronic applications
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/34—Oxidic
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/34—Oxidic
    • C04B2237/343—Alumina or aluminates
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/34—Oxidic
    • C04B2237/345—Refractory metal oxides
    • C04B2237/348—Zirconia, hafnia, zirconates or hafnates
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/36—Non-oxidic
    • C04B2237/365—Silicon carbide
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/36—Non-oxidic
    • C04B2237/366—Aluminium nitride
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
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    • C04B2237/32—Ceramic
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    • C04B2237/368—Silicon nitride
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/40—Metallic
    • C04B2237/407—Copper
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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/70—Forming laminates or joined articles comprising layers of a specific, unusual thickness
    • C04B2237/704—Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the ceramic layers or articles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
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    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333—Deposition techniques, e.g. coating
    • H05K2203/1344—Spraying small metal particles or droplets of molten metal

Definitions

  • This disclosure is directed to methods for the manufacture of ceramic, thermally conductive power substrates, ceramic, thermally conductive power substrates produced by the method, and power electronic modules containing the substrates.
  • a power electronic module is an assembly including interconnected power components that perform a power conversion function, such as such as semiconductor devices.
  • the power electronic module typically is in thermal communication with a heat sink to remove heat generated as a result of power loss.
  • the ceramic substrate is an important component of power electronics because it serves as a low-inductance interconnection as well as an interface between the power components and the heat sink.
  • the ceramic substrate typically includes a ceramic insulator layer with metal layers, e.g., copper or aluminum, bonded on the top and bottom of the ceramic layer.
  • the ceramic layer provides electrical isolation between the top and bottom metal layers while also providing thermal conduction.
  • the top metal layer provides electrical conduction and can include circuit traces, which provide electrical connection to the power components in the power electronic module.
  • the bottom metal layer of the ceramic substrate can be unpatterned to provide heat spreading, for example, it can be attached to a heat sink.
  • Ceramic substrates for power electronics are typically fabricated by depositing (e.g., by physical vapor deposition, electroplating, etc.) or attaching (e.g., by brazing, eutectic bonding) top and bottom metal layers to a previously sintered ceramic substrate.
  • a method of making a power electronic substrate comprises directly depositing a ceramic, electrically insulating layer onto a first side of a first electrically conductive layer at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 18 to 27°C, optionally wherein the first electrically conductive layer is a flat electrically conductive layer,
  • first electrically conductive layer optionally patterning the first electrically conductive layer into circuit traces, and optionally mounting one or more power electronic components on the first electrically conductive layer, the second electrically conductive layer, or both the first and second electrically conductive layers.
  • a power electronics unit comprises the power electronic substrate made by the above-described method.
  • FIG. 1 is a schematic drawing of the deposition of a ceramic layer on a first electrically conductive layer by aerosol deposition.
  • FIG. 2 is a schematic of the deposition of a second electrically conductive layer on a ceramic layer.
  • Described herein are methods for the fabrication of ceramic-based power electronic substrates that can achieve either thin or thick metallization, large dimensions, or high thermal conductivity, for example greater than 5 Watts per meter-Kelvin (W/m-K).
  • the ceramic insulating layer can be deposited on an electrically conducting layer at temperatures much lower than those required for brazing or eutectic bonding.
  • various thicknesses of ceramic can be applied without warping and while avoiding coefficient of thermal expansion mismatch during fabrication.
  • large-format fabrication can also be achieved.
  • the power electronic substrates described herein have an extended voltage application range from less than 1000 V (for low-voltage applications, such as LED, appliances, etc.) to greater than 5000 V (for very- high-voltage applications, such as solid-state transformers).
  • the methods described herein can be used to fabricate very thin power substrates for low voltage as well as very high voltage applications.
  • the method of making the power electronic substrate comprises directly depositing a ceramic, electrically insulating layer onto a first side of a first electrically conductive layer at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 18 to 27°C, or 20 to 24°C, for example at room temperature (e.g., 22 to 23°C).
  • the first electrically conductive layer is a flat electrically conductive layer.
  • the method can further comprise depositing or attaching a second electrically conductive layer on a second side of the deposited ceramic, electrically insulating layer, i.e., a side opposite the first electrically conductive layer.
  • the method further comprises patterning the first electrically conductive layer into circuit traces, and optionally mounting one or more power components on the first electrically conductive layer, the second electrically conductive layer, or both the first and second electrically conductive layers.
  • the methods described herein can be used to produce power electronic substrates having a single electrically conductive layer, e.g., a first electrically conductive layer, or power electronic substrates with two electrically conductive layers having the ceramic, electrically insulating layer between them.
  • the first electrically conductive layer of the power electronic substrate, onto which the ceramic layer is deposited is a sheet or film that can have low profile features, for example cooling pin-fins, cooling channels, or the like.
  • the first electrically conductive layer is a flat electrically conductive layer having no 3-dimensional features on at least a first surface, or on both opposite surfaces.
  • the first electrically conductive layer can comprise copper, a copper alloy, a copper composite, aluminum, an aluminum alloy, an aluminum composite, or a combination comprising at least one of the foregoing.
  • the ceramic layer is directly deposited onto the first electrically conductive layer at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 18 to 27°C, or 20 to 24°C, for example at room temperature (e.g., 22 to 23°C).
  • Exemplary methods for direct deposition of the ceramic layer include aerosol deposition, thermal spray, or sol-gel deposition.
  • the aerosol deposition method is a technology whereby a fine or ultrafme particle raw material is aerosolized by mixing with a gas, then applied to a substrate via, e.g. a one or more nozzle, thus forming a film on a substrate.
  • a device for aerosol deposition typically includes an aerosolization chamber and a film formation chamber.
  • a fine or ultrafme particle material ceramic material is aerosolized by being agitated and mixed with a gas in a dried state in the aerosolization chamber.
  • the aerosolized ceramic material is then conveyed to the film formation chamber by a gas flow generated by the difference in pressure between the two chambers, and by passing through the slit type nozzles, the aerosolized ceramic material is accelerated and sprayed onto a first surface of the first electrically conductive layer.
  • the starting ceramic material can have a particle diameter of 1 nanometer to 1 micrometer (pm), for example from 0.1 to 100 pm, or 0.1 to 50 pm, for example.
  • the aerosolized ultrafme particles can be accelerated to several hundred m/sec by being passed through the nozzles of minute openings in the depressurized chamber, forming a ceramic layer on a first side of the first electrically conductive layer.
  • FIG. 1 shows an aspect of a ceramic layer (2) deposited on a first side of a first electrically conductive layer (1) using aerosol deposition through an aerosol nozzle (3).
  • the thermal spray method of ceramic layer deposition is also known in the art as plasma spray, high-velocity oxygen fuel (HVOF), arc spray, or flame spray.
  • Thermal spray is a process in which ceramic powders (usually of a particle diameter of 50 to 150 pm) or wire enters into a highly reactive (due to high temperature) thermal spray gun and the liquid or molten materials can be emitted to a first side of the first electronically conductive layer with high velocity to form a layer.
  • the ceramic material that forms the ceramic layer preferably does not decompose during the thermal process, and exemplary coating materials are aluminum oxide, zirconium oxide, and titanium oxide.
  • the sol-gel method of ceramic layer deposition is a process in which a sol (a colloidal dispersion of a ceramic precursor) is subjected to a gelling, drying, and tempering process by means of chemical or physical reactions.
  • the sol or precursor is a liquid at the start of the process and is converted into a solid in the course of the process.
  • Exemplary ceramic precursors are preceramic polymers used to form polymer-derived ceramics such as polysilanes, polysilazanes, and polysiloxanes.
  • An exemplary polysilane is a polycarbosilane, such as poly(allyl)carbosilane, which thermally decomposes under vacuum or an inert gas into silicon carbide.
  • preceramic polymers can decompose into nitrides, carbides, oxides, or combinations thereof.
  • the preceramic polymer can include only the polymer, or the polymer and additional constituents.
  • the additional constituents can be, but are not limited to, additives, such as processing aids, reinforcement materials, and the like.
  • the ceramic, electrically insulating layer is deposited as a single layer.
  • the ceramic, electrically insulating layer is deposited as multiple layers, each layer deposited at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 23 °C, wherein each of the multiple layers has the same or a different ceramic composition.
  • the ceramic, electrically insulating layer, whether a single layer or multiple layers, can have a total thickness of 3 to 3000 micrometers, or 3 to 400 micrometers, or 400 to 3000 micrometers.
  • the electrically insulating layer is deposited as multiple layers comprising a core layer of a first ceramic material deposited on the first side of the electrically conductive layer and a top layer of a second ceramic material disposed on at least a portion of the core layer.
  • the top layer is directly disposed on the core layer, that is, without an added binder.
  • the core layer is thicker than the top layer, specifically, the ratio of thickness of the top layer to the core layer is less than 1, preferably less than 0.5, more preferably less than 0.2, and most preferably 0.13 to 0.18.
  • the core layer can have a thickness greater than 1 mm, preferably greater than 1.5 mm, and more preferably greater than 2 mm.
  • the core layer comprises A1N and the top layer comprises S13N4 or ZTA (zirconium toughened alumina).
  • the top layer can be directly attached to the core layer by depositing the second ceramic material onto the core layer using aerosol deposition, thermal spray, or sol-gel deposition as described herein.
  • the top layer may have a thickness of less than 25 pm, less than 15 pm or less than 10 pm.
  • Exemplary materials for the ceramic, electrically insulating layer include aluminum oxide, aluminum nitride, aluminum nitride oxide, aluminum oxynitride, boron nitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or a
  • the ceramic, electrically insulating layer comprises aluminum oxide, aluminum nitride, silicon nitride, boron nitride, or a combination comprising at least one of the foregoing.
  • the ceramic, electrically insulating layer has a thermal conductivity higher than 5 W/m-K, preferably higher than 10 W/m-K.
  • thermal conductivity higher than 5 W/m-K, preferably higher than 10 W/m-K.
  • a second electrically conductive layer is deposited on a second side of the deposited ceramic, electrically insulating layer, the second side being opposite the first electrically conductive layer.
  • the second layer optionally can have low profile features, for example cooling pin-fins, cooling channels, or the like.
  • the material for the second electrically conductive layer is the same as the materials described above for the first electrically conductive layer.
  • the second electrically conductive layer is present and comprises copper, a copper alloy, or a copper composite layer having a thickness of 1 to 1500 micrometers.
  • the second electrically conductive layer is present and is an electrically conductive layer, and comprises aluminum, an aluminum alloy, or an aluminum composite.
  • the second electrically conductive layer can be a continuous layer or can be discontinuous, e.g., patterned or comprising circuit traces.
  • depositing or attaching the second electrically conductive layer is by any method, for example, metal cold spraying, direct metal sintering, thermal evaporating, electroplating, or attaching via an adhesive.
  • the depositing or attaching the second electrically conductive layer is by a direct, relatively low temperature method such as metal cold spraying, direct metal sintering, thermal evaporating, or electroplating.
  • high temperature methods are not used, such as eutectic bonding (also called direct bonding, i.e., bonding through formation of a copper-oxygen eutectic) or active metal brazing (where a metal (e.g., titanium) is added to the braze alloy to promote reaction and wetting with a ceramic substrate).
  • eutectic bonding also called direct bonding, i.e., bonding through formation of a copper-oxygen eutectic
  • active metal brazing where a metal (e.g., titanium) is added to the braze alloy to promote reaction and wetting with a ceramic substrate).
  • Cold metal spray typically involves utilizing a high-speed gas to accelerate metal particles toward a substrate upon which the metal particles plastically deform and consolidate on impact.
  • a metal layer can be applied using a laser that can build the layer based upon a CAD model, for example.
  • thermal evaporation the source material for the layer is evaporated in a vacuum and the vapor particles then condense on the ceramic surface to provide a solid layer.
  • electroplating method the electrically conductive layer is deposited on a pre-deposited seed layer by an electrolytic process.
  • the seed layer can be deposited via thin-film technology such as physical vapor deposition
  • the seed layer can also be deposited via thick-film technology (e.g., printed-and-fired metal film).
  • exemplary adhesives for attaching the second metal layer include synthetic adhesive or a polymer which is suitable for use as an adhesive, such as a thermoplastic or thermoset polymeric material.
  • the second electrically conductive layer is deposited at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 18 to 27°C, or 20 to 2l°C, or at room temperature, e.g., 21 to 23°C.
  • FIG. 2 shows an aspect of a substrate having a ceramic layer (2) deposited on a first electrically conductive layer (1).
  • a second electrically conductive layer (4) is deposited on the ceramic layer (2) using cold spray deposition through a cold spray nozzle
  • the second electrically conductive layer When the second electrically conductive layer is present, it can be attached to a heat sink.
  • Heat sinks can comprise one or more cooling fins which facilitate heat dissipation.
  • the first electrically conductive layer, and optionally the second electrically conductive layer can be patterned into circuit traces. Patterning can be done, for example, by etching methods or other circuit board processing methods known in the art.
  • Exemplary power electronic substrate layers include Cu/ceramic/Cu;
  • Al/ceramic/Cu Al/ceramic/Al
  • Cu Cu/ceramic/Al
  • the power electronic substrates fabricated by the methods disclosed herein can have one or more of the following properties: a thermal conductivity of greater than 5 W/m-K; a breakdown voltage of greater than 10 kV/mm, preferably greater than 20 kV/mm; or an operating range of up to 200°C, preferably up to 800°C.
  • the method optionally comprises mounting one or more power electronic components as well as other circuit components on the first electrically conductive layer, the second electrically conductive layer, or both the first and second electrically conductive layers.
  • Power electronic components include power transistors, power thyristors, and power diodes.
  • Power transistors include metal-oxide-semiconductor field-effect transistors
  • Thyristors include gate turn-off thyristors (GTO), silicon-controlled thyristors (SCR), and MOS-controlled thyristors (MCT).
  • Power electronic components also include surface-mount passive components. Passive components include resistors, capacitors, inductors, and transformers. Other circuit components include but are not limited to IC chips, sensor chips, resistors, capacitors, inductors, and transformers. [0035] Also included herein are power electronic units comprising the power electronic substrate made by the methods disclosed herein.
  • a power electronics unit comprises a heat sink and a power electronic module comprising one or more power components.
  • the heat sink can be disposed on or in thermally conductive contact with the ceramic layer or the second electrically conductive layer of the ceramic substrate.
  • the power electronic module can be disposed on or in electrically conductive contact with the first electrically conductive layer of the ceramic substrate.
  • the power electronic unit can be suitable for use in low voltage applications at less than 1000 V, for use in medium voltage applications of 1 kV - 5 kV, or for use in high voltage applications at higher than 5 kV.
  • Advantages of the methods and compositions described herein include fabricating power substrates with a low cost of manufacturing, control of the thickness of the ceramic insulating layer and electrically conductive traces, and the possibility of a large format of substrate (e.g., those having a planar area of greater than 6 inches X 10 inches (15 X 26 centimeters.).
  • the methods described above can provide thicker single- or double- sided metallization.
  • the method is flexible, allowing the manufacture of thin (e.g., less than or equal to 4 mils (0.1 mm) or thick (e.g., greater than 4 mils (0.1 mm)) electrically conductive metal layers.
  • the methods described above can provide single- or double-sided metallization with less substrate warping. Thin and optionally flexible substrates with one or two-sided metallization can be fabricated.
  • Aspect 1 A method of making a power electronic substrate, the method comprising
  • first electrically conductive layer directly depositing onto a first side of a first electrically conductive layer at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 18 to 27°C, optionally wherein the first electrically conductive layer is a flat electrically conductive layer,
  • first electrically conductive layer optionally patterning the first electrically conductive layer into circuit traces, and optionally mounting one or more power electronic components on the first electrically conductive layer, the second electrically conductive layer, or both the first and second electrically conductive layers.
  • Aspect 2 The method of aspect 1, wherein the second electrically conductive layer is present, and further comprising attaching the second electrically conductive layer to a heat sink.
  • Aspect 3 The method of aspect 1, wherein the second electrically conductive layer is present, and further comprising patterning the second electrically conductive layer into circuit traces.
  • Aspect 4 The method of any one or more of the preceding aspects, wherein the ceramic, electrically insulating layer is deposited as a single layer.
  • Aspect 5 The method of any one or more of aspects 1-3, wherein the ceramic, electrically insulating layer is deposited as multiple layers, each layer being deposited at a temperature of less than 500°C, preferably less than l00°C, and more preferably at 18 to 27°C, wherein each of the multiple layers has the same or a different ceramic composition.
  • Aspect 6 The method of aspect 5, wherein the multiple layers comprise a core layer of a first ceramic material deposited on the first side of the electrically conductive layer, and a top layer of a second ceramic material disposed on at least a portion of the core layer.
  • Aspect 7 The method of aspect 6, wherein the core layer comprises aluminum nitride, and the top layer comprises silicon nitride or zirconia toughened alumina.
  • Aspect 8 The method of any one or more of the preceding aspects, wherein the ceramic, electrically insulating layer has a total thickness of 3 to 3000 micrometers, or 3 to 400 micrometers, or 400 to 3000 micrometers.
  • Aspect 9 The method of any one or more of the preceding aspects, wherein the ceramic, electrically insulating layer comprises
  • Aspect 10 The method of any one or more of the preceding aspects, wherein the ceramic, electrically insulating layer has a thermal conductivity higher than 5 W/m-K, preferably higher than 10 W/m-K.
  • Aspect 11 The method of any one or more of the preceding aspects, wherein the first electrically conductive layer and the optional second electrically conductive layer when present each comprise a metal film having a thickness of 10 micrometers to greater than 20 centimeters, a width of 2 millimeters to greater than 15 centimeters, and a length of 2 millimeters to greater than 25 centimeters.
  • Aspect 12 The method of any one or more of aspects 1 to 11, wherein the first electrically conductive layer is circuitized.
  • Aspect 13 The method of any one or more of aspects 1 to 11, wherein the first or second electrically conductive layer, or both, contain a cooling feature, preferably a cooling pin- fin or a cooling channel.
  • Aspect 14 The method of any one or more of the preceding aspects, wherein the first electrically conductive layer comprises copper, a copper alloy, a copper composite, aluminum, an aluminum alloy, an aluminum composite, or a combination comprising at least one of the foregoing.
  • Aspect 15 The method of any one or more of the preceding aspects, wherein the second electrically conductive layer is present and comprises copper, a copper alloy, a copper composite, aluminum, an aluminum alloy, an aluminum composite, or a combination comprising at least one of the foregoing.
  • Aspect 16 The method of any one or more of the preceding aspects, wherein the second electrically conductive layer is present and is a continuous or discontinuous electrically conductive layer, and comprises copper, a copper alloy, or a copper composite layer having a thickness of 1 to 1500 micrometers.
  • Aspect 17 The method of any one or more of aspects 1-13, wherein the second electrically conductive layer is present and comprises aluminum, an aluminum alloy, or an aluminum composite.
  • Aspect 18 The method of any one or more of the preceding aspects, wherein the directly depositing the ceramic, electrically insulating layer is by aerosol deposition, thermal spray, or a sol-gel method.
  • Aspect 19 The method of any one or more of the preceding aspects, wherein the depositing or attaching the second electrically conductive layer is by metal cold spraying, direct metal sintering, thermal evaporating, or electroplating.
  • Aspect 20 The method of any one or more of the preceding aspects, wherein the power electronic substrate has at least one of
  • a power electronic substrate made by the method of any one or more of the preceding claims
  • Aspect 22 A power electronics unit comprising the power electronic substrate of aspect 21.
  • Aspect 23 The power electronics unit of aspect 22, wherein the power electronic unit is suitable for use in low voltage applications at less than 1000 V, for use in medium voltage applications of 1 kV to 5 kV, or for use in high voltage applications at higher than 5 kV.
  • compositions, methods, and articles can alternatively comprise, consist of, or consist essentially of, any ingredients, steps, or components herein disclosed.
  • the compositions, methods, and articles can additionally, or alternatively, be formulated, conducted, or manufactured so as to be devoid, or substantially free, of any ingredients, steps, or components not necessary to the achievement of the function or objectives of the claims.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Structural Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat électronique de puissance, comprenant le dépôt direct d'une couche céramique électriquement isolante (2) sur un premier côté d'une première couche électriquement conductrice (1) à une température inférieure à 500 °C, de préférence inférieure à 100 °C, et idéalement à une température de 18 à 27 °C, la première couche électriquement conductrice (1) étant facultativement une couche électriquement conductrice plate ; éventuellement le dépôt ou la fixation d'une seconde couche électriquement conductrice (4) sur un côté de la couche céramique électriquement isolante (2) déposée qui est à l'opposé de la première couche électriquement conductrice (1) ; éventuellement la structuration de la première couche électriquement conductrice (1) en traces de circuits ; et éventuellement le montage d'un ou plusieurs composants électroniques de puissance sur la première couche électriquement conductrice (1), sur la seconde couche électriquement conductrice (4), ou à la fois sur les première et seconde couches électriquement conductrices (1), (4).
PCT/US2019/015075 2018-01-26 2019-01-25 Procédés de fabrication de substrats de puissance thermiquement conducteurs à base de céramique WO2019147886A1 (fr)

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US201862622354P 2018-01-26 2018-01-26
DE102018101750.2A DE102018101750A1 (de) 2018-01-26 2018-01-26 Verbundkeramik für eine Leiterplatte und Verfahren zu deren Herstellung
DE102018101750.2 2018-01-26
US62/622,354 2018-01-26

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DE202019005455U1 (de) 2020-09-10
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WO2019145441A1 (fr) 2019-08-01
DE102018101750A1 (de) 2019-08-01
CN111656870A (zh) 2020-09-11

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