WO2019145994A1 - Circuit film material, method for manufacturing circuit film, and display device - Google Patents

Abstract

A circuit film material (400a) is provided with a film base material (401), first and second side-wiring (402, 403), an IC chip (404), input-side center wiring (405), and output-side center wiring (406). A first non-wiring region (407) linearly extending from the input side of the film base material (401) toward the output side of the film base material (401) is provided between the first side-wiring (402), and the input-side center wiring (405), IC chip (404) and output-side center wiring (406). A second non-wiring region (408) linearly extending from the input side of the film base material (401) toward the output side of the film base material (401) is provided between the second side-wiring (403), and the input-side center wiring (405), IC chip (404), and output-side center wiring (406).

Description

Circuit film material, circuit film manufacturing method and display device

The present invention relates to a circuit film material, a method of manufacturing a circuit film using the circuit film material, and a display device.

Conventionally, as a circuit film, there is a so-called source COF (Chip On Film) (see, for example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2006-49514)). A plurality of source COFs are mounted on the liquid crystal display device. At this time, the plurality of source COFs are arranged in a line along one long side of the periphery of a TFT (thin film transistor) substrate having a rectangular shape in plan view, and have the same shape.

More specifically, each source COF includes a driver IC (integrated circuit), a source signal input wiring provided on the input side of the driver IC, and a source signal output wiring provided on the output side of the driver IC. Have. Further, each source COF also has a source signal input wiring, a driver IC, and a gate signal wiring provided on the side of the source signal output wiring.

JP 2006-49514 A

By the way, in the source COF arranged at the end of the column among the plurality of source COFs, the gate signal wiring outputs a gate signal to the so-called gate COF, but other source COFs not arranged at the end of the column Then, the gate signal wiring does not output the gate signal to the gate COF. That is, in the other source COF, unnecessary gate signal wiring is formed. For this reason, in the other source COF, as a result of the region for forming the output wiring for source signal being narrowed, the formation pitch of the output wiring for source signal becomes small.

Therefore, in the conventional source COF, there has been a problem that it becomes difficult to connect the source signal output wiring to the source wiring of the TFT substrate.

As a method of solving such a problem, there is a method of eliminating the gate signal wiring from the other source COF. However, when the gate signal wiring is removed from the other source COF and the area for forming the source signal output wiring is widened, the circuit pattern of the other source COF is the source arranged at the end of the column. It differs from the circuit pattern of COF.

As a result, it is not possible to design all of the plurality of source COFs with the same circuit pattern, resulting in a new problem that the burden on manufacturing the source COFs increases.

Then, the subject of this invention is providing the circuit film raw material which can reduce the burden concerning manufacture of a circuit film, the manufacturing method of a circuit film using this circuit film raw material, and a display apparatus.

The circuit film material according to one aspect of the present invention is
A film substrate having a first end and a second end opposite the first end;
First side wiring provided at the first end of the film substrate;
A second lateral wire provided at the second end of the film substrate;
An IC chip attached to the film substrate and located between the first side wiring portion and the second side wiring portion and having an input terminal and an output terminal;
Provided on the input side of the film base, located between the first side wiring and the second side wiring, and extending from the input side of the film base toward the input terminal of the IC chip Existing input center wiring,
Provided on the output side of the film base, located between the first side wiring and the second side wiring, extending from the output side of the film base toward the output terminal of the IC chip With the existing output side central wiring,
It extends linearly from the input side of the film base toward the output side of the film base between the first side wiring, the input side central wiring, the IC chip and the output side central wiring. First non-wiring area is provided,
It extends linearly from the input side of the film base toward the output side of the film base between the second side wiring and the input side central wiring, IC chip and output side central wiring. A second non-wired area is provided.

The method for producing a circuit film according to one aspect of the present invention is
It is a manufacturing method of the circuit film which manufactures a circuit film using the circuit film material of the above-mentioned mode,
Cutting the first non-wiring region along the extending direction of the first non-wiring region; cutting the second non-wiring region along the extending direction of the second non-wiring region; A step appropriately selected from the steps of cutting the first and second non-wiring regions along the extending direction of the first and second non-wiring regions is performed.

The display device according to one aspect of the present invention is
A substrate having a first side, a second side orthogonal to the first side, and a third side orthogonal to the first side and opposed to the second side;
A source driving circuit having a plurality of circuit films connected to the first side of the substrate;
A first gate drive circuit provided on the second side of the substrate;
The substrate is provided on the substrate so as to extend from the first side of the substrate toward the first gate drive circuit, and the gate signal output from the source drive circuit is driven to the first gate. And a first relay wire relaying to the circuit;
Each of the plurality of circuit films is
An IC chip having an input terminal and an output terminal;
An input side wiring extending from the input side of the circuit film toward the input terminal of the IC chip;
An output side wiring extending from the output side of the circuit film toward the output terminal of the IC chip;
It is disposed closer to the second side of the substrate than the input-side wiring, the IC chip, and the output-side wiring, and extends linearly from the input side of the circuit film to the output side of the circuit film The first unwired area to
It is disposed closer to the third side of the substrate than the input wiring, IC chip and output wiring, and extends linearly from the input side of the circuit film toward the output side of the circuit film. And a second non-wired area,
The above multiple circuit films are
A first circuit film closest to the second side of the substrate;
A second circuit film closest to the third side of the substrate;
A third circuit film positioned between the first circuit film and the second circuit film;
The first circuit film is
An end portion located on the second side of the substrate;
And a first side wire electrically connected to the first relay wire.

The circuit film material of the present invention has a plurality of circuit patterns different from each other by linearly extending the first and second non-wiring regions from the input side of the film base toward the output side of the film base. Because the circuit film of the present invention can be obtained, the burden on manufacturing the circuit film can be reduced.

According to the circuit film manufacturing method of the present invention, since the circuit film is manufactured using the above-described circuit film material, the burden on the manufacturing of the circuit film can be reduced.

Since the display device of the present invention can use a circuit film material, the burden on the production of the circuit film can be reduced.

It is a model top view of the liquid crystal panel carried in the liquid crystal display of a 1st embodiment of this invention. It is a model top view of 1st source COF of said 1st Embodiment. It is a model top view of 2nd source COF of the said 1st Embodiment. It is a model top view of 3rd source COF of said 1st Embodiment. It is a model top view of the tape carrier of the said 1st Embodiment. It is a schematic diagram for demonstrating the manufacturing method of said 1st, 2nd, 3rd source COF. It is another schematic diagram for demonstrating the manufacturing method of said 1st, 2nd, 3rd source COF. FIG. 14 is yet another schematic view for explaining the method of manufacturing the first, second, and third source COFs. It is a model top view of the liquid crystal panel mounted in the liquid crystal display of a 2nd embodiment of this invention. It is an enlarged view of a part of FIG. FIG. 2 is an enlarged view of another part of FIG. 1;

Hereinafter, the circuit film material, the circuit film manufacturing method and the display device of the present invention will be described in detail by the illustrated embodiments.

First Embodiment
FIG. 1 is a schematic view of a liquid crystal panel 1 mounted on a liquid crystal display device according to a first embodiment of the present invention as viewed from above.

The liquid crystal panel 1 is, for example, a 70-type liquid crystal panel, and includes a TFT (thin film transistor) substrate 11 and a color filter substrate 12 disposed to face the TFT substrate 11. The TFT substrate 11 and the color filter substrate 12 each have a rectangular shape in plan view. In addition, a liquid crystal layer is sandwiched between the TFT substrate 11 and the color filter substrate 12. Further, alignment films subjected to rubbing processing are disposed between the liquid crystal layer and the TFT substrate 11 and between the liquid crystal layer and the color filter substrate 12, respectively.

The TFT substrate 11 has a first side 11 a, a second side 11 b orthogonal to the first side 11 a, and a third side 11 c orthogonal to the first side 11 a and opposed to the second side 11 b. Although not shown, the TFT substrate 11 extends in the row direction in parallel with each other, with a plurality of TFTs arranged in a matrix, with each other in parallel with each other, with a plurality of source lines extending in the column direction. And a plurality of gate wirings. Each of the TFTs described above is electrically connected to the source wiring and the gate wiring, and controls voltage application to the pixel electrode. The terminals of the source wiring and the gate wiring are formed in the peripheral portion of the TFT substrate 11. Note that the source wiring and the gate line may be formed to cross each other at an angle of 90 °, or may be formed to cross each other at an angle other than 90 °.

Further, the source driver 2 is installed on one long side of the periphery of the TFT substrate 11. Further, on each short side of the peripheral edge of the TFT substrate 11, a plurality of gate COFs (chip on film) 23, 23, ... are provided. That is, while the source driver 2 is provided on the first side 11 a side of the TFT substrate 11, the gate COFs 23,..., 23 are on the second and third sides 11 b and 11 c side of the TFT substrate 11. It is provided. The number of gate COFs 23, 23,..., 23 is changed according to the size of the liquid crystal panel 1 and the like, and is not particularly limited. The source driver 2 is an example of a source drive circuit. The gate COF 23 provided on the second side 11 b side of the TFT substrate 11 is an example of a first gate drive circuit. The gate COF 23 provided on the third side 11c side of the substrate 11 is an example of a second gate drive circuit.

The color filter substrate 12 has a glass substrate, a color filter formed to cover the surface of the glass substrate on the TFT substrate 11 side, and a common electrode covering the color filter. The color filter is composed of, for example, a plurality of red color filters, a plurality of green color filters, and a plurality of blue color filters. The respective red color filters, the respective green color filters and the respective blue color filters correspond to red sub-pixels, green sub-pixels and blue sub-pixels. The color filter may include a plurality of at least one of a yellow color filter and a white color filter.

The source driver 2 has a printed board 21 extending along the longitudinal direction of the TFT substrate 11, one first source COF 22A, one second source COF 22B, and a plurality of third source COFs 22C. The printed board 21 has a plurality of wires (hereinafter referred to as “source signal wires”) to which a signal for driving a source wire of the TFT substrate 11 is input and a gate wire for driving the TFT substrate 11. And a plurality of wirings (hereinafter referred to as "gate signal wirings") to which a signal is input. The first, second, and third source COFs 22A, 22B, and 22C each have an input side connected to the printed board 21 and an output side connected to the first side 11a of the TFT substrate 11. The first, second and third source COFs 22A, 22B and 22C are examples of circuit films. Further, the number of first, second and third source COFs 22A, 22B and 22C is changed according to the size of the liquid crystal panel 1 and the like, and is not particularly limited. Also, the source COF means a flexible printed wiring board manufactured using a COF tape, on which the source driver 2 is mounted.

The half of the plurality of gate COFs 23, 23,..., 23 are arranged in a line along one short side of the TFT substrate 11. A signal is supplied to the gate COFs 23, 23, 23, 23 on one short side of the TFT substrate 11 via the first source COF 22A. The remaining half of the plurality of gate COFs 23, 23,..., 23 are arranged in a line along the other short side of the TFT substrate 11. A signal is supplied to the gate COFs 23, 23, 23, 23 on the other short side of the TFT substrate 11 via the second source COF 22B.

Each of the gate COFs 23 has, for example, a film base made of a polyimide resin, a gate driver IC attached to the film base, and a plurality of wirings provided on the film base. The plurality of wirings include an input wiring connected to the input side of the gate driver IC and an output wiring connected to the output side of the gate driver IC. The output side wiring outputs the signal output from the gate driver IC to the gate wiring of the TFT substrate 11. Furthermore, the plurality of gates COFs 23, 23, ... also have wiring for relaying the signal to the other gate COFs 23. In this case, the plurality of gate COFs 23, 23,..., 23 can have the same structure as each other, but are positioned at the end opposite to the source driver 2 (the lower long side of the TFT substrate 11 in FIG. 1). The gate COF 23 may not have the wiring for relaying to another gate COF 23. The gate driver IC may be attached to the TFT substrate 11.

Further, as shown in FIG. 10, on the surface of the TFT substrate 11 on the color filter substrate 12 side, the first gate signal relayed from the source driver 2 is relayed to the gate COF 23 on the second side 11 b side of the TFT substrate 11. A relay wiring 51 is provided. The first relay wiring 51 extends from the first side 11 a of the TFT substrate 11 toward the gate COF 23.

Further, on the surface of the TFT substrate 11 on the color filter substrate 12 side, as shown in FIG. 11, the gate signal output from the source driver 2 is relayed to the gate COF 23 on the third side 11 c side of the TFT substrate 11. A relay wire 52 is provided. The second relay wiring 52 extends from the side of the first side 11 a of the TFT substrate 11 toward the side of the gate COF 23 on the side of the third side 11 c of the TFT substrate 11.

Although a plurality of first and second relay wires 51 and 52 are provided on the surface of the TFT substrate 11 on the color filter substrate 12 side, only one is schematically shown in FIGS. 10 and 11. . Further, as shown in FIGS. 10 and 11, the first and second relay wires 51 and 52 may have a bending portion, for example, have no bending portion but have a bending portion. You may

FIG. 2 is a schematic view of the first source COF 22A as viewed from above.

The first source COF 22A includes a film substrate 101, a plurality of relay wires 102, 102, ..., 102, a source driver IC 104, a plurality of input wires 105, 105, ..., 105, and a plurality of output wires 106. , 106,. The relay wiring 102 is an example of the first side wiring. The input side wiring 105 is an example of the input side central wiring. The output side wiring 106 is an example of the output side central wiring.

The film substrate 101 is formed of, for example, a polyimide resin so that the top view has a rectangular shape. Further, the film substrate 101 has a first end 101 a and a second end 101 b opposite to the first end 101 a. That is, the first end 101 a of the film base 101 is located on the second side 11 b of the TFT substrate 11, while the second end 101 b of the film base 101 is on the third side 11 c of the TFT substrate 11. To position.

The plurality of relay wires 102 are provided on the first end 101 a side of the film base 101 so as to be parallel to one another, and linearly from the input side of the film base 101 toward the output side of the film base 101. It is extended. At this time, the distance between the relay wirings 102 is set, for example, to fall within the range of 27 μm to 500 μm. In addition, the end of the input side (printed board 21 side) of each relay wiring 102 is electrically connected to the gate signal wiring of the printed board 21. On the other hand, the end of the output side (the TFT substrate 11 side) of each relay wiring 102 is electrically connected to one end of the first relay wiring 51 (shown in FIG. 10) of the TFT substrate 11. The relay wire 102 may be formed to be bent at least once and extend, for example, as long as it can maintain a first non-wiring region 107 described later.

The source driver IC 104 is a semiconductor chip mounted on the film substrate 101 using COF mounting technology, and has a plurality of input terminals 109 on the input side and a plurality of output terminals 110 on the output side. It is done. The plurality of input terminals 109 and the plurality of output terminals 110 are respectively arranged in an example along the long side of the film base 101.

The plurality of input- side wires 105, 105,..., 105 are provided on the input side of the film substrate 101 so as to be located on the side of the relay wire 102. Each input side wiring 105 extends from the input side of the film base 101 toward the input terminal 109 of the source driver IC 104. In addition, an end portion on the input side (a side opposite to the source driver IC 104) of each input side wiring 105 is electrically connected to the source signal wiring of the printed circuit board 21. The end portion on the input side of the input side wiring 105 is formed, for example, at a pitch within the range of 300 μm and 500 μm. On the other hand, the end of the output side (the source driver IC 104 side) of each input wiring 105 is electrically connected to the input terminal 109 of the source driver IC 104.

The plurality of output side wirings 106, 106,..., 106 are provided on the output side of the film substrate 101 so as to be located on the side of the relay wiring 102. Each output side wiring 106 extends from the output side of the film substrate 101 to the output terminal 110 of the source driver IC 104. In addition, the end of the input side (the source driver IC 104 side) of each output side wiring 106 is electrically connected to the output terminal 110 of the source driver IC 104. On the other hand, the end of the output side (the opposite side to the source driver IC 104) of each output side wiring 106 is electrically connected to the terminal of the source wiring of the TFT substrate 11. The end portion on the output side of the output side wiring 106 is formed, for example, at a pitch within the range of 27 μm to 30 μm. In FIG. 2, the number of output side wires 106 is drawn to be the same as the number of input side wires 105, but the number is generally larger than the number of input side wires 105.

Also, the film substrate 101 has first and second non-wiring regions 107 and 108 in which the relay wiring 102, the input wiring 105 and the output wiring 106 are not provided. The width of the first non-wiring region 107 is wider than the width of the second non-wiring region 108.

The first non-wiring region 107 is located closer to the first end 101 a of the film substrate 101 than the second non-wiring region 108. In other words, the first non-wiring region 107 is provided on the opposite side of the second non-wiring region 108 with respect to the input side wiring 105, the source driver IC 104, and the output side wiring 106. Also, the first non-wiring region 107 extends from between the relay wiring 102 and the input wiring 105 to between the relay wiring 102 and the output wiring 106 via the relay wiring 102 and the source driver IC 104. It is provided. Further, the first non-wiring region 107 linearly extends from the input side of the film base 101 toward the output side of the film base 101. The width (length in the horizontal direction in FIG. 2) of the first non-wiring region 107 is set to fall within the range of, for example, 300 μm to 500 μm.

The second non-wiring region 108 is located closer to the second end 101 b of the film substrate 101 than the first non-wiring region 107. In other words, the second non-wiring region 108 is provided on the opposite side of the first non-wiring region 107 with respect to the input side wiring 105, the source driver IC 104, and the output side wiring 106. Further, the second non-wiring region 108 extends linearly from the input side of the film substrate 101 toward the output side of the film substrate 101 as in the case of the first non-wiring region 107. The width (length in the horizontal direction in FIG. 2) of the second non-wiring region 108 is narrower than the width of the first non-wiring region 107. That is, the width of the second non-wiring region 108 is set to a length within the range of 150 μm to 250, for example.

Further, on the output side of the film substrate 101, a pair of circular first alignment marks 111, 111 are provided. One of the first alignment marks 111 is located between the first non-wiring region 107 and the output-side wire 106. The other first alignment mark 111 is located between the second non-wiring region 108 and the output side wire 106. The number of first alignment marks 111 is two, but may be three or more. That is, at least two first alignment marks 111 may be provided.

Further, on the output side of the film substrate 101, a second alignment mark 112 positioned between the first non-wiring region 107 and the relay wiring 102 is also provided. Note that at least one second alignment mark 112 may be provided.

FIG. 3 is a schematic view of the second source COF 22B as viewed from above.

The second source COF 22B is different from the first source COF 22A in FIG. 2 in that the side on which the plurality of relay lines 203 are provided is opposite to the side on which the plurality of relay lines 103 in FIG. ing.

More specifically, the second source COF 22B includes a film base 201, a plurality of relay wirings 203, a source driver IC 204, a plurality of input wirings 205, and a plurality of output wirings 206. The relay wiring 203 is an example of a second side wiring. The input side wiring 205 is an example of the input side central wiring. Further, the output side wiring 206 is an example of the output side central wiring.

The film substrate 201 is formed of, for example, a polyimide resin so that the top view has a rectangular shape. Further, the film substrate 201 has a first end 201 a and a second end 201 b opposite to the first end 201 a. That is, while the first end 201 a of the film substrate 201 is located on the second side 11 b side of the TFT substrate 11, the second end 201 b of the film substrate 201 is located on the third side 11 c side of the TFT substrate 11. To position.

The plurality of relay wires 203 are provided on the second end 201 b side of the film base 201 so as to be parallel to one another, and linearly from the input side of the film base 201 toward the output side of the film base 201. It is extended. At this time, the distance between the relay wirings 203 is set, for example, within the range of 27 μm to 500 μm. In addition, the end portion on the input side (the printed circuit board 21 side) of each relay wiring 203 is electrically connected to the gate signal wiring of the printed circuit board 21. On the other hand, the end of the output side (the TFT substrate 11 side) of each relay wiring 203 is electrically connected to one end of the second relay wiring 52 (shown in FIG. 11) of the TFT substrate 11. The relay wiring 203 may be formed to be bent at least once and extend, for example, as long as the second non-wiring region 208 described later can be maintained.

The source driver IC 204 is a semiconductor chip mounted on the film substrate 201 using COF mounting technology, and has a plurality of input terminals 209 on the input side and a plurality of output terminals 210 on the output side. It is done. The plurality of input terminals 209 and the plurality of output terminals 210 are respectively arranged in an example along the long side of the film substrate 201.

The plurality of input- side wires 205, 205,..., 205 are provided on the input side of the film substrate 201 so as to be located on the side of the relay wire 203. Each input-side wiring 205 extends from the input side of the film base 201 toward the input terminal 209 of the source driver IC 204. Further, an end portion on the input side (a side opposite to the source driver IC 204) of each input side wiring 205 is electrically connected to the source signal wiring of the printed circuit board 21. The end portion on the input side of the input side wiring 205 is formed, for example, at a pitch within the range of 300 μm to 500 μm. On the other hand, the end of the output side (the source driver IC 204 side) of each input side wiring 205 is electrically connected to the input terminal 209 of the source driver IC 204.

The plurality of output side wirings 206, 206,..., 206 are provided on the output side of the film substrate 201 so as to be located on the side of the relay wiring 203. Each output wiring 206 extends from the output side of the film substrate 201 to the output terminal 210 of the source driver IC 204. In addition, the end of the input side (the source driver IC 204 side) of each output wiring 206 is electrically connected to the output terminal 210 of the source driver IC 204. On the other hand, the end of the output side (the opposite side to the source driver IC 204) of each output side wiring 206 is electrically connected to the terminal of the source wiring of the TFT substrate 11. The end portion on the output side of the output side wiring 206 is formed, for example, at a pitch within the range of 27 μm to 30 μm. In FIG. 3, the number of output side wirings 206 is drawn to be the same as the number of input side wirings 205, but in general, it is larger than the number of input side wirings 205.

Also, the film base 201 has first and second non-wiring regions 207 and 208 in which the relay wiring 203, the input wiring 205 and the output wiring 206 are not provided. The width of the first non-wiring region 207 is narrower than the width of the second non-wiring region 208.

The first non-wiring region 207 is located closer to the first end 201 a of the film substrate 201 than the second non-wiring region 208. In other words, the first non-wiring region 207 is provided on the side opposite to the second non-wiring region 208 with respect to the input side wiring 205, the source driver IC 204 and the output side wiring 206. Further, the first non-wiring region 207 linearly extends from the input side of the film base 201 toward the output side of the film base 201. The width (length in the horizontal direction in FIG. 3) of the first non-wiring region 207 falls within the range of, for example, 150 μm to 250 μm.

The second non-wiring region 208 is located closer to the second end portion 201 b of the film base 201 than the first non-wiring region 207. In other words, the second non-wiring region 208 is provided on the opposite side of the first non-wiring region 207 with respect to the input side wiring 205, the source driver IC 204 and the output side wiring 206. In addition, the second non-wiring region 208 extends from between the relay wiring 203 and the input-side wiring 205 to between the relay wiring 203 and the output-side wiring 206 via the relay wiring 203 and the source driver IC 204. It is provided. Further, the second non-wiring region 208 extends linearly from the input side of the film substrate 201 toward the output side of the film substrate 201 as in the case of the first non-wiring region 207. The width (length in the horizontal direction in FIG. 3) of the second non-wiring region 208 is wider than the width of the first non-wiring region 207. That is, the width of the second non-wiring region 208 is set to fall within the range of, for example, 300 μm to 500 μm.

In addition, on the output side of the film substrate 201, a pair of circular first alignment marks 211, 211 are provided. One first alignment mark 211 is located between the first non-wiring region 207 and the output side wiring 206. Further, the other first alignment mark 211 is located between the second non-wiring region 208 and the output side wiring 206. The number of first alignment marks 211 is two, but may be three or more. That is, at least two first alignment marks 211 may be provided.

In addition, on the output side of the film substrate 101, a third alignment mark 213 positioned between the second non-wiring region 208 and the relay wiring 203 is also provided. Note that at least one third alignment mark 213 may be provided.

FIG. 4 is a schematic view of the third source COF 22C as viewed from above.

The third source COF 22C is different from the first and second source COFs 22A and 22B in FIGS. 2 and 3 in that the third source COF 22C does not have the relay wirings 102 and 203 in FIGS.

More specifically, the third source COF 22C has a film base 301, a source driver IC 304, a plurality of input side wirings 305, and a plurality of output side wirings 306. The input side wiring 305 is an example of the input side central wiring. Also, the output side wiring 306 is an example of the output side central wiring.

The film base 301 is formed of, for example, a polyimide resin so that the top view has a rectangular shape. Further, the film substrate 301 has a first end 301 a and a second end 301 b located on the opposite side of the first end 301 a. That is, the first end 301 a of the film base 301 is located on the second side 11 b of the TFT substrate 11, while the second end 301 b of the film base 301 is on the third side 11 c of the TFT substrate 11. To position.

The source driver IC 304 is a semiconductor chip mounted on the film base 301 using COF mounting technology, and has a plurality of input terminals 309 on the input side and a plurality of output terminals 310 on the output side. It is done. The plurality of input terminals 309 and the plurality of output terminals 310 are respectively arranged in an example along the long side of the film base 301.

A plurality of input- side wires 305, 305, ..., 305 are provided on the input side of the film substrate 301. Each input-side wiring 305 extends from the input side of the film base 301 toward the input terminal 309 of the source driver IC 304. Further, an end portion on the input side (a side opposite to the source driver IC 304) of each input side wiring 305 is electrically connected to the source signal wiring of the printed circuit board 21. The end portion on the input side of the input side wiring 305 is formed, for example, at a pitch within the range of 300 μm to 500 μm. On the other hand, the end of the output side (the source driver IC 304 side) of each input wiring 305 is electrically connected to the input terminal 309 of the source driver IC 304.

The plurality of output side wirings 306, 306,..., 306 are provided on the output side of the film substrate 301. Each output side wire 306 extends from the output side of the film base 301 to the output terminal 310 of the source driver IC 304. Further, the end of the input side (the source driver IC 304 side) of each output side wiring 306 is electrically connected to the output terminal 310 of the source driver IC 304. On the other hand, the end of the output side (the opposite side to the source driver IC 304) of each output side wiring 306 is electrically connected to the terminal of the source wiring of the TFT substrate 11. The end portion on the output side of the output side wiring 306 is formed, for example, at a pitch within the range of 27 μm to 30 μm. In FIG. 4, the number of output-side wirings 306 is drawn to be the same as the number of input-side wirings 305, but in general, the number is larger than the number of input-side wirings 305.

Also, the film substrate 301 has first and second non-wiring regions 307 and 308 in which the input wiring 305 and the output wiring 306 are not provided.

The first non-wiring region 307 is located closer to the first end portion 301 a of the film base 301 than the second non-wiring region 308. In other words, the first non-wiring region 307 is provided on the opposite side of the second non-wiring region 308 with respect to the input side wiring 305, the source driver IC 304 and the output side wiring 306. Further, the first non-wiring region 307 linearly extends from the input side of the film base 301 toward the output side of the film base 301. The width (length in the horizontal direction in FIG. 4) of the first non-wiring region 307 falls within the range of, for example, 150 μm to 250 μm.

The second non-wiring region 308 is positioned closer to the second end portion 301 b of the film base 301 than the first non-wiring region 307. In other words, the second non-wiring region 308 is provided on the opposite side of the first non-wiring region 307 with respect to the input side wiring 305, the source driver IC 304 and the output side wiring 306. Further, the second non-wiring region 308 linearly extends from the input side of the film substrate 301 toward the output side of the film substrate 301 as in the case of the first non-wiring region 307. The width (length in the horizontal direction in FIG. 4) of the second non-wiring region 308 is the same as or substantially the same as the width of the first non-wiring region 307. That is, the width of the second non-wiring region 308 falls within the range of, for example, 150 μm to 250 μm.

Further, on the output side of the film substrate 301, a pair of circular first alignment marks 311, 311 are provided. One first alignment mark 311 is located between the first non-wiring region 307 and the output-side wire 306. Further, the other first alignment mark 311 is located between the second non-wiring region 308 and the output side wire 306. Although the number of first alignment marks 311 is two, it may be three or more. That is, at least two first alignment marks 311 may be provided.

FIG. 5 is a schematic view of a tape carrier 400 for obtaining the first, second and third source COFs 22A, 22B and 22C as viewed from above.

The tape carrier 400 is formed in a long shape. In the tape carrier 400, a plurality of (only one is shown in FIG. 5) circuit pattern portions 400a, 400a,..., 400a are arranged in a line along the longitudinal direction. The circuit pattern portions 400a, 400a,..., 400a have the same shape. That is, the circuit pattern portions 400a, 400a,..., 400a are portions formed to have the same circuit pattern, respectively.

Each circuit pattern portion 400a has a film base 401, a plurality of first relay wires 402, a plurality of second relay wires 403, a source driver IC 404, a plurality of input side central wires 405, and a plurality of output side central wires 406. The shape in plan view is rectangular. The first relay wiring 402 is an example of a first side wiring. The second relay wiring 403 is an example of a second side wiring. Further, the input side central wiring 405 is an example of the input side central wiring. Further, the output side central wiring 406 is an example of the output side central wiring.

The film substrate 401 is made of, for example, a polyimide resin. The film substrate 401 has a first end 401 a and a second end 401 b opposite to the first end 401 a.

The plurality of first relay wirings 402 are provided on the first end 401 a side of the film base 401 so as to be parallel to one another, and one long side of the film base 401 extends from the other long side of the film base 401. It extends in a straight line. At this time, the distance between the first relay wirings 402 is set, for example, in the range of 27 μm to 500 μm. The first relay wiring 402 may be formed to be bent at least once and extend, for example, as long as it can maintain a first non-wiring region 407 described later.

The plurality of second relay wirings 403 are provided on the second end 401 b side of the film base 401 so as to be parallel to each other, and one long side of the film base 401 from the other long side of the film base 401 It extends in a straight line. At this time, the distance between the second relay wirings 403 is set, for example, in the range of 27 μm to 500 μm. The second relay wiring 403 may be formed to be bent at least once and extend, for example, as long as it can maintain a second non-wiring region 408 described later.

The source driver IC 404 is a semiconductor chip mounted on the film substrate 401 using COF mounting technology, and has a plurality of input terminals 409 on the input side and a plurality of output terminals 410 on the output side. It is done. The plurality of input terminals 409 and the plurality of output terminals 410 are respectively arranged in an example along the long side of the film base 401.

A plurality of input side central wirings 405, 405,..., 405 are provided on the input side of the film base 401 so as to be located between the first relay wiring 402 and the second relay wiring 403. Each input-side central wire 405 extends from one long side of the film substrate 401 to the input terminal 409 of the source driver IC 404. Further, the end portion on the input side (the opposite side to the source driver IC 404) of each input-side central wiring 405 is formed at a pitch within the range of, for example, 300 μm to 500 μm. On the other hand, the end of the output side (the source driver IC 404 side) of each input side central wiring 405 is electrically connected to the input terminal 409 of the source driver IC 404.

The plurality of output side center wirings 406, 406,..., 406 are provided on the output side of the film base 401 so as to be located between the first relay wiring 402 and the second relay wiring 403. Each output side central wiring 406 extends from the other long side of the film base 401 to the output terminal 410 of the source driver IC 404. In addition, the end of the input side (the source driver IC 404 side) of each output side central wiring 406 is electrically connected to the output terminal 410 of the source driver IC 404. On the other hand, the end portion on the output side (the opposite side to the source driver IC 404) of each output side central wiring 406 is formed at a pitch within the range of, for example, 27 μm to 30 μm. In FIG. 5, the number of output-side central wirings 406 is drawn to be the same as the number of input-side central wirings 405, but in general, the number is larger than the number of input-side central wirings 405.

Also, the film substrate 401 has first and second non-wiring regions 407 and 408 in which the first relay wiring 402, the second relay wiring 403, the input-side central wiring 405, and the output-side central wiring 406 are not provided.

The first non-wired area 407 is positioned closer to the first end 401 a of the film base 401 than the second non-wired area 408. In other words, the first non-wiring region 407 is provided on the opposite side of the second non-wiring region 408 with respect to the input-side central wiring 405, the source driver IC 404 and the output-side central wiring 406. Further, the first non-wiring region 407 outputs the first relay wiring 402 and the output via the first relay wiring 402 and the source driver IC 404 from between the first relay wiring 402 and the input-side central wiring 405. It is provided up to the side central wiring 406. Further, the first non-wiring region 407 linearly extends from one long side of the film base 401 to the other long side of the film base 401. The width (length in the horizontal direction in FIG. 5) of the first non-wiring region 407 is set to fall within the range of, for example, 300 μm to 500 μm.

The second non-wiring region 408 is located closer to the second end 401 b of the film base 401 than the first non-wiring region 407. In other words, the second non-wiring region 408 is provided on the opposite side of the first non-wiring region 407 with respect to the input-side central wiring 405, the source driver IC 404, and the output-side central wiring 406. Further, the second non-wiring region 408 outputs the second relay wiring 403 and the output via the second relay wiring 403 and the source driver IC 404 from between the second relay wiring 403 and the input-side central wiring 405. It is provided up to the side central wiring 406. Further, the second non-wiring region 408 extends linearly from one long side of the film substrate 401 to the other long side of the film substrate 401 as in the case of the first non-wiring region 407. The width (length in the horizontal direction in FIG. 5) of the second non-wiring region 408 is set, for example, to fall within the range of 300 μm to 500.

In addition, on the output side of the film substrate 401, a pair of circular first alignment marks 411 and 411 are provided. One first alignment mark 411 is located between the first non-wiring area 407 and the output-side central wiring 406. Further, the other first alignment mark 411 is located between the second non-wiring region 408 and the output-side central wiring 406.

In addition, on the output side of the film base 401, a second alignment mark 412 located between the first non-wiring region 407 and the first relay wiring 402, and a second non-wiring region 408 and a second relay wiring 403. And a third alignment mark 413 located between them.

Here, the long sides of the first, second, and third alignment marks 411, 412, and 413 of the film substrate 401 are sides to be disposed on the TFT substrate 11 side. Further, the long side of the film base 401 opposite to the first, second and third alignment marks 411, 412 and 413 is one side to be disposed on the printed circuit board 21 side.

According to the circuit pattern portion 400 a configured as described above, the first non-wiring region 407 linearly extends from one long side of the film base 401 to the other long side of the film base 401. The first non-wiring region 407 can be easily cut, for example, by punching along the extending direction of the region 407.

Further, since the second non-wiring region 408 also linearly extends in the same manner as the first non-wiring region 407, the second non-wiring region 407 extends in the extending direction of the second non-wiring region 408 in the same manner as the first non-wiring region 407. The non-wiring region 408 can be easily cut, for example, by punching.

By cutting the first non-wiring region 407 along the extending direction of the first non-wiring region 407, the portion where the plurality of first relay wirings 402 are provided is separated from the circuit pattern portion 400a, as shown in FIG. Of the second source COF 22B.

Further, by cutting the second non-wiring region 408 along the extending direction of the second non-wiring region 408, the portion provided with the plurality of second relay wirings 403 is separated from the circuit pattern portion 400a, The first source COF 22A of FIG. 2 can be obtained.

Moreover, the part in which several 1st relay wiring 402 is provided by cut | disconnecting 1st, 2nd non-wiring area 407, 408 along the extension direction of 1st, 2nd non-wiring area 407, 408 The third source COF 22C shown in FIG. 4 can be obtained by separating the portion where the plurality of second relay wirings 403 are provided from the circuit pattern portion 400a.

Thus, if one of the first and second non-wiring regions 407 and 408 is cut or both of the first and second non-wiring regions 407 and 408 are cut, the first, second, and third Since the source COFs 22A, 22B and 22C are obtained, the circuit pattern portion corresponding to the first source COF 22A, the circuit pattern portion corresponding to the second source COF 22B, and the circuit pattern portion corresponding to the third source COF 22C are separately provided. It is not necessary to provide it. Therefore, the burden on manufacturing the first, second and third source COFs 22A, 22B and 22C can be reduced.

In addition, the first source COF 22A has first alignment marks 111 and 111 located between the first and second non-wiring regions 107 and 108 and the output side wiring 106. Thus, the output side of the first source COF 22A can be easily and accurately connected to the peripheral portion of the TFT substrate 11.

Further, like the first source COF 22A, the second and third source COFs 22B and 22C also have the first alignment marks 211 and 311, so the output of the second and third source COFs 22B and 22C at the peripheral portion of the TFT substrate 11 The side can be connected easily and accurately.

Also, the first alignment marks 111, 211, 311 correspond to the first alignment marks 411. The first alignment mark 411 is provided between the first and second non-wiring regions 407 and 408 and the output-side central wiring 406 and is not provided in the first and second non-wiring regions 407 and 408. As a result, the first alignment mark 411 can be reliably left even if either of the first and second non-wiring regions 407 and 408 is cut. Therefore, the first, second, and third source COFs 22A, 22B, 22C obtained by cutting at least one of the first, second non-wiring regions 407, 408 reliably have the first alignment marks 111, 211, 311. be able to.

Further, similarly to the first alignment mark 411, the second and third alignment marks 412 and 413 are also provided between the first and second non-wiring regions 407 and 408 and the first and second relay wirings 402 and 403. And not provided in the first and second non-wiring regions 407 and 408. Thereby, when one of the first and second non-wiring regions 407 and 408 is cut, the second alignment mark 412 or the third alignment mark 413 can be surely left. Therefore, the first and second source COFs 22A and 22B obtained by cutting one of the first and second non-wiring regions 407 and 408 can surely have the second and third alignment marks 112 and 213, respectively.

Further, when the first non-wiring region 407 is cut, the second alignment mark 412 disappears from the side of the first alignment mark 411 provided in the vicinity of the first non-wiring region 407. On the other hand, when the first non-wiring region 407 is not cut, the second alignment mark 412 does not disappear from the side of the first alignment mark 411 provided in the vicinity of the first non-wiring region 407. Therefore, based on the presence or absence of the second alignment mark 412, it can be easily determined whether the cutting of the first non-wiring region 407 has been performed.

In addition, when the second non-wiring region 408 is cut, the third alignment mark 413 disappears from the side of the first alignment mark 411 provided in the vicinity of the second non-wiring region 408. On the other hand, when the first non-wiring region 407 is not cut, the third alignment mark 413 does not disappear from the side of the first alignment mark 411 provided in the vicinity of the second non-wiring region 408. Therefore, based on the presence or absence of the third alignment mark 413, it can be easily determined whether or not the second non-wiring region 408 has been cut.

Hereinafter, a method of manufacturing the first, second, and third source COFs 22A, 22B, and 22C will be described with reference to FIGS.

First, for example, a wiring pattern and an alignment mark pattern are formed using a metal material on a polyimide-based insulating material, to obtain a tape carrier 400 of FIG.

Next, when it is desired to obtain the first source COF 22A, as shown in FIG. 6, the cutting along the first cutting line C1 is performed by, for example, punching. The first cutting line C1 is a cutting line passing through the second non-wiring region 408 inside the circuit pattern portion 400a. When it is desired to obtain the second source COF 22B instead of the first source COF 22A, as shown in FIG. 7, the cutting along the second cutting line C2 is performed, for example, by punching. The second cutting line C2 is a cutting line passing through the first non-wiring region 407 inside the circuit pattern portion 400a. When it is desired to obtain the third source COF 22C instead of the first and second source COFs 22A and 22B, as shown in FIG. 8, the cutting along the third cutting line C3 is performed by punching, for example. The third cutting line C3 is a cutting line passing through both the first non-wiring region 407 and the second non-wiring region 408 inside the circuit pattern portion 400a.

That is, after the tape carrier 400 is prepared, a cutting process employing the first cutting line C1, a cutting process employing the second cutting line C2, and a third cutting line C3 are employed according to the target COF. It selects suitably from among with a cutting process.

As described above, since the tape carrier 400 in which a plurality of circuit pattern portions 400a are arranged along the longitudinal direction is used, the first, second, and third source COFs 22A, 22B, 22C can be easily made only by selection of the cutting process. It can be manufactured. That is, the burden on manufacturing the first, second and third source COFs 22A, 22B and 22C can be reduced.

6 to 8, in order to make the first, second and third cutting lines C1, C2 and C3 easy to understand, the first and second non-wiring regions at the first cutting lines C1, C2 and C3 are shown. The portions not overlapping with 407 and 408 are illustrated apart from the periphery of the circuit pattern portion 400a.

Further, the first source COF 22A should be installed near the upper left corner of the TFT substrate 11 in FIG. Assuming that the second and third source COFs 22B and 22C are to be installed near the corner, the second and third source COFs 22B and 22C do not have the second alignment marks 112. , 22C can be easily noticed.

In addition, the second source COF 22B should be installed in the vicinity of the upper right corner of the TFT substrate 11 in FIG. If it is attempted to place the first and third source COFs 22A and 22C in the vicinity of the corner, the first and third source COFs 22A and 22C do not have the third alignment mark 213, so the second and third source COFs 22B , 22C can be easily noticed.

In addition, the third source COF 22 C is located on the upper edge of the TFT substrate 11 in FIG. 1 excluding the vicinity of the upper right corner of the TFT substrate 11 in FIG. 1 and the vicinity of the upper left corner of the TFT substrate 11 in FIG. Should be installed. Assuming that the first and second source COFs 22A and 22B are to be installed at the peripheral portion, the first and second source COFs 22A and 22B have the second and third alignment marks 112 and 213, so It is easy to notice installation errors of the source COFs 22A and 22B.

In the first embodiment, the planar view shape of the circuit pattern portion 400a is a rectangular shape, but may be, for example, a square shape or a T shape.

In the first embodiment, the first and second non-wiring regions 407 and 408 are formed to be orthogonal to both long sides of the film base 407, but both long sides of the film base 407 and 90 ° It may be formed to intersect at other angles.

In the first embodiment, the first, second and third alignment marks 411, 412 and 413 are formed in a circular shape, but may be formed in another shape (for example, a cross shape).

In the first embodiment, the first, second and third alignment marks 411, 412 and 413 have the same shape, but may have different shapes.

That is, the shapes of the first and second alignment marks 111 and 112 of the first source COF 22A, the first and third alignment marks 211 and 213 of the second source COF 22B, and the first alignment mark 311 of the third source COF 22C are also It is not limited to the above-mentioned embodiment, but may be changed suitably.

In the first embodiment, the first, second and third source COFs 22A, 22B and 22C are used, but a flexible printed wiring board manufactured using TAB (tape automated bonding) tape is used. May be

The liquid crystal display device according to the first embodiment may be any of a transmissive type, a reflective type, and a reflective / transmissive type.

In the first embodiment, the circuit film obtained by the circuit film material according to the embodiment of the present invention is used in the liquid crystal display device, but may be used, for example, in an organic EL (Electro Luminescence) display device.

Second Embodiment
FIG. 9 is a schematic view of a liquid crystal panel 1001 mounted on a liquid crystal display device according to a second embodiment of the present invention as viewed from above. In FIG. 9, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG.

The liquid crystal panel 1001 differs from the liquid crystal panel 1 of FIG. 1 in that the gate COF 23 is not disposed on the right side of the TFT substrate 1011 in FIG. 9 and that the source driver 1002 does not have the second source COF 22B. There is.

Further, the TFT substrate 1011 has a first side 1011a, a second side 1011b orthogonal to the first side 1011a, and a second side 1011a orthogonal to the first side 1011a, similarly to the TFT substrate 11 of FIG. And a third side 1011 c opposite to 1011 b.

Even with the liquid crystal panel 1001 having the above configuration, by using the tape carrier 400 of FIG. 5, the burden on manufacturing the first and third source COFs 22A and 22C can be reduced.

Although the first and second specific embodiments of the present invention have been described, the present invention is not limited to the first and second embodiments, and various modifications may be made within the scope of the present invention. Can. For example, one in which part of the contents described in the first and second embodiments is deleted or replaced may be set as an embodiment of the present invention.

The following is the summary of the above disclosure.

The circuit film material 400a according to one aspect of the present invention is
A film base 401 having a first end 401a and a second end 401b opposite to the first end 401a;
A first side wiring 402 provided at the first end 401 a of the film substrate 401;
A second side wire 403 provided at the second end 401 b of the film substrate 401;
An IC chip 404 attached to the film base 401 and positioned between the first side wiring 402 and the second side wiring 403 and having an input terminal 409 and an output terminal 410;
The input of the IC chip 404 is provided on the input side of the film base 401 and located between the first side wiring 402 and the second side wiring 403 from the input side of the film base 401. An input side central wire 405 extending toward the terminal 409;
The output side of the film base 401 is located between the first side wiring 402 and the second side wiring 403, and the output side of the IC chip 404 from the output side of the film base 401 An output side central wire 406 extending toward the terminal 410;
From the input side of the film base 401 to the output side of the film base 401 between the first side wiring 402, the input side central wiring 405, the IC chip 404 and the output side central wiring 406 A first unwired region 407 extending in a straight line,
From the input side of the film base 401 to the output side of the film base 401 between the second side wiring 403 and the input side central wiring 405, the IC chip 404 and the output side central wiring 406 A second non-wiring region 408 extending in a straight line is provided.

According to the above configuration, since the first non-wiring region 407 linearly extends from the input side of the film base 401 toward the output side of the film base 401, the extending direction of the first non-wiring region 407 The first non-wiring region 407 can be easily cut along, for example, by punching.

Further, similarly to the first non-wiring region 407, since the second non-wiring region 408 also linearly extends, for example, the second non-wiring region 408 is punched along the extending direction of the second non-wiring region 408. It can be easily cut by processing.

When the first non-wiring area 407 is cut along the extending direction of the first non-wiring area 407, the first side wiring 402 is not provided, but the second side wiring 403, the IC chip 404, the input side A circuit film 22B having a central wire 405 and an output side central wire 406 is obtained.

Further, when the second non-wiring region 408 is cut along the extending direction of the second non-wiring region 408, although the second side wiring 403 is not provided, the first side wiring 402, the IC chip 404, A circuit film 22A having an input side central wire 405 and an output side central wire 406 is obtained.

When the first and second non-wiring regions 407 and 408 are cut along the extending direction of the first and second non-wiring regions 407 and 408, the first and second side wirings 402 and 403 are provided. Although not required, a circuit film 22B having an IC chip 404, an input side central wiring 405 and an output side central wiring 406 is obtained.

As described above, when one of the first and second non-wiring regions 407 and 408 is cut, or both of the first and second non-wiring regions 407 and 408 are cut, a plurality of circuit patterns having different circuit patterns from one another can be obtained. Because the circuit films 22A, 22B, and 22C can be obtained, the burden on manufacturing the circuit films 22A, 22B, and 22C can be reduced.

The circuit film material 400a of one embodiment is
A first alignment mark 411 is provided between the first and second non-wiring regions 407 and 408 and the output-side central wiring 406.

According to the above embodiment, since the first alignment mark 411 is provided between the first and second non-wiring regions 407 and 408 and the output-side central wiring 406, for example, the wiring on the TFT substrate 11 And the output side central wiring 406 can be easily and accurately connected.

Further, since the first alignment mark 411 is provided between the first and second non-wiring regions 407 and 408 and the output-side central wiring 406, the first and second non-wiring regions 407 and 408 are cut. Even in this case, the first alignment mark 411 can be reliably left on the side of the output side central wiring 406.

The circuit film material 400a of one embodiment is
A second alignment mark 412 is provided between the first non-wiring region 407 and the first side wiring 402.

According to the above embodiment, since the second alignment mark 412 is provided between the first non-wiring region 407 and the first side wiring 402, even if the second non-wiring region 408 is cut, The second alignment mark 412 can be reliably left on the side of the first side wire 402.

In addition, since the second alignment mark 412 is provided between the first non-wiring region 407 and the first side wiring 402, when the first non-wiring region 407 is cut, the first alignment is performed. While the second alignment mark 412 disappears from the side of the mark 411, the second alignment mark 412 does not disappear from the side of the first alignment mark 411 if the first non-wiring region 407 is not cut. Therefore, based on the presence or absence of the second alignment mark 412, it can be easily determined whether or not the first non-wiring region 407 has been cut.

The circuit film material 400a of one embodiment is
A third alignment mark 413 is provided between the second non-wiring region 408 and the second side wiring 403.

According to the above embodiment, since the third alignment mark 413 is provided between the second non-wiring region 408 and the second side wiring 403, even if the first non-wiring region 407 is cut, The third alignment mark 413 can be reliably left on the side of the second side wire 403.

In addition, since the third alignment mark 413 is provided between the second non-wiring region 408 and the second side wiring 403, when the second non-wiring region 408 is cut, the first alignment is performed. While the third alignment mark 413 disappears from the side of the mark 411, the third alignment mark 413 does not disappear from the side of the first alignment mark 411 unless the second non-wiring region 408 is cut. Therefore, based on the presence or absence of the third alignment mark 413, it can be easily determined whether or not the second non-wiring region 408 has been cut.

The method for producing a circuit film according to one aspect of the present invention is
It is a manufacturing method of a circuit film which manufactures circuit film 22A, 22B, 22C using circuit film material 400a of the above-mentioned mode or embodiment,
Cutting the first non-wiring region 407 along the extending direction of the first non-wiring region 407; and cutting the second non-wiring region 408 along the extending direction of the second non-wiring region 408 And the step of cutting the first and second non-wiring regions 407 and 408 along the extending direction of the first and second non-wiring regions 407 and 408.

According to the above configuration, since the circuit films 22A, 22B and 22C are manufactured using the circuit film material 400a, the burden on manufacturing the circuit films 22A, 22B and 22C can be reduced.

The circuit film according to one aspect of the present invention is
The first side 11a, 1011a, the second side 11b, 1011b orthogonal to the first side 11a, 1011a, and the first side 11a, 1011a, and the second side 11b, 1011b A substrate 11, 1011 having three sides 11c, 1011c,
A source drive circuit 2 having a plurality of circuit films connected to the first sides 11a and 1011a of the substrates 11 and 1011;
A first gate drive circuit 23 provided on the side of the second side 11b or 1011b of the substrate 11 or 1011;
The substrate 11, 1011 is provided on the substrate 11, 1011 so as to extend from the side of the first side 11a, 1011a of the substrate 11, 1011 toward the side of the first gate drive circuit 23, and from the source drive circuit 2 And a first relay wire 51 for relaying the output gate signal to the first gate drive circuit 23;
Each of the plurality of circuit films 22A, 22B, 22C is
IC chips 104, 204, 304 having input terminals 109, 209, 309 and output terminals 110, 210, 310;
Input side wires 105, 205, 305 extending from the input side of the circuit film 22A, 22B, 22C to the input terminals 109, 209, 309 of the IC chip 104, 204, 304;
An output side wiring 106 extending from the output side of the circuit film 22A, 22B, 22C to the output terminal 110, 210, 310 of the IC chip 104, 204, 304;
The circuit film 22A is disposed closer to the second sides 11b and 1011b of the substrate 11 and 1011 than the input wires 105, 205 and 305, the IC chips 104, 204 and 304, and the output wires 106. , 22B, 22C, and first linearly extending non-wiring areas 107, 207, 307 extending linearly from the input side to the output side of the circuit films 22A, 22B, 22C;
The circuit film 22A is disposed closer to the third sides 11c and 1011c of the substrates 11 and 1011 than the input wires 105, 205 and 305, the IC chips 104, 204 and 304, and the output wires 106. , 22B, 22C and second non-wiring regions 108, 208, 308 linearly extending from the input side to the output side of the circuit film 22A, 22B, 22C,
The plurality of circuit films 22A, 22B, 22C are
A first circuit film 22A closest to the second sides 11b and 1011b of the substrates 11 and 1011;
A second circuit film 22B closest to the third sides 11c and 1011c of the substrates 11 and 1011;
A third circuit film 22C positioned between the first circuit film 22A and the second circuit film 22B;
The first circuit film 22A is provided at an end of the substrate 11, 1011 located on the second side 11b, 1011b side, and is also connected to the first relay wiring 51 on the first side. It is provided with the wiring 102.

According to the above configuration, the first, second and third circuit films 22A, 22B and 22C can be manufactured using the circuit film according to one aspect of the present invention or the circuit film of one embodiment. it can. As a result, the burden on manufacturing the display device can be reduced.

In the display device of one embodiment,
Each of the first, second and third circuit films 22A, 22B and 22C is a first alignment provided between the first and second non-wiring regions 108, 208 and 308 and the output wiring 106. Marks 111, 211 and 311 are provided.

In the display device of one embodiment,
The first circuit film 22 </ b> A includes a second alignment mark 112 provided between the first non-wiring region 107 and the first side wiring 102.

The display device of an embodiment
A second gate drive circuit 23 provided on the third side 11c side of the substrate 11;
The gate signal provided from the source drive circuit 2 is provided on the substrate 11 so as to extend from the first side 11a side of the substrate 11 toward the second gate drive circuit 23 side. A second relay wire 52 relaying to the second gate drive circuit 23;
The second circuit film 22B is provided at the end of the substrate 11 located on the third side 11c side, and the second side wiring 203 electrically connected to the second relay wiring 52 is used. Prepare.

In the display device of one embodiment,
The second circuit film 22B includes a third alignment mark 213 provided between the second non-wiring region 208 and the second side wiring 203.

In the display device of one embodiment,
The width of the first non-wiring region 107 of the first circuit film 22A is wider than the width of the second non-wiring region 108 of the first circuit film 22A.

In the display device of one embodiment,
The width of the first non-wiring region 207 of the second circuit film 22B is narrower than the width of the second non-wiring region 208 of the second circuit film 22B.

1,1001 liquid crystal panel 2,1002 source driver 11,1011 TFT substrate 12 color filter substrate 21 printed substrate 22A first source COF
22B Second Source COF
22C Third Source COF
23 gate COF
51 1st relay wiring 52 2nd relay wiring 101a, 201a, 301a, 401a 1st end 101b, 201b, 301b, 401b 2nd end 101, 201, 301, 401 film base material 102, 203 relay wiring 104, 204 , 304, 404 Source Driver IC
105, 205, 305 Input side wiring 106, 206, 306 Output side wiring 107, 207, 307, 407 1st non-wiring area 108, 208, 308, 408 2nd non-wiring area 111, 211, 311, 411 1st alignment Marks 112 and 412 Second alignment mark 213 and 413 Third alignment mark 400a Circuit pattern portion 402 First relay wiring 403 Second relay wiring 405 Input side central wiring 406 Output side central wiring

Claims (12)

1. A film substrate having a first end and a second end opposite the first end;
   First side wiring provided at the first end of the film substrate;
   A second lateral wire provided at the second end of the film substrate;
   An IC chip attached to the film substrate and located between the first side wiring portion and the second side wiring portion and having an input terminal and an output terminal;
   Provided on the input side of the film base, located between the first side wiring and the second side wiring, and extending from the input side of the film base toward the input terminal of the IC chip Existing input center wiring,
   Provided on the output side of the film base, located between the first side wiring and the second side wiring, extending from the output side of the film base toward the output terminal of the IC chip With the existing output side central wiring,
   It extends linearly from the input side of the film base toward the output side of the film base between the first side wiring, the input side central wiring, the IC chip and the output side central wiring. First non-wiring area is provided,
   It extends linearly from the input side of the film base toward the output side of the film base between the second side wiring and the input side central wiring, IC chip and output side central wiring. A second non-wiring region is provided.
2. In the circuit film material according to claim 1,
   A circuit film material characterized in that a first alignment mark is provided between the first and second non-wiring regions and the output-side central wiring.
3. In the circuit film material according to claim 2,
   A circuit film material characterized in that a second alignment mark is provided between the first non-wiring region and the first side wiring.
4. In the circuit film material according to claim 2 or 3,
   A circuit film material characterized in that a third alignment mark is provided between the second non-wiring region and the second side wiring.
5. It is a manufacturing method of the circuit film which manufactures a circuit film using the circuit film raw material as described in any one of Claim 1 to 4, Comprising:
   Cutting the first non-wiring region along the extending direction of the first non-wiring region; cutting the second non-wiring region along the extending direction of the second non-wiring region; A method of manufacturing a circuit film, comprising performing a step appropriately selected from the steps of cutting the first and second non-wiring regions along the extending direction of the first and second non-wiring regions.
6. A substrate having a first side, a second side orthogonal to the first side, and a third side orthogonal to the first side and opposed to the second side;
   A source driving circuit having a plurality of circuit films connected to the first side of the substrate;
   A first gate drive circuit provided on the second side of the substrate;
   The substrate is provided on the substrate so as to extend from the first side of the substrate toward the first gate drive circuit, and the gate signal output from the source drive circuit is driven to the first gate. And a first relay wire relaying to the circuit;
   Each of the plurality of circuit films is
   An IC chip having an input terminal and an output terminal;
   An input side wiring extending from the input side of the circuit film toward the input terminal of the IC chip;
   An output side wiring extending from the output side of the circuit film toward the output terminal of the IC chip;
   It is disposed closer to the second side of the substrate than the input-side wiring, the IC chip, and the output-side wiring, and extends linearly from the input side of the circuit film to the output side of the circuit film The first unwired area to
   It is disposed closer to the third side of the substrate than the input wiring, IC chip and output wiring, and extends linearly from the input side of the circuit film toward the output side of the circuit film. And a second non-wired area,
   The above multiple circuit films are
   A first circuit film closest to the second side of the substrate;
   A second circuit film closest to the third side of the substrate;
   A third circuit film positioned between the first circuit film and the second circuit film;
   The first circuit film is provided at an end positioned on the second side of the substrate, and further includes a first side wiring electrically connected to the first relay wiring. Display device.
7. In the display device according to claim 6,
   Each of the first circuit film, the second circuit film, and the third circuit film includes a first alignment mark provided between the first and second non-wiring regions and the output side wiring. Display device.
8. In the display device according to claim 7,
   A display device characterized in that the first circuit film includes a second alignment mark provided between the first non-wiring region and the first side wiring.
9. The display device according to any one of claims 6 to 8.
   A second gate drive circuit provided on the third side of the substrate;
   The substrate is provided on the substrate so as to extend from the first side of the substrate toward the second gate drive circuit, and the gate signal output from the source drive circuit is subjected to the second gate drive. And a second relay wire relaying to the circuit;
   The second circuit film is provided at an end located on the third side of the substrate, and includes a second side wiring electrically connected to the second relay wiring. Display device.
10. In the display device according to claim 9,
    The display device characterized in that the second circuit film includes a third alignment mark provided between the second non-wiring region and the second side wiring.
11. The display device according to any one of claims 6 to 10.
    A display device characterized in that a width of the first non-wiring region of the first circuit film is wider than a width of the second non-wiring region of the first circuit film.
12. The display device according to any one of claims 6 to 11.
    A display device characterized in that the width of the first non-wiring region of the second circuit film is narrower than the width of the second non-wiring region of the second circuit film.

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