WO2019136972A1 - Procédé permettant de réduire le taux d'erreur binaire d'une mémoire flash - Google Patents

Procédé permettant de réduire le taux d'erreur binaire d'une mémoire flash Download PDF

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Publication number
WO2019136972A1
WO2019136972A1 PCT/CN2018/099750 CN2018099750W WO2019136972A1 WO 2019136972 A1 WO2019136972 A1 WO 2019136972A1 CN 2018099750 W CN2018099750 W CN 2018099750W WO 2019136972 A1 WO2019136972 A1 WO 2019136972A1
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WO
WIPO (PCT)
Prior art keywords
flash memory
flash
read
voltage
control device
Prior art date
Application number
PCT/CN2018/099750
Other languages
English (en)
Chinese (zh)
Inventor
许豪江
李庭育
魏智汎
黄中柱
Original Assignee
江苏华存电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏华存电子科技有限公司 filed Critical 江苏华存电子科技有限公司
Publication of WO2019136972A1 publication Critical patent/WO2019136972A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/102—Error in check bits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

Definitions

  • the present invention relates to the field of flash memory technologies, and in particular, to a method for reducing a bit error rate of a flash memory.
  • Flash memory is a non-volatile solid-state storage device that can be electrically erased and rewritten, and is a specific type of electrically erasable writable write-only memory (EEPROM) device.
  • EEPROM electrically erasable writable write-only memory
  • Conventional flash memories store a single piece of information in each memory cell such that each memory cell can be programmed to assume two possible states.
  • Traditional flash memory is therefore often referred to as single-level cell (SLC) flash or single cell (SBC) flash memory.
  • SLC single-level cell
  • SBC single cell
  • Modern flash memories are capable of storing two or more bits of information in each memory cell such that each memory cell can be programmed to assume that there are more than two possible states.
  • Modern flash memory is therefore often referred to as multi-level cell (MLC) flash or multi-point cell (MBC) flash memory.
  • MLC multi-level cell
  • MLC multi-point cell
  • multi-level cell (MLC) flash memory data of different states is written to the floating gate of the flash memory. Since the charge of the floating gate specifically determines the corresponding threshold voltage, data can be read from the multi-level cell flash memory according to its different threshold voltages.
  • the threshold voltage of each state is not a fixed value, but a range, due to variations in the memory cells during manufacturing, operation, or other factors.
  • the threshold voltage of the battery is compared to the read voltage to determine its state.
  • the read voltage for reading data from a conventional multi-level cell flash memory is constant.
  • the threshold voltage distribution may be offset after the flash memory has been subjected to a predetermined number of write/erase cycles or a predetermined data retention time.
  • the distribution may be sufficiently enlarged such that adjacent states may partially overlap.
  • an initial distribution A with a read voltage threshold of 0 may suffer from retention problems after a long period of no write/erase cycles, thus drifting down to shift profile B with a new read voltage threshold of one.
  • the adjacent states of the shift distribution B partially overlap, resulting in an erroneous bit. If the range of overlap is large, Error Correction Control (ECC) may not be able to correct the error bit.
  • ECC Error Correction Control
  • Read adjacent pages set the trigger flag if the adjacent page is an interference page. At least two different read voltages read data from adjacent pages at least twice.
  • the threshold voltage distribution associated with the original page and adjacent pages is transmitted based on the read data and flags. Specifically, the rightmost portion of the threshold voltage distribution is turned left, or the left portion of the threshold voltage distribution is shifted to the right using the initial read voltage according to the read data, the read data is read backward using the read voltage, and the read data is read. The read voltage and flag are used.
  • the present invention provides the following technical solution: a method for reducing a bit error rate of a flash memory, comprising a flash memory control device and a plurality of flash memory chips, wherein the flash memory control device connects a plurality of flash memory chips via a bus, the flash memory
  • the control device is provided with a flash command control device that writes, erases, and reads commands to the flash memory chip, and an adjustment voltage device that adjusts the flash chip voltage.
  • the plurality of flash memory chips comprise a first flash chip, a second flash chip, a third flash chip and an Nth flash chip, N being an integer greater than 3, the flash chip having 1024 blocks, each block having 256 Pages, each with 32 fan shapes.
  • the method comprises the following steps:
  • step F Read data by error check; if reading through data error check, jump to step F; otherwise, find the best read flash voltage;
  • step D if the data error check, jump to step F, otherwise jump to step E;
  • the elimination of the coupling effect of the step E comprises the following steps:
  • step b If the reading is successful, the process ends; if the reading is not successful, the voltage V value is adjusted and then the process proceeds to step b.
  • the present invention has the beneficial effects that the present invention provides a method for reducing the flash bit error rate or reducing the coupling effect between adjacent pages of a flash memory by adjusting the read voltage.
  • Figure 1 is a schematic view of the overall structure of the present invention
  • Figure 2 is a flow chart of the present invention
  • Figure 3 is a flow chart showing the elimination of the coupling effect of the present invention.
  • the present invention provides a technical solution: a method for reducing a bit error rate of a flash memory, comprising a flash memory control device 1 and a plurality of flash memory chips, wherein the flash memory control device 1 connects a plurality of flash memory chips through a bus.
  • the flash memory control device 1 is provided with a flash command control device 2 for writing, erasing and reading commands to the flash memory chip, and an adjustment voltage device 3 for adjusting the voltage of the flash memory chip.
  • the plurality of flash memory chips include a first flash memory chip 4, a second flash memory chip 5, a third flash memory chip 6, and an Nth flash memory chip, and N is an integer greater than 3, and the flash memory chip has 1024 blocks, each of which has 256 pages, each with 32 sectors combined.
  • a method for reducing a bit error rate of a flash memory includes the following steps:
  • step F Read data by error check; if reading through data error check, jump to step F; otherwise, find the best read flash voltage;
  • this new read voltage can be used to solve the problem caused by the distributed shift
  • step D if the data error check, jump to step F, otherwise jump to step E;
  • step E includes the following steps:
  • step b If the reading is successful, the process ends; if the reading is not successful, the voltage V value is adjusted and then the process proceeds to step b.
  • the present invention provides a method for reducing the flash bit error rate or reducing the coupling effect between adjacent pages of a flash memory by adjusting the read voltage.
  • An inner side of the mold is respectively provided with a shaping needle and a shaping column; a controller is disposed in the base, and a stepping motor is further disposed in the base, the stepping motor is connected to the rotating platform through a rotating shaft; the stepping motor and the control The motors are respectively connected to the controller;
  • the lower mold is provided with a positioning optical point; and the upper mold is provided with an optical mirror corresponding to the positioning optical point.
  • the compression spring comprises a first contact end, a second contact end and a spring body
  • the spring body is formed by a long strip of metal or resin ring and is spiral, and the spring body is provided
  • the first contact end and the second contact end are respectively disposed at the top and the bottom of the spring body, and the first contact end and the second contact end are both horizontal planes;
  • a contact end fixedly connects the block, and the second contact end is fixedly connected to the upper die.
  • the rotating platform comprises an upper platform and a lower platform, a first hemispherical protrusion is arranged inside the upper platform, and a second hemispherical protrusion corresponding to the first hemispherical protrusion is arranged inside the lower platform.
  • a center of the first hemispherical protrusion and the second hemispherical protrusion is provided with a through hole, and a rotary bearing is mounted in the through hole.
  • the lower end of the shaping column adopts a hemispherical structure; the lower end of the shaping needle has a tapered structure.
  • the utility model has the simple structural principle, can realize the electric control of the upper mold and the lower mold, improves the shaping efficiency, and can improve the quality of the subsequent IC welding.
  • the compression spring used in the utility model has uniform force, is not easy to be deformed after being subjected to force, can realize rapid reset, and further improves work efficiency.
  • the rotating platform adopted by the utility model has good stability and can realize 360° arbitrary rotation, thereby further improving the efficiency of integrated circuit IC shaping.
  • Figure 1 is a front view of the utility model
  • Figure 2 is a schematic view showing the structure of the compression spring of the present invention.
  • Figure 3 is a schematic view showing the structure of the rotating platform of the present invention.
  • an integrated circuit IC semi-automatic pin shaping machine including a base 1, an upper mold 2, a lower mold 3, and a rotating platform 4, and the rotating platform 4 is installed.
  • the upper end surface of the rotating platform 4 is mounted with a plurality of lower molds 3, the lower mold 3 is provided with a groove 5 at the center thereof, and the lower mold 3 is provided with pin placement areas 6 on both sides thereof.
  • the size of the slot 5 is the same as the size of the integrated circuit IC.
  • the upper die 2 is disposed directly above the rotating platform 4.
  • the base 1 is fixedly mounted with a guiding rod 7, and the upper die 2 is provided with through holes on both sides thereof.
  • the rod 7 is inserted through the through hole, and the baffle 8 is fixedly mounted on the rear end of the base 1.
  • the middle portion of the baffle 8 is provided with a slide rail 9.
  • the slide rail 9 is provided with a rack 10, and the upper end surface of the upper mold 2
  • the middle portion is fixedly mounted with a pressing rod 11 , and the rear end of the pressing rod 11 is fixedly connected with a connecting rod 12 .
  • the connecting rod 12 is provided with a gear 13 matched with a rack 10 , and a control motor 14 is mounted on the top of the connecting rod 12 .
  • a stopper 15 is mounted on the top of the guide rod 7, and a compression spring 16 is fixedly mounted between the stopper 15 and the upper end surface of the upper mold 2, and the compression spring 16 is sleeved on
  • the inner side of the upper mold 2 is respectively provided with a shaping needle 17 and a shaping column 18, and the lower end portion of the shaping column 18 adopts a hemispherical structure; the lower end portion of the shaping needle 17 has a tapered structure, and the shaping column and shaping are adopted.
  • the special structure of the needle can prevent the damage of the pin;
  • the base 1 is provided with a controller 19, and the base 1 is further provided with a stepping motor 20, and the stepping motor 20 is connected to the rotating platform 4 through the rotating shaft 21;
  • the stepping motor 20 and the control motor 14 are respectively connected to the controller 19;
  • the lower mold 3 is provided with a positioning optical point 22; the upper mold 2 is provided with an optical mirror 23 corresponding to the positioning optical point 22; the positioning optical point and the optical mirror are arranged to facilitate the rotation of the lower mold and the upper mold Positioning improves the accuracy of shaping.
  • the compression spring 16 includes a first contact end 24, a second contact end 25 and a spring body 26, and the spring body 26 is formed by a long strip of metal or resin, and is spiraled.
  • the spring body 26 is provided with a plurality of equally spaced spiral ring bodies 27, and the first contact end 24 and the second contact end 25 are respectively disposed at the top and bottom of the spring body 26, and the first contact end 24,
  • the second contact end 25 is a horizontal plane; the first contact end 24 is fixedly connected to the stop block 15, and the second contact end 25 is fixedly connected to the upper mold 2.
  • the compression spring adopted by the utility model has uniform force, is not easy to be deformed after being subjected to force, can realize rapid reset, and further improves work efficiency.
  • the rotating platform 4 includes an upper platform 28 and a lower platform 29, and a first hemispherical protrusion 30 is disposed inside the upper platform 28, and the inner side of the lower platform 29 is disposed corresponding to the first hemispherical protrusion 30.
  • the second hemispherical protrusion 31 is provided with a through hole 32 in the center of the first hemispherical protrusion 30 and the second hemispherical protrusion 31, and a rotary bearing 33 is mounted in the through hole 32.
  • the rotating platform adopted by the utility model has good stability and can realize arbitrary rotation of 360°, thereby further improving the efficiency of integrated circuit IC shaping.
  • the stepper motor is controlled to rotate by the controller.
  • the stepping motor stops working.
  • the motor is controlled by the controller to control the motor control gear to rotate on the rack, thereby driving the pressure rod to move downward, the shaping needle is pressed from the top to the bottom of the pin gap, and the integral column passes the pressure to lift the pin.
  • the part is pressed down to return the deformed pin to the normal position; then the stepper motor is controlled to rotate again to perform the same operation.
  • the utility model has the simple structural principle, can realize the electric control of the upper mold and the lower mold, improves the shaping efficiency, and can improve the quality of the subsequent IC welding.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne un procédé permettant de réduire le taux d'erreur binaire d'une mémoire flash. Un dispositif de commande de mémoire flash et de multiples puces de mémoire flash sont compris, le dispositif de commande de mémoire flash étant connecté aux multiples puces de mémoire flash au moyen d'un bus ; un dispositif de commande d'instruction de mémoire flash et un dispositif de régulation de tension sont disposés dans le dispositif de commande de mémoire flash ; le dispositif de commande d'instruction de mémoire flash peut écrire, effacer et lire des instructions pour les puces de mémoire flash ; et le dispositif de régulation de tension peut réguler la tension de chaque puce de mémoire flash. La présente invention concerne un procédé permettant de réduire le taux d'erreur binaire d'une mémoire flash ou de réduire l'effet de couplage entre des pages adjacentes de la mémoire flash au moyen de la régulation de la tension de lecture.
PCT/CN2018/099750 2018-01-12 2018-08-09 Procédé permettant de réduire le taux d'erreur binaire d'une mémoire flash WO2019136972A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810030688.6 2018-01-12
CN201810030688.6A CN108108265A (zh) 2018-01-12 2018-01-12 一种降低快闪存储器比特错误率的方法

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WO2019136972A1 true WO2019136972A1 (fr) 2019-07-18

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101405812A (zh) * 2006-06-19 2009-04-08 桑迪士克股份有限公司 编程不同大小的容限及在选择状态下使用补偿进行感测以改进非易失性存储器中的读取操作
US8259506B1 (en) * 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
CN104217761A (zh) * 2013-05-31 2014-12-17 慧荣科技股份有限公司 数据储存装置及其错误校正方法
CN106205720A (zh) * 2016-07-06 2016-12-07 记忆科技(深圳)有限公司 一种恢复Nand Flash错误数据的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101405812A (zh) * 2006-06-19 2009-04-08 桑迪士克股份有限公司 编程不同大小的容限及在选择状态下使用补偿进行感测以改进非易失性存储器中的读取操作
US8259506B1 (en) * 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
CN104217761A (zh) * 2013-05-31 2014-12-17 慧荣科技股份有限公司 数据储存装置及其错误校正方法
CN106205720A (zh) * 2016-07-06 2016-12-07 记忆科技(深圳)有限公司 一种恢复Nand Flash错误数据的方法

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