WO2019135813A1 - Cellules de mémoire non volatile à deux bits pourvues de grilles flottantes dans des tranchées de substrat - Google Patents

Cellules de mémoire non volatile à deux bits pourvues de grilles flottantes dans des tranchées de substrat Download PDF

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Publication number
WO2019135813A1
WO2019135813A1 PCT/US2018/056833 US2018056833W WO2019135813A1 WO 2019135813 A1 WO2019135813 A1 WO 2019135813A1 US 2018056833 W US2018056833 W US 2018056833W WO 2019135813 A1 WO2019135813 A1 WO 2019135813A1
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Prior art keywords
trench
substrate
gate
insulated
conductive material
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PCT/US2018/056833
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English (en)
Inventor
Chunming Wang
Andy Liu
Xian Liu
Leo XING
Melvin DAO
Nhan Do
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Silicon Storage Technology, Inc.
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Publication date
Priority claimed from CN201810011007.1A external-priority patent/CN110010606B/zh
Application filed by Silicon Storage Technology, Inc. filed Critical Silicon Storage Technology, Inc.
Priority to JP2020537160A priority Critical patent/JP7097448B2/ja
Priority to EP23208893.0A priority patent/EP4301107A3/fr
Priority to KR1020207018470A priority patent/KR102390136B1/ko
Priority to EP18898634.3A priority patent/EP3735705B1/fr
Priority to TW107141720A priority patent/TWI699875B/zh
Publication of WO2019135813A1 publication Critical patent/WO2019135813A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to non-volatile memory devices.
  • each of these patents discloses a split gate non-volatile memory cell, where the source and drain regions are formed at the surface of the substrate, so that the channel region extending between the source and drain regions extends along the surface of the substrate.
  • the conductivity of the channel region is controlled by a floating gate and a second gate (e.g. a word line gate) disposed over and insulated from the channel region of the substrate.
  • trenches can be formed into the surface of the substrate, where a pair of memory cells are formed inside the trench. See for example, U.S. Patents 6,952,034, 7,151,021 and 8,148,768. With these configurations, the source region is formed underneath the trench, whereby the channel region extends along the sidewall of the trench and the surface of the substrate (i.e. the channel region is not linear). By burying a pair of floating gates in each trench, the overall size of the memory cells as a function of substrate surface area space is reduced.
  • pairs of memory cells sharing each trench also meant a reduction in surface area space occupied by each pair of memory cells.
  • a twin bit memory cell that includes a semiconductor substrate having an upper surface, first and second trenches formed into the upper surface and spaced apart from each other, a first floating gate of conductive material disposed in the first trench and insulated from the substrate, a second floating gate of conductive material disposed in the second trench and insulated from the substrate, a first erase gate of conductive material disposed over and insulated from the first floating gate, a second erase gate of conductive material disposed over and insulated from the second floating gate, a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches, a first source region formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench.
  • a continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second
  • a twin bit memory cell includes a semiconductor substrate having an upper surface, first and second trenches formed into the upper surface and spaced apart from each other, a first floating gate of conductive material disposed in the first trench and insulated from the substrate, a second floating gate of conductive material disposed in the second trench and insulated from the substrate, a first erase gate of conductive material disposed over and insulated from the first floating gate, a second erase gate of conductive material disposed over and insulated from the second floating gate, a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches, a first source region formed at the upper surface of the substrate adjacent the first trench, and a second source region formed at the upper surface of the substrate adjacent the second the second trench.
  • a continuous channel region of the substrate extends from the first source region, along a first side wall of the first trench, along a bottom wall of the first trench, along a second side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a first side wall of the second trench, along a bottom wall of the second trench, along a second side wall of the second trench and to the second source region.
  • a twin bit memory cell includes a semiconductor substrate having an upper surface, first and second trenches formed into the upper surface and spaced apart from each other, first and second floating gates of conductive material disposed in the first trench spaced apart from each other and insulated from the substrate, third and fourth floating gates of conductive material disposed in the second trench spaced apart from each other and insulated from the substrate, a first erase gate of conductive material disposed over and insulated from the first and second floating gates, a second erase gate of conductive material disposed over and insulated from the third and fourth floating gates, a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches, a first source region formed in the substrate under the first trench, a second source region formed in the substrate under the second trench, a first control gate of conductive material disposed in the first trench, and between and insulated from the first and second floating gates, and a second control gate of conductive material disposed in the second trench, and between and insulated from the first and second
  • a method of forming a twin bit memory cell includes forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other, forming a first floating gate of conductive material in the first trench and insulated from the substrate, forming a second floating gate of conductive material in the second trench and insulated from the substrate, forming a first erase gate of conductive material over and insulated from the first floating gate, forming a second erase gate of conductive material over and insulated from the second floating gate, forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches, forming a first source region in the substrate under the first trench, and forming a second source region in the substrate under the second trench.
  • a continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench.
  • a method of forming a twin bit memory cell includes forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other, forming a first floating gate of conductive material in the first trench and insulated from the substrate, forming a second floating gate of conductive material in the second trench and insulated from the substrate, forming a first erase gate of conductive material over and insulated from the first floating gate, forming a second erase gate of conductive material over and insulated from the second floating gate, forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches, forming a first source region at the upper surface of the substrate adjacent the first trench, and forming a second source region at the upper surface of the substrate adjacent the second the second trench.
  • a continuous channel region of the substrate extends from the first source region, along a first side wall of the first trench, along a bottom wall of the first trench, along a second side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a first side wall of the second trench, along a bottom wall of the second trench, along a second side wall of the second trench and to the second source region.
  • a method of forming a twin bit memory cell includes forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other, forming first and second floating gates of conductive material in the first trench spaced apart from each other and insulated from the substrate, forming third and fourth floating gates of conductive material in the second trench spaced apart from each other and insulated from the substrate, forming a first erase gate of conductive material over and insulated from the first and second floating gates, forming a second erase gate of conductive material over and insulated from the third and fourth floating gates, forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches, forming a first source region in the substrate under the first trench, forming a second source region in the substrate under the second trench, forming a first control gate of conductive material in the first trench, and between and insulated from the first and second floating gates, and forming a second control gate
  • Figs. 1A-1I are side cross sectional views illustrating the steps in forming the memory cells of the present invention.
  • FIGs. 2A-2C are side cross sectional views illustrating the steps in forming the memory cells of a second embodiment of the present invention.
  • Fig. 2D is a side cross sectional view illustrating a modification to the second embodiment of the present invention.
  • FIGs. 3A-3H are side cross sectional views illustrating the steps in forming the memory cells of a third embodiment of the present invention.
  • Fig. 4 is the schematic diagram of an array of the twin bit memory cells of Figs. II, 2C and 3H.
  • Fig. 5 is the schematic diagram of an array of the twin bit memory cells of Fig. 2D. DETAILED DESCRIPTION OF THE INVENTION
  • the present invention solves the above mentioned needs by forming two separate trenches into the surface of the substrate for a twin bit memory cell, and forming a floating gate in each trench.
  • a twin bit memory cell starts with a semiconductor substrate 10. While only one is shown and described, it should be understood that an array of such twin bit memory cells would be formed on the same substrate 10 end to end.
  • An oxide layer 12 is formed on the substrate.
  • a nitride layer 14 is formed on the oxide layer 12, and an oxide layer 16 is formed on the nitride layer 14.
  • the resulting structure is shown in Fig. 1A.
  • a photolithography masking process is then formed to etch through the oxide layer 16, nitride layer 14, oxide layer 12 and into the substrate 10, forming a pair of spaced apart trenches 18.
  • the masking step includes forming a layer of photo resist on the oxide layer 16, and selectively exposing portions of the photo resist.
  • Selected portions of the photo resist are removed, leaving portions of the oxide layer 16 exposed.
  • One or more etches are performed to remove the exposed portions of the oxide layer 16, and the underlying portions of the nitride layer 14, oxide layer 12 and substrate 10.
  • the resulting structure is shown in Fig. 1B (after removal of the photo resist).
  • An oxide etch is used remove oxide layer 16, and an oxide formation step is performed (e.g., thermal oxidation) to form oxide layer 20 on the exposed silicon substrate surfaces of trenches 18, as shown in Fig. 1C.
  • An implantation process is performed to form a source region 22 (i.e. a region having a second conductivity type different than the first conductivity type of the substrate) in the substrate portion underneath each trench 18.
  • a layer of polysilicon 24 is then deposited over the structure, filling each trench 18 with polysilicon 24, as shown in Fig. 1D.
  • the portions of polysilicon 22 above the surface of the substrate are removed (e.g., by CMP and etch back), leaving blocks of poly 22 in the substrate portion of trenches 18.
  • the upper surfaces of poly blocks 22 can be even with the upper surface of the substrate, or the etch back can be adjusted so that the upper surfaces of poly blocks 22 are above the substrate surface (i.e., the poly blocks 22 have an upper portion extending above the level of the substrate), or below the substrate surface (i.e., the poly blocks do not fully fill the portion of the trenches formed in the substrate).
  • the upper surfaces of the poly blocks 24 are substantially even with the substrate surface as shown in Fig. 1E.
  • Oxide spacers 26 are formed along the nitride sidewalls of trenches 18 by depositing a layer of oxide, following by an oxide etch, leaving spacers 26 of the oxide, as shown in Fig. 1F. Formation of spacers is well known in the art, and includes forming a conformal layer of material over a structure, followed by an etch that removes the material except for those portions along vertically oriented structural features. An oxide formation step (e.g., thermal oxidation) is then used to form a layer of oxide 28 on the exposed upper surfaces of poly blocks 24.
  • An oxide formation step e.g., thermal oxidation
  • a polysilicon layer is formed over the structure, and partially removed (e.g., CMP and etch back), leaving blocks of polysilicon 30 disposed on oxide layer 28 and between spacers 26, as shown in Fig. 1G.
  • Nitride 14 is then removed by a nitride etch, as shown in Fig. 1H.
  • a layer of polysilicon is formed over the structure, which is partially removed by CMP, leaving poly blocks 32 disposed between the back sides of spacers 26 (i.e., spacers 26 are disposed between poly blocks 30 and 32).
  • a word line 34 and word line contacts 36 are formed (e.g. of a metal material) to electrically connect the poly blocks 32 together.
  • the final structure is shown in Fig. II.
  • the twin bit memory cell includes a pair of floating gates 24 in trenches 18 and are insulated from the substrate by oxide 20.
  • the upper surfaces of the floating gates are preferably even with the upper surface of substrate 10, but could extend above the height of the substrate upper surface, or be disposed below the surface of the substrate, if desired.
  • An erase gate 30 is disposed over and insulated from each of the floating gates 24.
  • a word line gate 32 is disposed between the erase gates 30, and is disposed over and insulated from the substrate.
  • the twin bit memory cell also includes a channel region 38 of the substrate that extends from the source region 22 under one of the floating gates 24, along a sidewall of that trench 18, along the surface of the substrate, along a sidewall of the other trench 18, and to the source region 22 under the other floating gate 24.
  • the conductivity of the portions of the channel region along the trenches are controlled by the floating gates 24.
  • the conductivity of the portion of the channel region along the surface of the substrate 10 is controlled by the word line gate 32. Programming of the floating gates is enhanced because the horizontal portion of the channel region is aimed at the floating gate, which enhances hot electron injection.
  • each trench contains only a single floating gate, where the dimensions of the floating gate are dictated by the trench dimensions, the channel region is folded to extend downwardly into the substrate instead of extending entirely along the substrate surface, and no drain region is required, reducing cell height and cell lateral dimensions.
  • the twin bit memory cell can store a bit of information in each floating gate.
  • the cell operation is as follows.
  • the erase gates 30 are both placed at a positive voltage, such as 4.5 volts, which is coupled to the floating gates 24.
  • the word line gate 32 is placed at a positive voltage, such as 1 volt, to turn on the underlying channel region portion.
  • a positive voltage is placed on the right hand source region 22, and a current of around 1 mA is supplied to the left hand source region 22.
  • Electrons from the left hand source region 22 will travel along the channel region portion adjacent the left hand floating gate (which is turned on by the coupled positive voltage from the left hand erase gate), along the channel region portion under the word line gate 32, until the electrons see the positive voltage coupled onto the right hand floating gate, where some electrons are deposited onto the right hand floating gate through hot electron injection.
  • Programming the left hand floating gate is performed the same way, but reversing the voltages and current.
  • a high voltage e.g., 11.5 volts
  • a positive voltage (e.g., Vcc) is applied to the word line gate 32 to turn on that portion of the channel region.
  • a positive voltage is applied to the left hand erase gate 30 (which is coupled to the left hand floating gate to turn on that portion of the channel region).
  • a positive voltage is applied to the left hand source region (e.g., 0.6 - 1 volt).
  • a small positive voltage is supplied to the right hand erase gate, which is coupled to the right hand floating gate. This coupled voltage is high enough to turn on the channel region adjacent the right hand floating gate only if the floating is erased of electrons. Current is supplied to the right hand source region. If current flows along the channel region, then the right hand floating gate is read to be in its erased state.
  • the right hand floating gate is read to be in its programmed state. Reading the left hand floating gate is performed the same way, but reversing the voltages and current. These operations are performed without the need for a third source/drain region between the floating gates using multiple channel regions, and instead are performed using a single continuous channel region extending from one source region to another source region.
  • Figs. 2A-2C illustrate the formation of another embodiment.
  • the formation of this embodiment starts with the same structure shown in Fig. 1G, except no source regions 22 are formed under the trenches, as shown in Fig. 2A.
  • Nitride 14 is removed by nitride etch.
  • Source regions 40 are then formed by photolithographic and implantation steps into the surface portion of the substrate adjacent alternate pairs of floating gates 24, as shown in Fig. 2B.
  • a layer of polysilicon is formed over the structure, which is partially removed by CMP, leaving poly blocks 42 disposed between the back sides of spacers 26 (i.e., spacers 26 are disposed between poly blocks 30 and 42).
  • a word line 44 and word line contacts 46 are formed (e.g. of a metal material) to electrically connect the poly blocks 42 together.
  • the final structure is shown in Fig. 2C.
  • the twin bit memory cell is similar to that of Fig. II, except the source regions 40 are formed at the substrate surface, instead of being disposed underneath the floating gates.
  • the channel regions 48 still extend along the trenches and substrate surface. Therefore the twin bit memory cell is programmed, erased and read in a manner similar to that described with respect to Fig. II.
  • Fig. 2D illustrates an optional modification to the second embodiment.
  • the twin bit memory cell is the same as that shown in Fig. 2C, except that the poly block and oxide layer over the source region 40 is removed.
  • a bit line contact 48 is formed that extends between and electrically connects the source regions 40 to a conductive bit line 49.
  • Figs. 3A-3H illustrate the formation of another embodiment.
  • the formation of this embodiment starts with the same structure shown in Fig. 1F, except without the formation of the source regions, as shown in Fig. 3A.
  • An anisotropic poly etch is performed to remove the exposed portions of poly blocks 24 between spacers 26, leaving two separate poly blocks 24 in each trench.
  • An implantation process is then performed to form a source region 50 under each trench, as shown in Fig. 3B.
  • An insulation layer 52 is formed over the structure, as shown in Fig. 3C.
  • insulation layer 52 is an ONO layer, meaning it has oxide, nitride, oxide sublayers.
  • a poly deposition and etch process (e.g., CMP and etch back) is performed to form poly blocks 54 in the bottom of trenches 18, as shown in Fig. 3D.
  • Oxide is deposited over the structure, followed by CMP oxide removal, which fills the trenches with oxide 56, as shown in Fig. 3E.
  • An oxide etch is performed to remove the oxide in the top portions of the trenches, to expose the top portions of poly blocks 24, as shown in Fig. 3F.
  • An oxide deposition and etch is used to form oxide layer 58 and oxide spacer 59 over each of the exposed portions of poly blocks 24, as shown in Fig. 3G.
  • Nitride layer 14 is removed by nitride etch.
  • a poly deposition and CMP is performed to form poly blocks 60 over poly blocks 54, and poly blocks 62 on oxide 12 over the substrate surface.
  • a word line 64 and word line contacts 66 are formed (e.g. of a metal material) to electrically connect the poly blocks 62 together.
  • the final structure is shown in Fig. 3H.
  • each trench includes two floating gates 24, each one being for a different twin bit memory cell.
  • Poly block 54 serves as a control gate disposed in the trench and between floating gates of different twin bit memory cells.
  • the erase gate is disposed over the floating gates in each trench, with a lower narrower portion that extends into the trench, and a wider upper portion that extends up and over the floating gates, so that the erase gate wraps around the upper edges of the floating gates for enhanced Fowler Nordheim tunneling efficiency.
  • the channel region 68 extends between source regions 50, along the trench sidewalls and along the substrate surface. Cell size is reduced by forming the floating gates in trenches with non-linear channel regions, by not having a separate drain region, and operating the memory cell as a twin bit cell as opposed to two separately operating memory cells.
  • the twin bit memory cell of this embodiment operates similarly to the other two embodiments described above.
  • the erase gates 30 are both placed at a positive voltage, such as 4.5 volts, which are coupled to the floating gates 24.
  • the word line gate 62 is placed at a positive voltage, such as 1 volt, to turn on the underlying channel region portion.
  • a positive voltage is applied to the left hand control gate 54, which is coupled to the left hand floating gate to turn on that portion of the channel region.
  • a positive voltage is placed on the right hand source region 50, and a current of around 1 mA is supplied to the left hand source region 54.
  • a positive voltage may be applied to the right hand control gate.
  • Electrons from the left hand source region 54 will travel along the channel region portion adjacent the left hand floating gate (which is turned on by the coupled positive voltage to the left hand floating gate), along the channel region portion under the word line gate 62, until they see the positive voltage coupled onto the right hand floating gate from the erase gate and/or control gate, where some electrons are deposited on the right hand floating gate through hot electron injection.
  • Programming the left hand floating gate is performed the same way, but reversing the voltages and current.
  • a high voltage e.g., 11.5 volts
  • is applied to the erase gates 60 where electrons tunnel from the floating gates to the erase gates via Fowler-Nordheim tunneling.
  • a positive voltage (e.g., Vcc) is applied to the word line gate 62.
  • a positive voltage is applied to the left hand erase gate 60 and/or left hand control gate 54 (which is coupled to the left hand floating gate to turn on that portion of the channel region).
  • a positive voltage is applied to the left hand source region (e.g., 0.6 - 1.1 volt).
  • a small positive voltage is supplied to the right hand erase gate and/or right hand control gate, which is coupled to the right hand floating gate. This voltage is high enough to turn on the channel region adjacent the right hand floating gate only if the floating is erased of electrons.
  • Current is supplied to the right hand source region. If current flows along the channel region, then the right hand floating gate is read to be in its erased state. If low or no current flows along the channel region, then the right hand floating gate is read to be in its programmed state. Reading the left hand floating gate is performed the same way, but reversing the voltages and current.
  • Fig. 4 is the schematic diagram of an array of the twin bit memory cells of Figs.
  • Fig. 5 is the schematic diagram of an array of the twin bit memory cells of Fig. 2D.
  • the operational voltages and currents for such an array is illustrated in Table 2 below.
  • references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims.
  • Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims.
  • not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell configurations of the present invention. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
  • the terms“forming” and “formed” as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed.
  • the term“adjacent” includes“directly adjacent” (no intermediate materials, elements or space disposed there between) and“indirectly adjacent” (intermediate materials, elements or space disposed there between),“mounted to” includes“directly mounted to” (no intermediate materials, elements or space disposed there between) and“indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and“electrically coupled” includes“directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and“indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element“over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

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  • Non-Volatile Memory (AREA)

Abstract

L'invention porte sur une cellule de mémoire à deux bits qui comprend des première et seconde grilles flottantes espacées l'une de l'autre, formées dans des première et seconde tranchées dans la surface supérieure d'un substrat semi-conducteur. Une grille d'effacement, ou une paire de grilles d'effacement, sont disposées sur des grilles flottantes et isolées de celles-ci, respectivement. Une grille de ligne de mot est disposée sur une partie de la surface supérieure qui se trouve entre les première et seconde tranchées, et est isolée de celle-ci. Une première zone de source est formée dans le substrat sous la première tranchée, et une seconde zone de source est formée dans le substrat sous la seconde tranchée. Une zone de canal continue du substrat s'étend à partir de la première zone de source, le long d'une paroi latérale de la première tranchée, le long de la partie de la surface supérieure qui se trouve entre les première et seconde tranchées, le long d'une paroi latérale de la seconde tranchée, et jusqu'à la seconde zone de source.
PCT/US2018/056833 2018-01-05 2018-10-22 Cellules de mémoire non volatile à deux bits pourvues de grilles flottantes dans des tranchées de substrat WO2019135813A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2020537160A JP7097448B2 (ja) 2018-01-05 2018-10-22 基板トレンチ内に浮遊ゲートを有するツインビット不揮発性メモリセル
EP23208893.0A EP4301107A3 (fr) 2018-01-05 2018-10-22 Cellules de mémoire non volatile à deux bits pourvues de grilles flottantes dans des tranchées de substrat
KR1020207018470A KR102390136B1 (ko) 2018-01-05 2018-10-22 기판 트렌치들 내의 플로팅 게이트들을 갖는 트윈 비트 비휘발성 메모리 셀들
EP18898634.3A EP3735705B1 (fr) 2018-01-05 2018-10-22 Cellules de mémoire non volatile à deux bits pourvues de grilles flottantes dans des tranchées de substrat
TW107141720A TWI699875B (zh) 2018-01-05 2018-11-22 於基材溝中具有浮閘之雙位元非揮發性記憶體單元及其形成方法

Applications Claiming Priority (4)

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CN201810011007.1 2018-01-05
CN201810011007.1A CN110010606B (zh) 2018-01-05 2018-01-05 衬底沟槽中具有浮栅的双位非易失性存储器单元
US16/160,812 US10600794B2 (en) 2018-01-05 2018-10-15 Twin bit non-volatile memory cells with floating gates in substrate trenches
US16/160,812 2018-10-15

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WO2019135813A1 true WO2019135813A1 (fr) 2019-07-11

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US6093606A (en) * 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device
US20040238874A1 (en) * 2003-03-21 2004-12-02 Bomy Chen Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region
US20050077566A1 (en) * 2003-10-10 2005-04-14 Wei Zheng Recess channel flash architecture for reduced short channel effect
US20050169041A1 (en) * 2003-06-06 2005-08-04 Chih-Hsin Wang Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093606A (en) * 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device
US20040238874A1 (en) * 2003-03-21 2004-12-02 Bomy Chen Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region
US20050169041A1 (en) * 2003-06-06 2005-08-04 Chih-Hsin Wang Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby
US20050077566A1 (en) * 2003-10-10 2005-04-14 Wei Zheng Recess channel flash architecture for reduced short channel effect

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