WO2019135443A1 - Transmetteur permettant une annulation simultanée du bruit de commutation et une transmission d'horloge et de données et son procédé de fonctionnement - Google Patents

Transmetteur permettant une annulation simultanée du bruit de commutation et une transmission d'horloge et de données et son procédé de fonctionnement Download PDF

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Publication number
WO2019135443A1
WO2019135443A1 PCT/KR2018/002027 KR2018002027W WO2019135443A1 WO 2019135443 A1 WO2019135443 A1 WO 2019135443A1 KR 2018002027 W KR2018002027 W KR 2018002027W WO 2019135443 A1 WO2019135443 A1 WO 2019135443A1
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WO
WIPO (PCT)
Prior art keywords
signal lines
voltage level
clock
voltage
input data
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Application number
PCT/KR2018/002027
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English (en)
Korean (ko)
Inventor
유창식
Original Assignee
한양대학교 산학협력단
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Publication of WO2019135443A1 publication Critical patent/WO2019135443A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present invention relates to a transmitter capable of simultaneously transmitting clock and input data while eliminating simultaneous switching noise and a method of operation thereof.
  • 1 is a view showing a general display system.
  • the TCON (Timing controller) of the display system processes display data according to the characteristics of the display panel, and transmits the processed data to the driver at a timing matching the structure and resolution of the panel.
  • the interface connecting the TCON and the driver is called an intra-panel interface.
  • a single output transmitter can transmit a clock through a separate signal line different from a signal line transmitting data.
  • EMI electro-magnetic interference
  • a transmitter with a differential output structure can be used, but a transmitter with a differential output structure has a large power consumption and needs twice as many signal lines as a single output transmitter. As a result, the number of chip pins increases, resulting in an increase in area and cost.
  • the present invention provides a transmitter capable of simultaneously transmitting clock and input data while eliminating simultaneous switching noise, and a method of operation thereof.
  • a transmitter including: a mapping unit for mapping a clock and input data to one of codes; And transmission drivers for transmitting the clock and the input data through the signal lines in accordance with the mapped code.
  • the mapped code is set to a voltage level of the signal lines and each of the signal lines has a voltage level of '+1', '0', or '-1', and the clock has a voltage level corresponding to the mapped code
  • the bits of the input data are transmitted through the second signal lines having voltage levels corresponding to the mapped codes, respectively.
  • the number of signal lines having a voltage level of '+1' is the same as the number of signal lines having a voltage level of '-1'.
  • a transmitter including a mapping unit for mapping first data and second data different from the first data to one of codes; And transmission drivers for transmitting the first data and the second data through the signal lines according to the mapped code.
  • the voltage levels of the signal lines are set in the mapped code and the signal lines have a voltage level of '+1', '0', or '-1', and the first data is a voltage level corresponding to the mapped code
  • the bits of the second data are transmitted through the second signal lines having a voltage level corresponding to the mapped code, respectively.
  • the number of signal lines having a voltage level of '+1' is the same as the number of signal lines having a voltage level of '-1'.
  • a transmission method includes: mapping clock and input data to one of codes; And transmitting the clock and the input data through signal lines according to the mapped code.
  • the voltage levels of the signal lines are set in the mapped code, the signal lines have a voltage level of '+1', '0' or '-1', and the clock has a voltage level corresponding to the mapped code
  • the bits of the input data are transmitted through the second signal lines having voltage levels corresponding to the mapped codes, respectively.
  • the number of signal lines having a voltage level of '+1' is the same as the number of signal lines having a voltage level of '-1'.
  • a transmission method includes: setting codes having voltage levels of signal lines; And transmitting clock and input data through signal lines according to a code selected from the set codes. Wherein each of the signal lines has a voltage level of '+1', '0', or '-1', the clock is transmitted through a first signal line having a voltage level corresponding to the selected code, And are transmitted through the second signal lines having voltage levels corresponding to the selected codes, respectively.
  • the clock and the input data are transmitted, the number of signal lines having the voltage level of '+1' and the voltage level of '-1' in the signal lines including the first signal line and the second signal lines The number is the same.
  • the transmitter and the control method of the present invention make the number of signal lines having a voltage level of '+1' equal to the number of signal lines having a voltage level of '-1' when transmitting clock and input data.
  • the transmitter and its control method can simultaneously remove the switching noise while simultaneously transmitting the clock and the input data.
  • the number of signal lines required for the transmission can be reduced more than the number of signal lines required for the differential output structure.
  • 1 is a view showing a general display system.
  • FIG. 2 is a schematic diagram of a transmission / reception system according to an embodiment of the present invention.
  • 3 and 4 are diagrams illustrating a mapping process according to an embodiment of the present invention.
  • FIG 5 and 6 are views showing clock and data according to an embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a transmission driver according to an embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a waveform of a signal generated using a transmission driver according to an embodiment of the present invention.
  • the present invention relates to a transmitter capable of simultaneously transmitting clock and data while eliminating simultaneous switching noise (power supply noise) and an operation method thereof.
  • the transmitter of the present invention simultaneously transmits clock and input data, and simultaneously keeps the amount of current flowing in the power line and the ground line constant regardless of the clock and the input data pattern during transmission, thereby reducing the simultaneous switching noise have.
  • the data rate can be increased while reducing the number of signal lines as described later.
  • the transmission technology of the present invention can be applied to all interfaces for transmitting data, and includes, for example, a data transmission / reception interface, an interface between a memory (for example, HBM (High Bandwidth Memory) memory) And the like.
  • a memory for example, HBM (High Bandwidth Memory) memory
  • the interface between the conventional memory and the control chip uses a single ended structure, a simultaneous switching noise is generated and the data transmission rate is inevitably lowered. Also, the interface between the displays uses a differential output structure to eliminate the simultaneous switching noise, but this structure has the disadvantage of requiring twice as many signal lines. As a result, the transmitter has to be implemented at a high cost and a large area.
  • the transmission technology of the present invention can reduce simultaneous switching noise while reducing the number of signal lines compared to the differential output structure when simultaneously transmitting clock and input data.
  • the transmitter can be implemented at low cost and small area while eliminating simultaneous switching noise.
  • FIG. 2 schematically illustrates a transmitting / receiving system according to an embodiment of the present invention.
  • FIG. 3 and FIG. 4 illustrate a mapping process according to an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a clock and data according to an embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a transmission driver according to an embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a waveform of a signal generated using a transmission driver according to an embodiment of the present invention.
  • the transmission / reception system of the present embodiment includes a transmitter 200, signal lines 214, and a receiver 202. [ That is, the transmitter 200 and the receiver 202 can transmit and receive data through the signal lines 214.
  • the transmitter 200 includes a mapping unit 210 and at least one transmission driver 212.
  • the number of the transmission drivers 212 may be the same as the number of the signal lines 214.
  • the mapping unit 210 may map the clock and input data to one of predetermined codes.
  • the code may be set to the voltage levels of the signal lines 214.
  • the clock and input data are divided into a first signal line 214 having a '+1' voltage level, a second signal line 214 having a '0' Through the third signal line 214 having a voltage level of '-1'.
  • the signal line 214 may have three voltage levels of '+1', '0', and '-1'.
  • the voltage level '+1' means a level equal to or higher than the first reference voltage V REF1 as shown in FIG. 8, and the voltage level '0' denotes a level higher than the first reference voltage V REF1 and the first reference voltage V REF1 refers to a level between the small second reference voltage (V REF2) than V REF1), and a voltage level '1' it refers to a level below the second reference voltage (V REF2). That is, the voltage level corresponds to a high voltage, an intermediate voltage, or a low voltage, and the value of the voltage is not specified.
  • the mapping process of the mapping unit 210 will be described in detail.
  • the clock is transmitted through the first signal line
  • the input data is transmitted through the remaining signal lines (second signal lines)
  • the clock is mapped to the voltage level '+1' And reference numerals of signal lines are omitted.
  • the arrangement of the signal lines for transmitting the clock and the input data may be variously modified, and the clock may be mapped to the voltage level '+1' or '0' of the signal line, the voltage level '0' It is possible.
  • the code to which the clock and the input data are mapped is set so that the number of signal lines having a '+1' voltage level and the number of signal lines having a '-1' voltage level are equal to each other to eliminate simultaneous switching noise .
  • the magnitude of the current flowing to the power line VDD and the ground line VSS when the signal line has the voltage level of +1 is indicated as I VDD + 1 and I VSS + 1 , respectively, in one transmission driver 212 , this one indicates the magnitude of the current flowing to the VDD and VSS when in the transmit driver 212, a signal line is to have a voltage level of "0" to the I VDD0, I VSS0 each signal line in one transmission driver 212 '
  • V DD current is the current flowing in the power line
  • V SS current is the current flowing in the ground line.
  • I VDD-1 flows from the power supply voltage through the power line and I VSS + 1 flows to the ground through the ground line when the voltage level is +1, and I VDD-1 flows from the power supply voltage when the voltage level is -1.
  • I VSS0 flows through the ground line VSS-I 1 flows to the ground, when the voltage level '0' through the power line VDD0 I flows from the power supply voltage through a ground line that can flow to ground.
  • Equation 1 calculating the total current flowing through the power line based on Table 1 is as shown in the following Equation 1, and the total current flowing in the ground line is calculated as shown in Equation 2 below.
  • I VDD0 0.5 * (I VDD + 1 + I VDD-1 ) in Equation 1
  • the current flowing through the power line becomes N * I VDD0 regardless of the clock and input data. That is, the current flowing to the power line is constant regardless of the clock and input data, and the current change rate becomes zero.
  • an inductance is formed in a power line and a ground line, and a noise v of a power line and a ground line formed by the inductance is expressed by the following equation (3).
  • the current flowing to the power line and the ground line is constant regardless of the clock and input data. That is, the amount of change of the current flowing to the power line or the ground line is zero. As a result, no simultaneous switching noise occurs.
  • clock and input data may be mapped into codes as shown in Table 2 below.
  • the code mapping can be variously set in addition to Table 2.
  • Table 2 Clock Input data code The voltage level of the first signal line The voltage level of the second signal line The voltage level of the third signal line The voltage level of the fourth signal line One 00 +1 +1 -One -One 01 +1 -One -One +1 10 +1 -One 0 0 11 +1 0 0 -One 0 00 -One -One +1 +1 01 -One +1 -One +1 10 -One +1 0 0 11 -One 0 0 +1 +1
  • the transmission technique of the present invention can simultaneously transmit a clock and 2-bit input data using four signal lines.
  • the conventional differential output structure requires six signal lines in order to transmit a clock and two bits of input data.
  • only four signal lines are required to transmit a clock and two bits of input data in need. That is, the transmission technique of the present invention can simultaneously transmit clock and input data while reducing simultaneous switching noise, and can also reduce the number of signal lines.
  • the transmitter 200 can simultaneously transmit the clock and 4-bit input data.
  • the conventional differential output structure requires 10 signal lines to transmit clock and 4-bit input data.
  • only five signal lines are required to transmit a clock and 4-bit input data . That is, the number of signal lines can be reduced.
  • the frequency of the clock signal and the data rate of the data signal may be the same as shown in FIG. 5 or may be different from each other as shown in FIG. 5 and 6 show a clock signal and a data signal when five signal lines are used.
  • the frequency of the clock signal is 1 / K (K is a positive integer larger than 1) of the data rate of the data signal. to be.
  • the transmission driver 212 will be described with reference to FIG.
  • the characteristic impedance of the signal line 214 is Z0. It is possible to make the characteristic impedance of the signal line 214 equal to the output impedance of the transmission driver 212 so that there is no reflection of the signal. As a result, the voltage of the node corresponding to the voltage level of the signal line 214 can be similarly transmitted at the receiver 202.
  • the transmission driver 212 may include three resistors R 1 , R 2, and R 3 and capacitors connected in parallel with respect to a corresponding signal line.
  • the capacitor is connected between the resistor R 3 and the ground and has a voltage of (V DDQ ) / 2, and V DDQ is the power supply voltage.
  • Resistance (R 1) it is connected between the connection between the node (three resistors have to see node) corresponding to the supply voltage and the signal line 214, and, a resistor (R 2) is the node to ground, the resistance (R 3 Is connected between the node and the capacitor.
  • the relationship between the resistors (R 1 , R 2, and R 3 ) is shown in the table of FIG.
  • the voltage of the node corresponds to the voltage level of the signal line 214.
  • the above structure is an example of the transmission driver 212, and can be variously modified.
  • the transmission technique of the present embodiment transmits the clock and the input data at the same time, and the number of the signal lines 214 having the voltage level of '+1' and the number of the signal lines 214 having the voltage level of '-1' .
  • the number of signal lines can be reduced while the simultaneous switching noise is eliminated.
  • the clock is mapped to the voltage level '+1' or '-1' of the signal line, but the clock is shifted to the voltage level '+1' or '0' Or may be mapped.
  • the clock and the input data are simultaneously transmitted.
  • signals other than the clock and input data may be simultaneously transmitted.
  • the mapping and transmission process is the same as the above process.
  • each component can be identified as a respective process. Further, the process of the above-described embodiment can be easily grasped from the viewpoint of the components of the apparatus.
  • the above-described technical features may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium.
  • the computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination.
  • the program instructions recorded on the medium may be those specially designed and constructed for the embodiments or may be available to those skilled in the art of computer software.
  • Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.
  • program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like.
  • the hardware device may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un émetteur permettant une annulation simultanée du bruit de commutation ainsi que la transmission simultanée d'une horloge et de données d'entrée et son procédé de fonctionnement. Le transmetteur comprend : une unité de mappage pour mapper une horloge et des données d'entrée pour l'un des codes; et des pilotes de transmission pour transmettre l'horloge et les données d'entrée au moyen de lignes de signal conformément au code mappé. Le code mappé est réglé sur les niveaux de tension des lignes de signal. Chacune des lignes de signal a un niveau de tension de " +1 ", "0" ou "-1". L'horloge est transmise au moyen d'une première ligne de signal ayant un niveau de tension correspondant au code mappé. Des bits des données d'entrée sont transmis respectivement au moyen de secondes lignes de signal ayant un niveau de tension correspondant au code mappé. En ce qui concerne les lignes de signal comprenant la première ligne de signal et les secondes lignes de signal, le nombre de lignes de signal ayant un niveau de tension de "+1" et le nombre de lignes de signal ayant un niveau de tension de "-1" sont les mêmes.
PCT/KR2018/002027 2018-01-05 2018-02-19 Transmetteur permettant une annulation simultanée du bruit de commutation et une transmission d'horloge et de données et son procédé de fonctionnement WO2019135443A1 (fr)

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KR1020180001658A KR102034369B1 (ko) 2018-01-05 2018-01-05 동시 스위칭 잡음을 제거하면서 클록 및 데이터를 전송할 수 있는 송신기 및 이의 동작 방법
KR10-2018-0001658 2018-01-05

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KR102346845B1 (ko) * 2020-01-03 2022-01-04 고려대학교 산학협력단 다중 레벨 브레이드 신호법을 이용한 송수신 장치 및 그 동작 방법
US11088878B2 (en) 2020-01-03 2021-08-10 Korea University Research And Business Foundation Transceiver using multi-level braid signaling and method of operating the same

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JP2013236246A (ja) * 2012-05-09 2013-11-21 Renesas Electronics Corp 半導体装置、及びそのデータ転送方法
KR20150126906A (ko) * 2013-03-07 2015-11-13 퀄컴 인코포레이티드 N-페이즈 시스템들을 위한 전압 모드 드라이버 회로
KR20160105093A (ko) * 2015-02-27 2016-09-06 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템
KR20170025868A (ko) * 2015-08-31 2017-03-08 에스케이하이닉스 주식회사 고속 통신을 위한 전송 장치, 이를 포함하는 인터페이스 회로 및 시스템
KR20170035027A (ko) * 2015-09-22 2017-03-30 에스케이하이닉스 주식회사 데이터 송신장치, 데이터 수신장치, 데이터 송수신 시스템

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Publication number Priority date Publication date Assignee Title
EP2903171B1 (fr) 2014-01-30 2019-08-28 Analog Devices Global Unlimited Company Suppression de bruit d'émetteur dans un système d'émetteur-récepteur multiple

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013236246A (ja) * 2012-05-09 2013-11-21 Renesas Electronics Corp 半導体装置、及びそのデータ転送方法
KR20150126906A (ko) * 2013-03-07 2015-11-13 퀄컴 인코포레이티드 N-페이즈 시스템들을 위한 전압 모드 드라이버 회로
KR20160105093A (ko) * 2015-02-27 2016-09-06 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템
KR20170025868A (ko) * 2015-08-31 2017-03-08 에스케이하이닉스 주식회사 고속 통신을 위한 전송 장치, 이를 포함하는 인터페이스 회로 및 시스템
KR20170035027A (ko) * 2015-09-22 2017-03-30 에스케이하이닉스 주식회사 데이터 송신장치, 데이터 수신장치, 데이터 송수신 시스템

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KR20190083792A (ko) 2019-07-15

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