WO2019134376A1 - Procédé et appareil de détermination d'adresse virtuelle, processeur et support de stockage - Google Patents

Procédé et appareil de détermination d'adresse virtuelle, processeur et support de stockage Download PDF

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Publication number
WO2019134376A1
WO2019134376A1 PCT/CN2018/102225 CN2018102225W WO2019134376A1 WO 2019134376 A1 WO2019134376 A1 WO 2019134376A1 CN 2018102225 W CN2018102225 W CN 2018102225W WO 2019134376 A1 WO2019134376 A1 WO 2019134376A1
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Prior art keywords
address
instruction
previous
target
offset
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PCT/CN2018/102225
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English (en)
Chinese (zh)
Inventor
劳咏仪
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Definitions

  • the present application relates to the field of processor technologies, and in particular, to a virtual address determining method and apparatus, a processor, and a storage medium.
  • a typical operational pipeline of the central processing unit is: fetching instructions (ie, fetching instructions), decoding instructions, transmitting instructions, executing instructions, accessing memory and submitting results, fetching instructions, decoding instructions, transmitting instructions, executing instructions, and accessing memory. Any of the body and the submitted results is called a pipeline stage.
  • the central processing unit includes units corresponding to each pipeline stage, each unit is configured to perform a corresponding pipeline stage operation, for example, the central processing unit includes an instruction fetch unit, and the instruction fetch unit performs an instruction fetch operation, and the fetched instruction is required.
  • branch instructions may include direct branch instructions and non-direct branch instructions.
  • the fetching unit first needs to determine the virtual address of the target instruction to be acquired, and then acquires the target instruction based on the virtual address.
  • the virtual address may be a program counter (PC) address.
  • the instruction fetch unit determines the virtual address of the target instruction according to the virtual address of the previous instruction of the target instruction, and then determines the physical address of the target instruction according to the virtual address and address mapping of the target instruction, and finally stores the physical address according to the target instruction.
  • the target instruction is fetched from the space (for example, the level one instruction cache).
  • the previous instruction of the target instruction is an instruction that the instruction instruction unit has taken out.
  • the previous instruction is a direct branch instruction
  • the previous instruction includes an offset address
  • the instruction unit is virtualized according to the previous instruction of the target instruction.
  • the address determining the virtual address of the target instruction may include: the instruction fetch unit decodes the previous instruction to obtain an offset address included in the previous instruction, and then performs sign extend on the offset address to obtain an extended bias. The address is shifted, the extended offset address is aligned with the virtual address of the previous instruction, and the width is equal. Finally, the instruction fetch unit adds the extended offset address to the virtual address of the previous instruction to obtain the virtual address of the target instruction. .
  • the address width of the processor increases, the amount of calculation for adding the offset address to the virtual address is larger and larger. Therefore, the delay of determining the virtual address of the target instruction is large, and the processing speed of the central processing unit is slow.
  • the present application provides a virtual address determining method and apparatus, a processor, and a storage medium, which are helpful in solving the problem that the delay of determining a virtual address is large and the processing speed of the processor is slow.
  • the technical solution of the present application is as follows:
  • a virtual address determining method comprising:
  • Determining the remaining address of the target instruction the sum of the width of the remaining address of the target instruction and the width of the lower address of the target instruction being equal to the width of the virtual address of the previous instruction;
  • the lower address of the target instruction is combined with the remaining address of the target instruction to obtain the virtual address of the target instruction.
  • the lower address stored in the instruction space of different instructions is aligned in the 0th bit of the instruction space.
  • the solution provided by the present application since it is not necessary to calculate the lower address of the target instruction in determining the virtual address of the target instruction, only the remaining address of the target instruction needs to be calculated (the remaining address is the virtual address of the target instruction except the lower address) The address), and then the remaining address of the target instruction is combined with the lower address of the target instruction to obtain the virtual address of the target instruction, so that the delay of determining the virtual address of the target instruction can be reduced, and the processing speed of the processor can be improved.
  • the method further includes:
  • the lower address of the target instruction is stored into the instruction space of the previous instruction.
  • the solution provided by the present application can facilitate the determination of the virtual address of the target instruction by pre-calculating the lower address of the target instruction and storing the lower address of the target instruction to the instruction space of the previous instruction of the target instruction.
  • the instruction space of an instruction reads the lower address of the target instruction.
  • the lower address of the target instruction is calculated, including:
  • the lower address of the previous instruction is added to the lower address of the offset address to obtain the lower address of the target instruction, and the lower address of the target instruction is aligned with the lower address of the previous instruction and the width is equal.
  • the solution provided by the present application generates the lower address of the target instruction by adding the lower address of the previous instruction of the target instruction to the lower address of the included offset address of the target instruction, thereby facilitating the determination of the lower address of the target instruction.
  • the method further includes: storing the low carry into the extended instruction space, the low bit The carry is a carry generated by adding the lower address of the previous instruction to the lower address of the offset address, and the extended instruction space is an instruction space obtained by expanding the instruction space of the previous instruction.
  • the solution provided by the present application can facilitate reading the lower carry from the extended instruction space in the process of determining the virtual address of the target instruction by storing the lower carry into the extended instruction space.
  • the remaining address includes a median address and a high address
  • determining a remaining address of the target instruction includes:
  • the offset address is composed of the upper address of the offset address and the lower address of the offset address
  • the upper address of the target instruction is determined according to the median carry, the upper address of the previous instruction, and the sign of the offset address.
  • the median carry is the median address of the previous instruction, the upper address of the offset address, and the lower carry phase. Add the resulting carry.
  • determining a high-order address of the target instruction according to a median carry, a high-order address of the previous instruction, and a symbol of the offset address including:
  • the lower address of the target instruction is calculated, including:
  • the lower address of the previous instruction is added to the offset address to obtain the lower address of the target instruction, and the lower address of the target instruction is aligned with the lower address of the previous instruction and the width is equal.
  • the solution provided by the present application generates the lower address of the target instruction by adding the lower address of the previous instruction of the target instruction to the offset address, thereby facilitating the determination of the lower address of the target instruction.
  • the remaining address includes a high-order address
  • the method further includes:
  • Determining the upper address of the target instruction according to the lower carry, the upper address of the previous instruction, and the sign of the offset address, and the lower carry is a carry generated by adding the lower address and the offset address of the previous instruction;
  • the address indication symbol is stored in an extended instruction space, which is an instruction space obtained by expanding the instruction space of the previous instruction.
  • the solution provided by the present application can store the address indication symbol into the extended instruction space by predetermining the upper address of the target instruction and generating the address indication symbol, which can facilitate reading the address from the extended instruction space in the process of determining the virtual address of the target instruction.
  • determining a remaining address of the target instruction includes:
  • the upper address of the target instruction is determined according to the address indication symbol.
  • the solution provided by the present application can save the delay of calculating the upper address of the target instruction and improve the processing speed of the processor by determining the upper address of the target instruction according to the address indication symbol.
  • determining a high-order address of the target instruction according to a low-order carry, a high-order address of the previous instruction, and a symbol of the offset address including:
  • a virtual address determining apparatus comprising at least one module, the at least one module configured to implement the virtual address determination provided by the foregoing first aspect or any of the optional aspects of the first aspect method.
  • a processor comprising the virtual address determining apparatus provided by the second aspect or the optional aspect of the second aspect.
  • a computer readable storage medium having stored therein instructions that, when executed on a processor of a computer, cause the processor to perform the first aspect or the first aspect The virtual address determination method provided by any of the alternatives.
  • a computer program product comprising instructions for causing a processor to perform the virtualization provided by the first aspect or any of the alternatives of the first aspect when the computer program product is run on a processor of the computer Address determination method.
  • a processing apparatus comprising at least one circuit for performing the virtual address determining method provided by the first aspect or any alternative of the first aspect.
  • a chip comprising programmable logic circuitry and/or program instructions for implementing virtual address determination provided by the first aspect or any of the alternatives of the first aspect when the chip is running method.
  • the virtual address determining method and apparatus, processor, and storage medium provided by the present application in the process of determining the virtual address of the target instruction, because the lower address of the target instruction is read from the instruction space of the previous instruction of the target instruction No need to calculate the lower address of the target instruction, only need to calculate the remaining address of the target instruction (the remaining address is the address of the virtual address of the target instruction except the lower address), and then merge the remaining address of the target instruction with the lower address of the target instruction.
  • the virtual address of the target instruction can be obtained, so that the calculation amount of the virtual address of the target instruction can be reduced, which helps to solve the problem that the delay of determining the virtual address of the target instruction is large, and the processing speed of the processor is slow. Small determines the delay of the virtual address of the target instruction, and improves the processing speed of the processor.
  • FIG. 1 is a schematic diagram of a pipeline of a processor according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of address mapping involved in an embodiment of the present application.
  • FIG. 3 is another schematic diagram of address mapping according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an instruction space of a direct branch instruction according to an embodiment of the present application.
  • FIG. 5 is a flowchart of a method for determining a virtual address according to an embodiment of the present application
  • FIG. 6 is a flowchart of a method for determining another virtual address provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an instruction space provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of calculating a virtual address according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another computing virtual address provided by an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for determining a virtual address determining method according to an embodiment of the present application
  • FIG. 11 is a schematic diagram of another instruction space provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of still another computing virtual address provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of still another computing virtual address provided by an embodiment of the present application.
  • FIG. 14 is a block diagram of a virtual address determining apparatus according to an embodiment of the present application.
  • FIG. 15 is a block diagram of another virtual address determining apparatus according to an embodiment of the present application.
  • 16 is a block diagram of a first determining module according to an embodiment of the present application.
  • FIG. 17 is a block diagram of still another virtual address determining apparatus according to an embodiment of the present application.
  • the central processing unit is a typical processor. Most of the central processing units operate in a pipeline.
  • the pipeline consists of a number of different pipeline stages.
  • the central processing unit includes units corresponding to each pipeline stage. Used to perform the corresponding pipeline-level operations, and different pipelines contain different pipeline stages depending on the speed requirements of the central processor and the chip process. As shown in FIG. 1, it shows a typical operation pipeline of the central processing unit. Referring to FIG.
  • the pipeline includes: fetching instructions, decoding instructions, transmitting instructions, executing instructions, accessing memory and submitting results, fetching instructions,
  • Each of the decoding instruction, the transmission instruction, the execution instruction, the access memory, and the submission result may be referred to as a pipeline stage, and the central processing unit may include an instruction fetch unit, a decoding unit, a transmitting unit, an execution unit, The access unit and the submitting unit, the fetching unit is configured to perform the fetching operation, and after fetching the fetching instruction, the instruction unit transmits the instruction to the decoding unit, the decoding unit decodes the instruction, and transmits the decoded instruction to the transmitting unit, and transmits The unit transmits the instruction to the execution unit. After the execution unit executes the instruction, the instruction is transmitted to the access unit, and the access unit accesses the memory according to the instruction, and then the submit unit submits the result.
  • the embodiment of the present application mainly relates to fetching instructions in the above pipeline. Therefore, the process of fetching instructions by the fetching unit is mainly described herein.
  • the instruction fetch unit may first determine the virtual address of the target instruction to be acquired, and then acquire the target instruction according to the virtual address of the target instruction (that is, fetch the instruction according to the virtual address).
  • a virtual address is also called a logical address.
  • a virtual address can be a PC address.
  • the instruction unit adds an address value to the virtual address of the previous instruction of the target instruction (the address value) Depending on how many instructions are fetched in one cycle and the width of each instruction, the virtual address of the target instruction is obtained, and the target instruction is obtained according to the virtual address of the target instruction. If the previous instruction of the target instruction is a branch instruction, the target instruction may or may not jump, and the instruction instruction unit may predict whether the target instruction jumps.
  • the fetch unit adds an address value to the virtual address of the previous instruction of the target instruction to obtain the virtual address of the target instruction, and fetches the instruction according to the virtual address of the target instruction. If the instruction fetch unit predicts the target instruction jump, the fetch unit needs to calculate a branch target address, and then fetches the instruction according to the jump destination address, which is also the virtual address of the target instruction. . Generally, the instruction fetch unit can add an offset address to the virtual address of the previous instruction of the target instruction to obtain the jump destination address. The offset address may be located in the previous instruction of the target instruction, or may be located in the register.
  • the previous instruction of the target instruction may be referred to as a direct branch (directbranch).
  • the instruction if the offset address is in a register, the previous instruction of the target instruction may be referred to as an indirect branch instruction.
  • the instruction fetch unit can decode the previous instruction of the target instruction to obtain an offset address, and then compare the virtual address of the previous instruction of the target instruction with the decoded offset address. Add the jump destination address.
  • the instruction instruction unit may use a branch target buffer (BTB) to predict the jump destination address, or The instruction unit waits until the subsequent execution unit reads the offset address from the register according to the previous instruction of the target instruction, and adds the virtual address of the previous instruction of the target instruction to the offset address read from the register, and then The address obtained by adding the execution units is determined as the jump destination address.
  • BTB branch target buffer
  • the execution unit may identify the instruction, and when the execution unit recognizes that the instruction is an indirect branch instruction, the execution unit reads the offset address from the register, and may be based on the offset address.
  • the jump destination address is calculated and the jump destination address is fed back to the instruction fetch unit. It should be noted that after the processor is powered on, the address reset may be performed, and the instruction fetch unit may acquire the first instruction after the processor is powered on according to the reset virtual address, and then the processor fetches the instruction according to the above method.
  • the fetching instruction unit fetching the instruction according to the virtual address of the target instruction may include: the fetching instruction unit determines the physical address of the target instruction according to the virtual address and the address mapping of the target instruction, and acquires the target from the storage space according to the physical address of the target instruction.
  • the address mapping may be a physical index physical tag (PIPT) address mapping or a virtual index physical tag (VIPT) address mapping, or may be a direct mapping.
  • FIG. 2 is a schematic diagram of address mapping involved in the embodiment of the present application.
  • the address mapping diagram may represent a PIPT address mapping or a VIPT address mapping. Referring to FIG.
  • a virtual address is stored in a virtual address space, and physical
  • the address is stored in the physical address space, where the physical address space is usually a level one instruction cache of the processor, and the mapping table is used to record the mapping relationship between the virtual address stored in the virtual address space and the physical address stored in the physical address space, and fetch instructions.
  • the unit can obtain the physical address of the target instruction according to the virtual address lookup mapping table of the target instruction. As shown in FIG. 2, in a PIPT address mapping or a VIPT address mapping, different virtual addresses can be mapped to the same physical address, and the same physical address stores the same instruction, so that the different virtual addresses have the same offset address.
  • the jump destination address obtained by adding the different virtual addresses to the offset address is different.
  • the lower address of the virtual address is equal to the lower address of the physical address, and therefore, the different virtual addresses are respectively the same.
  • FIG. 3 is another schematic diagram of address mapping involved in the embodiment of the present application.
  • the address mapping diagram may represent direct mapping.
  • the virtual address is stored in the virtual address space
  • the physical address is stored in the physical address.
  • the physical address space is usually the processor's level one instruction cache.
  • the lower address of the virtual address of the target instruction can be determined as the physical address of the target instruction.
  • determining the virtual address of the target instruction as the physical address of the target instruction specifically determining the lower address of the virtual address of the target instruction as the physical address of the target instruction, or determining the virtual address of the target instruction as the physical address of the target instruction. , can be determined according to the width of the physical address of the target instruction.
  • the address width of the processor increases continuously (for example, the address width of the processor increases from 32 bits to 64 bits), so that the calculation amount of adding the offset address to the virtual address is correspondingly increased, The delay of determining the virtual address of the target instruction is large.
  • the offset addresses included in different direct branch instructions may be different.
  • the offset addresses contained in different direct branch instructions may not be aligned in the instruction space.
  • the width of the offset address is the virtual address of the previous instruction of the target instruction. The width may be different. Before adding the offset address to the virtual address of the previous instruction of the target instruction, the offset address needs to be sign-extended so that the width of the offset address is the virtual address of the previous instruction of the target instruction.
  • the width is equal, and the offset address is aligned with the virtual address of the previous instruction of the target instruction, and then the bit address is added by bit to the virtual address of the previous instruction of the target instruction to obtain the virtual address of the target instruction, which results in The delay in determining the virtual address of the target instruction is further increased.
  • FIG. 4 shows a schematic diagram of a direct branch instruction according to an embodiment of the present application.
  • the instruction BL is a direct branch instruction, and the instruction field of each instruction is the 0th bit to the 31st bit, imm* represents the instruction space in which the offset address is stored, and * represents the width of the offset address. As shown in FIG.
  • the width of the offset address included in the instruction B.cond, the width of the offset address included in the instruction CBNZ, and the width of the offset address included in the instruction CBZ are both 19 bits, and the instruction B.cond
  • the instruction space in which the offset address is stored, the instruction space in which the offset address is stored in the instruction CBNZ, and the instruction space in which the offset address is stored in the instruction CBZ are the 5th to 23rd bits, and the width of the offset address included in the instruction TBNZ
  • the offset address included in the instruction TBZ is 14 bits wide, and the instruction space in which the offset address is stored in the instruction TBNZ and the instruction space in which the offset address is stored in the instruction TBZ are all 5th to 18th bits, and the instruction B is
  • the width of the included offset address and the width of the offset address included in the instruction BL are both 26 bits, and the instruction space in which the offset address is stored in the instruction B and the instruction space in which the offset address is stored in the instruction BL are all the 0
  • the instruction fetch unit symbolically expands the offset address, and then adds the offset address to the virtual address of the previous instruction of the target instruction by bit to obtain the virtual of the target instruction.
  • the address can be expressed by the following equation (1):
  • br_trgt[63:0] represents the virtual address of the target instruction (that is, the jump destination address)
  • cur_pc[63:0] represents the virtual address of the previous instruction of the target instruction
  • * indicates a partial The width of the shift address
  • imm[*] indicates the sign of the offset address (that is, the sign of the highest bit of the offset address)
  • imm[(*-1):0] indicates the offset address
  • ⁇ (64-*) ⁇ imm[*] ⁇ is a sign extension of the offset address, indicating that imm[*] is copied (64-*) bits
  • imm[(*-1) :0] ⁇ indicates the extended offset address.
  • imm[(*-1):0] 10101010101010101010
  • imm[*] 1
  • ⁇ (64-*) ⁇ imm[*] ⁇ imm[(*-1):0] ⁇ indicates that the copied 50-bit 1 is added to the high bit of 101010101010 to obtain an extended offset. address.
  • imm[*] if imm[*] is 0, the equation (1) represents a 64-bit virtual address (ie, the virtual address of the previous instruction of the target instruction) and 64 bits.
  • the offset addresses (ie, the extended offset addresses) are added to obtain a 64-bit virtual address (ie, the virtual address of the target instruction). If imm[*] is 1, the equation (1) represents 64 bits. The virtual address is subtracted from the 64-bit offset address to obtain a 64-bit virtual address.
  • the jump target address is calculated by the instruction unit according to the offset address in the direct branch instruction and the virtual address of the previous instruction of the target instruction, or is the execution unit according to the offset address and the target instruction.
  • the virtual address of the previous instruction is calculated, or the instruction fetch unit is predicted by the BTB. Due to the increase of the address width of the processor, the delay of determining the jump destination address is large, and in addition, in the same stage pipeline. In addition to determining the jump destination address, other logical operations are required, which causes the processor to process the instruction with a large delay, which directly affects the processing speed of the processor.
  • the virtual address determining method and apparatus, the processor, and the storage medium provided by the embodiments of the present application predict to calculate a partial address in the virtual address of the target instruction before fetching the instruction, and only need to calculate the virtual address of the target instruction in the process of fetching instructions.
  • the remaining address in the middle and then combine the predicted partial address with the remaining address to obtain the virtual address of the target instruction (that is, the jump destination address). Since the partial address is expected to be calculated, the address to be calculated in the process of fetching the instruction is required.
  • the smaller width can reduce the delay of determining the jump destination address and improve the processing speed of the processor.
  • the target instruction is an instruction that needs to be acquired
  • the “previous instruction” is a noun
  • the previous instruction is the previous instruction of the target instruction
  • the previous instruction is before the target instruction is acquired. It has been obtained, and in the following embodiments, all lower address, all median address, all upper address and all offset addresses refer to a virtual address, and the offset address refers to the previous instruction. Offset address.
  • FIG. 5 is a flowchart of a method for determining a virtual address according to an embodiment of the present application.
  • the virtual address determining method may be used to determine a virtual address of a target instruction. Referring to Figure 5, the method includes:
  • Step 501 Calculate a lower address of the target instruction to be acquired.
  • the instruction fetch unit may calculate the lower address of the target instruction according to the lower address of the virtual address of the previous instruction of the target instruction and the offset address included in the previous instruction of the target instruction.
  • the width of the lower address may be determined according to the address mapping method, the size of the page table, and the width of the offset address included in the previous instruction of the target instruction.
  • the instruction fetch unit can calculate the lower address of the target instruction in a different manner.
  • the address mapping is a PIPT address mapping or a VIPT address mapping
  • the instruction fetch unit may calculate the target instruction according to the lower address of the previous instruction of the target instruction and the lower address of the offset address included in the previous instruction of the target instruction.
  • the calculation process can refer to the following embodiment shown in FIG. 6.
  • the instruction fetch unit can be based on the lower address of the previous instruction of the target instruction and the bias of the previous instruction of the target instruction.
  • the address of the target address is calculated by shifting the address.
  • Step 502 Store the lower address of the target instruction to the instruction space of the previous instruction of the target instruction.
  • the instruction fetch unit can store the lower address of the target instruction to the instruction space of the previous instruction of the target instruction, so as to directly read the low address of the target instruction from the instruction space of the previous instruction of the target instruction when subsequently determining the virtual address of the target instruction.
  • the address thereby saving the time for calculating the lower address of the target instruction, and reducing the delay of determining the virtual address of the target instruction.
  • Step 503 Write the previous instruction of the target instruction into the first-level instruction cache.
  • the first level instruction cache is a level 1 cache for storing instructions, and the level 1 cache and the main memory (the instruction fetch unit can be a unit in the main memory) have a faster interaction speed. Therefore, the instruction fetch unit can target the instruction.
  • the previous instruction is written to the level one instruction cache so that the previous instruction of the target instruction can be quickly read during the instruction fetching process.
  • the lower address stored in the instruction space of the different instruction is aligned in the 0th bit of the instruction space, and therefore, the lower address stored in the instruction space of the previous instruction of the target instruction is in the The 0th bit of the instruction space of the previous instruction is aligned, that is, the lower address of the target instruction is aligned with the 0th bit of the instruction space of the previous instruction of the target instruction.
  • Step 504 Read the lower address of the target instruction from the instruction space of the previous instruction of the target instruction.
  • the fetching unit can read the lower address of the target instruction from the instruction space of the previous instruction of the target instruction. According to steps 501 to 503, it is not difficult to understand that the lower address of the target instruction is The address of the instruction instruction space of the previous instruction is calculated and stored before the previous instruction of the target instruction is written to the level one instruction cache.
  • Step 505 Determine the remaining address of the target instruction, the sum of the width of the remaining address of the target instruction and the width of the lower address of the target instruction is equal to the width of the virtual address of the previous instruction of the target instruction.
  • the instruction fetch unit After the instruction fetch unit reads the lower address of the target instruction from the instruction space of the previous instruction of the target instruction, the remaining address of the target instruction can be determined, and the instruction fetch unit can use the width of the virtual address of the previous instruction of the target instruction minus the target.
  • the width of the lower address of the instruction gets the width of the remaining address of the target instruction, which in turn determines the remaining address of the target instruction.
  • the primary instruction cache uses the PIPT address mapping or the VIPT address mapping
  • the remaining address includes a median address and a high address
  • the process of the instruction unit determining the remaining address of the target instruction may be implemented by using the following FIG.
  • the remaining address includes a high-order address
  • the process of the instruction unit determining the remaining address of the target instruction may refer to the embodiment shown in FIG. 10 described below.
  • Step 506 Combine the lower address of the target instruction with the remaining address of the target instruction to obtain a virtual address of the target instruction.
  • the instruction fetch unit reads the lower address of the target instruction from the instruction space of the previous instruction of the target instruction, and after determining the remaining address of the target instruction, the lower address of the target instruction can be merged with the remaining address of the target instruction to obtain the target instruction.
  • Virtual address the instruction fetch unit may merge the lower address of the target instruction with the remaining address of the target instruction according to the address bit, and in the same virtual address, the address bits are sequentially raised from right to left. For example, the instruction fetch unit arranges the remaining address of the target instruction at the upper bit of the lower address of the target instruction to obtain the virtual address of the target instruction.
  • the virtual address determining method provided by the embodiment of the present application in the process of determining the virtual address of the target instruction, is that the lower address of the target instruction is read from the instruction space of the previous instruction of the target instruction. There is no need to calculate the lower address of the target instruction, only the remaining address of the target instruction (the remaining address is the address other than the lower address in the virtual address of the target instruction), and then the remaining address of the target instruction is merged with the lower address of the target instruction.
  • the virtual address of the target instruction can be obtained, so that the calculation amount of the virtual address of the target instruction can be reduced, which helps to solve the problem that the delay of determining the virtual address of the target instruction is large, and the processing speed of the processor is slow, and the problem is reduced. Determine the delay of the virtual address of the target instruction and increase the processing speed of the processor.
  • FIG. 6 is a flowchart of another method for determining a virtual address according to an embodiment of the present application.
  • the virtual address determining method may be used to determine a virtual address of a target instruction, and FIG. 6 maps the address to a PIPT.
  • the address mapping or the VIPT address mapping is described as an example.
  • the remaining addresses of the target instruction may include a median address and a high address. Referring to Figure 6, the method includes:
  • Step 601 Determine a virtual address of a previous instruction of the target instruction and an offset address included in a previous instruction of the target instruction.
  • the fetching unit usually fetches an instruction according to the virtual address of the instruction. Therefore, when the fetching unit fetches the previous instruction of the target instruction, the virtual address of the previous instruction of the target instruction is for the fetching unit.
  • the previous instruction of the target instruction includes an offset address, and the instruction fetch unit can decode the previous instruction of the target instruction to obtain the offset address included in the previous instruction of the target instruction.
  • Step 602 Determine, according to the size of the page table, the lower address of the previous instruction of the target instruction from the virtual address of the previous instruction of the target instruction, and determine the target instruction from the offset address included in the previous instruction of the target instruction. The lower address of the offset address contained in the previous instruction.
  • the lower address of the previous instruction of the target instruction is aligned with the lower address of the offset address included in the previous instruction of the target instruction and has the same width.
  • the size of the page table is also the granularity of the page table, and the size of the page table may be represented as 2n, where n is an integer greater than or equal to 1, and the n is the width of the lower address.
  • the instruction fetch unit may determine the lowest n bits of the virtual address of the previous instruction of the target instruction as the lower address of the previous instruction of the target instruction, and determine the lowest n bits of the offset address included in the previous instruction of the target instruction.
  • the lower address of the offset address where the virtual address is a PC address.
  • n is equal to 12
  • the fetch unit can determine the lowest 12 bits of the virtual address of the previous instruction of the target instruction as the lower address of the previous instruction, and the target instruction is The lowest 12 bits of the offset address contained in an instruction are determined as the lower address of the offset address.
  • cur_pc represents the virtual address of the last instruction of the target instruction (since the virtual address of the previous instruction of the target instruction is known when determining the virtual address of the target instruction, the target instruction
  • the virtual address of the previous instruction can be represented by cur_pc)
  • imm represents the offset address contained in the previous instruction of the target instruction
  • cur_pc_lo represents the lower address of the previous instruction of the target instruction
  • imm_lo represents the previous instruction included in the target instruction.
  • cur_pc_lo can be the lowest n bits of cur_pc
  • imm_lo can be the lowest n bits of imm.
  • Step 603 adding the lower address of the previous instruction of the target instruction to the lower address of the offset address included in the previous instruction of the target instruction to obtain the lower address of the target instruction.
  • the instruction fetch unit can add the lower address of the previous instruction of the target instruction to the lower address of the offset address included in the previous instruction of the target instruction to obtain the lower address of the target instruction, and the lower address and the target of the target instruction.
  • the lower address of the previous instruction of the instruction is aligned and the width is equal. For example, when the lower address of the previous instruction of the target instruction is the lowest 12 bits of the virtual address of the previous instruction of the target instruction, and the lower address of the offset address is the lowest 12 bits of the offset address, the low order of the target instruction The address is also 12 bits, and the lower address of the target instruction is aligned with the lower address of the previous instruction of the target instruction.
  • the virtual address is a PC address
  • br_trgt represents a virtual address of the target instruction
  • br_trgt_lo represents a lower address of the target instruction
  • cur_pc_lo represents a lower address of a previous instruction of the target instruction
  • imm_lo represents a previous instruction included in the target instruction.
  • the lower address of the offset address, br_trgt_lo is the lower address of the target instruction obtained by adding cur_pc_lo and imm_lo
  • br_trgt_lo is aligned with cur_pc_lo and has the same width.
  • steps 601 to 603 can be understood as the refinement of step 501 in the embodiment shown in FIG. 5 when the address mapping is a PIPT address mapping or a VIPT address mapping.
  • Step 604 Store the lower address of the target instruction to the instruction space of the previous instruction of the target instruction.
  • the lower address stored in the instruction space of different instructions is aligned in the 0th bit of the instruction space.
  • the instruction fetching unit may first adjust the offset address stored in the instruction space of the previous instruction of the target instruction, so that the offset address is aligned in the 0th bit of the instruction space of the previous instruction, and then Deleting the lower address of the offset address results in an idle instruction space, and stores the lower address of the target instruction into the free instruction space, thereby aligning the lower address stored in the instruction space of the different instructions in the 0th bit of the instruction space.
  • FIG. 7 shows a schematic diagram of an instruction space provided by an embodiment of the present application.
  • an instruction B.cond an instruction CBNZ, an instruction CBZ, an instruction TBNZ, an instruction TBZ, an instruction B, and an instruction.
  • the instruction space of each instruction is the 0th bit to the 31st bit
  • the instruction B.cond, the instruction CBNZ, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B, and the instruction BL all store the lower address, and the different instructions
  • the lower address stored in the instruction space can be the lower address of the instruction target space.
  • the lower address stored in the instruction space of the instruction B.cond, the instruction CBNZ, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B and the instruction BL is aligned in the 0th bit of the instruction space.
  • the previous instruction of the target instruction may be the instruction B.cond in FIG. 7, and the lower address of the target instruction may be br_trgt_lo[11:0] in the instruction space of the instruction B.cond, br_trgt_lo[11 :0] indicates that the lower address of the target instruction has a width of 12 bits, and the lower address of the target instruction starts from the 0th bit of the previous instruction of the target instruction. 4 and FIG.
  • the instruction fetch unit adjusts the offset address stored in the instruction space of the instruction B.cond shown in FIG. 4 from the 5th bit to the 23rd bit to the 0th bit to the 18th bit. And deleting the lowest 12 bits of the offset address to obtain an idle instruction space, the free instruction space is from the 0th bit to the 11th bit of the instruction B.cond, and the fetching unit stores br_trgt_lo[11:0] to the Free instruction space.
  • the case of the instruction CBNZ, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B, and the instruction BL is similar to the instruction B.cond, and will not be described herein.
  • the instruction fetch unit in the process of storing the lower address of the target instruction to the instruction space of the previous instruction of the target instruction, for the remaining address of the offset address, usually only adjusts the remaining address of the offset address in the instruction space.
  • imm_hi[6:0] represents the upper address of the offset address
  • br_trgt_lo[11:0] into the instruction space of the instruction B.cond, the instruction unit is fetched.
  • Step 605 Store the lower carry into the extended instruction space.
  • the lower carry is a carry generated by adding the lower address of the previous instruction of the target instruction to the lower address of the offset address included in the previous instruction of the target instruction, and the lower carry can be 0 or 1, When the lower carry is 0, it can be understood that the carry is not generated in the process of adding the lower address of the previous instruction of the target instruction to the lower address of the offset address included in the previous instruction of the target instruction.
  • the extended instruction space is an instruction space obtained by expanding the instruction space of the previous instruction.
  • the fetching unit may expand the instruction space of the previous instruction of the target instruction to expand the instruction space, and then store the lower carry into the extended instruction space.
  • the instruction instruction unit may expand the instruction space of the instruction B.cond to obtain the instruction space of the 32nd bit, and store the low-order carry to In the instruction space of the 32nd bit of the instruction B.cond.
  • the lower carry is stored in the extended instruction space, and the lower carry can be added to the remaining address of the previous instruction of the target instruction in the process of determining the remaining address of the target instruction, thereby quickly calculating The remaining address of the target instruction.
  • Step 606 Write the previous instruction of the target instruction into the first level instruction cache.
  • the lower address stored in the instruction space of different instructions is aligned in the 0th bit of the instruction space.
  • the instruction B.cond, the instruction CBNZ, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B, and the instruction BL shown in FIG. 7 may all be instructions in the level one instruction cache, the instruction CBNZ, the instruction CBZ, the instruction TBNZ, The lower bits stored in the instruction TBZ, instruction B, and instruction BL are aligned in the 0th bit of the instruction space.
  • the instruction fetching unit may call the write command of the processor to write the previous instruction of the target instruction to the first-level instruction cache. For detailed writing process, reference may be made to related technologies, and details are not described herein again.
  • steps 601 to 606 are generally performed before the instruction fetch unit acquires the target instruction, and the following steps 607 to 614 are processes for determining the virtual address of the target instruction by the fetching unit, and the steps 607 to 614 are performed. This can occur during the fetch unit's acquisition of the target instruction.
  • Step 607 Read the lower address of the target instruction from the instruction space of the previous instruction of the target instruction.
  • the lower address of the target instruction is an address calculated and stored in the instruction space of the previous instruction before the previous instruction of the target instruction is written into the level one instruction cache.
  • the fetching instruction unit may call the read command of the processor to read the lower address of the target instruction from the instruction space of the previous instruction of the target instruction, and the detailed reading process may refer to related technologies, and the embodiment does not stop here. Narration.
  • Step 608 Determine an upper address of an offset address included in a previous instruction of the target instruction from an offset address included in a previous instruction of the target instruction.
  • the offset address included in the previous instruction of the target instruction is composed of the upper address of the offset address and the lower address of the offset address.
  • the instruction fetch unit may determine, in the offset address, an address other than the lower address of the offset address determined in the above step 602 as the upper address of the offset address. For example, if the previous instruction of the target instruction includes an offset address of 19 bits, and the lower address of the offset address included in the previous instruction of the target instruction is the lowest 12 bits of the offset address, the target instruction
  • the upper address of the offset address included in the previous instruction is the address of the 19-bit offset address except the lowest 12 bits, that is, the high bit of the offset address included in the previous instruction of the target instruction.
  • the address is the highest 7 bits of the offset address.
  • the virtual address is a PC address
  • imm represents an offset address included in a previous instruction of the target instruction
  • imm_lo represents a lower address of the offset address included in the previous instruction of the target instruction
  • imm_hi represents the target instruction.
  • the upper address of the offset address contained in an instruction, imm_hi can be an address other than imm_lo in imm.
  • the relationship of imm, imm_hi, and imm_lo can be expressed by the following equation (2):
  • Step 609 Determine a median address of a previous instruction of the target instruction from the virtual address of the previous instruction of the target instruction according to the upper address of the offset address included in the previous instruction of the target instruction.
  • the median address of the previous instruction of the target instruction is aligned with the upper address of the offset address included in the previous instruction of the target instruction and has the same width.
  • the instruction fetching unit may determine, in the virtual address of the previous instruction of the target instruction, a portion aligned with the upper address of the offset address and having the same width as the median address of the previous instruction of the target instruction, and the instruction of the previous instruction of the target instruction The median address is contiguous with the lower address of the previous instruction of the target instruction.
  • the fetching unit may determine the d bit adjacent to the lower address of the previous instruction of the target instruction as the median address of the previous instruction of the target instruction, and d represents the width of the upper address of the offset address.
  • the instruction fetch unit can set the virtual address of the previous instruction of the target instruction with the previous one of the target instruction.
  • the 7 bits adjacent to the lower address of the instruction are determined as the median address of the previous instruction of the target instruction.
  • cur_pc represents the virtual address of the previous instruction of the target instruction
  • cur_pc_lo represents the lower address of the previous instruction of the target instruction
  • cur_pc_mid represents the median address of the previous instruction of the target instruction
  • imm_hi represents The upper address of the offset address contained in the previous instruction of the target instruction
  • cur_pc_mid is the d bit adjacent to cur_pc_lo in cur_pc
  • cur_pc_mid is aligned with imm_hi and the width is equal.
  • Step 610 Read a low carry from the extended instruction space.
  • the extended instruction space is an instruction space obtained by extending the instruction space of the previous instruction, and the extended instruction space is an instruction space in the first-level instruction cache, and the low-level carry is also stored in the extended instruction space in step 605. carry.
  • the instruction fetch unit can call the read command of the processor to read the lower carry from the extended instruction space.
  • Step 611 adding the median address of the previous instruction of the target instruction, the upper address of the offset address included in the previous instruction of the target instruction, and the lower carry, to obtain the median address of the target instruction.
  • the instruction fetch unit may add the median address of the previous instruction of the target instruction, the upper address and the lower carry of the offset address included in the previous instruction of the target instruction, and add the bitwise address to obtain the median address of the target instruction.
  • the median address of the target instruction is aligned with the median address of the previous instruction of the target instruction and the width is equal. For example, when the median address of the previous instruction of the target instruction is the virtual address of the previous instruction of the target instruction, 7 bits adjacent to the lower address of the previous instruction, and the upper address of the offset address is offset When the address is the highest 7 bits, the median address of the target instruction is also 7 bits, and the median address of the target instruction is aligned with the median address of the previous instruction of the target instruction.
  • the virtual address is a PC address
  • br_trgt represents the virtual address of the target instruction
  • br_trgt_mid represents the median address of the target instruction
  • cur_pc_mid represents the median address of the previous instruction of the target instruction
  • imm_hi represents the previous instruction of the target instruction.
  • the upper address of the included offset address, C1 represents the low carry
  • br_trgt_mid is the median address of the target instruction obtained by adding cur_pc_mid, imm_hi and C1
  • br_trgt_mid is aligned with cur_pc_mid and the width is equal.
  • Step 612 Determine a high address of a previous instruction of the target instruction from a virtual address of a previous instruction of the target instruction.
  • the virtual address of the previous instruction of the target instruction is composed of the upper address of the previous instruction of the target instruction, the median address of the previous instruction of the target instruction, and the lower address of the previous instruction of the target instruction.
  • the fetching unit may set the virtual address of the previous instruction of the target instruction, in addition to the lower address of the previous instruction of the target instruction determined by 602 above, and the median address of the previous instruction of the target instruction determined in step 609 above.
  • the address is determined as the upper address of the previous instruction of the target instruction. For example, assuming that the virtual address of the previous instruction of the target instruction is 64 bits, the lower address of the previous instruction of the target instruction is the lowest 12 bits of the virtual address of the previous instruction, and the median address of the previous instruction of the target instruction. For the 7 bits adjacent to the lowest 12 bits of the virtual address of the previous instruction, the upper address of the previous instruction of the target instruction is the highest 45 bits of the virtual address of the previous instruction of the target instruction.
  • cur_pc_lo the lower address of the previous instruction of the target instruction
  • cur_pc_mid the median address of the previous instruction of the target instruction
  • cur_pc_hi The upper address of the previous instruction of the target instruction
  • cur_pc_hi the address in cur_pc except for cur_pc_lo and cur_pc_mid.
  • equation (3) the relationship of cur_pc, cur_pc_lo, cur_pc_mid, and cur_pc_hi can be expressed by the following equation (3):
  • cur_pc ⁇ cur_pc_hi, cur_pc_mid, cur_pc_lo ⁇ .
  • Step 613 Determine a high-order address of the target instruction according to the median carry, the upper address of the previous instruction of the target instruction, and the symbol of the offset address included in the previous instruction of the target instruction.
  • the median carry is a carry generated by adding the median address of the previous instruction of the target instruction, the upper address of the offset address included in the previous instruction of the target instruction, and the lower carry.
  • the median carry can be 0 or 1.
  • the median carry it can be understood as: adding the median address of the previous instruction of the target instruction, the upper address and the lower carry of the offset address included in the previous instruction of the target instruction by bit. There is no carry in the process.
  • the sign of the offset address is the sign of the most significant bit of the offset address, and the sign of the offset address may be 0 or 1.
  • the instruction fetch unit determines, according to the median carry, the upper address of the previous instruction of the target instruction, and the symbol of the offset address included in the previous instruction of the target instruction, the upper address of the target instruction may include: the median carry is 1 and the offset address symbol is 0, the instruction fetch unit determines that the upper address of the target instruction is equal to the upper address of the previous instruction of the target instruction plus one; the middle carry is 0 and the sign of the offset address is 0, or, When the bit carry is 1 and the sign of the offset address is 1, the instruction fetch unit determines that the upper address of the target instruction is equal to the upper address of the previous instruction of the target instruction; when the median carry is 0 and the sign of the offset address is 1, The instruction unit determines that the upper address of the target instruction is equal to the upper address of the previous instruction of the target instruction minus one.
  • the virtual address is a PC address
  • br_trgt represents a virtual address of the target instruction
  • br_trgt_hi represents a high-order address of the target instruction
  • imm[*] represents a symbol of the offset address
  • cur_pc_hi represents a high-order address of a previous instruction of the target instruction
  • C2 represents the median carry
  • steps 608 to 613 can be understood as the refinement of step 505 in the embodiment shown in FIG. 5 when the address mapping is a PIPT address mapping or a VIPT address mapping.
  • Step 614 Combine the lower address of the target instruction, the median address of the target instruction, and the upper address of the target instruction to obtain a virtual address of the target instruction.
  • the instruction fetch unit may combine the lower address of the target instruction, the median address of the target instruction, and the upper address of the target instruction according to the address bit to obtain a virtual address of the target instruction, and in the same virtual address, the address bit Raise from right to left.
  • the instruction fetch unit arranges the median address of the target instruction at the upper bit of the lower address of the target instruction, and arranges the upper address of the target instruction at the upper bit of the median address of the target instruction to obtain the virtual address of the target instruction.
  • br_trgt represents a virtual address of the target instruction
  • br_trgt_lo represents a lower address of the target instruction
  • br_trgt_mid represents a median address of the target instruction
  • br_trgt_hi represents a high-order address of the target instruction
  • br_trgt ⁇ br_trgt_hi, br_trgt_mid, br_trgt_lo ⁇ .
  • the virtual address determining method provided by the embodiment of the present application in the process of determining the virtual address of the target instruction, is that the lower address of the target instruction is read from the instruction space of the previous instruction of the target instruction. There is no need to calculate the lower address of the target instruction, only the remaining address of the target instruction (the remaining address is the address other than the lower address in the virtual address of the target instruction), and then the remaining address of the target instruction is merged with the lower address of the target instruction.
  • the virtual address of the target instruction can be obtained, so that the calculation amount of the virtual address of the target instruction can be reduced, which helps to solve the problem that the delay of determining the virtual address of the target instruction is large, and the processing speed of the processor is slow, and the problem is reduced. Determine the delay of the virtual address of the target instruction and increase the processing speed of the processor.
  • the virtual address determining method provided in the embodiment of the present invention greatly reduces the address width of the virtual address in the process of determining the virtual address, and reduces the delay of determining the virtual address.
  • the solution provided by the embodiment of the present application does not need to increase the pipeline level. To avoid delays due to increased pipeline levels and to avoid processor performance degradation due to exceptions, prediction errors, and cache misses.
  • FIG. 6 The solution provided by the embodiment shown in FIG. 6 is exemplified below with reference to FIG. 8 and FIG. 9.
  • 8 and 9 show the virtual address as the PC address, and FIG. 8 shows the offset address as 0, and FIG. 9 shows the offset address as 1 as an example.
  • cur_pc represents the PC address of the previous instruction of the target instruction
  • cur_pc_lo represents the lower address of the previous instruction of the target instruction
  • cur_pc_mid represents the median address of the previous instruction of the target instruction
  • cur_pc_hi represents the target.
  • the upper address of the previous instruction of the instruction; imm indicates the offset address contained in the previous instruction of the target instruction
  • imm_lo indicates the lower address of the offset address contained in the previous instruction of the target instruction
  • imm_hi indicates the previous instruction of the target instruction.
  • br_trgt represents the PC address of the target instruction
  • br_trgt_lo represents the lower address of the target instruction
  • br_trgt_mid represents the median address of the target instruction
  • br_trgt_hi represents the upper address of the target instruction
  • the imm may be first sign extended according to the symbol of imm so that the width of the imm is equal to the width of the cur_pc.
  • the scheme stores br_trgt_lo to the instruction space of the previous instruction of the target instruction, and stores C1 into the extended instruction space according to the scheme provided in step 605; finally, writes the previous instruction of the target instruction to the first-level instruction cache according to the scheme provided in step 606. .
  • br_trgt_hi cur_pc_hi
  • br_trgt_lo in the process of determining br_trgt, br_trgt_lo can be read from the instruction space of the previous instruction of the target instruction, and br_trgt_hi can be based on C2 and the symbols of the offset address in cur_pc_hi+1, cur_pc_hi, and cur_pc_hi-1.
  • br_trgt_mid needs to be calculated, and br_trgt_lo, br_trgt_mid and br_trgt_hi can be combined to obtain br_trgt, which greatly reduces the delay of determining br_trgt.
  • FIG. 10 is a flowchart of still another method for determining a virtual address according to an embodiment of the present application.
  • the virtual address determining method may be used to determine a virtual address of a target instruction.
  • the mapping is described as an example. In the direct mapping, the remaining address of the target instruction may include a high address.
  • the method includes:
  • Step 1001 Determine a virtual address of a previous instruction of the target instruction and an offset address included in a previous instruction of the target instruction.
  • step 100 For the implementation of the step 1001, reference may be made to the step 601 of the embodiment shown in FIG. 6, which is not described herein again.
  • Step 1002 Determine a lower address of a previous instruction of the target instruction according to an offset address included in a previous instruction of the target instruction.
  • the lower address of the previous instruction of the target instruction is aligned with the offset address included in the previous instruction of the target instruction and has the same width.
  • the instruction fetch unit may be the lowest w of the virtual address of the previous instruction of the target instruction.
  • the bit is determined as the lower address of the previous instruction of the target instruction, wherein the virtual address is a PC address.
  • cur_pc_lo can be the lowest w bit of cur_pc, which is aligned with imm and has the same width.
  • Step 1003 Add the lower address of the previous instruction of the target instruction and the offset address included in the previous instruction of the target instruction to obtain the lower address of the target instruction.
  • the instruction fetch unit may add the lower address of the previous instruction of the target instruction to the offset address included in the previous instruction of the target instruction to obtain the lower address of the target instruction, and the lower address of the target instruction and the target instruction
  • the lower address of an instruction is aligned and the width is equal.
  • the lower address of the previous instruction of the target instruction is the lowest w bit of the virtual address of the previous instruction of the target instruction, and the offset address is w bits
  • the lower address of the target instruction is also w bits.
  • the lower address of the target instruction is aligned with the lower address of the previous instruction of the target instruction.
  • br_trgt represents a virtual address of the target instruction
  • br_trgt_lo represents a lower address of the target instruction
  • imm represents an offset address included in a previous instruction of the target instruction
  • br_trgt_lo is added to the im_cur_pc_lo and the imm
  • the lower address of the resulting target instruction, br_trgt_lo is aligned with cur_pc_lo and has the same width.
  • steps 1001 to 1003 can be understood as the refinement of step 501 in the embodiment shown in FIG. 5 when the address mapping is direct mapping.
  • Step 1004 Store the lower address of the target instruction to the instruction space of the previous instruction of the target instruction.
  • the lower address stored in the instruction space of different instructions is aligned in the 0th bit of the instruction space.
  • the instruction fetching unit may first adjust the offset address stored in the instruction space of the previous instruction of the target instruction, so that the offset address is aligned in the 0th bit of the instruction space of the previous instruction, and then Deleting the lower address of the offset address results in an idle instruction space, and stores the lower address of the target instruction into the free instruction space, thereby aligning the lower address stored in the instruction space of the different instructions in the 0th bit of the instruction space.
  • FIG. 11 shows a schematic diagram of an instruction space provided by an embodiment of the present application.
  • an instruction B.cond an instruction CBNZ, an instruction CBZ, an instruction TBNZ, an instruction TBZ, an instruction B, and an instruction.
  • the instruction space of each instruction is the 0th bit to the 31st bit
  • the instruction B.cond, the instruction CBNZ, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B, and the instruction BL all store the lower address, and the different instructions
  • the lower address stored in the instruction space can be the lower address of the instruction target space.
  • the lower address stored in the instruction space of the instruction B.cond, the instruction CBNZ, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B and the instruction BL is aligned in the 0th bit of the instruction space.
  • the previous instruction of the target instruction may be the instruction CBNZ in FIG. 11, and the lower address of the target instruction may be br_trgt_lo[18:0] in the instruction space of the instruction CBNZ, and br_trgt_lo[18:0] represents
  • the lower address of the target instruction has a width of 19 bits, and the lower address of the target instruction starts from the 0th bit of the previous instruction of the target instruction. 4 and FIG.
  • the instruction fetch unit adjusts the offset address stored in the instruction space of the instruction CBNZ shown in FIG. 4 from the 5th bit to the 23rd bit to the 0th bit to the 18th bit, and deletes The offset address obtains an idle instruction space, which is the space from the 0th bit to the 18th bit of the instruction CBNZ, and the fetching unit stores br_trgt_lo[18:0] into the idle instruction space.
  • the case of the instruction B.cond, the instruction CBZ, the instruction TBNZ, the instruction TBZ, the instruction B, and the instruction BL is similar to the case of the instruction CBNZ, and will not be described herein.
  • Step 1005 Determine a high address of a previous instruction of the target instruction from a virtual address of a previous instruction of the target instruction.
  • the virtual address of the previous instruction of the target instruction is composed of the upper address of the previous instruction and the lower address of the previous instruction.
  • the instruction fetch unit may determine, in the virtual address of the previous instruction of the target instruction, an address other than the lower address determined in the above step 1002 as the upper address of the previous instruction of the target instruction. For example, assuming that the virtual address of the previous instruction of the target instruction is 64 bits, and the lower address of the previous instruction of the target instruction is the lowest 19 bits of the virtual address of the previous instruction, the upper address of the previous instruction of the target instruction For the 64 bits, the address other than the lowest 19 bits, that is, the upper address of the previous instruction of the target instruction is the highest 45 bits of the virtual address of the previous instruction.
  • cur_pc_hi is An address other than cur_pc_lo in cur_pc.
  • the relationship of cur_pc, cur_pc_lo, and cur_pc_hi can be expressed by the following equation (5):
  • cur_pc ⁇ cur_pc_hi, cur_pc_lo ⁇ .
  • Step 1006 Determine the upper address of the target instruction according to the lower carry, the upper address of the previous instruction of the target instruction, and the symbol of the offset address included in the previous instruction of the target instruction.
  • the lower carry is a carry generated by adding the lower address of the previous instruction of the target instruction and the offset address included in the previous instruction of the target instruction, and the lower carry can be 0 or 1, when the low bit is When the carry is 0, it can be understood that there is no carry in the process of adding the lower address of the previous instruction of the target instruction to the offset address included in the previous instruction of the target instruction.
  • the sign of the offset address is the sign of the most significant bit of the offset address, and the sign of the offset address may be 0 or 1.
  • the instruction fetch unit determines, according to the lower carry, the upper address of the previous instruction of the target instruction, and the symbol of the offset address included in the previous instruction of the target instruction, determining that the upper address of the target instruction may include: when the low carry is 1 And when the sign of the offset address is 0, the instruction fetch unit determines that the upper address of the target instruction is equal to the upper address of the previous instruction of the target instruction plus one; when the lower carry is 0 and the sign of the offset address is 0, or the low carry
  • the instruction fetch unit determines that the upper address of the target instruction is equal to the upper address of the previous instruction of the target instruction; when the lower carry is 0 and the sign of the offset address is 1, the instruction fetch unit It is determined that the upper address of the target instruction is equal to the upper address of the previous instruction of the target instruction minus one.
  • the virtual address is a PC address
  • br_trgt represents a virtual address of the target instruction
  • br_trgt_hi represents a high-order address of the target instruction
  • imm[*] represents a symbol of the offset address
  • cur_pc_hi represents a high-order address of a previous instruction of the target instruction
  • C1 represents a low carry
  • Step 1007 Generate an address indication symbol, and the address indication symbol indicates a high address of the target instruction.
  • the fetching unit may generate an address indication symbol indicating the upper address of the target instruction.
  • the address indication symbol may be represented by br_trgt_hi_sel, and the address indication symbol may be 2 bits.
  • the address indication symbol may be 00, 01 or 10, 00 indicating that the upper address of the target instruction is equal to cur_pc_hi, 01 indicates the target instruction.
  • the upper address is equal to cur_pc_hi+1, and 10 indicates that the upper address of the target instruction is equal to cur_pc_hi-1.
  • the address indication symbol provided by the embodiment of the present application is merely exemplary. In an actual application, the address indication symbol may be embodied in other forms. The embodiment of the present application does not limit the address indication symbol.
  • Step 1008 Store the address indication symbol into the extended instruction space.
  • the instruction space of the previous instruction of the target instruction may be extended to expand the instruction space, and then the address indication symbol is stored in the extended instruction space, so as to facilitate the process of subsequently determining the virtual address of the target instruction.
  • the address indication symbol is read from the extended instruction space, and the upper address of the target instruction is determined according to the address indication symbol, the delay of calculating the upper address of the target instruction is saved, and the delay of determining the virtual address of the target instruction is reduced.
  • the instruction instruction unit may expand the instruction space of the instruction CBNZ to obtain the instruction space of the 32nd bit and the 33rd bit, and store the address indication symbol. Up to the instruction space of the 32nd and 33rd bits of the instruction CBNZ.
  • Step 1009 Write the previous instruction of the target instruction into the level one instruction cache.
  • step 1009 For the implementation process of the step 1009, reference may be made to the step 606 of the embodiment shown in FIG. 6, which is not described herein again.
  • steps 1001 to 1009 are generally performed before the instruction fetch unit acquires the target instruction, and the following steps 1010 to 1013 are processes for determining the virtual address of the target instruction for the fetching unit, and the step 1010 to step 1013 are performed. This can occur during the fetch unit's acquisition of the target instruction.
  • Step 1010 Read the lower address of the target instruction from the instruction space of the previous instruction of the target instruction.
  • step 1010 For the implementation of the step 1010, reference may be made to the step 607 of the embodiment shown in FIG. 6, which is not described herein again.
  • Step 1011 Read an address indication symbol from the extended instruction space.
  • the extended instruction space is also the extended instruction space in step 1008.
  • the instruction fetch unit can call the read command of the processor to read the address indication symbol from the extended instruction space.
  • Step 1012 Determine a high address of the target instruction according to the address indication symbol.
  • the instruction fetch unit may determine the upper address of the target instruction based on the indication of the address indication symbol.
  • the instruction fetch unit determines that the upper address of the target instruction is equal to cur_pc_hi, and when the address indication symbol is 01, the instruction fetch unit determines that the upper address of the target instruction is equal to cur_pc_hi+1, when the address indication symbol When it is 10, the instruction fetch unit determines that the upper address of the target instruction is equal to cur_pc_hi-1.
  • steps 1011 to 1012 can be understood as the refinement of step 505 in the embodiment shown in FIG. 5 when the address mapping is direct mapping.
  • Step 1013 Combine the lower address of the target instruction with the upper address of the target instruction to obtain a virtual address of the target instruction.
  • the instruction fetch unit may combine the lower address of the target instruction with the upper address of the target instruction according to the address bit to obtain a virtual address of the target instruction, and in the same virtual address, the address bit is sequentially raised from right to left. .
  • the instruction fetch unit arranges the upper address of the target instruction at the upper bit of the lower address of the target instruction to obtain the virtual address of the target instruction.
  • br_trgt represents a virtual address of the target instruction
  • br_trgt_lo represents a lower address of the target instruction
  • br_trgt_hi represents a higher address of the target instruction
  • br_trgt ⁇ br_trgt_hi, br_trgt_lo ⁇ .
  • the virtual address determining method provided by the embodiment of the present application in the process of determining the virtual address of the target instruction, is that the lower address of the target instruction is read from the instruction space of the previous instruction of the target instruction. There is no need to calculate the lower address of the target instruction, only the remaining address of the target instruction (the remaining address is the address other than the lower address in the virtual address of the target instruction), and then the remaining address of the target instruction is merged with the lower address of the target instruction.
  • the virtual address of the target instruction can be obtained, so that the calculation amount of the virtual address of the target instruction can be reduced, which helps to solve the problem that the delay of determining the virtual address of the target instruction is large, and the processing speed of the processor is slow, and the problem is reduced. Determine the delay of the virtual address of the target instruction and increase the processing speed of the processor.
  • the virtual address determining method provided by the embodiment of the present invention greatly reduces the address width of the virtual address in the process of determining the virtual address, and reduces the delay of determining the virtual address.
  • the solution provided by the embodiment of the present application does not need to increase the pipeline level. Avoid delays due to increased pipeline levels and avoid processor performance degradation due to exceptions, prediction errors, and cache misses.
  • FIG. 10 The solution provided by the embodiment shown in FIG. 10 is exemplified below with reference to FIG. 12 and FIG. 12 and FIG. 13 show the virtual address as the PC address, and FIG. 12 shows the offset address as 0.
  • FIG. 13 illustrates the offset address as 1 as an example.
  • cur_pc represents the PC address of the previous instruction of the target instruction
  • cur_pc_lo represents the lower address of the previous instruction of the target instruction
  • cur_pc_hi represents the upper address of the previous instruction of the target instruction
  • imm represents the target instruction.
  • the offset address included in the previous instruction; br_trgt indicates the PC address of the target instruction
  • br_trgt_lo indicates the lower address of the target instruction
  • br_trgt_hi indicates the upper address of the target instruction
  • C1 indicates the lower carry, and the scheme of the embodiment shown in FIG. 10 is executed. Before, you can first extend the imm according to the symbol of imm, so that the width of imm is equal to the width of cur_pc.
  • cur_pc is split into cur_pc_lo and cur_pc_hi, and cur_pc_lo is aligned with imm. This process may correspond to steps 1001 and 1002 of the embodiment shown in FIG.
  • br_trgt_lo is read from the instruction space of the previous instruction of the target instruction according to the scheme provided in step 1010; then, the extended instruction is obtained according to the scheme provided in step 1011.
  • the address indication symbol is read in space, and br_trgt_hi is determined according to the scheme provided in step 1012.
  • br_trgt_lo in the process of determining br_trgt, can be read from the instruction space of the previous instruction of the target instruction, and br_trgt_hi can be determined from the address indication symbol read from the instruction space of the previous instruction of the target instruction. Combining br_trgt_lo and br_trgt_hi to obtain br_trgt, so that in the process of determining br_trgt, no addition operation is required, and the delay for determining br_trgt is greatly reduced.
  • FIG. 14 is a block diagram of a virtual address determining apparatus 1400 provided by an embodiment of the present application.
  • the virtual address determining apparatus 1400 may be an instruction fetching unit in a processor.
  • the virtual address determining apparatus 1400 includes:
  • the first reading module 1401 is configured to read the lower address of the target instruction from the instruction space of the previous instruction of the target instruction to be acquired, and the lower address of the target instruction is calculated before writing the previous instruction to the first instruction cache. And storing the address in the instruction space of the previous instruction;
  • a first determining module 1402 configured to determine a remaining address of the target instruction, a sum of a width of a remaining address of the target instruction and a width of a lower address of the target instruction is equal to a width of a virtual address of the previous instruction;
  • the merging module 1403 is configured to combine the lower address of the target instruction with the remaining address of the target instruction to obtain a virtual address of the target instruction.
  • the virtual address determining apparatus in the process of determining the virtual address of the target instruction, is that the lower address of the target instruction is read from the instruction space of the previous instruction of the target instruction. There is no need to calculate the lower address of the target instruction, only the remaining address of the target instruction (the address other than the lower address in the virtual address of the target instruction) is calculated, and then the remaining address of the target instruction is merged with the lower address of the target instruction to obtain the target.
  • the virtual address of the instruction so that the calculation amount of the virtual address of the target instruction can be reduced, which helps to solve the problem that the delay of determining the virtual address of the target instruction is large, the processing speed of the processor is slow, and the determination target instruction is reduced.
  • the latency of the virtual address increases the processing speed of the processor.
  • FIG. 15 is a block diagram of another virtual address determining apparatus 1400 provided by an embodiment of the present application.
  • the virtual address determining apparatus 1400 further includes:
  • a calculation module 1404 configured to calculate a lower address of the target instruction
  • the first storage module 1405 is configured to store the lower address of the target instruction to the instruction space of the previous instruction.
  • calculation module 1404 is configured to:
  • the lower address of the previous instruction is determined from the virtual address of the previous instruction, and the lower address of the offset address is determined from the offset address, and the lower address of the previous instruction is aligned with the lower address of the offset address.
  • the width is equal;
  • the lower address of the previous instruction is added to the lower address of the offset address to obtain the lower address of the target instruction, and the lower address of the target instruction is aligned with the lower address of the previous instruction and the width is equal.
  • the virtual address determining apparatus 1400 further includes:
  • the second storage module 1406 is configured to store the lower carry into the extended instruction space, and the lower carry is a carry generated by adding the lower address of the previous instruction and the lower address of the offset address, and the extended instruction space is the instruction for the previous instruction.
  • the instruction space obtained by expanding the space.
  • the remaining address includes a median address and a high-order address.
  • FIG. 16 is a block diagram of a first determining module 1402 according to an embodiment of the present application.
  • the first determining module 1402 includes:
  • the first determining sub-module 14021 is configured to determine, from the offset address, a high-order address of the offset address, where the offset address is composed of a high-order address of the offset address and a low-order address of the offset address;
  • the second determining sub-module 14022 is configured to determine, according to the upper address of the offset address, the median address of the previous instruction from the virtual address of the previous instruction, where the median address of the previous instruction is aligned with the upper address of the offset address and Equal in width;
  • a reading submodule 14023 configured to read the lower carry from the extended instruction space
  • the adding sub-module 14024 is configured to add the median address of the previous instruction, the upper address of the offset address, and the lower carry, to obtain a median address of the target instruction;
  • the third determining sub-module 14025 is configured to determine a high-order address of the previous instruction from the virtual address of the previous instruction, where the virtual address of the previous instruction is the upper address of the previous instruction, the median address of the previous instruction, and the previous instruction. Composition of the lower address;
  • the fourth determining sub-module 14026 is configured to determine a high-order address of the target instruction according to a median carry, a high-order address of the previous instruction, and a symbol of the offset address, and the median carry is a median address and an offset address of the previous instruction. The higher address and the lower carry add up the resulting carry.
  • the fourth determining submodule 10426 is configured to:
  • calculation module 1404 is configured to:
  • the lower address of the previous instruction is aligned with the offset address and the width is equal;
  • the lower address of the previous instruction is added to the offset address to obtain the lower address of the target instruction, and the lower address of the target instruction is aligned with the lower address of the previous instruction and the width is equal.
  • the remaining address includes a high-order address.
  • FIG. 17 shows a block diagram of another virtual address determining apparatus 1400 provided by an embodiment of the present application. Referring to FIG. 17, on the basis of FIG. 15, the virtual address is used.
  • the determining device 1400 further includes:
  • a second determining module 1407 configured to determine a high-order address of the previous instruction from a virtual address of the previous instruction, where the virtual address of the previous instruction is composed of a high-order address of the previous instruction and a lower-order address of the previous instruction;
  • the third determining module 1408 is configured to determine, according to the lower carry, the upper address of the previous instruction, and the sign of the offset address, the upper address of the target instruction, and the lower carry is generated by adding the lower address and the offset address of the previous instruction. carry;
  • a generating module 1409 configured to generate an address indication symbol, where the address indication symbol indicates a high-order address of the target instruction
  • the third storage module 1410 is configured to store the address indication symbol into the extended instruction space, where the extended instruction space is an instruction space obtained by expanding the instruction space of the previous instruction.
  • the first determining module 1402 is configured to:
  • the upper address of the target instruction is determined according to the address indication symbol.
  • the third determining module 1408 is configured to:
  • the lower address stored in the instruction space of the different instructions is aligned in the 0th bit of the instruction space.
  • the virtual address determining apparatus in the process of determining the virtual address of the target instruction, is that the lower address of the target instruction is read from the instruction space of the previous instruction of the target instruction. There is no need to calculate the lower address of the target instruction, only the remaining address of the target instruction (the address other than the lower address in the virtual address of the target instruction) is calculated, and then the remaining address of the target instruction is merged with the lower address of the target instruction to obtain the target.
  • the virtual address of the instruction so that the calculation amount of the virtual address of the target instruction can be reduced, which helps to solve the problem that the delay of determining the virtual address of the target instruction is large, the processing speed of the processor is slow, and the determination target instruction is reduced.
  • the latency of the virtual address increases the processing speed of the processor.
  • the virtual address determining apparatus when determining the virtual address of the target instruction, only exemplifies the division of each functional unit. In actual applications, the function may be assigned differently according to needs.
  • the functional unit is completed, that is, the internal structure of the device is divided into different functional units to complete all or part of the functions described above.
  • the virtual address determining apparatus and the virtual address determining method are provided in the same embodiment. For details, refer to the method embodiment, and details are not described herein.
  • the embodiment of the present application further provides a processor including the virtual address determining apparatus 1400 shown in FIG. 14, FIG. 15, or FIG.
  • the embodiment of the present application further provides a computer readable storage medium, where the instructions are stored, when the instruction is run on a processor of the computer, causing the processor to execute the above FIG. 5, FIG. 6 or The virtual address determination method described in 10.
  • the embodiment of the present application further provides a computer program product comprising instructions for causing a processor to execute the virtual address determining method described in FIG. 5, FIG. 6, or FIG. 10 above when the computer program product runs on a processor of the computer.
  • the embodiment of the present application further provides a processing apparatus, where the processing apparatus includes at least one circuit for performing the virtual address determining method described in FIG. 5, FIG. 6, or FIG.
  • the embodiment of the present application further provides a chip, which includes programmable logic circuits and/or program instructions, and is used to implement the virtual address determining method described in FIG. 5, FIG. 6, or FIG.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

L'invention concerne un procédé et un appareil de détermination d'adresse virtuelle, un processeur et un support de stockage, se rapportant au domaine technique des processeurs. Le procédé consiste : à lire, dans un espace d'instruction de l'instruction précédente d'une instruction cible à obtenir, une adresse de rang inférieur de l'instruction cible, l'adresse de rang inférieur de l'instruction cible étant une adresse calculée avant que l'instruction précédente soit écrite dans une mémoire cache d'instruction de premier niveau et stockée dans l'espace d'instruction de l'instruction précédente; à déterminer l'adresse restante de l'instruction cible, la somme de la largeur de l'adresse restante de l'instruction cible et de la largeur de l'adresse de rang inférieur de l'instruction cible étant égale à la largeur de l'adresse virtuelle de l'instruction précédente (505); et à combiner l'adresse de rang inférieur de l'instruction cible avec l'adresse restante de l'instruction cible pour obtenir l'adresse virtuelle de l'instruction cible (506). Le procédé résout le problème de longueur de délai de détermination d'adresses virtuelles et de lenteur de traitement de processeurs, réduit le délai de détermination d'adresses virtuelles et améliore les vitesses de traitement des processeurs.
PCT/CN2018/102225 2018-01-03 2018-08-24 Procédé et appareil de détermination d'adresse virtuelle, processeur et support de stockage WO2019134376A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374342B1 (en) * 2000-01-31 2002-04-16 Kabushiki Kaisha Toshiba Translation lookaside buffer match detection using carry of lower side bit string of address addition
CN1536493A (zh) * 2003-04-11 2004-10-13 ������������ʽ���� 信息处理装置和方法、存储介质、程序及摄像装置
CN103885893A (zh) * 2012-12-19 2014-06-25 辉达公司 用于访问内容寻址存储器的技术
CN103970507A (zh) * 2014-05-21 2014-08-06 龙芯中科技术有限公司 64位虚拟机处理访存指令的方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS623338A (ja) * 1985-06-28 1987-01-09 Yokogawa Hewlett Packard Ltd 直接値処理方式
JPH06231047A (ja) * 1993-02-05 1994-08-19 Fujitsu Ltd アドレス変換方法および装置
US6592449B2 (en) * 2001-02-24 2003-07-15 International Business Machines Corporation Smart fan modules and system
JP4484630B2 (ja) * 2004-01-29 2010-06-16 パナソニック株式会社 可変長復号化装置および可変長復号化方法および再生システム
CN102841865B (zh) * 2011-06-24 2016-02-10 上海芯豪微电子有限公司 高性能缓存系统和方法
US10108424B2 (en) * 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
CN104679481B (zh) * 2013-11-27 2020-04-28 上海芯豪微电子有限公司 一种指令集转换系统和方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374342B1 (en) * 2000-01-31 2002-04-16 Kabushiki Kaisha Toshiba Translation lookaside buffer match detection using carry of lower side bit string of address addition
CN1536493A (zh) * 2003-04-11 2004-10-13 ������������ʽ���� 信息处理装置和方法、存储介质、程序及摄像装置
CN103885893A (zh) * 2012-12-19 2014-06-25 辉达公司 用于访问内容寻址存储器的技术
CN103970507A (zh) * 2014-05-21 2014-08-06 龙芯中科技术有限公司 64位虚拟机处理访存指令的方法及装置

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