WO2019132193A1 - Circuit intégrateur à condensateur commuté pour compenser une erreur de pôle de fonction de transfert d'intégrateur - Google Patents

Circuit intégrateur à condensateur commuté pour compenser une erreur de pôle de fonction de transfert d'intégrateur Download PDF

Info

Publication number
WO2019132193A1
WO2019132193A1 PCT/KR2018/011806 KR2018011806W WO2019132193A1 WO 2019132193 A1 WO2019132193 A1 WO 2019132193A1 KR 2018011806 W KR2018011806 W KR 2018011806W WO 2019132193 A1 WO2019132193 A1 WO 2019132193A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
node
negative
amplifier
positive
Prior art date
Application number
PCT/KR2018/011806
Other languages
English (en)
Korean (ko)
Inventor
박홍준
조성은
Original Assignee
포항공과대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 포항공과대학교 산학협력단 filed Critical 포항공과대학교 산학협력단
Publication of WO2019132193A1 publication Critical patent/WO2019132193A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00—Networks using time-varying elements, e.g. N-path filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00—Networks using time-varying elements, e.g. N-path filters
    • H03H19/004—Switched capacitor networks

Definitions

  • the present invention relates to a technique for compensating for the pole-error of an integrator-transfer function in a switched-capacitor integrator circuit, particularly for use in a switched-capacitor integrator circuit without significantly increasing power consumption and circuit size.
  • a switched-capacitor integrator circuit that compensates for the pole-error of an integrator-transfer function that can compensate for gain errors and offset voltages caused by the finite voltage gain of the amplifier.
  • FIG. 1 is a circuit diagram of an auto-zeroed non-inverting switched-capacitor integrator according to the prior art.
  • a prior art auto zero non-inverting switched-capacitor integrator circuit (hereinafter referred to as a "switched-capacitor integrator circuit") 10 includes a first switch SW1 and a second switch SW2 A first amplifier unit 13 having a first amplifier A1 and an integrating capacitor Cf are connected to the first switch unit 11, the sample capacitor unit 12 having the sample capacitor Cs, And an integrated capacitor unit 14 and a second switch unit 15 including a third switch SW3 and a fourth switch SW4.
  • the first switch SW1 of the first switch unit 11 is turned on when the non-overlapping first clock signal ph1 is high (logic 1) To the first node N1.
  • the second switch SW2 of the first switch unit 11 is turned on when the second clock signal ph2 of the non-overlapping type is 'high' to turn on the first reference voltage Vref1 to the first node N1, .
  • the sample capacitor Cs of the sample capacitor unit 12 samples the voltage between the two nodes N1 and N2.
  • the first amplifier A1 of the first amplifier 13 amplifies the input node voltage Vx of the second node N2 with a negative voltage gain and outputs the amplified voltage as an output voltage Vout.
  • the integral capacitor Cf of the integral capacitor unit 14 performs an integrating function in conjunction with the first amplifier A1.
  • the third switch SW3 of the second switch unit 15 is turned on by the first clock signal ph1 to connect the second node N2 to the output voltage Vout.
  • the fourth switch SW4 of the second switch unit 15 is turned on when the second clock signal ph2 is high so that one node is connected to the inverting input node of the first amplifier A1 And connects the other node of the integrating capacitor Cf to the output voltage Vout.
  • the output voltage Vout becomes a voltage obtained by integrating the input voltage Vin with respect to time.
  • the output voltage Vout (n) is expressed by the following equations (1) and (2): " (1) " do.
  • the Z-domain transfer function of the switched-capacitor integration opportunity (10) is defined as the output voltage (Vout) divided by the input voltage (Vin) in the Z-region.
  • the transfer function pole value of the switched-capacitor integration opportunity (10) can be obtained from the above-mentioned equation (1) . Therefore, when using the switched-capacitor integration opportunity 10 in a delta-sigma modulator, the signal to noise ratio (SNR) of the output of the delta-sigma modulator due to low-frequency quantization noise, .
  • SNR signal to noise ratio
  • the switched-capacitor integrator circuit uses an auto-zeroed integrator circuit to eliminate the influence of the input offset voltage.
  • the Z-region pole value of the switched-capacitor integrator circuit is less than one.
  • the problem to be solved by the present invention is to improve the signal-to-noise ratio of the output signal without increasing the power consumption and the size of the circuit by adding an amplifier having a voltage gain equal to or more than a predetermined value to the auto zero invertible switched-capacitor integrator circuit.
  • Another object of the present invention is to improve the signal-to-noise ratio of the output signal without increasing the power consumption by increasing the integrator-pole value of the Z-domain transfer function of the switched-capacitor integrator circuit.
  • a switched-capacitor integrator circuit for compensating a pawl error of an integrator transfer function according to the first embodiment of the present invention
  • a first switch unit for connecting a first reference voltage to the first node voltage according to a second clock signal
  • a sample capacitor portion having a sample capacitor connected between the first node voltage and the second node voltage
  • a second switch unit connecting the second node voltage to the fourth node voltage according to the first clock signal and connecting the second node voltage to the third node voltage according to the second clock signal
  • a first amplifier for amplifying a differential input voltage obtained by subtracting a second reference voltage from the third node voltage and outputting the amplified differential input voltage as an output voltage, the first amplifier having a negative voltage gain
  • An integrating capacitor unit having an integrating capacitor connected between the third node voltage and the output voltage
  • a second amplifier having a positive voltage gain to amplify a differential input voltage which is a value obtained by subtracting the second reference voltage from the input offset voltage from the third no
  • a switched-capacitor integrator circuit for compensating a pole-error of an integrator-transfer function according to a second embodiment of the present invention, And a first reference voltage is connected to the first positive node voltage in accordance with a second clock signal, and the first reference voltage is connected to the first negative voltage, A first switch part connected to the first negative polarity node; A positive polarity sample capacitor coupled between the first positive node voltage and the second positive node voltage and a negative polarity sample capacitor coupled between the first negative node voltage and the second negative node voltage; A sample capacitor section; The second positive node voltage is connected to the fourth positive node voltage in accordance with the first clock signal, the second negative node voltage is connected to the fourth negative node voltage, A second switch for connecting the second positive node voltage to the third positive node voltage and for connecting the second negative node voltage to the third negative node voltage, And a fully differential output differential amplifier having a negative voltage gain so that a value obtained by subtracting the third
  • the present invention has the effect of improving the signal-to-noise ratio of the output signal without significantly increasing the power consumption and the circuit size by adding an amplifier having a voltage gain equal to or greater than a predetermined value to the auto zero inversion switched-capacitor integrator circuit.
  • the present invention also has the effect of increasing the signal-to-noise ratio of the output signal without increasing the power consumption by making the integrator-pole value of the Z-domain transfer function of the switched-capacitor integrator circuit greater than a fixed value .
  • Figure 1 is a prior art auto zero noninverting switched-capacitor integrator circuit diagram.
  • FIG. 2 is a block diagram of a switched-capacitor integrator circuit that compensates for the pole-error of an integrator-transfer function according to the present invention
  • FIG. 3 is an exemplary diagram of a second amplifier implemented with an amplifier having a single gain feedback structure.
  • FIG. 4 is a block diagram of a switched-capacitor integrator circuit that compensates for pole-error
  • 5 is a detailed block diagram illustrating an implementation of 4.
  • FIG. 6 is a detailed block diagram of the second amplifying unit.
  • FIG. 7 is a detailed block diagram of a first embodiment of a fourth amplifier.
  • FIG. 8 is a circuit diagram of a first differential amplifier implemented as a first amplifier
  • Figure 9 is an example implementation of a second amplifier
  • FIG. 10 is a detailed block diagram showing a second embodiment of a fourth amplifier.
  • FIG. 11 is a simulation graph for a switched-capacitor integrator circuit according to the present invention.
  • Figure 12 is a block diagram of a third order delta-sigma modulator implemented using a switched-capacitor integrator circuit in accordance with the present invention.
  • 13 is a frequency spectrum of a differential output voltage measured by a third-order delta-sigma modulator chip.
  • FIG. 2 is a block diagram of a switched-capacitor integrator circuit that compensates for the pole-error of the integrator-transfer function according to the present invention.
  • a switched-capacitor integration opportunity furnace 100 for compensating a pole-error of an integrator-transfer function includes a first switch unit 110, a sample capacitor unit 120, A second amplification unit 130, a first amplification unit 140, an integrated capacitor unit 150, and a second amplification unit 160.
  • Figure 2 is a non-inverting switched-capacitor integrator circuit that compensates for pole-error.
  • the switched-capacitor integrator circuit of FIG. 2 operates when the input voltage Vin and the output voltage Vout are both single-ended signals.
  • FIG. 2 is different from FIG. 1 in that a second amplifier unit 150 having a positive voltage gain is added and the position of the second switch unit 130 is changed.
  • a negative feedback is established by connecting an element between the second input node (inverting input node) of the first amplifier A1 having a negative voltage gain and the output node of the first amplifier A1,
  • the voltage between the first input node (non-inverting input node) and the second input node (non-inverting input node) of the first amplifier A1 becomes Vos1-Vout / Av1.
  • the term '-Vout / Av1' which is a differential input voltage generated when the voltage gain Av1 of the first amplifier A1 has a finite value, is defined as a gain error term.
  • the switched-capacitor integration opportunity 10 of FIG. 1 samples the input offset voltage Vos1 in the sample capacitor Cs and does not sample the gain error.
  • the switched- The capacitor integration opportunity 100 samples the input offset voltage Vos1 and the gain error together in the sample capacitor Cs so that the output of the switched-capacitor integration opportunity 100 includes the input offset voltage Vos1, The gain error term does not appear.
  • the first switch unit 110 includes a first switch SW1 for connecting the input voltage Vin to the first node voltage V1 according to the first clock signal ph1, And a second switch SW2 for connecting one reference voltage Vref1 to the first node voltage V1.
  • the first clock signal (ph1) and the second clock signal (ph2) have a phase in which 'high' sections do not overlap with each other.
  • the first switch SW1 receives the first clock signal ph1 in non-overlapping form
  • the second switch SW2 is turned on when the second clock signal ph2 in the non-overlapping form is 'HIGH (logic 1)' to transmit the input voltage Vin to the first node voltage V1, Quot; high " to turn on the first reference voltage Vref1 to the first node voltage V1.
  • the first switch SW1 When the switched-capacitor integration opportunity 100 operates in an inverting integrator mode, the first switch SW1 is turned on when the second clock signal ph2 is high to turn off the input voltage Vin Node voltage V1 and the second switch SW2 is turned on when the first clock signal ph1 is high to transfer the first reference voltage Vref1 to the first node voltage V1 do.
  • the sample capacitor unit 120 has a sample capacitor Cs connected between the first node voltage V1 and the second node voltage V2.
  • the sample capacitor Cs samples the voltage between the two node voltages V1 and V2.
  • the second switch unit 130 is connected to the third switch SW3 and the second clock signal ph2 that connect the second node voltage V2 to the fourth node voltage V4 in accordance with the first clock signal ph1. And a fourth switch SW4 for connecting the second node voltage V2 to the third node voltage V3.
  • the third switch SW3 is turned on when the first clock signal ph1 is high and connects the second node voltage V2 to the fourth node voltage V4.
  • the fourth switch SW4 is turned on when the second clock signal ph2 is high and connects the second node voltage V2 to the third node voltage V3.
  • the first amplifying unit 140 may be configured such that a first input node, which is a non-inverting input node (-), is connected to the third node voltage (V3) And a first amplifier A1 connected to the output node Vref2 and the output node connected to the output voltage Vout.
  • the first amplifier A1 amplifies the differential input voltage which is a value obtained by subtracting the second reference voltage Vref2 from the third node voltage V3 and outputs the amplified differential output voltage Vout as the output voltage Vout And its amplification principle is expressed by the following equation (3).
  • the integrating capacitor unit 150 includes an integration capacitor Cf connected between the third node voltage V3 and the output voltage Vout.
  • the second amplifying unit 160 is connected to the first input node of the non-inverting input node (+) to the second reference voltage Vref2 and the second input node of the non-inverting input node (+ And a second amplifier A2 connected to the node voltage V3 and having an output node connected to the fourth node voltage V4.
  • the second amplifier A2 is an amplifier having a positive voltage gain Av2 close to 1 and is a value obtained by subtracting the second reference voltage Vref2 and the input offset voltage Vos2 from the third node voltage V3
  • the differential input voltage is amplified and output to the fourth node voltage (V4).
  • the amplification principle thereof is shown in the following Equation (4).
  • the switched-capacitor integration opportunity 100 When the switched-capacitor integration opportunity 100 operates in the non-inverting integrator mode, if the voltage gain Av2 of the second amplifier A2 is +1.0, the first clock signal ph1 remains high
  • the third node voltage V3 supplied to the second input node of the first amplifier A1 The voltage stored in the sample capacitor Cs becomes Cs * ⁇ Vref1 - Vout (n) / Av1 - Vos1 - Vref2 ⁇ The voltage stored in the capacitor Cf becomes Cf * ⁇ Vout (n) * (1 + 1 / Av1) -Vos1 ⁇ , where the output voltage Vout (n) 6].
  • the capacitance of the sample capacitor Cs is 2.5 pF
  • the capacitance of the integrating capacitor Cf is 12.5 pF
  • the voltage gain Av1 of the first amplifier A1 is 10
  • the voltage gain (Av2) is 0.9
  • the following equation (2) (6) The Z-pole value of the switched-capacitor integration opportunity 100 becomes 0.98 in the switched-capacitor integration opportunity 10 of FIG. 1, resulting in a switched-capacitor integration opportunity 100 ) Is 0.9979 which is greater than 0.99.
  • a switched- (SNR) of the delta sigma modulator to which the delay-sigma modulator is applied is about 10 dB larger than the SNR of the delta-sigma modulator applied to the switched-capacitor integration opportunity (10).
  • the switched-capacitor integration opportunity 100 is advantageous in that even if the voltage gain Av1 is small as in Equation (6), the second pole- It is possible to reduce the power consumption of the first amplifier A1 having a negative voltage gain as compared with the case of the switched-capacitor integration opportunity 10.
  • a switched-capacitor integration opportunity 100 in accordance with the present invention includes a second amplifier A2 having a positive voltage gain as compared to the prior art switched-capacitor integration opportunity 10, An amplification unit 160 is added.
  • a switched-capacitor integration opportunity 100 is applied to the delta sigma modulator, the power consumption of the second amplifier A2 is reduced while the second pole- Can be greatly reduced.
  • FIG. 3 shows an example in which the second amplifier 160 of FIG. 2 is implemented with a third amplifier A3 having a unity-gain feedback structure.
  • the third amplifier A3 has a first input node IN1 which is a non-inverting input node (+) connected to the third node voltage V3 and a second input node IN2 which is an inverting input node (- And the output node OUT is connected to the fourth node voltage V4 and operates as an amplifier having a positive voltage gain.
  • the third voltage gain Av3 which is the voltage gain of the third amplifier A3 is a value obtained by subtracting the second reference voltage Vref2 from the voltage of the output node OUT to the voltage V3 of the first input node IN1, Divided by a value obtained by subtracting the voltage of the second input node IN2 from the voltage of the second input node IN2.
  • the third voltage gain Av3 thus defined is a positive value greater than unity.
  • the voltage gain Av2 of the second amplifier A2 having the positive voltage gain is expressed by Equation (7) as the third voltage gain Av3.
  • FIG. 4 is a block diagram of a switched-capacitor integrator circuit that compensates for pole-error
  • FIG. 5 is a detailed block diagram illustrating an implementation of 4.
  • FIG. 2 operates in the case where the input voltage Vin and the output voltage Vout are single-ended signals, whereas FIGS. 4 and 5 show the input voltage Vin, And the output voltage Vout are both differential signals.
  • Figures 4 and 5 are illustrations of a fully-differential form of a switched-capacitor integrator circuit.
  • a switched-capacitor integration opportunity path 100 for compensating a pole-error of an integrator-transfer function includes a first switch unit 210, a sample capacitor unit 220, A second switch unit 230, a first amplification unit 240, an integrated capacitor unit 250, and a second amplification unit 260.
  • a switched-capacitor integration opportunity 100 in accordance with another embodiment of the present invention includes a positive input voltage Vinp, a negative input voltage Vinm, first and second clock signals ph1 and ph2, A value obtained by integrating a value obtained by subtracting the negative polarity input voltage Vinm from the positive polarity input voltage Vinp from the positive polarity output voltage Voutp by receiving the two reference voltages Vref1 and Vref2, And outputs the positive polarity output voltage Voutp and the negative polarity output voltage Voutm so as to be proportional to the value obtained by subtracting the polarity output voltage Voutm.
  • the first switch unit 210 includes an eleventh switch SW11 for connecting the positive input voltage Vinp to the first positive node voltage V1p according to the first clock signal ph1, A second switch SW12 for connecting the first reference voltage Vref1 to the first positive node voltage V1p in accordance with the first clock signal ph1 and a negative input voltage Vinm according to the first clock signal ph1, A thirteenth switch SW13 for connecting to the polar node voltage V1m and a fourteenth switch SW14 for connecting the first reference voltage Vref1 to the first negative node voltage V1m in accordance with the second clock signal ph2, .
  • the first clock signal (ph1) and the second clock signal (ph2) have a phase in which 'high' sections do not overlap with each other.
  • the eleventh switch SW11 When the switched-capacitor integration opportunity 100 operates in a non-inverting integrator mode, the eleventh switch SW11 is turned on when the first clock signal ph1 is high (logic 1) The positive input voltage Vinp is connected to the first positive node voltage V1p and the thirteenth switch SW13 is turned on to connect the negative input voltage Vinm to the first negative node voltage V1m .
  • the twelfth switch SW12 is turned on to turn the first reference voltage Vref1 to the first positive node voltage
  • the fourteenth switch SW14 is turned on to connect the first reference voltage Vref1 to the first negative node voltage V1m.
  • the switched-capacitor integration opportunity 100 When the switched-capacitor integration opportunity 100 operates in the inverting integrator mode, when the second clock signal ph2 is high, the eleventh switch SW11 is turned on and the positive input voltage Vinp Is connected to the first positive node voltage V1p and the thirteenth switch SW13 is turned on to connect the negative input voltage Vinm to the first negative node voltage V1m.
  • the twelfth switch SW12 is turned on to connect the first reference voltage Vref1 to the first positive node voltage V1p
  • the fourteenth switch SW14 is turned on to connect the first reference voltage Vref1 to the first negative node voltage V1m.
  • the sample capacitor unit 220 includes a positive polarity sample capacitor Csp and a first negative node voltage V1m connected between the first positive node voltage V1p and the second positive node voltage V2p, And a negative polarity sample capacitor Csm connected between the negative node voltage V2m.
  • the capacitance value of the positive polarity sample capacitor Csp and the capacitance value of the negative polarity sample capacitor Csm are equal to each other.
  • the positive polarity sample capacitor Csp samples the voltage between the first positive node voltage V1p and the second positive node voltage V2p.
  • the negative polarity sample capacitor Csm samples the voltage between the first negative node voltage V1m and the second negative node voltage V2m.
  • the second switch unit 230 includes a fifteenth switch SW15 for connecting the second positive node voltage V2p to the fourth positive node voltage V4p in accordance with the first clock signal ph1, a sixth switch SW16 for connecting the second positive node voltage V2p to the third positive node voltage V3p according to the second clock signal ph2, A seventeenth switch SW17 for connecting the fourth negative polarity node voltage V2m to the fourth negative polarity node voltage V4m and a second negative polarity node voltage V2m in accordance with the second clock signal ph2 to the third negative polarity node voltage V3m And an eighteenth switch (SW18) for connecting the first switch
  • the fifteenth switch SW15 When the first clock signal ph1 is high, the fifteenth switch SW15 is turned on, the second positive node voltage V2p is connected to the fourth positive node voltage V4p, and the seventeenth switch SW17 Is turned on to connect the second negative node voltage V2m to the fourth negative node voltage V4m.
  • the sixteenth switch SW16 When the second clock signal ph2 is high, the sixteenth switch SW16 is turned on, the second positive node voltage V2p is connected to the third positive node voltage V3p, and the eighteenth switch SW18 Is turned on to connect the second negative node voltage V2m to the fourth negative node voltage V4m.
  • the first amplifying unit 240 includes a first input node IN1 that is a non-inverting input node (+) and a second input node (-) that is connected to the third negative node voltage V3m and an inverting input node IN2 is connected to the third positive node voltage V3p and the third input node IN3 is connected to a second reference voltage Vref2 which is a common mode reference voltage, And a first amplifier A1 for outputting a differential output voltage between a voltage Voutp and a negative output voltage Voutm.
  • the first amplifier A1 is a fully-differential output differential amplifier having a negative voltage gain.
  • the first amplifier A1 amplifies the third positive node voltage V3m at the third positive node voltage V3p,
  • the value obtained by multiplying the subtracted value by the negative voltage gain (-Av1) is equal to the positive output voltage Voutp minus the negative output voltage Voutm, and the built-in common mode feedback (CMFB) circuit Polarity output voltage Voutp and the negative polarity output voltage Voutm so that a value obtained by averaging the positive polarity output voltage Voutp and the negative polarity output voltage Voutm becomes equal to the second reference voltage Vref2, Output.
  • CMFB common mode feedback
  • the integrating capacitor unit 250 includes a positive polarity integrating capacitor Cfp connected between the third positive node voltage V3p and the positive polarity output voltage Voutp and a negative polarity integrating capacitor Cfp connected between the third negative node voltage V3m and the negative polarity node, And a negative polarity integration capacitor Cfm connected between the output voltage Voutm.
  • the capacitance value of the positive polarity integrating capacitor Cfp and the capacitance value of the negative polarity integrating capacitor Cfm are equal to each other.
  • the second amplifying unit 260 includes a first input node IN1 which is an inverting input node and a second input node IN2 which is connected to the third negative polarity node V3m and a non- ) Is connected to the third positive node voltage (V3p), the third input node (IN3) is connected to a second reference voltage (Vref2) which is a common mode reference voltage, and the fourth positive node voltage And a second amplifier A2 for outputting the fourth negative node voltage V4m.
  • the second amplifier A2 is a fully-differential output differential amplifier having a positive voltage gain and outputs a third negative node voltage V3m at the third positive node voltage V3p Subtracts the fourth positive polarity node voltage V4p from the fourth positive polarity node voltage V4p by a value obtained by multiplying the fourth positive polarity node voltage V4p by the positive voltage gain Av2, And outputs the fourth positive node voltage V4p and the fourth negative node voltage V4m such that a value obtained by averaging the fourth negative polarity node voltage V4m becomes equal to the second reference voltage Vref2.
  • the voltage gain Av2 of the second amplifier A2 having the positive voltage gain has a value close to 1, the first amplifier A2 having a negative voltage gain
  • the input offset voltage Vos1 of the amplifier A1 does not appear in the output voltage Voutp (n) -Voutm (n).
  • the input offset voltage Vos2 of the second amplifier A2 having a positive voltage gain is amplified to the same value as the differential input voltage Vinp (n-0.5) -Vinm (n-0.5) Output voltage Voutp (n) -Voutm (n).
  • the input offset voltage Vos2 may be amplified in the second amplification unit 260 and appear in the differential output voltage Voutp (n) -Voutm (n) of the switched-capacitor integration opportunity 100, And a second amplifying unit 260 having a function of preventing this.
  • the second amplifying unit 260 includes a second dividing unit 261, an input stage chopper 262, a fourth amplifier A4, and an output stage chopper 263.
  • the divide-by-two circuit 261 divides the first clock signal ph1 or the second clock signal ph2 by two and outputs the third clock signal ph3.
  • the input stage chopper 262 couples the third positive node voltage V3p to the fifth positive node voltage V5p when the third clock signal ph3 is high, (V3m) to the fifth negative polarity node voltage V5m.
  • the input stage chopper 262 couples the third positive node voltage V3p to the fifth negative node voltage V5m when the third clock signal ph3 is at a low level, And connects the node voltage V3m to the fifth positive polarity node voltage V5p.
  • the fourth amplifier A4 is a fully differential amplifier, in which a first input node IN1, which is an inverting input node, is connected to a fifth negative-polarity node voltage V5m, and a second input node IN2, which is a non-
  • the third input node IN3 is connected to the second reference voltage Vref2 which is a common mode reference voltage and the first output node OUT1 is connected to the fifth positive polarity node voltage V5p, Is connected to the sixth negative polarity node voltage (V6m), and the second output node (OUT2) is connected to the sixth positive polarity node voltage (V6p).
  • the differential mode voltage gain of the fourth amplifier A4 is a little less than one but has a positive value close to unity.
  • the input offset voltage Vos2m is present at the first input node IN1 of the fourth amplifier A4 and the input offset voltage Vos2p is present at the second input node IN2.
  • a voltage outputted from the first output node OUT1 of the fourth amplifier A4 to the sixth negative node voltage V6m and a voltage outputted from the second output node OUT2 to the sixth positive node voltage V6p (Common mode output voltage) is equal to the second reference voltage Vref2.
  • the output stage chopper 263 connects the sixth positive polarity node voltage V6p to the fourth positive polarity node voltage V4p when the third clock signal ph3 is high, And connects the voltage V6m to the fourth negative polarity node voltage V4m.
  • the output stage chopper 263 connects the sixth positive node voltage V6p to the fourth negative node voltage V4m when the third clock signal ph3 is at a low level, And connects the node voltage V6m to the fourth positive polarity node voltage V4p.
  • the average value (Vos2p + Vos2m) / 2) of the input offset voltages Vos2p and Vos2m of the fourth amplifier A4 is multiplied by the voltage gain Av2 of the fourth amplifier A4 and the fourth negative node voltage (DC) component which is an average value of the fourth positive polarity node voltage V4p and the fourth positive polarity node voltage V4p.
  • DC negative node voltage
  • the high frequency AC component which is the difference between the fourth positive node voltage V4p and the fourth negative node voltage V4m generated by the input offset voltages Vos2p and Vos2m of the fourth amplifier A4, Is canceled by the integral capacitors Cfp and Cfm of the switched-capacitor integration opportunities 100 and appears as a negligible degree of ripple voltage waveform on the differential output voltages Voutp and Voutm of the switched-capacitor integration circuit 100.
  • the direct current (DC) component which is an average value of the fourth positive node voltage V4p and the fourth positive node voltage V4m, generated by the input offset voltages Vos2p and Vos2m of the fourth amplifier A4, Is removed by the common mode feedback circuit of the first amplifier A1 having the negative voltage gain (-Av1), and is not present in the differential output voltages Voutp, Voutm.
  • the difference value Vos2p-Vos2m of the input offset voltages Vos2p and Vos2m of the third amplifier A3 is controlled by the operation of the input stage chopper 262 and the output stage chopper 263, (AC) component which is a difference between the fourth positive polarity node voltage V4p and the fourth negative polarity node voltage V4m.
  • FIG. 7 is a detailed block diagram showing a first embodiment of a fourth amplifier A4 included in the fourth amplifier 264 of FIG. 6, which is an example of a fully-differential amplifier.
  • the fourth amplifier A4 includes a fifth amplifier A5 and a sixth amplifier A6, which are single-ended output amplifiers.
  • the fifth amplifier A5 and the sixth amplifier A6 have the same structure as the third amplifier A3 in Fig. 3 in terms of circuit.
  • the fifth amplifier A5 is connected between the fifth positive polarity node voltage V5p and a second input node IN2 which is a non-inverting input node connected to the fifth positive polarity node voltage V5p, ) Connected to the sixth positive polarity node voltage (V6p).
  • the sixth amplifier A6 has a first input node IN1 as a non-inverting input node connected to the fifth negative polarity node V5m and a second input node IN2 as an inverting input node connected to the output node OUT ) Connected to the sixth negative-polarity node voltage (V6m).
  • the fifth amplifier A5 and the sixth amplifier A6 have a voltage gain that is a little smaller than 1 but has a positive value close to unity. Therefore, the fourth amplifier A4 of the fourth amplifying unit 264 has a differential mode voltage gain that is slightly smaller than 1 but is positive (+).
  • the common mode voltage of the fifth positive polarity node voltage V5p and the fifth negative node voltage V5m is equal to the second reference voltage Vref2
  • the sixth positive polarity node voltage V6p and the sixth negative polarity node voltage The common mode voltage of the node voltage V6m becomes equal to the second reference voltage Vref2.
  • the reason why the common mode voltage of the fifth positive node voltage V5p and the fifth negative node voltage V5m is equal to the second reference voltage Vref2 is that the fifth positive node voltage V5p,
  • the common mode voltage of the negative node voltage V5m is equal to the common mode voltage of the third positive node voltage V3p and the third negative node voltage V3m of FIG. 6,
  • the common mode voltage of the third negative voltage V3p and the third negative node voltage V3m is lower than the second reference voltage Vref2 by the common mode feedback circuit of the second amplifier A2 having the negative voltage gain of FIG. ).
  • FIG. 8 is a circuit diagram of the first amplifier A1 of FIG. 5 implemented with a fully differential amplifier according to an embodiment of the present invention.
  • the first amplifier A1 having the negative voltage gain operates as an integrator and outputs the first clock signal ph1 and the second clock signal ph2
  • the slew-rate may be small and the settling time may be short since the value of the differential output voltage Voutp-Voutm that is changed during one period of the output voltage Voutp-Voutm is relatively small.
  • the first amplifier A1 places two of the simplest CMOS inverters among the single-stage amplifier circuits in parallel and uses a common mode feedback circuit in the form of a switched-capacitor to shorten the stabilization time while minimizing power consumption .
  • the first amplifier A1 includes a twenty-first inverter I21 connected between the third positive node voltage V3p and the positive output voltage Voutp, a third negative node voltage V3m, A first common mode feedback in the form of a switched-capacitor connected between the second inverter I22 and the third positive node voltage V3p and the positive output voltage Voutp connected between the negative output voltage Voutm and the negative output voltage Voutm, Circuit 241 and a second common mode feedback circuit 242 in the form of a switched-capacitor connected between the third negative-polarity node voltage V3m and the negative-polarity output voltage Voutm.
  • the types of the inverters I21 and I22 are not particularly limited, the present invention is exemplified by a CMOS inverter.
  • the first common mode feedback circuit 241 includes first and second capacitors C21 and C22 having one node connected to the third positive node voltage V3p in common by the first clock signal ph1
  • a twenty-first switch SW21 that is turned on and connects the other node of the twenty-first capacitor C21 to the positive output voltage Voutp
  • a twenty-first switch SW21 turned on by the second clock signal ph2
  • a second switch SW22 that is turned on by the first clock signal ph1 and connects the other node of the twenty-second capacitor C22 to the negative output voltage Vref2
  • a seventeenth switch SW23 which is turned on by the second clock signal ph2 and connects the other node of the twenty-second capacitor C22 to the second reference voltage Vref2, (SW24).
  • the second common mode feedback circuit 242 includes a 23rd and 24th capacitors C23 and C24 having one node connected to the third negative node voltage V3m in common by the first clock signal ph1
  • a twenty-fifth switch SW25 which is turned on and connects the other node of the twenty-third capacitor C23 to the positive output voltage Voutp
  • a twenty-fifth switch SW25 turned on by the second clock signal ph2
  • a sixth switch SW26 that is turned on by the first clock signal ph1 to connect the other node of the twenty-fourth capacitor C24 to the negative output voltage Vref2, (28) for turning on the second clock signal (ph2) and connecting the other node of the 24th capacitor (C24) to the second reference voltage (Vref2) (SW28).
  • the first common mode feedback circuit 241 and the second common mode feedback circuit 242 output the common mode voltage of 0.5 * ( Voutp + Voutm) is equal to the second reference voltage Vref2 and the positive output voltage Voutp and the third negative node voltage V3m operate in the same manner as the logic of the inverters I21 and I22, And operates to be equal to the threshold voltage.
  • FIG. 9 is a block diagram illustrating the structure of a class-AB type amplifier applied to the third amplifier A3 of FIG. 4, the fifth amplifier A5 and the sixth amplifier A6 of the second amplifier A2 shown in FIG. Figure 1 is a circuit diagram of a single-ended output differential amplifier.
  • a description will be given by taking as an example the circuit diagram of the single-ended output differential amplifier of the class-AB type applied to the fifth amplifier A5.
  • the second amplifier A2 samples the positive input voltage Vinp of the positive-polarity sample capacitor Csp with the switched-capacitor integration opportunity 100 in the interval in which the first clock signal ph1 is high, And the negative polarity input voltage Vinm is sampled in the negative polarity sample capacitor Csm.
  • the positive polarity sample capacitor Csp and the negative polarity sample capacitor Csm are switched-capacitors in which the previously charged voltage is lower than the first reference voltage Vref1 And is discharged to the second reference voltage Vref2.
  • the positive polarity sample capacitor Csp and the negative polarity sample capacitor Csm are charged to the signal voltages Vinp-Vref2 and (Vinm-Vref2) in the interval where the first clock signal ph1 is high.
  • the amount of charge change is large between the section where the second clock signal ph2 is high and the section where the first clock signal ph1 is high.
  • the second amplifier A2 is connected between the sample capacitor Csp and the sample capacitor Csp which are changed between a period where the second clock signal ph2 is high and a period during which the first clock signal ph1 is high.
  • Csm is supplied in a short period of time in order to supply a large value of output current in response to a sharp increase in the differential input voltage with respect to time.
  • the second amplifier A2 must have a large slew-rate. It is advantageous to use a class-AB type amplifier in order to increase the slew rate while reducing the power consumption of the second amplifier A2.
  • the second amplifier A2 is a single-ended first-class single-ended output of a Class-AB type, arranged in parallel, for implementation in a fully differential amplifier with relatively low power consumption and high slew rate.
  • ended output amplifier 261 and a second single-ended output amplifier 262 of the positive (+) slew rate class-AB type the first single-ended output amplifier 261 and the second single- One input node of the output amplifier 262 is commonly connected to the first input node IN1 which is a non-inverting (+) input node and the other input node is connected to the second input node IN2 , And connects the output node OUT to the sixth positive polarity node voltage V6p.
  • the amount (+ ) Of the slew rate and the slew rate of the negative (-) are both large.
  • the first inverter includes a PMOS transistor (MP11) and an NMOS transistor (N-channel MOS transistor) MN11 connected in series between the power supply terminal VDD and the first common node CN1 do.
  • the second inverter includes a PMOS transistor MP12 and an NMOS transistor MN12 connected in series between the power supply terminal VDD and the first common node CN1.
  • the first current source includes an NMOS transistor MN13 connected between the first common node CN1 and the ground terminal VSS.
  • the first input node IN1 is commonly connected to the gates of the PMOS transistor MP11 and the NMOS transistor MN11 and the output node of the first inverter is connected to the gate of the NMOS transistor MN13 do.
  • the second input node IN2 is commonly connected to the gates of the PMOS transistor MP12 and the NMOS transistor MN12 and the output node of the second inverter is connected to the output node OUT.
  • the second single-ended output amplifier 262 includes a second current source connected between the power supply terminal VDD and the second common node CN2, a second current source connected between the second common node CN2 and the ground terminal VSS in parallel And a third inverter and a fourth inverter connected to each other.
  • the second current source includes a PMOS transistor MP21 connected between the power supply terminal VDD and the second common node CN2.
  • the third inverter includes a PMOS transistor MP22 and an NMOS transistor MN21 connected in series between the second common node CN2 and the ground terminal VSS.
  • the fourth inverter includes a PMOS transistor MP23 and an NMOS transistor MN23 connected in series between the second common node CN2 and the ground terminal VSS.
  • the first input node IN1 is commonly connected to the gates of the PMOS transistor MP22 and the NMOS transistor MN21 and the output node of the third inverter is connected to the gate of the PMOS transistor MP21 do.
  • the second input node IN2 is commonly connected to the gates of the PMOS transistor MP23 and the NMOS transistor MN22 and the output node of the fourth inverter is connected to the output node OUT.
  • a 65 nm CMOS process was used to implement the first single-ended output amplifier 261 and the second single-ended output amplifier 262 in accordance with an embodiment of the present invention.
  • the fifth amplifier A5 which is a single-ended output differential amplifier of the class-AB type in Fig. 9, can reduce the average power consumption by flowing a relatively small amount of current in a stable state and flow a relatively large amount of current in the slew state The operation speed can be increased.
  • FIG. 10 is a detailed block diagram showing a second embodiment of the fourth amplifier A4 of FIG. 6, which is an example of a fully differential amplifier.
  • a fully differential amplifier is implemented using two single-ended output amplifiers A5 and A6, whereas in the second embodiment of the fully differential amplifier of FIG. 10, There is a difference in that linearity is improved by removing an even harmonic component from a differential output voltage using a seventh amplifier A7 which is one fully differential amplifier having differential inputs.
  • the seventh amplifier A7 is supplied with two pairs of differential inputs IN_p1 and IN_m1 and IN_p2 and IN_m2 and supplies a second reference voltage Vref2 as a common mode reference voltage to a pair of output nodes OUT_p, OUT_m to output a differential voltage.
  • the positive polarity output node OUT_p and the negative polarity output node OUT_m of the seventh amplifier A7 are connected to the first negative input node IN_m1 and the first positive polarity input node IN_p1 respectively,
  • the sixth negative polarity node voltage V6m and the sixth positive polarity node voltage V6p which are the differential inputs of the fourth amplifier A4 are connected to the second negative input node IN_m2 and the second positive polarity input node IN_p2, And outputs the sixth positive polarity node voltage V6p and the sixth negative node voltage V6m which are the differential outputs of the fourth amplifier A4 to the positive polarity output node OUT_p and the negative polarity output node OUT_m Connect.
  • Fig. 11 is a block diagram of the conventional auto-zeroed non-inverting switched-capacitor integration opportunity 10 of Fig. 1 and the switched-capacitor integration 10 compensating the pole- And a simulation result of an impulse response of a circuit designed by the 65-nm CMOS process for the opportunistic path 100 is shown in FIG.
  • the design conditions for designing the two integrator circuits 10, 100 are identical to each other as follows.
  • the first reference voltage Vref1, the second reference voltage Vref2 and the supply voltage VDD are 0.35V, 0.35V and 0.7V, respectively.
  • the capacitance of the sample capacitor Cs and the capacitance of the integration capacitor Cf Are respectively 2.5 pF and 12.5 pF and the frequencies of the first clock signal ph1 and the second clock signal ph2 are both 4 MHz and the first clock signal ph1 is high
  • the maximum value of the 0.1% settling time is 100 ns for the period where the second clock signal ph2 is 'high'.
  • the 0.1% stabilization time for a period in which the first clock signal ph1 is high and a period in which the second clock signal ph1 is high is equal to the first clock signal ph1 or the second clock signal ph1,
  • the output voltage value of (10), (100) from the rising edge of the clock signal ph2 to the switched-capacitor integration opportunity starts to be maintained at a value between 99.95% and 100.05% of the final output voltage value It is defined as time until time.
  • the amplifier having the negative voltage gain at (10) and (100) is implemented by a CMOS inverter having a voltage gain of 25, and the 0.1% stabilization time condition is satisfied
  • the operating point current of the CMOS inverter is 2.5 times higher than the switched-capacitor integration opportunity 100 according to the present invention in a switched-capacitor integration opportunity 10 according to the prior art.
  • the second amplifier A2 having a positive (+) voltage gain in FIG. 2 has a voltage gain Av2 of 0.97 because the third amplifier is in unity-gain feedback form as in FIG. And implemented.
  • a transient simulation was performed in a time domain using a predetermined program (H-spice program).
  • H-spice program a predetermined program
  • t represents a time
  • T represents a period of the first clock signal ph1 and the second clock signal ph2.
  • the voltage gain of the amplifier having the negative voltage gain constituting the two switched-capacitor integration opportunities (10) and (100) is finite as 25,
  • the above x (n) series value is expressed by the following equation (9) for 0 and all positive integers n.
  • Equation (9) In the ideal integrator circuit in which the voltage gain of the amplifier having the negative voltage gain constituting the integrator is infinite as the pole-error, In the conventional integrator circuit in which the voltage gain of the amplifier having the negative voltage gain constituting the integrator is finite is expressed by Equation (2) And in the switched-capacitor integration opportunity (100) according to the present invention, Equation (6) .
  • the normalized value of the x (n) series value is divided by the x (0) value for all n in FIG. 11 and is expressed by dB (20log10 (x (n) / x ))) Is plotted on the ordinate axis and the normalized time (n) is plotted on the abscissa axis.
  • dB 20log10 (x (n) / x ))
  • the normalized time (n) is plotted on the abscissa axis.
  • a conventional switched-capacitor integration opportunity 10 and a switched-capacitor integration opportunity 100 according to the present invention and 0.01111 and 0.00038, respectively.
  • According to the above equations (2) and (6) and Are calculated as 0.008 and 0.00025, respectively.
  • the reason why the pole-error value obtained by the simulation is larger than the calculated value is due to the parasitic capacitance.
  • FIG. 12 is a block diagram of a third order delta-sigma modulator implemented using the switched-capacitor integration opportunity 100 according to the present invention.
  • the third-order delta-sigma modulator 300 includes a subtracter 310 connected in a feed-forward structure, first through third integration opportunities 320A through 320C, a summer 330, And a quantizer 340.
  • 13 is a frequency spectrum of the differential output voltage (Vop-Vom) measured by fabricating the third-order delta-sigma modulator 300 of FIG. 12 as a chip.
  • the differential input voltages Vip and Vim of the third delta-sigma modulator 300 can be expressed by the following equations (10) and (11), respectively.
  • the power consumption of the third delta-sigma modulator 300 was measured at 47 uW.
  • the signal to noise and distortion ratio (SNDR) and the effective number of bits (ENOB) including the distortion are 89 dB and 14.5, respectively, when the signal bandwidth is 20 kHz Bit.
  • the power consumption is 47 uW and the signal bandwidth is 20 kHz, as in the embodiment of the present invention shown in Figs. 12 and 13
  • the frequency of the first clock signal ph1 and the second clock signal ph2 is designed to be 4 MHz, the signal-to-noise ratio (SNDR) including the distortion becomes about 75 dB.
  • the modulator 300 has a signal-to-noise ratio (SNDR) that includes more than 10 dB of distortion compared to a delta-sigma modulator using the switched-capacitor integration opportunity 10 of the prior art.
  • SNDR signal-to-noise ratio
  • the conventional auto-zeroed switched-capacitor integrator circuit of FIG. 1 with respect to the switched-capacitor integration opportunity 100 comprises an amplifier (not shown) having a positive voltage gain with a voltage gain of +1 To compensate for the gain error of the amplifier having the negative voltage gain.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

La présente invention concerne une technique de compensation d'une erreur de pôle d'une fonction de transfert d'intégrateur dans un circuit intégrateur à condensateur commuté. La présente invention est caractérisée par l'amélioration d'un rapport signal-bruit d'un signal de sortie sans augmentation significative de la consommation d'énergie et de la taille d'un circuit par ajout d'un amplificateur ayant un gain de tension supérieur ou égal à une certaine valeur à un circuit intégrateur à condensateur commuté non inverseur avec mise à zéro automatique. De plus, la présente invention est caractérisée en ce que, lorsque l'intégrateur selon la présente invention est appliqué à un modulateur delta-sigma, le rapport signal-bruit du signal de sortie est amélioré sans augmenter la consommation d'énergie par réalisation d'une valeur de pôle d'intégrateur d'une fonction de transfert de domaine Z du circuit d'intégrateur à condensateur commuté qui est supérieure à une certaine valeur.
PCT/KR2018/011806 2017-12-29 2018-10-08 Circuit intégrateur à condensateur commuté pour compenser une erreur de pôle de fonction de transfert d'intégrateur WO2019132193A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170183410A KR102012504B1 (ko) 2017-12-29 2017-12-29 적분기-전달함수의 폴-오차를 보상하는 스위치드-커패시터 적분기회로
KR10-2017-0183410 2017-12-29

Publications (1)

Publication Number Publication Date
WO2019132193A1 true WO2019132193A1 (fr) 2019-07-04

Family

ID=67067685

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2018/011806 WO2019132193A1 (fr) 2017-12-29 2018-10-08 Circuit intégrateur à condensateur commuté pour compenser une erreur de pôle de fonction de transfert d'intégrateur

Country Status (2)

Country Link
KR (1) KR102012504B1 (fr)
WO (1) WO2019132193A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113395468A (zh) * 2020-03-11 2021-09-14 格科微电子（上海）有限公司 图像传感器信号的采样与放大方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030044277A (ko) * 2001-11-29 2003-06-09 주식회사 하이닉스반도체 스위칭 노이즈가 제거된 스위치드 커패시터 적분기
KR100794310B1 (ko) * 2006-11-21 2008-01-11 삼성전자주식회사 스위치드 커패시터 회로 및 그것의 증폭 방법
KR20130059995A (ko) * 2011-11-29 2013-06-07 삼성전자주식회사 연산 증폭기 회로, 이를 포함하는 이미지 센서, 및 연산 증폭기의 주파수 응답 보상 방법
JP2013526745A (ja) * 2010-05-14 2013-06-24 ジニティクス カンパニー リミテッド 反転積分回路及び非反転積分回路が結合された積分回路
KR20170049052A (ko) * 2015-10-28 2017-05-10 엘지전자 주식회사 인버터(inverter) 및 적어도 하나의 스위치드 커패시터(Switched Capacitor)를 이용한 적분기 회로

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9558845B2 (en) * 2015-03-25 2017-01-31 Qualcomm Incorporated Sampling network and clocking scheme for a switched-capacitor integrator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030044277A (ko) * 2001-11-29 2003-06-09 주식회사 하이닉스반도체 스위칭 노이즈가 제거된 스위치드 커패시터 적분기
KR100794310B1 (ko) * 2006-11-21 2008-01-11 삼성전자주식회사 스위치드 커패시터 회로 및 그것의 증폭 방법
JP2013526745A (ja) * 2010-05-14 2013-06-24 ジニティクス カンパニー リミテッド 反転積分回路及び非反転積分回路が結合された積分回路
KR20130059995A (ko) * 2011-11-29 2013-06-07 삼성전자주식회사 연산 증폭기 회로, 이를 포함하는 이미지 센서, 및 연산 증폭기의 주파수 응답 보상 방법
KR20170049052A (ko) * 2015-10-28 2017-05-10 엘지전자 주식회사 인버터(inverter) 및 적어도 하나의 스위치드 커패시터(Switched Capacitor)를 이용한 적분기 회로

Also Published As

Publication number Publication date
KR102012504B1 (ko) 2019-08-20
KR20190081097A (ko) 2019-07-09

Similar Documents

Publication Publication Date Title
JP3485895B2 (ja) オフセットおよびノンリニアリティを補償した増幅器およびその方法
US6400301B1 (en) amplifying signals in switched capacitor environments
US7336123B2 (en) Chopper amplifier circuit apparatus operable at low voltage utilizing switched operational amplifier
US9667194B2 (en) Differential switched capacitor circuits having voltage amplifiers, and associated methods
US6445331B1 (en) Apparatus and method for common-mode regulation in a switched capacitor circuit
US7525383B2 (en) Differential amplifier
US7205839B2 (en) High bandwidth apparatus and method for generating differential signals
JP2010074636A (ja) 差動演算増幅回路とそれを用いたパイプライン型ａ／ｄ変換装置
JPH11103422A (ja) 低ノイズ低パワーｃｍｏｓ相関型ダブルサンプラー
EP0901232A2 (fr) Comparateur de tension, amplificateur opérationelle et convertisseur analogique-numérique l'utilisant
US6954169B1 (en) 1/f noise, offset-voltage charge injection induced error cancelled op-amp sharing technique
US10686464B2 (en) Latched comparator and analog-to-digital converter making use thereof
US6756928B2 (en) Pseudo-differential amplifier and analog-to-digital converter using the same
WO2019132193A1 (fr) Circuit intégrateur à condensateur commuté pour compenser une erreur de pôle de fonction de transfert d'intégrateur
EP4258554A1 (fr) Circuit de correction de décalage temporel discret intégré dans un amplificateur de résidu dans un convertisseur analogique-numérique (adc) en pipeline
WO2019083267A2 (fr) Appareil à semi-conducteur pour lire et produire en sortie un signal de capteur
US20070164888A1 (en) Robust reference generation circuit for A/D converter
JPH11112305A (ja) 電圧比較器、演算増幅器、アナログ−デジタル変換器およびアナログ−デジタル変換回路
CN111446946B (zh) 一种单端输出的低噪声全差分开关电容滤波器
WO2021167129A1 (fr) Convertisseur analogique/numérique
US10523231B1 (en) Dynamic integrator with boosted output impedance of the transconductance
WO2021145480A1 (fr) Convertisseur analogique-numérique
Wang et al. A capacitor-mismatch-insensitive switch-capacitor amplifier for Pipeline ADC
Alaybeyoğlu High speed comparator design for the implementation of successive approximation register ADC
Feng et al. A Wideband ADC Input Buffer Based on AC-Coupled Super Source Follower

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18894827

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18894827

Country of ref document: EP

Kind code of ref document: A1