US10686464B2 - Latched comparator and analog-to-digital converter making use thereof - Google Patents
Latched comparator and analog-to-digital converter making use thereof Download PDFInfo
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- US10686464B2 US10686464B2 US16/507,875 US201916507875A US10686464B2 US 10686464 B2 US10686464 B2 US 10686464B2 US 201916507875 A US201916507875 A US 201916507875A US 10686464 B2 US10686464 B2 US 10686464B2
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- 230000001052 transient effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/331—Sigma delta modulation being used in an amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Definitions
- the present inventive concept relates to a latched comparator, for example for use in an analog to digital converter (ADC).
- ADC analog to digital converter
- a comparator compares two inputs and takes a binary decision.
- Latched comparators are driven by a clock signal, allowing for resetting the circuitry ahead of each comparison.
- Latched comparators employing a dynamic pre-amplifier stage are known for their low power consumption, since their dominant sub-threshold operation and no DC bias current makes the power consumption only proportional to the operating frequency. Further, the pre-amplifier stage reduces kick-back noise of a subsequent latch.
- ADCs analog-to-digital converters
- SAR ADCs successive approximation register ADCs
- SDM ADCs sigma-delta modulation ADCs
- the comparator of a high resolution SAR ADC is the input referred noise, which is directly related to the signal-to-noise ratio (SNR) performance of the ADC.
- SNR signal-to-noise ratio
- the comparator has a range where noise influences the decision no matter the sign of the difference of the input signal. This noise range needs to become smaller when the resolution of the ADC increases.
- a low-power low-noise comparator is required.
- An objective of the present inventive concept is to provide a low-power, low-noise latched comparator.
- a latched comparator comprising a pre-amplifier stage with a positive input, a negative input; and a differential output comprising a first output and a second output
- the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor and a first cascode transistor connected at a first cascode node, the first amplifying transistor being controlled by the positive input and the first cascode transistor being connected, opposite to the first cascode node, to the first output;
- a second cascode pair comprising a second amplifying transistor and a second cascode transistor connected at a second cascode node, the second amplifying transistor being controlled by the negative input and the second cascode transistor being connected, opposite to the second cascode node, to the second output, a first gain-boosting transistor connected between the first output and the first cascode node; and a second gain-boosting transistor connected between the second output and the second cascode node, wherein the first gain-
- pre-amplifier pre-amplifier stage, and similar, are to be understood as relating to an amplifying stage which is followed by further circuitry of any kind. In particular, it shall not be read as being limited to denote an amplifying stage which is followed by further amplification.
- the cascode pairs and the gain-boosting transistors in the pre-amplifier stage have the effect of increasing the pre-amplifier gain and making the gain substantially time-invariant. This allows the decision point of a subsequent latch to be chosen more freely in an optimal pre-amplifier voltage range where the input referred noise of the input transistors is low. The higher gain also reduces the contribution to the input referred noise of the sampling capacitors and the noise of the latch at the decision point.
- a comparator with low noise, suitable for a high-resolution ADC is provided which still operates at low power. Further, this is provided in a circuit with a relatively simple topology, that can be implemented in a small integrated circuit (IC) area.
- the latched comparator is controlled by a clock signal and/or supplied by a supply voltage.
- the dock signal may be used to reset the latched comparator, so that each comparison is started from a well-defined state, avoiding hysteresis.
- the supply voltage may be used to power the latched comparator.
- the first cascode transistor and the second cascode transistor each are controlled by a common-mode voltage. Compared to using the supply voltage, this has an advantage of a better-controlled and slightly larger output range of the pre-amplifier stage.
- the first cascode transistor and the second cascode transistor are each controlled by the supply voltage. Compared to using a common-mode voltage, this has an advantage of requiring less power, as using the common-mode voltage requires buffering of a mid-supply voltage.
- the first amplifying transistor, the second amplifying transistor, the first cascode transistor, and the second cascode transistor are NMOS transistors.
- MOS transistors allow for a low-current, low-power device.
- the latched comparator further comprises a block pulling the first output and the second output towards the supply voltage absent the clock signal, the block preferably comprising a first, preferably PMOS, transistor and a second, preferably PMOS, transistor, each controlled by the clock signal and connected between the supply voltage and, respectively, the first output and the second output.
- the first output and the second output are reset to a high state near the supply voltage, which will be the state at the start of the next comparison upon the next raising of the clock signal. This ensures that each comparison is started from a well-defined state, avoiding hysteresis.
- the latched comparator further comprises a block pulling the first amplifying transistor opposite to the first cascode node and the second amplifying transistor opposite to the second cascode node towards ground when the clock signal is present, the block preferably comprising an NMOS connected between ground and the lower transistor of the first cascode pair and the lower transistor of the second cascode pair, the NMOS transistor being controlled by the clock signal.
- the latched comparator further comprises a block pulling the first cascode node and the second cascode node towards the supply voltage absent the clock signal, the block preferably comprising a first, preferably PMOS, transistor and a second, preferably PMOS, transistor, each connected between the supply voltage and, respectively, the first cascode node and the second cascode node and controlled by the clock signal. This further contributes to reducing hysteresis by starting each comparison with the circuit in a well-defined state.
- the latched comparator further comprises a latch stage, which is configured to receive the differential output from the pre-amplifier stage.
- the pre-amplifier stage and the latch stage provide a complete latched comparator with the advantages described above.
- an analog-to-digital converter comprising the latched comparator according to the first aspect, wherein the analog-to-digital converter is configured to provide an analog signal to be converted and a reference signal on, respectively, the positive input and the negative input of the latched comparator.
- the analog-to-digital converter is a successive approximation register analog-to-digital converter.
- This aspect may generally present the same or corresponding advantages as the former aspect.
- a biomedical sensor device comprising the latched comparator according to the first aspect or an analog-to-digital converter according to the second aspect.
- the latched comparator and/or the analog-to-digital converter may advantageously be used in a biomedical sensor device for measurement circuitry which may be used in the biomedical sensor device.
- measurement circuitry may be provided with a low-noise comparator, which enables an analog-to-digital converter having a high resolution.
- FIG. 1 is a schematic showing a latched comparator according to the present inventive concept, where the cascode transistors are controlled by the supply voltage.
- FIG. 2 is a schematic showing a latched comparator not according to the present inventive concept, as a comparison.
- FIG. 3 shows simulated transient behavior of the latched comparator of FIG. 2 .
- FIG. 4 shows simulated transient behavior of the latched comparator of FIG. 1 .
- FIG. 1 shows a schematic of a latched comparator 2 according to the present inventive concept.
- the latched comparator comprises a pre-amplifier stage 4 .
- the pre-amplifier stage 4 has a positive input V in,p and a negative input V in,n , suitable for, when used in an ADC, respectively, an analog voltage that is to be digitized and a reference voltage to which, as part of the digitization procedure, the analog voltage is to be compared. Further, the pre-amplifier stage 4 has differential output comprising a first output V out,1 and a second output V out,2 .
- the circuitry of the latched comparator 2 may be powered by a supply voltage V dd and controlled by a clock signal V clk .
- the clock signal V clk then controls the pacing of comparison, having a leading edge of a positive pulse at the start of each comparison and being at ground potential between comparisons.
- the latched comparator 4 comprises an amplifying block 14 comprising a first 8 and a second cascode pair 10 and a first gain-boosting transistor MN 6 and a second gain-boosting transistor MN 7 .
- the first cascode pair 8 comprises a first amplifying transistor MN 2 and a first cascode transistor MN 4 .
- the second cascode pair 10 comprises a second amplifying transistor MN 3 and a second cascode transistor MN 5 .
- MN 2 , MN 3 , MN 4 , MN 5 , MN 6 , and MN 7 are NMOS transistors.
- the gate terminals of the cascode transistors MN 4 and MN 5 may be connected to the supply voltage V dd .
- they may be connected to a common-mode voltage V cm , which may be generated in a conventional way by buffering a mid-supply.
- the supply voltage V dd or the common-mode voltage V cm thus controls transistors MN 4 and MN 5 .
- the cascode transistors MN 4 and MN 5 will be in a saturated permanently conducting stage between source and drain.
- the drain terminals of MN 4 and MN 5 are connected to, respectively, the first output V out,1 and the second output V out,2 , while the opposite source terminals are connected to, respectively, a first cascode node 20 and a second cascode node 22 .
- the gate terminals of the amplifying transistors MN 2 and MN 3 are connected, respectively, to the positive input V in,p and the negative input V in,n , those inputs thereby controlling the respective transistors, while the drain terminals are connected to, respectively the first cascode node 20 and the second cascode node 22 .
- the amplifying transistors MN 2 and MN 3 work in weak-inversion.
- the first gain-boosting transistor MN 6 is connected at its drain terminal to the first output V out,1 and at its source terminal to the first cascode node 20 . Thus, it is connected in parallel to the cascode transistor MN 4 .
- the second gain-boosting transistor MN 7 is connected at its drain terminal to the second output V out,2 and at its source terminal to the second cascode node 20 . Thus, it is connected in parallel to the cascode transistor MN 5 .
- the first gain-boosting transistor MN 6 and the second gain-boosting transistor MN 7 are cross-coupled in the sense that the first output V out,1 is connected to the gate terminal of the second gain-boosting transistor MN 7 , while the second output V out,2 is connected to the gate terminal of the first gain-boosting transistor V out,1 .
- the first output V out,1 controls the second gain-boosting transistor
- the second output V out,2 controls the first gain-boosting transistor.
- This positive feedback structure provides a gain boost for the pre-amplifier stage 4 . However, it is not used as a latch. To achieve a high gain of the pre-amplifier stage, the transconductance of transistors MN 6 and MN 7 needs to be small (see below). Therefore, the positive feedback structure does not have enough loop gain to work as a latch.
- the latched comparator 4 may comprise a block 12 comprising PMOS transistors MP 1 and MP 2 , to the respective gate terminals of which the clock signal V clk is connected, the clock signal V clk thus controlling transistors MP 1 and MP 2 . Further, to the drain terminals of each of MP 1 and MP 2 , the supply voltage V dd is connected. The source terminals of MP 1 and MP 2 are connected, respectively, to the outputs V out,1 and V out,2 .
- the pre-amplifier stage 4 may comprise a block 16 comprising a single NMOS transistor MN 1 , wherein a source terminal of the transistor MN 1 is connected to ground, a drain terminal of the transistor MN 1 is connected to each of the drain terminals of cascode transistors MN 2 and MN 3 , and a gate terminal of the transistor MN 1 is connected to the clock signal V clk .
- MN 1 When the clock signal goes high at the start of a comparison, MN 1 will become conductive between source and drain, thus pulling the drain terminals, i.e., the terminals opposite the cascode nodes 20 and 22 , of the cascode transistors MN 2 and MN 3 towards ground.
- the pre-amplifier stage 4 may comprise a block 18 comprising two PMOS transistors MP 3 and MP 4 , to the respective gate terminals of which the clock signal V clk is connected. Further, the supply voltage V dd is connected to the drain terminals of each and MP 3 and MP 4 . To the source terminals of MP 3 and MP 4 are connected, respectively, the cascode nodes 20 , 22 of the first cascode pair 8 and the second cascode pair 10 . When the clock signal V clk is absent, i.e., in a low state, the transistors MP 3 and MP 4 will become conductive between drain and source, pulling the respective cascode node towards the supply voltage V dd .
- the latched comparator 2 may comprise a latch stage 6 , forming a complete latched comparator 2 .
- FIG. 1 gives one example of such a latch stage, but other options are equally possible.
- the differential outputs V out,1 and V out,2 of the pre-amplifier stage 6 are connected, respectively, to the gate terminals of PMOS transistors MP 5 and MP 6 , whose respective source terminals are connected to the supply voltage V dd .
- the latch stage 6 is configured to receive the differential output from the pre-amplifier stage 4 .
- differential outputs V out,1 and V out,2 of the pre-amplifier stage 6 are connected, respectively, to the gate terminals of NMOS transistors MN 9 and MN 12 , the source terminals of which are connected to ground and the drain terminals of which are connected, respectively, to the first and second latch outputs V q and V qn .
- Latching is performed by latch transistors MP 7 and MP 8 (PMOS) and MN 10 and MN 11 (NMOS), wherein the first latch output V q is connected to the gate terminals of transistors MP 8 and MN 11 and to the drain terminals of transistors MP 7 and MN 10 , while the second latch output V qn is connected to the gate terminals of transistors MP 7 and MN 10 and to the drain terminals of transistors MP 8 and MN 11 .
- the source terminals of transistors MN 9 , MN 10 , MN 11 , and MN 12 are connected to ground, while the source terminals of transistors MP 7 and MP 8 are connected to the drain terminals of, respectively, transistors MP 5 and MP 6 .
- NMOS transistors MN 8 and MN 13 are connected at their respective gate terminals to a signal V clkn which is a logical negation of the clock signal V clk , at their respective source terminals to ground and at their respective drain terminals to, respectively, the drain terminal of transistor MP 5 and the source terminal of transistor MP 7 , and the drain terminal of transistor MP 6 and the source terminal of transistor MP 8 .
- the latched comparator of FIG. 1 may form part of an analog-to-digital converter (ADC), specifically a successive-approximation analog-to-digital converter (SAR ADC) or a delta-sigma modulation analog-to-digital converter (DSM ADC).
- ADC analog-to-digital converter
- SAR ADC successive-approximation analog-to-digital converter
- DSM ADC delta-sigma modulation analog-to-digital converter
- the analog voltage to be converted will then be provided on the positive input V in,p while a reference signal, with which the analog voltage is to be compared, is provided on the negative input V in,n .
- the ADC may be used in a biomedical sensor device having measurement circuitry which may utilize the ADC comprising the latched comparator.
- FIG. 2 shows a latched comparator 102 not according to the present inventive concept, comprising a pre-amplifier stage 104 and a latch stage 106 .
- the latched comparator 104 comprises a block 112 comprising PMOS transistors MP 1 and MP 2 functioning similar to the block 12 as described above in conjunction with FIG. 1 .
- the pre-amplifier stage comprises a block 116 comprising a single NMOS transistor MN 1 functioning similar to the block 16 as described above in conjunction with FIG. 1 .
- the amplifying block 114 instead of a two cascode pairs and two gain-boosting transistors, in the amplifying block 114 there are only two single amplifying NMOS transistors MN 2 and MN 3 .
- MN 2 is at its gate terminal connected to the positive input V in,p , at its drain terminal connected to the drain terminal of MP 1 and to the first output Vout, 1 and at its source terminal connected to the drain terminal of transistor MN 1 .
- MN 3 is at its gate terminal connected to the negative input V in,n , at its drain terminal connected to the drain terminal of MP 2 and to the second output V out,2 and at its source terminal connected to the drain terminal of transistor MN 1 .
- the latched comparator 102 comprises a latching stage 106 as depicted in FIG. 2 .
- the gain A of the pre-amplifier stage 104 in FIG. 2 can be constructed, under the assumption that the transconductance of transistor MN 2 g m,MN2 is constant, as:
- the gain A of the latched comparator of FIG. 1 according to the present inventive concept can be constructed as:
- FIG. 4 shows a simulated time-domain transient behavior of the latched comparator 2 of FIG. 1 .
- the upper graph shows the latch outputs V q and V qn
- the middle graph shows the pre-amplifier stage 4 outputs V out,1 and V out,2
- the lower graph shows the difference of V out,1 and V out,2 , i.e., the differential output of the pre-amplifier stage 4 .
- the latch decision point is marked by a vertical line.
- the input voltage difference is 200 ⁇ V and the output is 9.2 mV, giving a pre-amplifier stage 4 gain of 46 at the decision point.
- the differential output has a plateau around the decision point, indicating constant gain, giving opportunity for control of the decision point of the latch.
- FIG. 3 shows the time-domain transient behavior of the latched comparator 102 of FIG. 2 .
- the upper graph shows the latch outputs V q and V qn
- the middle graph shows the pre-amplifier stage 104 outputs V out,1 and V out,2
- the lower graph shows the difference of V out,1 and V out,2 , i.e., the differential output of the pre-amplifier stage 104 .
- the latch decision point is marked by a vertical line.
- the gain is clearly time-varying.
- the input voltage difference is 200 ⁇ V and the output is 2.0 mV, giving a pre-amplifier stage 104 gain A of 10 at the decision point.
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Abstract
Description
wherein gm,MN6 is the transconductance of transistor MN6. As can be seen, the time-dependence of the gain A is to a large degree canceled out. Further, it can be seen that for a large gain A, gm,MN6 should be small.
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EP18182958.1A EP3594950A1 (en) | 2018-07-11 | 2018-07-11 | Latched comparator and analog-to-digital converter making use thereof |
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US10686431B1 (en) * | 2019-10-18 | 2020-06-16 | Realtek Semiconductor Corp. | High-sensitivity clocked comparator and method thereof |
CN111865315B (en) * | 2020-07-13 | 2022-07-26 | 同济大学 | Comparator circuit suitable for assembly line flash ADC |
CN113556104B (en) * | 2021-07-12 | 2022-08-09 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
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US9197198B2 (en) * | 2013-10-29 | 2015-11-24 | Qualcomm Incorporated | Latch comparator circuits and methods |
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US20200021304A1 (en) | 2020-01-16 |
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