WO2019104484A1 - 薄膜晶体管及其制备方法、显示基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、显示基板和显示装置 Download PDF

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WO2019104484A1
WO2019104484A1 PCT/CN2017/113394 CN2017113394W WO2019104484A1 WO 2019104484 A1 WO2019104484 A1 WO 2019104484A1 CN 2017113394 W CN2017113394 W CN 2017113394W WO 2019104484 A1 WO2019104484 A1 WO 2019104484A1
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layer
thin film
film transistor
metal layer
active layer
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PCT/CN2017/113394
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English (en)
French (fr)
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叶江波
何家伟
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深圳市柔宇科技有限公司
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Priority to PCT/CN2017/113394 priority Critical patent/WO2019104484A1/zh
Priority to CN201780095838.5A priority patent/CN111201613A/zh
Publication of WO2019104484A1 publication Critical patent/WO2019104484A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present invention relates to the field of semiconductor technology, and in particular to a thin film transistor, a method of fabricating the same, a display substrate, and a display device.
  • the BCE (Back Channel Etching Type) structure has an etch barrier layer to etch the active layer when etching to form the source and the drain, resulting in poor electrical performance of the TFT.
  • the ESL (etch-blocking) structure adds an insulating layer to the active layer, so that when the etching is performed to form the source and the drain, the underlying active layer is protected from etching, thereby avoiding affecting electrical performance, but ESL The structure will thus form a mask and affect the production capacity.
  • an object of the present invention is to provide an operation that is simple, convenient, easy to implement, easy to industrialize, high in productivity, and can protect the active layer from being etched when etching is performed to form the source and the drain.
  • the invention provides a method of making a thin film transistor.
  • the thin film transistor includes a gate, a source, a drain and an active layer, the source and the drain are respectively in contact with the active layer, the gate and the source The pole, the drain and the active layer are electrically insulated.
  • the source and the drain are formed by forming a metal layer on an upper surface of the active layer; on the metal layer A groove having an upper end opening is formed, a residual metal layer is left between the bottom of the groove and the active layer; and the residual metal layer is oxidized to form a metal oxide layer.
  • the inventors have found that the method for fabricating a thin film transistor is simple, convenient, easy to implement, easy to industrialize, and has high productivity, and can protect the active layer from being etched when etching is performed to form a source and a drain, thereby
  • the prepared thin film transistor has excellent electrical properties as well as good stability.
  • the thickness of the residual metal layer is
  • the metal layer comprises a plurality of stacked metal sublayers, directly with the active layer A portion of the contacted metal sublayer constitutes the residual metal layer.
  • the metal layer includes a first titanium sub-layer, the first titanium sub-layer is disposed on an upper surface of the active layer; an aluminum sub-layer, the aluminum sub-layer is disposed on the first An upper surface of the titanium sub-layer; a second titanium sub-layer disposed on an upper surface of the aluminum sub-layer; wherein a portion of the first titanium sub-layer constitutes the residual metal layer.
  • the recess forming the upper end opening on the metal layer is formed by dry etching.
  • the forming the recess before performing the oxidation treatment, further comprising performing a passivation treatment on a sidewall of the recess to form a passivation layer.
  • the oxidation treatment is performed using at least one of ozone and oxygen plasma.
  • the invention provides a thin film transistor.
  • the transistor is fabricated using the methods previously described. The inventors have found that the active layer of the thin film transistor is not etched while performing etching to form the source and the drain, and has excellent electrical properties and good stability.
  • the invention provides a display substrate.
  • the display substrate comprises the thin film transistor described above.
  • the inventors have found that the display substrate has excellent electrical properties and good stability, and can be applied to a display device to achieve a desired display effect, and has all the features and advantages of the above-described thin film transistor, which will not be described in detail herein.
  • the invention provides a display device.
  • the display device comprises the display substrate described above.
  • the inventors have found that the display device has excellent electrical properties and good stability, can achieve a desired display effect, and has all the features and advantages of the above-described thin film transistor and display substrate, which will not be described in detail herein.
  • FIG. 1 is a flow chart showing a method of preparing a thin film transistor according to an embodiment of the present invention.
  • FIGS. 2a-2c are schematic flow charts showing a method of fabricating a thin film transistor according to another embodiment of the present invention.
  • FIG. 3 is a flow chart showing a method of fabricating a thin film transistor according to still another embodiment of the present invention.
  • 4a to 4d are schematic flow charts showing a method of fabricating a thin film transistor according to still another embodiment of the present invention.
  • 5a to 5d are schematic flow charts showing a method of fabricating a thin film transistor according to still another embodiment of the present invention.
  • 6a to 6b are schematic flow charts showing a method of fabricating a thin film transistor in the prior art.
  • Fig. 7 is a view showing the structure of a thin film transistor of one embodiment of the present invention.
  • Fig. 8 is a graph showing the transfer characteristics of a thin film transistor prepared in an embodiment of the present invention.
  • active layer 200 metal layer 210: first titanium sublayer 211: residual metal layer 212: metal oxide layer 220: aluminum sublayer 230: second titanium sublayer 300: groove 310: passivation layer 400: Gate 500: gate insulating layer 600: source 700: drain
  • the invention provides a method of making a thin film transistor.
  • the thin film transistor includes a gate, a source, a drain and an active layer, and the source and the drain are respectively associated with the active layer In contact, the gate is electrically insulated from the source, the drain and the active layer.
  • a source and a drain of the thin film transistor are formed by the following steps:
  • S100 forming a metal layer 200 on the upper surface of the active layer 100. See FIG. 2a for a schematic structural view.
  • the specific material type of the active layer 100 is not particularly limited, as long as the requirements are met, those skilled in the art can flexibly select according to needs, for example, but not limited to a-Si (amorphous) Silicon), p-Si (low temperature polysilicon), organic semiconductor material, or inorganic metal oxide.
  • the specific material type of the active layer 100 may be an inorganic metal oxide such as, but not limited to, ZnO, Zn-Sn-O, In-Zn-O, MgZnO, In- Ga-O, In 2 O 2 and the like.
  • the prepared thin film transistor can have a high switching current ratio and a high field effect mobility, a fast response speed, can realize a large driving current, and the material is inexpensive, easy to obtain, and low in cost.
  • the specific material type of the metal layer 200 is not particularly limited, as long as the requirements are met, the person skilled in the art can flexibly select according to needs, for example, but not limited to, Al, Cu, Ag, Ti, Pt, Mo, etc.
  • specific material types of the metal layer 200 may include Ti, Al, and Mn.
  • the thickness of the metal layer 200 is not particularly limited, and a person skilled in the art can flexibly select as needed as long as the requirements are met. In some embodiments of the present invention, the thickness of the metal layer 200 may be
  • a specific method of forming the metal layer 200 on the upper surface of the active layer 100 is not particularly limited, and a person skilled in the art can flexibly select according to requirements as long as the requirements are met, for example, It is not limited to magnetron sputtering coating, pulsed laser deposition coating, molecular beam epitaxy, sol-gel method, metal organic chemical vapor deposition, and the like.
  • a specific method of forming the metal layer 200 on the upper surface of the active layer 100 may be a magnetron sputtering coating method. Therefore, the operation is simple, convenient, easy to implement, easy to industrialize, and better in controllability and repeatability.
  • S200 forming a recess 300 with an upper end opening on the metal layer 200.
  • a residual metal layer 211 is left between the bottom of the recess 300 and the active layer 100. See FIG. 2b for a schematic structural view.
  • the groove 300 is formed by etching, and the specific kind of the etching method is not particularly limited, as long as the requirements are met, those skilled in the art can flexibly select according to needs, for example, may include However, it is not limited to dry etching, wet etching, and the like.
  • a specific method of forming the recess 300 on the metal layer 200 may be dry etching. Thereby, anisotropic etching can be performed, and the etching selectivity is good, the processing volume is large, the control is easy, the cost is low, and the environmental pollution is small, and it is suitable for industrial production.
  • the specific kind of the dry etching is not particularly limited, as long as the requirements are met, those skilled in the art can flexibly select according to requirements, for example, may include ion milling etching, plasma etching, reactive ion etching, etc. .
  • the specific type of dry etching may be plasma etching. Thus, it has better etching selectivity and a higher etching rate.
  • specific process parameters of the plasma etching are not particularly limited, and those skilled in the art can flexibly select as needed, as long as the requirements are met.
  • the pressure at which the etching is performed may be 8-12 mT
  • the power may be 8-20 kW
  • the gas flow rate may be 3000-5000 sccm.
  • a specific method of retaining the residual metal layer 211 between the bottom of the recess 300 and the active layer 100 is not particularly limited, and may be flexible as needed by those skilled in the art as long as the requirements are met.
  • the selection may, for example, include, but is not limited to, detecting the etching end point using an EPD (etching end point detector), and then controlling a portion of the residual metal layer or the like by controlling the etching time.
  • EPD etching end point detector
  • the groove 300 may be formed by etching only part of the metal layer directly by controlling parameters such as etching time, thereby being active at the bottom of the groove 300.
  • the residual metal layer is left between the layers; when the metal layer 200 is a multi-layered structure of the multilayer metal sub-layer, the EPD can be used to detect the etching end point (ie, the interface of different metal sub-layers), when the EPD detects direct contact with the active layer
  • the interface between the metal sublayer and the metal sublayer of the upper surface thereof is controlled, parameters such as the time of continuing etching are controlled such that a residual metal layer remains between the bottom of the formed recess 300 and the active layer.
  • the etching process can be avoided Damage to the active layer affects the electrical performance of the thin film transistor, and the operation is simple and convenient, and the accuracy is high.
  • the thickness of the residual metal layer 211 is not particularly limited, and a person skilled in the art can flexibly select as needed as long as the requirements are met.
  • the thickness of the residual metal layer 211 may be In some more preferred embodiments of the present invention, the thickness of the residual metal layer 211 may be Thereby, the active layer 100 can be effectively protected from etching when the metal layer 200 is etched to form the source and the drain of the thin film transistor, so that the thin film transistor prepared by the method has excellent electrical properties and good stability. Sex.
  • S300 The residual metal layer 211 is oxidized to form a metal oxide layer 212. See FIG. 2c for a schematic structural view.
  • the specific process of the oxidation treatment is not particularly limited, as long as the requirements are met, those skilled in the art can flexibly select according to needs, for example, the residual metal layer can be oxidized by using a gas having a relatively high oxygen content.
  • the residual metal layer 211 is oxidized by generating an oxygen plasma by a plasma generator or generating ozone by an ozone generator to form a metal oxide layer 212. Since the metal oxide layer 212 is an insulator, a short circuit phenomenon between the source and the drain of the thin film transistor prepared by the method can be prevented.
  • specific process parameters of the oxidation treatment such as temperature, pressure, gas flow rate and the like, are not particularly limited, and those skilled in the art can flexibly select as needed, as long as the requirements are met.
  • the method of fabricating a thin film transistor may include the following steps:
  • S400 after forming the recess 300, before performing the oxidation treatment, further comprising performing a passivation treatment on the sidewall of the recess 300 to form a passivation layer 310. See FIG. 4c and FIG. 4d for a schematic structural view. .
  • the specific process of performing passivation treatment on the sidewall of the groove 300 is not particularly limited, and those skilled in the art can flexibly select as needed as long as the requirements are met.
  • a specific process for passivating the sidewalls of the recess 300 may be a passivation of a mixture of CF 4 and O 2 such that sidewalls of the recess 300 are passivated. Thereby, the side wall of the groove 300 can be protected so that it does not corrode, and the use effect is better.
  • the specific process parameters for passivating the sidewall of the groove 300 such as temperature, pressure, partial pressure of CF 4 and O 2 , gas flow rate, passivation time, etc., are not It is specifically limited, as long as the requirements are met, those skilled in the art can flexibly select as needed.
  • the metal layer 200 may specifically include: a first titanium sub-layer 210 disposed on an upper surface of the active layer 100; aluminum Sublayer 220, the aluminum sub-layer 220 An upper surface of the first titanium sub-layer 210; a second titanium sub-layer 230 disposed on an upper surface of the aluminum sub-layer 220; wherein the first titanium sub-layer A portion of 210 constitutes the residual metal layer 211.
  • the metal layer 200 has a three-layer structure, and both upper and lower layers are titanium, and the middle is aluminum. As a result, the cost is reduced and it is easier to achieve large-scale industrial production.
  • the method for preparing a thin film transistor in this embodiment may include the following steps: First, a first titanium sub-layer 210 and an aluminum sub-layer 220 are sequentially formed on an upper surface of the active layer 100. And the second titanium sub-layer 230, the three together form the metal layer 200, the structure of the product is shown in FIG. 5a; then, the upper end opening groove 300 is formed on the metal layer 200, and the residual metal layer 211 is left.
  • the first titanium sub-layer 210 constitutes the residual metal layer 211, and the obtained product structure is schematically shown in FIG. 5b.
  • the sidewall of the recess 300 is passivated to form a passivation layer 310, and the obtained product structure is schematic.
  • the residual metal layer 211 is oxidized to form a metal oxide layer 212.
  • the structure of the obtained product is shown in FIG. 5d. The steps may be the same as the specific methods described in the foregoing embodiments, and details are not described herein again.
  • the invention provides a thin film transistor.
  • the transistor is fabricated using the methods previously described. The inventors have found that the active layer 100 of the thin film transistor is not etched while etching the source and drain electrodes, and has excellent electrical properties and good stability.
  • the specific structure of the thin film transistor is not particularly limited, and those skilled in the art can flexibly select according to the needs as long as the usage requirements are met. It will be understood by those skilled in the art that in addition to the active layer and the source and drain structures described above, the thin film transistor has other structures of a conventional thin film transistor, for example, a gate electrode, a gate insulating layer, etc., which is not Too much more details.
  • the thin film transistor includes a gate 400, a gate insulating layer 500, an active layer 100, a source 600, a drain 700, and a metal oxide layer 212.
  • the gate insulating layer 500 is located on the upper surface of the gate 400
  • the active layer 100 is located on the upper surface of the gate insulating layer 500
  • the source 600 is located on one side of the upper surface of the active layer 100.
  • the drain 700 is located on the other side of the upper surface of the active layer 100, and the source 600 and the drain 700 sequentially include a first titanium sub-layer 210, an aluminum sub-layer 220, and a second titanium sub-layer 230.
  • a three-layer structure, the metal oxide layer 212 is located on an upper surface of the active layer 100 and between the source 600 and the drain 700.
  • the invention provides a display substrate.
  • the display substrate comprises the thin film transistor described above.
  • the inventors have found that the display substrate has excellent electrical properties and good stability, can achieve a desired display effect when applied to a display device, and has all the features and advantages of the above-described thin film transistor, which will not be described in detail herein.
  • the configuration and the manufacturing process of the display substrate are not particularly limited, and those skilled in the art can flexibly select according to the needs as long as the use requirements are met. And those skilled in the art can understand that in addition to the previous In addition to the thin film transistor, the display substrate has a structure of a conventional display substrate, for example, including a control circuit, an electrode, and the like, and will not be described in detail herein.
  • the invention provides a display device.
  • the display device comprises the display substrate described above.
  • the inventors have found that the display device has excellent electrical properties and good stability, can achieve a desired display effect, and has all the features and advantages of the above-described thin film transistor and display substrate, which will not be described in detail herein.
  • the shape, configuration, and manufacturing process of the display device are not particularly limited, and those skilled in the art can flexibly select according to needs as long as the use requirements are met. It can be understood by those skilled in the art that, in addition to the display substrate described above, the display device has the structure of a conventional display device, for example, an OLED light-emitting device or a liquid crystal, a color filter substrate, and the like, which are not described in detail herein.
  • the specific type of the display device is not particularly limited, and includes, for example, but not limited to, a display panel and a device including the display panel, such as an LCD display panel, an OLED display panel, a mobile phone, a tablet, and a wearable device. , game consoles, etc.
  • Embodiment 1 (refer to FIGS. 5a to 5d, the glass substrate, the gate, the gate insulating layer are not shown)
  • barrier layer (Barrier layer, SiNx / SiOx);
  • Gate layer PVD coating, photoresist coating (PR coating), exposure, development, wet etching, photoresist stripping (PR Strip), wherein the gate layer may be Mo, Mo/Al Double layer structure, etc.
  • gate insulating layer (GI layer) CVD coating SiNx / SiOx
  • active layer Active layer, indium gallium zinc oxide (IGZO) PVD coating, PR Coating, exposure, development, wet etching, PR Strip;
  • I ds represents the source current
  • V gs represents the gate source voltage
  • Comparative Example 1 (refer to Figures 6a to 6b, the glass substrate, the gate, the gate insulating layer are not shown)
  • I ds represents the source current
  • V gs represents the gate source voltage
  • the transfer characteristic curve of the thin film transistor in Embodiment 1 is substantially unchanged with time, indicating that it has good stability; and the transfer characteristic curve of the thin film transistor in Comparative Example 1 changes greatly with time, indicating The thin film transistor in Comparative Example 1 was inferior in stability.
  • the thin film transistor of Embodiment 1 has a low source current, and the threshold voltage is not high, and the electrical effect is excellent; and the threshold voltage of the thin film transistor in Comparative Example 1 is large at the beginning, indicating that the electrical effect is generally The threshold voltage gradually decreases with time, but the source current is too large, and the electrical effect is still not ideal.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • the meaning of "a plurality” is two or more unless specifically and specifically defined otherwise.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

提供了薄膜晶体管及其制备方法、显示基板和显示装置，该制备薄膜晶体管的方法包括提供栅极（400）、源极（600）、漏极（700）与有源层（100），所述源极（600）与漏极（700）分别与所述有源层（100）相接触，所述栅极（400）与所述源极（600）、漏极（700）和有源层（100）电性绝缘，其中，所述薄膜晶体管的源极（600）与漏极（700）通过以下步骤形成：在有源层（100）的上表面形成金属层（200）；在所述金属层（200）上形成上端开口的凹槽（300），所述凹槽（300）的底部与所述有源层（100）之间保留有残留金属层（211）；对所述残留金属层（211）进行氧化处理，形成金属氧化物层（212）。该制备薄膜晶体管的方法操作简单、方便，容易实现，易于工业化生产，产能高，在蚀刻所述金属层（200）以形成源极（600）和漏极（700）时可以保护有源层（100）不被蚀刻，从而使得由该方法制备的薄膜晶体管具有优异的电学性能以及良好的稳定性。

Description

薄膜晶体管及其制备方法、显示基板和显示装置 技术领域
本发明涉及半导体技术领域，具体的，涉及薄膜晶体管及其制备方法、显示基板和显示装置。
背景技术
目前的TFT(薄膜晶体管)中，BCE(背沟道蚀刻型)结构因没有蚀刻阻挡层从而在进行蚀刻以形成源极和漏极时会对有源层造成蚀刻，使得TFT的电学性能较差，而ESL(蚀刻阻挡型)结构会在有源层上增加一层绝缘层，从而在进行蚀刻以形成源极和漏极时保护下方的有源层不受到蚀刻，避免影响电学性能，但是ESL结构会因此多形成一道光罩，影响产能。
因而，现有制备薄膜晶体管的相关技术仍有待改进。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的一个目的在于提出一种操作简单、方便、容易实现、易于工业化生产、产能高、在进行蚀刻以形成源极和漏极时可以保护有源层不被蚀刻、使获得的薄膜晶体管具有优异的电学性能、或者良好的稳定性的制备薄膜晶体管的方法。
在本发明的一个方面，本发明提供了一种制备薄膜晶体管的方法。根据本发明的实施例，所述薄膜晶体管包括栅极、源极、漏极与有源层，所述源极与漏极分别与所述有源层相接触，所述栅极与所述源极、漏极和有源层电性绝缘，在该制备薄膜晶体管的方法中，所述源极与漏极通过以下步骤形成：在有源层的上表面形成金属层；在所述金属层上形成上端开口的凹槽，所述凹槽的底部与所述有源层之间保留有残留金属层；对所述残留金属层进行氧化处理，形成金属氧化物层。发明人发现，该制备薄膜晶体管的方法操作简单、方便，容易实现，易于工业化生产，产能高，在进行蚀刻以形成源极和漏极时可以保护有源层不被蚀刻，从而使得由该方法制备的薄膜晶体管具有优异的电学性能以及良好的稳定性。
根据本发明的实施例，所述残留金属层的厚度为
Figure PCTCN2017113394-appb-000001
根据本发明的实施例，所述金属层包括多个层叠设置的金属亚层，与所述有源层直接 接触的金属亚层的一部分构成所述残留金属层。
根据本发明的实施例，所述金属层包括第一钛亚层，所述第一钛亚层设置在所述有源层的上表面；铝亚层，所述铝亚层设置在所述第一钛亚层的上表面；第二钛亚层，所述第二钛亚层设置在所述铝亚层的上表面；其中，所述第一钛亚层的一部分构成所述残留金属层。
根据本发明的实施例，所述在所述金属层上形成上端开口的凹槽是通过干法蚀刻形成的。
根据本发明的实施例，在形成所述凹槽之后，进行所述氧化处理之前，还包括对所述凹槽的侧壁进行钝化处理，形成钝化层。
根据本发明的实施例，所述氧化处理是利用臭氧和氧气等离子体中的至少一种进行的。
在本发明的另一个方面，本发明提供了一种薄膜晶体管。根据本发明的实施例，该晶体管是利用前面所述的方法制备的。发明人发现，该薄膜晶体管的有源层不会在进行蚀刻以形成源极和漏极时被蚀刻，具有优异的电学性能以及良好的稳定性。
在本发明的又一个方面，本发明提供了一种显示基板。根据本发明的实施例，该显示基板包括前面所述的薄膜晶体管。发明人发现，该显示基板具有优异的电学性能以及良好的稳定性，进而应用于显示装置时能够实现理想的显示效果，且具有上述薄膜晶体管的所有特征和优点，在此不再过多赘述。
在本发明的再一个方面，本发明提供了一种显示装置。根据本发明的实施例，该显示装置包括前面所述的显示基板。发明人发现，该显示装置具有优异的电学性能以及良好的稳定性，能够实现理想的显示效果，且具有上述薄膜晶体管和显示基板的所有特征和优点，在此不再过多赘述。
附图说明
图1显示了本发明一个实施例的制备薄膜晶体管的方法的流程示意图。
图2a-图2c显示了本发明另一个实施例的制备薄膜晶体管的方法的流程示意图。
图3显示了本发明又一个实施例的制备薄膜晶体管的方法的流程示意图。
图4a至图4d显示了本发明再一个实施例的制备薄膜晶体管的方法的流程示意图。
图5a至图5d显示了本发明再一个实施例的制备薄膜晶体管的方法的流程示意图。
图6a至图6b显示了现有技术中的制备薄膜晶体管的方法的流程示意图。
图7显示了本发明一个实施例的薄膜晶体管的结构示意图。
图8显示了本发明实施例制备的薄膜晶体管的转移特性曲线。
附图标记：
100：有源层 200：金属层 210：第一钛亚层 211：残留金属层 212：金属氧化物层 220：铝亚层 230：第二钛亚层 300：凹槽 310：钝化层 400：栅极 500：栅绝缘层 600：源极 700：漏极
具体实施方式
下面详细描述本发明的实施例。下面描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规产品。
在本发明的一个方面，本发明提供了一种制备薄膜晶体管的方法。根据本发明的实施例，参照图1和图2a至图2c，所述薄膜晶体管包括栅极、源极、漏极与有源层，所述源极与漏极分别与所述有源层相接触，所述栅极与所述源极、漏极和有源层电性绝缘，在该制备薄膜晶体管的方法中，所述薄膜晶体管的源极与漏极通过以下步骤形成：
S100：在有源层100的上表面形成金属层200，结构示意图参见图2a。
根据本发明的实施例，形成所述有源层100的具体材料种类不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以包括但不限于a-Si(无定形硅)、p-Si(低温多晶硅)、有机半导体材料、或者无机金属氧化物等。在本发明的一些实施例中，形成所述有源层100的具体材料种类可以为无机金属氧化物，例如包括但不限于ZnO、Zn-Sn-O、In-Zn-O、MgZnO、In-Ga-O、In2O2等。由此，可以使得制备的薄膜晶体管具有较高的开关电流比和较高的场效应迁移率，响应速度快，能够实现较大的驱动电流，且材料价廉、易得，成本较低。
根据本发明的实施例，所述金属层200的具体材料种类不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以包括但不限于Al、Cu、Ag、Ti、Pt、Mo等。在本发明的一些实施例中，所述金属层200的具体材料种类可以包括Ti、Al、Mn。由此，构成薄膜晶体管的源极与漏极的具体材料功函数均较低，可以使得源极与漏极与有源层之间的接触电阻减小，从而具有良好的物理接触和能级匹配。
根据本发明的实施例，所述金属层200的厚度不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择。在本发明的一些实施例中，所述金属层200的厚度可以为
Figure PCTCN2017113394-appb-000002
根据本发明的实施例，在所述有源层100的上表面形成所述金属层200的具体方法不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以包括但不限于磁控溅射镀膜法、脉冲激光沉积镀膜法、分子束外延法、溶胶凝胶法、金属有机化学气相沉积法等。在本发明的一些实施例中，在所述有源层100的上表面形成所述金属层200的具体方法可以为磁控溅射镀膜法。由此，操作简单、方便，容易实现，易于工业化生产，且可控性和重复性均较佳。
S200：在所述金属层200上形成上端开口的凹槽300，所述凹槽300的底部与所述有源层100之间保留有残留金属层211，结构示意图参见图2b。
根据本发明的实施例，所述凹槽300是通过蚀刻的方法形成的，所述蚀刻方法的具体种类不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以包括但不限于干法蚀刻、湿法蚀刻等。在本发明的一些实施例中，在所述金属层200上形成所述凹槽300的具体方法可以为干法蚀刻。由此，可以进行各向异性蚀刻，且具有良好的蚀刻选择性，加工批量大，容易控制，成本低，对环境污染少，适用于工业生产。
根据本发明的实施例，所述干法蚀刻的具体种类不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以包括离子铣蚀刻、等离子蚀刻、或者反应离子蚀刻等。在本发明的一些实施例中，所述干法蚀刻的具体种类可以为等离子蚀刻。由此，具有较好的蚀刻选择性和较高的刻蚀速率。
根据本发明的实施例，所述等离子蚀刻的具体工艺参数，例如压力、功率、气体流量等均不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择。在本发明的一些实施例中，进行所述蚀刻时的压力可以为8-12mT，功率可以为8-20kW，气体流量可以为3000-5000sccm。由此，在蚀刻过程中的各个工艺参数均为最佳工艺参数，使得该制备薄膜晶体管的方法进一步适用于实际工业生产。
根据本发明的实施例，在所述凹槽300的底部与所述有源层100之间保留残留金属层211的具体方法不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以包括但不限于利用EPD(蚀刻终点检测仪)检测蚀刻终点，然后通过控制蚀刻时间使得保留一部分残留金属层等。在本发明的一些实施例中，当金属层200为单一金属形成的单层结构时，可以直接通过控制蚀刻时间等参数仅蚀刻部分金属层形成凹槽300，从而在凹槽300底部与有源层之间保留残留金属层；当金属层200为多层金属亚层的多层结构时，可以利用EPD检测蚀刻终点(即不同金属亚层的界面)，当EPD检测到与有源层直接接触的金属亚层与其上表面的金属亚层之间的界面时，控制继续蚀刻的时间等参数，从而使得形成的凹槽300底部与有源层之间保留残留金属层。由此，可以避免蚀刻过程中 对有源层产生伤害而影响薄膜晶体管的电学性能，且该操作简单方便、且准确度较高。
根据本发明的实施例，所述残留金属层211的厚度不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择。在本发明的一些实施例中，所述残留金属层211的厚度可以为
Figure PCTCN2017113394-appb-000003
在本发明的一些更加优选的实施例中，所述残留金属层211的厚度可以为
Figure PCTCN2017113394-appb-000004
由此，可以在对金属层200进行蚀刻以形成薄膜晶体管的源极与漏极时有效保护有源层100不被蚀刻，从而使得由该方法制备的薄膜晶体管具有优异的电学性能以及良好的稳定性。
S300：对所述残留金属层211进行氧化处理，形成金属氧化物层212，结构示意图参见图2c。
根据本发明的实施例，所述氧化处理的具体工艺不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择，例如可以采用氧含量比较高的气体对残留金属层进行氧化处理，使其形成金属氧化物层。在本发明的一些实施例中，通过等离子体发生器生成氧气等离子体或者通过臭氧发生器生成臭氧对所述残留金属层211进行氧化处理，以形成金属氧化物层212。由于金属氧化物层212为绝缘体，可以使得由该方法制备成的薄膜晶体管的源极与漏极之间不会出现短路现象。
根据本发明的实施例，所述氧化处理的具体工艺参数，例如温度、压力，气体流量等均不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择。
根据本发明的另一个实施例，参照图3和图4a至图4d，该制备薄膜晶体管的方法该可以包括以下步骤：
S400：在形成所述凹槽300之后，进行所述氧化处理之前，还包括对所述凹槽300的侧壁进行钝化处理，形成钝化层310的步骤，结构示意图参见图4c和图4d。
根据本发明的实施例，对所述凹槽300的侧壁进行钝化处理的具体工艺不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择。在本发明的一些实施例中，对所述凹槽300的侧壁进行钝化处理的具体工艺可以为通入CF4和O2的混合气体使得所述凹槽300的侧壁发生钝化。由此，可以在对所述凹槽300的侧壁进行保护，以使得其不会发生腐蚀，使用效果更佳。
根据本发明的实施例，所述对所述凹槽300的侧壁进行钝化处理的具体工艺参数，例如温度、压力、CF4和O2的分压、气体流量、钝化时间等均不受特别限制，只要满足要求，本领域技术人员可以根据需要进行灵活选择。
根据本发明的又一个实施例，参照图5a，所述金属层200可以具体包括：第一钛亚层210，所述第一钛亚层210设置在所述有源层100的上表面；铝亚层220，所述铝亚层220 设置在所述第一钛亚层210的上表面；第二钛亚层230，所述第二钛亚层230设置在所述铝亚层220的上表面；其中，所述第一钛亚层210的一部分构成所述残留金属层211。所述金属层200为三层结构，上下两层均为钛，中间为铝。由此，降低了成本，更加易于实现大规模工业生产。
根据本发明的实施例，参照图5a至图5d，该实施例中制备薄膜晶体管方法可以包括以下步骤：首先，在有源层100的上表面依次形成第一钛亚层210、铝亚层220和第二钛亚层230，三者共同构成金属层200，得到的产品结构示意图参见图5a；接着，在所述金属层200上形成上端开口的凹槽300，剩余残留金属层211，其中，第一钛亚层210构成所述残留金属层211，得到的产品结构示意图参见图5b；然后，对所述凹槽300的侧壁进行钝化处理，形成钝化层310，得到的产品结构示意图参见图5c；接下来，对所述残留金属层211进行氧化处理，形成金属氧化物层212，得到的产品结构示意图参见图5d。其中，各个步骤均可与前面实施例中所述的具体方法相同，在此不再过多赘述。
在本发明的另一个方面，本发明提供了一种薄膜晶体管。根据本发明的实施例，该晶体管是利用前面所述的方法制备的。发明人发现，该薄膜晶体管的有源层100不会在蚀刻源极和漏极时被蚀刻，具有优异的电学性能以及良好的稳定性。
根据本发明的实施例，该薄膜晶体管的具体结构不受特别限制，只要满足使用要求，本领域技术人员可以根据需要灵活选择。且本领域技术人员可以理解，除前面所述的有源层和源极与漏极结构外，该薄膜晶体管具有常规薄膜晶体管的其他结构，例如还包括栅极、栅绝缘层等，在此不再过多赘述。
在本发明的一些实施例中，参照图7，该薄膜晶体管包括：栅极400、栅绝缘层500、有源层100、源极600、漏极700、金属氧化物层212。所述栅绝缘层500位于所述栅极400上表面，所述有源层100位于所述栅绝缘层500上表面，所述源极600位于所述有源层100上表面的一侧，所述漏极700位于所述有源层100上表面的另一侧，且所述源极600和所述漏极700依次包括第一钛亚层210、铝亚层220和第二钛亚层230三层结构，所述金属氧化物层212位于所述有源层100上表面且在所述源极600和所述漏极700之间。
在本发明的又一个方面，本发明提供了一种显示基板。根据本发明的实施例，该显示基板包括前面所述的薄膜晶体管。发明人发现，该显示基板具有优异的电学性能以及良好的稳定性，应用于显示装置时能够实现理想的显示效果，且具有上述薄膜晶体管的所有特征和优点，在此不再过多赘述。
根据本发明的实施例，该显示基板的构造、制造工艺均不受特别限制，只要满足使用要求，本领域技术人员可以根据需要灵活选择。且本领域技术人员可以理解，除了前面所 述的薄膜晶体管之外，该显示基板具有常规显示基板的结构，例如包括控制电路、电极等等，在此不再过多赘述。
在本发明的再一个方面，本发明提供了一种显示装置。根据本发明的实施例，该显示装置包括前面所述的显示基板。发明人发现，该显示装置具有优异的电学性能以及良好的稳定性，能够实现理想的显示效果，且具有上述薄膜晶体管和显示基板的所有特征和优点，在此不再过多赘述。
根据本发明的实施例，该显示装置的形状、构造、制造工艺均不受特别限制，只要满足使用要求，本领域技术人员可以根据需要灵活选择。且本领域技术人员可以理解，除了前面所述的显示基板，该显示装置具有常规显示装置的结构，例如还可以包括OLED发光器件或液晶、彩膜基板等等，在此不再过多赘述。
根据本发明的实施例，该显示装置的具体种类不受特别限制，例如包括但不限于显示面板和包括显示面板的设备等，如LCD显示面板、OLED显示面板、手机、平板电脑、可穿戴设备、游戏机等等。
下面详细描述本发明的实施例。
实施例1(参照图5a至图5d，图中未示出玻璃衬底、栅极、栅绝缘层)
薄膜晶体管制备方法：
a、玻璃衬底上进行CVD镀膜，形成阻隔层(Barrier层，SiNx/SiOx)；
b、栅极层(Gate层)PVD镀膜、光刻胶涂覆(PR Coating)、曝光、显影、湿蚀刻、光刻胶剥离(PR Strip)，其中，栅极层可以为Mo、Mo/Al双层结构等等；
c、栅绝缘层(GI层)CVD镀膜(SiNx/SiOx)；
d、有源层(Active层，铟镓锌氧化物(IGZO))PVD镀膜、PR Coating、曝光、显影、湿蚀刻、PR Strip；
e、源漏极层(SD层，Ti/Al/Ti)PVD镀膜(得到的产品结构示意图可参见图5a)、PR Coating、曝光、显影、干蚀刻、PR Strip(得到的产品结构示意图可参见图5b)，其中，刻蚀步骤中与有源层直接接触的Ti层未被全部刻蚀，保留一部分，厚度约为
Figure PCTCN2017113394-appb-000005
f、利用CF4/O2气体对刻蚀得到的凹槽的侧壁进行钝化处理(得到的产品结构示意图可参见图5c)；
g、氧气等离子体(O2Plasma)处理，形成TiOx，得到薄膜晶体管，得到的产品结构示意图可参见图5d。
分别在放置一天后、三天后、十五天后采用TEG机台测试得到的薄膜晶体管的转移特 性曲线，测试结果见图7，图中Ids表示源电流，Vgs表示栅源电压。
对比例1(参照图6a至图6b，图中未示出玻璃衬底、栅极、栅绝缘层)
薄膜晶体管制备方法：
a、Glass上进行CVD镀膜，成Barrier层(SiNx/SiOx)；
b、Gate层PVD镀膜、PR Coating、曝光、显影、湿蚀刻、PR Strip，其中，Gate层可为Mo、Mo/Al双层结构等等；
c、GI层(SiNx/SiOx)CVD镀膜；
d、Active层(IGZO)PVD镀膜、PR Coating、曝光、显影、湿蚀刻、PR Strip；
e、SD层(Ti/Al/Ti)PVD镀膜(得到的产品结构示意图可参见图6a)、PR Coating、曝光、显影、干蚀刻、PR Strip，其中，蚀刻步骤中SD层蚀刻干净，没有残留，得到薄膜晶体管，得到的产品结构示意图可参见图6b。
分别在放置一天后、三天后、十五天后采用TEG机台测试得到的薄膜晶体管的转移特性曲线，测试结果见图7，图中Ids表示源电流，Vgs表示栅源电压。
根据图7，实施例1中的薄膜晶体管随时间变化其转移特性曲线基本不变，表明其具有良好的稳定性；而对比例1中的薄膜晶体管随时间变化其转移特性曲线变化较大，表明对比例1中的薄膜晶体管的稳定性较差。
根据图7，实施例1中的薄膜晶体管其源电流不高，同时阈值电压也不高，电性效果优异；而对比例1中的薄膜晶体管开始时阈值电压较大，表明其电性效果一般，随时间变化阈值电压逐渐减小，但源电流过大，电性效果仍不理想。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 一种制备薄膜晶体管的方法，所述薄膜晶体管包括栅极、源极、漏极与有源层，所述源极与漏极分别与所述有源层相接触，所述栅极与所述源极、漏极和有源层电性绝缘，其特征在于，所述源极与所述漏极通过以下步骤形成：
    在所述有源层的上表面形成金属层；
    在所述金属层上形成上端开口的凹槽，所述凹槽的底部与所述有源层之间保留有残留金属层；
    对所述残留金属层进行氧化处理，形成金属氧化物层。
  2. 根据权利要求1所述的方法，其特征在于，所述残留金属层的厚度为
    Figure PCTCN2017113394-appb-100001
  3. 根据权利要求1所述的方法，其特征在于，所述金属层包括多个层叠设置的金属亚层，与所述有源层直接接触的金属亚层的一部分构成所述残留金属层。
  4. 根据权利要求3所述的方法，其特征在于，所述金属层包括：
    第一钛亚层，所述第一钛亚层设置在所述有源层的上表面；
    铝亚层，所述铝亚层设置在所述第一钛亚层的上表面；
    第二钛亚层，所述第二钛亚层设置在所述铝亚层的上表面；
    其中，所述第一钛亚层的一部分构成所述残留金属层。
  5. 根据权利要求1所述的方法，其特征在于，所述在所述金属层上形成上端开口的凹槽是通过干法蚀刻形成的。
  6. 根据权利要求1所述的方法，其特征在于，在形成所述凹槽之后，进行所述氧化处理之前，还包括：
    对所述凹槽的侧壁进行钝化处理，形成钝化层。
  7. 根据权利要求1所述的方法，其特征在于，所述氧化处理是利用臭氧和氧气等离子体中的至少一种进行的。
  8. 一种薄膜晶体管，其特征在于，是利用权利要求1-7中任一项所述的方法制备的。
  9. 一种显示基板，其特征在于，包括权利要求8所述的薄膜晶体管。
  10. 一种显示装置，其特征在于，包括权利要求9所述的显示基板。
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CN101908537A (zh) * 2009-06-03 2010-12-08 乐金显示有限公司 用于显示设备的阵列基板及其制造方法
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CN101908537A (zh) * 2009-06-03 2010-12-08 乐金显示有限公司 用于显示设备的阵列基板及其制造方法
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