WO2019097685A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2019097685A1
WO2019097685A1 PCT/JP2017/041524 JP2017041524W WO2019097685A1 WO 2019097685 A1 WO2019097685 A1 WO 2019097685A1 JP 2017041524 W JP2017041524 W JP 2017041524W WO 2019097685 A1 WO2019097685 A1 WO 2019097685A1
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WIPO (PCT)
Prior art keywords
metal pattern
solder resist
semiconductor module
semiconductor chip
insulating substrate
Prior art date
Application number
PCT/JP2017/041524
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English (en)
French (fr)
Inventor
貴之 松本
林田　幸昌
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三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112017008209.9T priority Critical patent/DE112017008209B4/de
Priority to CN201780096759.6A priority patent/CN111344858B/zh
Priority to JP2019554150A priority patent/JP6760518B2/ja
Priority to US16/638,071 priority patent/US11049803B2/en
Priority to PCT/JP2017/041524 priority patent/WO2019097685A1/ja
Publication of WO2019097685A1 publication Critical patent/WO2019097685A1/ja

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Definitions

  • the present invention relates to a semiconductor module.
  • a semiconductor chip and a terminal are soldered to a metal pattern of an insulating substrate.
  • a metal pattern is adsorbed by a suction pad of a mounter (see, for example, Patent Document 1).
  • the suction pad is mainly made of silicone
  • the silicone of the suction pad is volatilized to generate siloxane gas.
  • the siloxane gas is oxidized to contaminate the surface of the adsorbed metal pattern with the SiO 2 film.
  • the strength of wire bonding or soldering to be bonded to the metal pattern is reduced.
  • the adhesion between the metal pattern and the sealing material contaminated with the SiO 2 film may be reduced to peel off the sealing material, and the peeling may extend and the adhesion between the semiconductor chip and the sealing material may be reduced. As a result, there is a problem that a device failure occurs.
  • the present invention has been made to solve the problems as described above, and an object thereof is to obtain a semiconductor module capable of reducing the occurrence of device failure.
  • a semiconductor module according to the present invention comprises an insulating substrate, a metal pattern provided on the insulating substrate, a solder resist provided on the metal pattern, and an opening on the metal pattern in the opening of the solder resist. And a suction region surrounded by a groove is provided in a part of the solder resist.
  • an adsorption region surrounded by a groove is provided in part of the solder resist.
  • the adsorption area is adsorbed by the adsorption pad, the surface of the adsorption area is contaminated with the SiO 2 film, but the adsorption area which is a part of the solder resist is not used for direct bonding of semiconductor chips etc. .
  • the adhesion between the suction area and the sealing material is lowered and the sealing material is peeled, since the extension of the peeling is suppressed by the groove surrounding the suction area, the peeling does not easily extend to the semiconductor chip. As a result, the occurrence of device failure can be reduced.
  • FIG. 1 is a plan view showing a semiconductor module according to Embodiment 1;
  • FIG. 2 is a cross-sectional view taken along line I-II of FIG.
  • FIG. 7 is a plan view showing a semiconductor module according to a second embodiment.
  • FIG. 18 is a plan view showing a semiconductor module according to Embodiment 3;
  • a semiconductor module according to the embodiment will be described with reference to the drawings.
  • the same or corresponding components may be assigned the same reference numerals and repetition of the description may be omitted.
  • FIG. 1 is a plan view showing a semiconductor module according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line I-II of FIG.
  • the insulating substrate 1 is, for example, a ceramic substrate, the metal pattern 2 is provided on the upper surface, and the metal pattern 3 is provided on the lower surface.
  • a solder resist 4 is provided on the metal pattern 2 to prevent solder leakage during soldering.
  • the semiconductor chip 5 is mounted on the metal pattern 2 at the opening of the solder resist 4.
  • Position recognition marks 7 are provided adjacent to the terminal bonding plating 6.
  • the position recognition mark 7 is a plating or a hole, and is used for wire bonding or alignment when bonding a terminal to the terminal bonding plating 6.
  • a circular adsorption area 9 surrounded by the groove 8 is provided in a part of the solder resist 4.
  • the adsorption area 9 is provided at the center of the insulating substrate 1.
  • the size of the suction area 9 is set to ⁇ 3 mm or more.
  • the size of the suction area 9 is preferably 10 mm or less.
  • the suction area 9 is suctioned by a suction pad.
  • the adsorption area 9 can be easily understood visually. Therefore, since the insulating substrate 1 can be automatically transported by the mounter, the workability can be improved, and the occurrence of defects due to human factors can be reduced. Since the adhesion between the solder resist 4 and the metal pattern 2 is high, the adsorption area 9 is not peeled off by adsorbing the adsorption area 9 and lifting the insulating substrate 1. After transporting the insulating substrate 1, the metal pattern 2, the solder resist 4 and the semiconductor chip 5 are sealed by the sealing material 10.
  • the suction area 9 surrounded by the groove 8 is provided in a part of the solder resist 4.
  • the adsorption area 9 is adsorbed by the adsorption pad, the surface of the adsorption area 9 is contaminated with the SiO 2 film, but the adsorption area 9 which is a part of the solder resist 4 has no use for directly bonding a semiconductor chip or the like.
  • the impact of Further even if the adhesion between the adsorption area 9 and the sealing material 10 is reduced and the sealing material 10 is peeled, the extension of the peeling is suppressed by the groove 8 surrounding the adsorption area 9, so the peeling is extended to the semiconductor chip 5 It is difficult to do. As a result, the occurrence of device failure can be reduced.
  • FIG. 3 is a plan view showing a semiconductor module according to the second embodiment.
  • suction areas 9 are provided at the four corners of the insulating substrate 1 respectively.
  • the stability of the insulating substrate 1 during transportation can be improved.
  • FIG. 4 is a plan view showing a semiconductor module according to the third embodiment.
  • the suction area 9 is provided adjacent to the terminal bonding plating 6. Thereby, the suction area 9 can be used as a position recognition mark. Therefore, the degree of freedom in design can be increased while saving space.
  • the semiconductor chip 5 is an IGBT or a diode, but may be a MOSFET or an SBD.
  • the semiconductor chip 5 is not limited to one formed of silicon, and may be formed of a wide band gap semiconductor having a larger band gap than silicon.
  • the wide band gap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond.
  • a semiconductor chip formed of such a wide band gap semiconductor can be miniaturized because of high voltage resistance and allowable current density.
  • the semiconductor module incorporating this semiconductor chip can also be miniaturized and highly integrated.
  • the heat resistance of the semiconductor chip is high, the heat radiation fins of the heat sink can be miniaturized, and the water cooling portion can be air cooled, so that the semiconductor module can be further miniaturized.

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Abstract

絶縁基板（１）の上に金属パターン（２）が設けられている。金属パターン（２）の上にソルダーレジスト（４）が設けられている。ソルダーレジスト（４）の開口部において金属パターン（２）の上に半導体チップ（５）が実装されている。金属パターン（２）、ソルダーレジスト（４）及び半導体チップ（５）は封止材（１０）により封止される。ソルダーレジスト（４）の一部に溝（８）で囲まれた吸着領域（９）が設けられている。

Description

半導体モジュール
　本発明は、半導体モジュールに関する。
　電鉄等に使用される半導体モジュールでは、絶縁基板の金属パターンに半導体チップ及び端子がはんだ付けされる。従来は絶縁基板を搬送する際に金属パターンをマウンタの吸着パッドで吸着していた（例えば、特許文献１参照）。
日本特開２００４－２４１６８９号公報
　吸着パッドは主にシリコーンで構成されるため、吸着パッドのシリコーンが揮発してシロキサンガスが発生する。このシロキサンガスが酸化して、吸着した金属パターンの表面がＳｉＯ２膜で汚染される。これにより、金属パターンに接合するワイヤーボンド又ははんだ付け等の強度が低下する。また、ＳｉＯ２膜で汚染された金属パターンと封止材の密着性が低下して封止材が剥がれ、その剥がれが伸展して半導体チップと封止材の密着性が低下する場合もある。この結果、デバイス不良が発生するという問題があった。
　本発明は、上述のような課題を解決するためになされたもので、その目的はデバイス不良の発生を低減させることができる半導体モジュールを得るものである。
　本発明に係る半導体モジュールは、絶縁基板と、前記絶縁基板の上に設けられた金属パターンと、前記金属パターンの上に設けられたソルダーレジストと、前記ソルダーレジストの開口部において前記金属パターンの上に実装された半導体チップとを備え、前記ソルダーレジストの一部に溝で囲まれた吸着領域が設けられていることを特徴とする。
　本発明では、ソルダーレジストの一部に溝で囲まれた吸着領域が設けられている。吸着領域を吸着パッドで吸着すると吸着領域の表面がＳｉＯ２膜で汚染されるが、ソルダーレジストの一部である吸着領域には半導体チップ等を直接接合する用途はないため、汚染の影響は少ない。また、吸着領域と封止材の密着性が低下して封止材が剥がれても、吸着領域を囲む溝により剥がれの伸展が抑制されるため、剥がれが半導体チップまで伸展しにくい。この結果、デバイス不良の発生を低減させることができる。
実施の形態１に係る半導体モジュールを示す平面図である。 図１のＩ－ＩＩに沿った断面図である。 実施の形態２に係る半導体モジュールを示す平面図である。 実施の形態３に係る半導体モジュールを示す平面図である。
　実施の形態に係る半導体モジュールについて図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、実施の形態１に係る半導体モジュールを示す平面図である。図２は、図１のＩ－ＩＩに沿った断面図である。絶縁基板１は例えばセラミック基板であり、上面に金属パターン２が設けられ、下面に金属パターン３が設けられている。
　金属パターン２の上に、はんだ付けの際にはんだ漏れを防ぐためのソルダーレジスト４が設けられている。ソルダーレジスト４の開口部において金属パターン２の上に半導体チップ５が実装されている。
　金属パターン２の半導体チップ５の実装部分以外に端子接合用めっき６が設けられている。位置認識マーク７が端子接合用めっき６に隣接して設けられている。位置認識マーク７は、めっき又は穴であり、ワイヤーボンドの際又は端子接合用めっき６に端子を接合する際の位置合わせに用いられる。
　ソルダーレジスト４の一部に溝８で囲まれた円形の吸着領域９が設けられている。吸着領域９は絶縁基板１の中央に設けられている。吸着パッドで吸着するため、吸着領域９の大きさをφ３ｍｍ以上にする。一方、省スペース化のため、吸着領域９の大きさはφ１０ｍｍ以下にすることが好ましい。また、ソルダーレジスト４に溝８を掘ることで吸着領域９が形成されるため、ソルダーレジスト４の吸着領域９とその他の部分は同じ材料からなり膜厚も同じである。
　絶縁基板１を搬送する際に吸着領域９を吸着パッドで吸着する。吸着領域９を溝８で囲むことにより、吸着領域９が視覚的に分かり易くなる。従って、絶縁基板１をマウンタにより自動搬送できるため、作業性が向上し、人的要因による不良の発生を低減させることができる。なお、ソルダーレジスト４と金属パターン２の密着性は高いため、吸着領域９を吸着して絶縁基板１を持ち上げる程度では吸着領域９は剥がれない。絶縁基板１を搬送した後、金属パターン２、ソルダーレジスト４及び半導体チップ５は封止材１０により封止される。
　以上説明したように、本実施の形態では、ソルダーレジスト４の一部に溝８で囲まれた吸着領域９が設けられている。吸着領域９を吸着パッドで吸着すると吸着領域９の表面がＳｉＯ２膜で汚染されるが、ソルダーレジスト４の一部である吸着領域９には半導体チップ等を直接接合する用途はないため、汚染の影響は少ない。また、吸着領域９と封止材１０の密着性が低下して封止材１０が剥がれても、吸着領域９を囲む溝８により剥がれの伸展が抑制されるため、剥がれが半導体チップ５まで伸展しにくい。この結果、デバイス不良の発生を低減させることができる。
実施の形態２．
　図３は、実施の形態２に係る半導体モジュールを示す平面図である。本実施の形態では吸着領域９が絶縁基板１の四隅にそれぞれ設けられている。このように絶縁基板１の上において吸着領域９を複数設けることにより、絶縁基板１の搬送時の安定性を向上させることができる。
実施の形態３．
　図４は、実施の形態３に係る半導体モジュールを示す平面図である。本実施の形態では吸着領域９が端子接合用めっき６に隣接して設けられている。これにより、吸着領域９を位置認識マークとして用いることができる。このため、省スペース化を図りつつ、設計の自由度を上げることができる。
　なお、半導体チップ５はＩＧＢＴ又はダイオードであるが、ＭＯＳＦＥＴ又はＳＢＤ等でもよい。また、半導体チップ５は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された半導体チップは、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された半導体チップを用いることで、この半導体チップを組み込んだ半導体モジュールも小型化・高集積化できる。また、半導体チップの耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。
１　絶縁基板、２　金属パターン、４　ソルダーレジスト、５　半導体チップ、７　位置認識マーク、８　溝、９　吸着領域、１０　封止材

Claims (5)

  1. 　絶縁基板と、
    　前記絶縁基板の上に設けられた金属パターンと、
    　前記金属パターンの上に設けられたソルダーレジストと、
    　前記ソルダーレジストの開口部において前記金属パターンの上に実装された半導体チップと、
    　前記金属パターン、前記ソルダーレジスト及び前記半導体チップを封止する封止材とを備え、
    　前記ソルダーレジストの一部に溝で囲まれた吸着領域が設けられていることを特徴とする半導体モジュール。
  2. 　前記吸着領域の大きさはφ３ｍｍ以上１０ｍｍ以下であることを特徴とする請求項１に記載の半導体モジュール。
  3. 　前記絶縁基板の上において前記吸着領域が複数設けられていることを特徴とする請求項１又は２に記載の半導体モジュール。
  4. 　前記金属パターンの上に設けられた端子接合用めっきを更に備え、
    　前記吸着領域は前記端子接合用めっきに隣接して設けられていることを特徴とする請求項１～３の何れか１項に記載の半導体モジュール。
  5. 　前記半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１～４の何れか１項に記載の半導体モジュール。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4131361A4 (en) * 2020-03-26 2024-02-14 Denka Company Limited CERAMIC CIRCUIT BOARD, HEAT DISSIPATION ELEMENT AND ALUMINUM-DIAMOND COMPLEX

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001185664A (ja) * 1999-12-24 2001-07-06 Toshiba Corp セラミックス回路基板
JP2002246731A (ja) * 2001-02-20 2002-08-30 Matsushita Electric Ind Co Ltd 回路基板とその製造方法
JP2004241689A (ja) * 2003-02-07 2004-08-26 Denso Corp マルチチップモジュールの実装構造並びに取外し方法及び取外し装置、マルチチップモジュール及びその製造方法並びにマルチチップモジュール上の部品の取外し方法
JP2005347659A (ja) * 2004-06-07 2005-12-15 Alps Electric Co Ltd 薄膜電子部品を備えた回路基板
WO2015107997A1 (ja) * 2014-01-14 2015-07-23 住友ベークライト株式会社 モジュール基板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199449A (ja) * 1996-01-19 1997-07-31 Hitachi Ltd 半導体集積回路装置の製造方法
JP3732378B2 (ja) * 2000-03-03 2006-01-05 新光電気工業株式会社 半導体装置の製造方法
JP2001250875A (ja) * 2000-03-03 2001-09-14 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
KR100778597B1 (ko) * 2003-06-03 2007-11-22 가시오게산키 가부시키가이샤 적층 반도체 장치와 그 제조방법
JP5641449B2 (ja) 2012-04-04 2014-12-17 山栄化学株式会社 はんだ実装基板及びその製造方法、並びに半導体装置
WO2014080476A1 (ja) * 2012-11-21 2014-05-30 三菱電機株式会社 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001185664A (ja) * 1999-12-24 2001-07-06 Toshiba Corp セラミックス回路基板
JP2002246731A (ja) * 2001-02-20 2002-08-30 Matsushita Electric Ind Co Ltd 回路基板とその製造方法
JP2004241689A (ja) * 2003-02-07 2004-08-26 Denso Corp マルチチップモジュールの実装構造並びに取外し方法及び取外し装置、マルチチップモジュール及びその製造方法並びにマルチチップモジュール上の部品の取外し方法
JP2005347659A (ja) * 2004-06-07 2005-12-15 Alps Electric Co Ltd 薄膜電子部品を備えた回路基板
WO2015107997A1 (ja) * 2014-01-14 2015-07-23 住友ベークライト株式会社 モジュール基板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4131361A4 (en) * 2020-03-26 2024-02-14 Denka Company Limited CERAMIC CIRCUIT BOARD, HEAT DISSIPATION ELEMENT AND ALUMINUM-DIAMOND COMPLEX
US11983586B2 (en) 2020-03-26 2024-05-14 Denka Company Limited Ceramic circuit board, heat-dissipating member, and aluminum-diamond composite

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