WO2019095924A1 - 一种利用极化掺杂制备增强型GaN基晶体管的方法 - Google Patents

一种利用极化掺杂制备增强型GaN基晶体管的方法 Download PDF

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WO2019095924A1
WO2019095924A1 PCT/CN2018/110708 CN2018110708W WO2019095924A1 WO 2019095924 A1 WO2019095924 A1 WO 2019095924A1 CN 2018110708 W CN2018110708 W CN 2018110708W WO 2019095924 A1 WO2019095924 A1 WO 2019095924A1
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房育涛
叶念慈
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厦门市三安集成电路有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the present invention relates to semiconductor material growth and semiconductor device fabrication, and more particularly to a method for fabricating an enhanced GaN-based transistor using polarization doping.
  • a gallium nitride based high electron mobility transistor is a heterojunction field effect transistor formed of an Al x Ga 1-x N barrier and a GaN channel layer due to an Al x Ga 1-x N barrier and a GaN trench
  • the channel interface has large spontaneous polarization and piezoelectric polarization discontinuity, so there is a large amount of residual polarization charge at the heterojunction interface to form a high concentration of two-dimensional electron gas at the interface.
  • the composition, thickness and crystal quality of the Al x Ga 1-x N barrier layer are important epitaxial parameters that affect the gallium nitride based transistor.
  • GaN-based HEMTs are widely used in high-frequency and high-voltage microwave devices because of their high concentration of two-dimensional electrons (2DEG), high mobility, and strong breakdown electric field.
  • the gallium-based HEMT is a normally open device.
  • the most commonly used transistor in power electronic circuits is a normally-off transistor, so it is necessary to fabricate a normally-off GaN-based transistor.
  • the barrier is implanted with a negative ion or a two-dimensional electron gas that depletes the conductive channel by growing a P-GaN layer on the barrier, thereby directly fabricating a normally-off GaN-based transistor.
  • the first method has the advantages of high temperature resistance and fast switching speed of the gallium nitride based transistor due to the fact that a silicon transistor is connected in series in the circuit.
  • the second method directly produces an enhanced GaN-based transistor, which can effectively exert the advantages of high temperature resistance, small on-resistance, and fast switching frequency of the GaN-based transistor, but the device is difficult to manufacture, the stability and reliability of the turn-on voltage, and device fabrication.
  • the process and the epitaxial structure are closely related.
  • the object of the present invention is to overcome the deficiencies of the prior art, and to provide a composite barrier epitaxial structure and a preparation method of the enhanced GaN-based transistor by using a polarization doping to obtain a P-type Al x Ga 1-x N barrier.
  • a composite barrier layer composed of a P-Al x Ga 1-x N layer and an Al x Ga 1-x N layer which are doped with a polarization-grading composition, not only a high on-resistance can be obtained but also a large one can be obtained. Turn on the voltage.
  • a method of preparing an enhanced GaN-based transistor using polarization doping comprising the steps of:
  • An Al x Ga 1-x N layer is grown on the x Ga 1-x N layer, the P-type Al x Ga 1-x N layer and the Al x Ga 1-x N layer forming a composite barrier layer; wherein the P The Al composition x of the -type Al x Ga 1-x N layer is changed from 35% to 15% to 10% to 0%, and the Al x Ga 1-x N layer is increased from 0% to 10% to 15 %-35% of the component gradient layer or x is 15%-35% of the component fixing layer;
  • the TMAl flow rate is reduced from 250-150 sccm to 120-0 sccm, the TMGa flow rate is increased from 65-120 sccm to 130-200 sccm, and the NH 3 flow rate is 9000. -12000 sccm; the P-type Al x Ga 1-x N layer has a thickness of 5-20 nm.
  • the surface temperature of the P-type Al x Ga 1-x N layer epitaxial growth is 1050-1100 ° C.
  • the TMAl flow rate is increased from 0-120 sccm to 150-250 sccm during the growth process, and the TMGa flow rate is decreased from 130-200 sccm to 65-120 sccm, NH. 3
  • the flow rate is 9000-12000 sccm; the thickness of the Al x Ga 1-x N layer is 5-20 nm.
  • the TMAl flow rate is 250-150 sccm during the growth process
  • the TMGa flow rate is 65-120 sccm
  • the NH 3 flow rate is 9000-12000 sccm
  • the Al x Ga The 1-x N layer has a thickness of 5-20 nm.
  • the surface temperature of the Al x Ga 1-x N layer epitaxial growth is 1050-1100 ° C.
  • step (3) metal is deposited on the predetermined source region and the drain region, respectively, and annealed at 850-950 ° C for 25-50 seconds to form an ohmic contact to form the source and the drain.
  • a metal is deposited on the surface of the exposed P-type Al x Ga 1-x N layer, and annealed at 600-800 ° C for 20-60 min to form a Schottky contact to form the gate.
  • the enhanced GaN-based transistor prepared by the above method comprises a substrate, a buffer layer, a channel layer and a composite barrier layer from bottom to top, a source, a drain and a gate are disposed on the composite barrier layer, and the gate is located at the source and between the drain electrode; said composite layer comprising a barrier disposed on the channel layer P- type Al x Ga 1-x N layer and the Al x 1-x N layer is provided on the P- type Al x Ga a Ga 1-x N layer in which the x of the P-type Al x Ga 1-x N layer is changed from 35% to 15% to 10% to 0%, and the Al x Ga 1-x N layer is an Al composition x of 15 %-35% of the component pinned layer or Al component x is increased from 0%-10% to 15%-35% of the composition gradient layer; the source and drain are formed with the Al x Ga 1-x N layer In ohmic contact, the gate forms a Schottky contact with the P-type Al x Ga 1-x N layer.
  • the present invention forms a P-type Al x Ga 1- by a polarization doping method above the channel layer by controlling the growth conditions of the barrier layer and utilizing the relationship between the polarization of Al x Ga 1-x N and the Al composition.
  • the x N layer is then grown on a P-type Al x Ga 1-x N layer to form a single layer of Al x Ga 1-x N to form a composite barrier structure.
  • the device turn-on voltage can be adjusted by the thickness of the composition of the P-type Al x Ga 1-x N, and the on-resistance can be adjusted by the thickness and composition of the single-layer Al x Ga 1-x N, thereby obtaining a high low on-resistance.
  • a stable device turn-on voltage can be obtained by combining a polarization-doped P-type barrier and an etch barrier with two depletion channel 2DEGs during device fabrication.
  • the Al composition of Al x Ga 1-x N gradually decreases, the spontaneous polarization decreases gradually. Therefore, there is a residual polarization negative charge in the graded layer in which the Al composition gradually decreases to form a polarized P type.
  • Al x Ga 1-x N layer When the single layer of Al x Ga 1-x N in the gate region is etched away, only 2DEG (two-dimensional electron gas) in the channel is depleted when only the P-type Al x Ga 1-x N layer remains. Thereby an enhanced GaN-based HEMT device is realized.
  • the production method is simple, no special process requirements, strong controllability, can effectively control the opening voltage and on-resistance of the device and improve the high-voltage characteristics of the device, which is suitable for practical production applications.
  • Figure 1 is a schematic cross-sectional view of the present invention
  • FIG. 3 is a schematic view showing a composite barrier layer in which an Al x Ga 1-x N layer is a fixed component according to Embodiment 1 of the present invention
  • FIG. 4 is a schematic view showing a composite barrier layer in which an Al x Ga 1-x N layer is a graded composition according to Embodiment 2 of the present invention.
  • an enhancement type GaN-based transistor includes a substrate 1, a buffer layer 2, a channel layer 3, and a composite barrier layer from bottom to top, and a source electrode 6 and a drain electrode 7 are disposed on the composite barrier layer.
  • a gate 8 having a gate 8 between the source 6 and the drain 7;
  • the composite barrier layer comprising a P-type Al x Ga 1-x N layer 4 disposed on the channel layer 3 and disposed on P- type Al x Ga 1-x Al x Ga 1-x N layer 5, on the preparation method 4 N layer comprises the steps of:
  • Buffer layer 2 (nucleation layer and transition layer) is grown on selected heteroepitaxial substrate 1 (sapphire, SiC, Si) by metal organic chemical vapor deposition (MOCVD) a 200 nm GaN channel layer 3 is grown on the buffer layer 2 at a high temperature (surface temperature 1040 ° C);
  • the flow rate of TMAl (trimethylaluminum) during this growth period is from 250-150 sccm to 120- 0sccm gradually decreases
  • TMGa (trimethylgallium) flow gradually increases from 65-120sccm to 130-200sccm while NH 3 flow rate is 9000-12000sccm
  • epitaxial growth surface temperature is 1050-1100 ° C; in the above MO flow, V /
  • the barrier growth rate is about 0.5 ⁇ m/h-1 ⁇ m/h under the growth conditions of III ratio and surface temperature
  • the Al composition (ie, x) of P-type Al x Ga 1-x N is gradually increased from 35% to 15%. Reduced to 10%-0%, thickness 5-20nm.
  • Al x Ga 1-x N which is gradually reduced due to the polarization effect component forms a P-type Al x Ga 1-x N layer 4.
  • This layer may be a gradual increase of the composition of the Al component.
  • the specific growth conditions are: the flow of TMAl increases from 0-120 sccm to 150-250 sccm during the growth process, and the TMGa flow decreases from 200-130 sccm to 120-65 sccm.
  • the flow rate of NH 3 is 9000-12000 sccm, and the surface temperature of epitaxial growth is 1050-1100 ° C; the growth rate of the barrier is 0.5 ⁇ m/h-1 ⁇ m/h under the growth conditions of MO flow, V/III ratio and surface temperature.
  • the Al composition of the Al x Ga 1-x N layer 5 is gradually increased from about 0% to about 10% to 15% to 35%, and the thickness is from 5 to 20 nm.
  • This layer may also be a fixed layer of a fixed Al component.
  • the specific growth conditions are: TMAl flow rate during the growth process is 150-250 sccm, TMGa flow rate is 65-120 sccm, and NH 3 flow rate is 9000-12000 sccm, epitaxial growth
  • the surface temperature is 1050-1100 ° C; the barrier growth rate is about 0.5-1 ⁇ m/h under the above MO flow rate, the V/III ratio and the surface temperature growth condition, and the Al composition of the Al x Ga 1-x N layer is 15
  • the thickness is about -35% and the thickness is 5-20 nm.
  • Source-drain electrodes Photoresist patterns required for preparing source-drain electrodes on the surface of AlxGal-xN layer 5 by photolithography (electron beam exposure (EBL), ultraviolet exposure (UVL)), overlying photoresist epitaxial wafers
  • EBL electron beam exposure
  • UVL ultraviolet exposure
  • the surface of the source and drain electrode metal Ti/Al/Ni/Au, thickness 20nm/150nm/70nm/100nm
  • the source and drain electrodes are annealed by a rapid annealing furnace (annealing temperature 850) -950 ° C, annealing time 25-50s, annealing is atmospheric nitrogen (nitrogen flow rate 6L / min)); as shown in Figures 1 and 2, source electrode 6, drain electrode 7;
  • the specific etching conditions are: power 300W/15W, pressure 5- 20mtorr, Cl 2 (10sccm-30sccm), Ar (5sccm-20sccm), etching rate of about 5-20nm / min, etching the surface of the Al x Ga 1-x N monolayer by controlling the etching time;
  • a gate metal a photoresist pattern required for preparing a gate electrode on a surface of a P-type Al x Ga 1-x N layer 4 by a photolithography method (electron beam exposure (EBL), ultraviolet exposure (UVL)), using magnetic
  • the controlled sputtering apparatus covers the photoresist epitaxial wafer vapor-deposited gate electrode (TiN, thickness 150-200 nm), strips the metal in the stripping solution to obtain a gate electrode, and annealed the gate electrode by an annealing furnace (annealing temperature 600-800 ° C, Annealing time 20-60min, annealing atmosphere is nitrogen (nitrogen flow rate 20L / min)); as shown in Figures 1 and 2, the gate electrode 8;
  • the buffer layer includes a high temperature (surface temperature of 1100 ° C) AlN nucleation layer of 200 nm, a 1.5 ⁇ m compositionally tapered AlGaN transition layer (Al 0.75 Ga 0.25 N-200 nm, Al 0.55 Ga 0.45 N-400 nm, Al 0.25 Ga 0.75 N -900 nm, surface temperature 1060 ° C) and then a 2.0 ⁇ m GaN high resistance layer (surface temperature 980 ° C) was grown.
  • the channel layer is a high temperature (surface temperature of 1060 ° C) GaN layer of 200 nm;
  • the polarization-doped P-type AlxGa 1-x N layer was epitaxially grown on the surface of the GaN channel layer of (1) by MOCVD.
  • the growth conditions are MO flow rate, wherein TMGa is increased from 90 linear shape to 150 sccm, TMAl is reduced from 200 sccm linear shape to 100 sccm, and NH 3 flow rate is 9000 sccm (Al composition is changed from 20% to 6%); growth time 50s is about 10 nm thick.
  • an Al x Ga 1-x N layer is grown, and the specific growth conditions are TMGa flow rate 60 sccm, TMAl flow rate 120 sccm, NH 3 flow rate 9000 sccm (Al composition is about 25%), growth time 90 s thickness about 15 nm, and the obtained composite potential
  • the structure of the barrier layer refers to Figure 3;
  • the photoresist pattern required for the source and the drain of the surface of the Al x Ga 1-x N layer by the ultraviolet lithography method (source-drain electrode edge pitch 25 ⁇ m, electrode length 20 ⁇ m, electrode width 100 ⁇ m), using electrons
  • the beam evaporation device evaporates Ti/Al/Ni/Au (20nm/150nm/70nm/100nm) on the surface of the photoresist; strips the metal in the stripping solution to obtain the source and drain electrodes, and uses the rapid annealing furnace to set the source and drain electrodes at 900 °C. Annealing for 50s (nitrogen flow rate 6L/min)) makes the source-drain electrode and the barrier form an ohmic contact;
  • the etching conditions are: power 300 W / 15 W, pressure 5 mtorr, Cl 2 (12 sccm), Ar (5 sccm), etching rate 6 nm / Around min, the etching time is 3 min 10 s; the 20 nm Al x Ga 1-x N layer etched away from the surface leaks out the polarization-doped P-type Al x Ga 1-x N layer;
  • sputtering apparatus covers the photoresist epitaxial wafer vapor-deposited gate electrode (TiN, thickness: 180 nm), strips the metal in the stripping solution to obtain a gate electrode, and anneals the gate electrode in a tubular annealing furnace at 650 ° C for 40 min in a nitrogen atmosphere.
  • the gate electrode and the P-type Al x Ga 1-x N layer form a Schottky contact.
  • the growth conditions of the Al x Ga 1-x N layer are: the TMAl flow rate gradually increases from 100 sccm to 200 sccm, and the TMGa flow rate gradually decreases from 150 sccm to 90 sccm while NH
  • the flow rate of 3 is 9000 sccm, and the surface temperature of epitaxial growth is 1070 ° C;
  • the growth rate of the barrier is about 0.6 ⁇ m/h under the growth conditions of the above MO flow rate, V/III ratio and surface temperature, and the Al x Ga 1-x N barrier
  • the Al composition of the layer is gradually increased from about 6% to 20%, and the thickness is about 10 nm.
  • the resulting composite barrier layer structure is referred to FIG.

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Abstract

本发明公开了一种通过极化掺杂的方法制备增强型GaN基晶体管的方法。利用AlN和GaN 的自发极化强度之间存在较大的差别，可以通过组分渐变AlxGa1-xN实现极化掺杂获得P型AlxGa1-xN层。在GaN基材料外延生长Al组分逐渐减小的P-型AlxGa1-xN层，然后在P-型AlxGa1-xN层上生长AlxGa1-xN层，AlxGa1-xN层为Al组分x从0%-10%增加到15%-35%的组分渐变层或x为15%-35%的组分固定层，再制作与AlxGa1-xN层形成欧姆接触的源、漏极以及与P-型AlxGa1-xN层形成肖特基接触的栅极。通过改变P-型AlxGa1-xN的组分厚度可以调节器件开启电压，通过改变AlxGa1-xN层的厚度和组分可以调节导通电阻，从而获得低导通电阻高开启电压的增强型GaN基晶体管。制作方法简单，无特殊工艺要求，可控性强。

Description

一种利用极化掺杂制备增强型GaN基晶体管的方法 技术领域
本发明涉及半导体材料生长和半导体器件制作，特别是涉及一种利用极化掺杂制备增强型GaN基晶体管的方法。
背景技术
氮化镓基高电子迁移率晶体管(HEMT)是由Al xGa 1-xN势垒和GaN沟道层形成的异质结场效应晶体管，由于Al xGa 1-xN势垒和GaN沟道层界面有着较大的自发极化和压电极化不连续性，因此在异质结界面存在大量的剩余极化电荷从而在界面形成高浓度的二维电子气。Al xGa 1-xN势垒层的组分，厚度以及晶体质量都是影响氮化镓基晶体管的关键外延参数。GaN基HEMT具有二维电子(2DEG)浓度高，迁移率高，击穿电场强等优点被广泛用于高频和高压微波器件。
由于GaN基HEMT的2DEG来自于极化电荷不连续性，因此在势垒没有掺杂和偏压的情况下，GaN沟道层中仍存在高浓度的二维电子气，所以通常情况下氮化镓基HEMT是常开型器件。在电力电子电路中最常用到的晶体管是常关型晶体管，因此需要制作常关型GaN基晶体管。通常实现常关型GaN基晶体管的方法有两大类：一种是将常开型GaN基晶体管与一个硅基常关晶体管组合封装实现常关晶体管的功能；另一种是直接通过刻蚀势垒，势垒注入负离子或者在势垒上生长P-GaN层耗尽导电沟道的二维电子气，从而直接制作出常关型GaN基晶体管。第一种方法由于在电路中串联了一个硅晶体管限制了氮化镓基晶体管具有的耐高温，开关速度快等优点的发挥。第二种方法直接制作增强型GaN基晶体管可以有效发挥GaN基晶体管的耐高温，导通电阻小，开关频率快等优点，但是其器件制作难度大，开启电压的稳定性和可靠性与器件制作工艺以及外延结构密切相关。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明的目的在于克服现有技术之不足，提供一种利用包含极化掺杂获得P-型Al xGa 1-xN势垒的复合势垒外延结构及增强型GaN基晶体管的制备方法，通过采用极化掺杂渐变组分的P-Al xGa 1-xN层和Al xGa 1-xN层构成的复合势垒层，不仅可以获得高的导通电阻同时可以获得较大的开启电压。
本发明解决其技术问题所采用的技术方案是：
一种利用极化掺杂制备增强型GaN基晶体管的方法，所述方法包括以下步骤：
(1)于一衬底上依次生长缓冲层和沟道层；
(2)采用MOCVD工艺，首先调节TMAl流量逐渐减小、TMGa流量逐渐增加于沟道层上生长极化掺杂的P-型Al xGa 1-xN层，然后改变流量于P-型Al xGa 1-xN层上生长Al xGa 1-xN层，所述P-型Al xGa 1-xN层和Al xGa 1-xN层组成复合势垒层；其中所述P-型Al xGa 1-xN层的Al组分x由35％-15％渐变到10％-0％，所述Al xGa 1-xN层为x从0％-10％增加到15％-35％的组分渐变层或x为15％-35％的组分固定层；
(3)于Al xGa 1-xN层表面上形成源极和漏极，所述源极和漏极分别Al xGa 1-xN层形成欧姆接触；
(4)于源极和漏极之间定义一栅极区域，去除栅极区域的Al xGa 1-xN层，于裸露的P-型Al xGa 1-xN层表面上形成栅极，所述栅极与P-型Al xGa 1-xN层形成肖特基接触。
可选的，所述P-型Al xGa 1-xN层的生长过程中TMAl流量由250-150sccm降低到120-0sccm，TMGa流量由65-120sccm增加到130-200sccm，NH 3流量为9000-12000sccm；所述P-型Al xGa 1-xN层的厚度为5-20nm。
可选的，所述P-型Al xGa 1-xN层外延生长的表面温度为1050-1100℃。
可选的，所述Al xGa 1-xN层为组分渐变层时，其生长过程中TMAl流量由0-120sccm增加到150-250sccm，TMGa流量由130-200sccm降低到65-120sccm，NH 3流量为9000-12000sccm；所述Al xGa 1-xN层的厚度为5-20nm。
可选的，所述Al xGa 1-xN层为组分固定层时，其生长过程中TMAl流量250-150sccm，TMGa流量为65-120sccm，NH3流量为9000-12000sccm，所述Al xGa 1-xN层的厚度为5-20nm。
可选的，所述Al xGa 1-xN层外延生长的表面温度为1050-1100℃。
可选的，步骤(3)中，于预设源极区域和漏极区域分别沉积金属，于850-950℃下退火25-50秒形成欧姆接触，形成所述源极和漏极。
可选的，步骤(4)中，于裸露的P-型Al xGa 1-xN层表面沉积金属，于600-800℃下退火20-60min形成肖特基接触，形成所述栅极。
由上述方法制备的增强型GaN基晶体管由下至上包括衬底、缓冲层、沟道层及复合势垒层，复合势垒层上设置有源极、漏极及栅极，且栅极位于源极和漏极之间；所述复合势垒层包括设于沟道层上的P-型Al xGa 1-xN层和设于P-型Al xGa 1-xN层上的Al xGa 1-xN层，其中P-型Al xGa 1-xN层的x由35％-15％渐变到10％-0％，Al xGa 1-xN层为Al组分x为15％-35％的组分固定层或者Al组分x由0％-10％增加到15％-35％的组分渐变层；所述源极和漏极与Al xGa 1-xN层形成欧姆接触，所述栅极与P-型Al xGa 1-xN层形成肖特基接触。
发明的有益效果
有益效果
本发明的有益效果是：
1.本发明通过控制势垒层的生长条件，利用Al xGa 1-xN极化强度与Al组分的关系在沟道层上方通过极化掺杂方法形成P-型Al xGa 1-xN层，然后在P-型Al xGa 1-xN层上生长单层Al xGa 1-xN形成复合势垒结构。通过P-型Al xGa 1-xN的组分厚度可以调节器件开启电压，通过单层Al xGa 1-xN的厚度和组分可以调节导通电阻，从而获得制备低导通电阻高开启电压的增强型GaN基晶体管外延材料。
2.在器件制作过程中通过结合极化掺杂P-型势垒和刻蚀势垒两种耗尽沟道2DEG的方法可以获得稳定的器件开启电压。当Al xGa 1-xN的Al组分逐渐减小时自发极化强度也逐渐减小，因此在Al组分逐渐减小的渐变层中会存在剩余的极化负电荷从而形成极化P型Al xGa 1-xN层。当栅极区域的单层Al xGa 1-xN被刻蚀掉后，仅剩下P型Al xGa 1-xN层时沟道中有2DEG(二维电子气)也会被耗尽，从而实现增强型GaN基HEMT器件。
3.制作方法简单，无特殊工艺要求，可控性强，可以有效控制器件的开启电压和导通电阻和改善器件高压特性，适合实际生产应用。
对附图的简要说明
附图说明
图1为本发明之截面结构示意图；
图2为本发明之俯视结构示意图；
图3为本发明实施例1的Al xGa 1-xN层为固定组分的复合势垒层的示意图；
图4为本发明实施例2的Al xGa 1-xN层为渐变组分的复合势垒层的示意图。
发明实施例
本发明的实施方式
下文中将结合附图对本发明的实施例进行详细说明。本发明的所有附图仅为示意以便更容易理解本发明，其具体比例可依照设计需求进行调整。本文中描述的器件制作过程中的元件的尺寸和个数仅为示例，实际可以根据设计需要对其进行调整。
参考图1和图2，一种增强型GaN基晶体管由下至上包括衬底1、缓冲层2、沟道层3及复合势垒层，复合势垒层上设置有源极6、漏极7及栅极8，且栅极8位于源极6和漏极7之间；所述复合势垒层包括设于沟道层3上的P-型Al xGa 1-xN层4和设于P-型Al xGa 1-xN层4上的Al xGa 1-xN层5，其制备方法包括如下步骤：
1)GaN沟道层及缓冲层生长：利用金属有机化学气相沉积设备(MOCVD)在所选用的异质外延衬底1(蓝宝石，SiC，Si)上生长缓冲层2(成核层和过渡层)，在缓冲层2上高温(表面温度1040℃)生长200nmGaN沟道层3；
2)在1)上面继续外延生长复合势垒层，为了获得P-型Al xGa 1-xN层4，这一层生长过程中TMAl(三甲基铝)流量从250-150sccm到120-0sccm逐渐减小，TMGa(三甲基镓)流量从65-120sccm到130-200sccm逐渐增加同时NH 3的流量为9000-12000sccm，外延生长的表面温度1050-1100℃；在上述MO流量，V/III比和表面温度的生长条件下势垒生长速度为0.5μm/h-1μm/h左右，P-型Al xGa 1-xN的Al组分(即x)从35％-15％左右逐渐降低到10％-0％，厚度为5-20nm。由于极化效应组分逐渐减低的Al xGa 1-xN形成P-型Al xGa 1-xN层4。
3)在P-型Al xGa 1-xN层4上面生长Al xGa 1-xN层5。这一层可以是Al组分逐渐增加的组分渐变层，具体生长条件为：生长过程中TMAl流量从0-120sccm到150-250sccm逐渐增加，TMGa流量从200-130sccm到120-65sccm逐渐减小同时NH 3的流 量为9000-12000sccm，外延生长的表面温度1050-1100℃；在上述MO流量，V/III比和表面温度的生长条件下势垒生长速度为0.5μm/h-1μm/h左右，Al xGa 1-xN层5的Al组分从0％-10％左右逐渐增加到15％-35％，厚度为5-20nm。这一层也可以是固定Al组分的组分固定层，具体生长条件为：生长过程中TMAl流量为150-250sccm，TMGa流量为65-120sccm，同时NH 3的流量为9000-12000sccm，外延生长的表面温度1050-1100℃；在上述MO流量，V/III比和表面温度的生长条件下势垒生长速度为0.5-1μm/h左右，Al xGa 1-xN层的Al组分为15％-35％左右，厚度为5-20nm。
4)制备源漏电极：通过光刻方法(电子束曝光(EBL)、紫外曝光(UVL))在AlxGal-xN层5表面制备源漏电极需要的光刻胶图形，在覆盖光刻胶外延片表蒸镀源漏电极金属(Ti/Al/Ni/Au，厚度20nm/150nm/70nm/100nm)，在剥离液中剥离金属得到源漏电极，利用快速退火炉将源漏电极退火(退火温度850-950℃，退火时间25-50s，退火是气氛是氮气(氮气流量6L/min))；如图1和2所示，源电极6，漏电极7；
5)利用ICP的方法刻蚀栅极区域的Al xGa 1-xN层5漏出P-型Al xGa 1-xN层4表面；具体刻蚀条件为：功率300W/15W，压力5-20mtorr，Cl 2(10sccm-30sccm)，Ar(5sccm-20sccm)，刻蚀速率5-20nm/min左右，通过控制刻蚀时间刻蚀掉表面的Al xGa 1-xN单层；
6)制备栅金属：通过光刻方法(电子束曝光(EBL)、紫外曝光(UVL))在P-型Al xGa 1-xN层4表面制备栅电极需要的光刻胶图形，用磁控溅射设备在覆盖光刻胶外延片表蒸镀栅电极(TiN，厚度150-200nm)，在剥离液中剥离金属得到栅电极，利用退火炉将栅电极退火(退火温度600-800℃，退火时间20-60min，退火气氛是氮气(氮气流量20L/min))；如图1和2所示，栅电极8；
下面以具体应用示例对本发明的实施以实例方式作进一步描述：
实施例1
(1)利用MOCVD在1mm的6寸硅衬底上生长沟道层和缓冲层。缓冲层包括200nm的高温(表面温度1100℃)AlN成核层，1.5μm的组分递变的AlGaN过渡层(Al 0.75Ga 0.25N-200nm，Al 0.55Ga 0.45N-400nm，Al 0.25Ga 0.75N-900nm，表面温度1060 ℃)和接着生长2.0μm的GaN高阻层(表面温度980℃)。沟道层为200nm的高温(表面温度为1060℃)GaN层；
(2)利用MOCVD继续在(1)的GaN沟道层表面外延生长极化掺杂的P-型AlxGa 1-xN层。生长条件为MO流量其中TMGa从90线形增加到150sccm，TMAl从200sccm线形减小到100sccm，同时NH 3的流量为9000sccm(Al组分从20％渐变到6％)；生长时间50s厚度为10nm左右；然后生长Al xGa 1-xN层，具体生长条件为TMGa流量60sccm，TMAl流量120sccm，同时NH 3流量9000sccm(Al组分约为25％)，生长时间90s厚度15nm左右，得到的复合势垒层结构参考图3；
(3)通过紫外光刻方法在Al xGa 1-xN层的表面指标源极和漏极所需要光刻胶图形(源漏电极边缘间距25μm，电极长度20μm，电极宽度100μm)，利用电子束蒸发设备在光刻胶表面蒸镀Ti/Al/Ni/Au(20nm/150nm/70nm/100nm)；在剥离液中剥离金属得到源漏电极，利用快速退火炉将源漏电极在900℃条件下退火50s(氮气流量6L/min))使源漏电极和势垒形成欧姆接触；
(4)通过ICP刻蚀栅极区域的Al xGa 1-xN单层，刻蚀条件为：功率300W/15W，压力5mtorr，Cl 2(12sccm)，Ar(5sccm)，刻蚀速率6nm/min左右，刻蚀时间3min10s；刻蚀掉表面的20nm的Al xGa 1-xN层漏出极化掺杂的P-型Al xGa 1-xN层；
(5)通过紫外曝光方法在势垒层表面源漏电极间制备栅电极需要的光刻胶图形(栅长2μm，距离源极距离3μm，距离漏极距离15μm，栅宽100μm)，用磁控溅射设备在覆盖光刻胶外延片表蒸镀栅电极(TiN，厚度180nm)，在剥离液中剥离金属得到栅电极，利用管式退火炉在650℃氮气气氛下将栅电极退火40min，使栅电极和P-型Al xGa 1-xN层形成肖特基接触。
实施例2
实施例2与实施例1的差别在于：步骤(2)中，Al xGa 1-xN层的生长条件为：TMAl流量从100sccm到200sccm逐渐增加，TMGa流量从150sccm到90sccm逐渐减小同时NH 3的流量为9000sccm，外延生长的表面温度1070℃；在上述MO流量，V/III比和表面温度的生长条件下势垒生长速度为0.6μm/h左右，Al xGa 1-xN势垒层的Al组分从6％左右逐渐增加到20％，厚度为10nm左右。得到 的复合势垒层结构参考图4。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

  1. 一种利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于包括以下步骤：
    (1)于一衬底上依次生长缓冲层和沟道层；
    (2)采用MOCVD工艺，首先调节TMAl流量逐渐减小、TMGa流量逐渐增加于沟道层上生长极化掺杂的P-型Al xGa 1-xN层，然后改变流量于P-型Al xGa 1-xN层上生长Al xGa 1-xN层，所述P-型Al xGa 1-xN层和Al xGa 1-xN层组成复合势垒层；其中所述P-型Al xGa 1-xN层的Al组分x由35％-15％渐变到10％-0％，所述Al xGa 1-xN层为x从0％-10％增加到15％-35％的组分渐变层或x为15％-35％的组分固定层；
    (3)于Al xGa 1-xN层表面上形成源极和漏极，所述源极和漏极分别与Al xGa 1-xN层形成欧姆接触；
    (4)于源极和漏极之间定义一栅极区域，去除栅极区域的Al xGa 1-xN层，于裸露的P-型Al xGa 1-xN层表面上形成栅极，所述栅极与P-型Al xGa 1-xN层形成肖特基接触。
  2. 根据权利要求1所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：所述P-型Al xGa 1-xN层的生长过程中TMAl流量由250-150sccm降低到120-0sccm，TMGa流量由65-120sccm噌加到130-200sccm，NH3流量为9000-12000sccm；所述P-型Al xGa 1-xN层的厚度为5-20nm。
  3. 根据权利要求1或2所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：所述P-型Al xGa 1-xN层外延生长的表面温度为1050-1100℃。
  4. 根据权利要求1所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：所述Al xGa 1-xN层为组分渐变层时，其生长过程中TMAl流量由0-120sccm增加到150-250sccm，TMGa流量由130-200sccm降低到65-120sccm，NH 3流量为9000-12000sccm；所述Al x Ga 1-xN层的厚度为5-20nm。
  5. 根据权利要求1所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：所述Al xGa 1-xN层为组分固定层时，其生长过程中TMAl流量为250-150sccm，TMGa流量为65-120sccm，NH 3流量为9000-12000sccm，所述Al xGa 1-xN层的厚度为5-20nm。
  6. 根据权利要求1、4或5所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：所述Al xGa 1-xN层外延生长的表面温度为1050-1100℃。
  7. 根据权利要求1所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：步骤(3)中，于预设源极区域和漏极区域分别沉积金属，于850-950℃下退火25-50秒形成欧姆接触，形成所述源极和漏极。
  8. 根据权利要求1所述的利用极化掺杂制备增强型GaN基晶体管的方法，其特征在于：步骤(4)中，于裸露的P-型Al xGa 1-xN层表面沉积金属，于600-800℃下退火20-60min形成肖特基接触，形成所述栅极。
  9. 一种由权利要求1-8任一项所述方法制备的增强型GaN基晶体管，其特征在于：所述晶体管由下至上包括衬底、缓冲层、沟道层及复合势垒层，复合势垒层上设置有源极、漏极及栅极，且栅极位于源极和漏极之间；所述复合势垒层包括设于沟道层上的P-型Al xGa 1-xN层和设于P-型Al xGa 1-xN层上的Al xGa 1-xN层，其中P-型Al xGa 1-xN层的x由35％-15％渐变到10％-0％，Al xGa 1-xN层为Al组分x为15％-35％的组分固定层或者Al组分x由0％-10％增加到15％-35％的组分渐变层；所述源极和漏极与Al xGa 1-xN层形成欧姆接触，所述栅极与P-型Al xGa 1-xN层形成肖特基接触。
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