WO2019095441A1 - Oled驱动电路及amoled显示面板 - Google Patents

Oled驱动电路及amoled显示面板 Download PDF

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Publication number
WO2019095441A1
WO2019095441A1 PCT/CN2017/114035 CN2017114035W WO2019095441A1 WO 2019095441 A1 WO2019095441 A1 WO 2019095441A1 CN 2017114035 W CN2017114035 W CN 2017114035W WO 2019095441 A1 WO2019095441 A1 WO 2019095441A1
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Prior art keywords
thin film
film transistor
oled
storage capacitor
voltage
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French (fr)
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毛鹏
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/745,095 priority Critical patent/US10600366B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display driving technologies, and in particular, to an OLED driving circuit and an AMOLED display panel.
  • Organic Light-Emitting Diode (OLED) display panels are favored by people because of their thinness, energy saving, wide viewing angle, wide color gamut and high contrast.
  • Organic light-emitting diode display panels are classified into passive organic light-emitting diodes.
  • the OLED driving circuit commonly used in the AMOLED is shown in FIG. 1.
  • the OLED driving circuit is used to drive an OLED.
  • the OLED driving circuit includes a switching TFT (TTFT) T2, a driving thin film transistor (Driver TFT) T1, and a
  • the storage capacitor Cst this structure is also called a 2T1C structure.
  • the gate of the switching thin film transistor T2 receives the nth-stage scan signal Scan(n), the drain of the switching thin film transistor T2 receives the data voltage Vdata, and the source of the switching thin film transistor T2 is electrically connected to the driving film
  • the source of the switching thin film transistor T2 and the drain of the switching thin film transistor T2 are turned on or off under the control of the nth scanning signal Scan(n).
  • the data voltage Vdata is transmitted to the driving film.
  • the source of the driving thin film transistor T1 is electrically connected to a power supply voltage VDD
  • the power supply voltage VDD is a high potential voltage
  • the drain of the driving thin film transistor T1 is electrically connected to the positive electrode of the OLED.
  • the negative electrode of the OLED is electrically connected to a low potential voltage VSS.
  • Both ends of the storage capacitor Cst are electrically connected to the gate of the driving thin film transistor T1 and the drain of the driving thin film transistor T1, respectively.
  • the current I OLED flowing through the OLED is:
  • I OLED k(Vgs-Vth) 2 .
  • the I OLED is a current flowing through the OLED, which is also referred to as a driving current of the OLED; k is a current amplification factor of the driving thin film transistor T1, which is determined by characteristics of the driving thin film transistor T1 itself; Vgs is The voltage between the gate and the source of the driving thin film transistor T1; Vth is a threshold voltage of the driving thin film transistor T1. It can be seen that the driving current of the OLED is related to the threshold voltage Vth of the driving thin film transistor T1.
  • the variation of the driving current I OLED of the OLED may cause a change in the luminance of the OLED, thereby affecting the The image quality of the AMOLED display panel.
  • the power supply voltage VDD may cause a voltage drop due to long-distance transmission, thereby causing a variation in the driving current I OLED flowing through the OLED, which is a problem of the IR drop, which also causes the luminance of the OLED to occur. The change, in turn, affects the image quality of the OLED display panel.
  • the technical problem to be solved by the embodiments of the present invention is to provide an OLED driving circuit and an AMOLED display panel.
  • the problem of uneven illumination of the OLED due to the threshold voltage drift of the driving thin film transistor and the voltage drop of the power supply voltage can be improved.
  • an embodiment of the first aspect of the present invention provides an OLED driving circuit including an OLED, a switching thin film transistor, and a driving thin film transistor; a first end of the switching thin film transistor receives a data voltage, and the switching thin film transistor a second end electrically connected to a gate of the driving thin film transistor, a gate of the switching thin film transistor receiving an nth-th scan signal, wherein n is an integer greater than or equal to 2, a first end of the driving thin film transistor Receiving a power supply voltage, a second end of the driving thin film transistor is electrically connected to a positive electrode of the OLED, and a negative electrode of the OLED is loaded with a low level voltage; wherein the OLED driving circuit further comprises a eliminating capacitor and eliminating a thin film transistor, A method for eliminating a change in a driving current of the OLED due to a drift of a threshold voltage of the driving thin film transistor and a voltage drop of a power supply voltage.
  • the elimination capacitor includes a first storage capacitor and a second storage capacitor, the first storage capacitor and the second storage capacitor are connected in series, and the first electrode of the first storage capacitor is electrically connected to drive the thin film crystal a gate of the body tube, a second electrode of the first storage capacitor is electrically connected to the first electrode of the second storage capacitor, and a second electrode of the second storage capacitor receives the power source voltage.
  • the thin film transistor includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor, wherein the first end of the third thin film transistor is electrically connected to the switching film a second end of the transistor, the second end of which is electrically connected to the anode of the OLED, the gate thereof receives the n-1th stage scanning signal, the first end of the fourth eliminating thin film transistor receives the reference voltage, and the second end thereof is electrically connected To the second end of the switching thin film transistor, the gate thereof receives the n-1th-th scan signal, the first end of the fifth thin film transistor receives the power supply voltage, and the second end of the second thin film transistor is electrically connected to the first electrode of the second storage capacitor
  • the gate of the fifth thin film transistor receives an enable signal
  • the first end of the sixth erase thin film transistor is electrically connected to the first electrode of the second storage capacitor
  • the second end thereof is electrically connected to the driving thin film transistor At the first end, the gate thereof receives the reverse signal,
  • one cycle of the OLED driving circuit includes a reset period, a threshold voltage capture period, a writing period, and a lighting period, wherein
  • the fifth thin film transistor is turned on and turned off, and the third thin film transistor, the fourth thin film transistor, and the sixth thin film transistor are turned on, and the driving thin film transistor is guided. Turning off until the voltage between the gate and the first end of the driving thin film transistor is equal to the threshold voltage of the driving thin film transistor;
  • the fourth thin film transistor is turned off, the switching thin film transistor is turned on, and the data voltage is supplied to the gate of the driving thin film transistor and stored in the first storage capacitor;
  • the fifth eliminating thin film transistor and the sixth eliminating thin film transistor are turned on, the driving thin film transistor is turned on, the OLED is illuminated, and the driving current I OLED is calculated as:
  • K is the current amplification factor of the driving thin film transistor
  • Vdata is the data voltage
  • Vref is the reference voltage
  • the switching thin film transistor, the driving thin film transistor, the third erasing thin film transistor, the fourth erasing thin film transistor, the fifth erasing thin film transistor, and the sixth erasing thin film transistor are all N-type thin film transistors.
  • the difference between the power supply voltage and the reference voltage is greater than a threshold voltage of the driving thin film transistor.
  • Vref is a reference voltage
  • Vth is a threshold voltage of a driving thin film transistor
  • Vth is a threshold voltage of a driving thin film transistor
  • Vdata is a data voltage
  • the gate voltage of the driving thin film transistor is abruptly changed due to the coupling of the first storage capacitor:
  • C1 is the capacitance value of the first storage capacitor
  • C2 is the capacitance value of the second storage capacitor
  • Vdata is the data voltage
  • Vref is the reference voltage
  • VDD is the power supply voltage
  • Vth is the threshold voltage of the driving thin film transistor.
  • the first end is a source, and the second end is a drain; or the first end is a drain, and the second end is a source.
  • a second aspect of the present invention provides an AMOLED display panel, where the AMOLED display panel includes the OLED driving circuit described above.
  • the OLED driving circuit further includes a eliminating capacitor and eliminating a thin film transistor, it is for eliminating a variation of a driving current of the OLED due to a drift of a threshold voltage of the driving thin film transistor and a voltage drop of a power supply voltage. Due to the setting of the cancellation circuit, the threshold voltage of the driving thin film transistor is not calculated in the calculation formula of the driving current, so that the influence of the drift of the threshold voltage of the driving thin film transistor on the driving current can be eliminated, so that the driving current is relatively stable, and the luminance of the OLED is compared. Uniform, AMOLED display panel has better picture quality.
  • FIG. 1 is a schematic diagram of a prior art OLED driving circuit
  • FIG. 2 is a schematic diagram of an OLED driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a timing diagram of an OLED drive circuit in accordance with an embodiment of the present invention.
  • An embodiment of the present invention provides an OLED driving circuit.
  • an OLED, a driving thin film transistor T1, and a switching thin film transistor T2 are included.
  • the OLED is used for illuminating; the first end of the switching thin film transistor T2 receives the data voltage Vdata, and the second end of the switching thin film transistor T2 is electrically connected to the gate of the driving thin film transistor T1, and the switching thin film transistor T2
  • the gate receives the nth-th scan signal Scan(n), where n is an integer greater than or equal to 2, for example, 2, 3, 4, 5, 6, 7, 8, 9, 10, etc.; driving the thin film transistor T1 One end receives the power supply voltage VDD.
  • the power supply voltage VDD is a high level voltage
  • the second end of the driving thin film transistor T1 is electrically connected to the positive electrode of the OLED
  • the negative electrode of the OLED is loaded with the low level voltage VSS.
  • the switch film crystal The body tube T2 and the driving thin film transistor T1 have a first end as a source and a second end as a drain.
  • the first end of the switching thin film transistor and the driving thin film transistor is a drain
  • the second end is a source.
  • the OLED driving circuit further includes a eliminating capacitor and a thin film transistor for eliminating the OLED caused by the drift of the threshold voltage of the driving thin film transistor T1 and the voltage drop of the power supply voltage VDD.
  • the drive current changes.
  • the elimination capacitor includes a first storage capacitor C1 and a second storage capacitor C2, the first storage capacitor C1 and the second storage capacitor C2 are connected in series, and the first electrode of the first storage capacitor C1 is electrically
  • the first electrode of the first storage capacitor C1 is electrically connected to the second end of the switching thin film transistor T2, and the second electrode of the first storage capacitor C1 and the second storage capacitor C2 are connected to the second electrode of the first storage capacitor C1.
  • the first electrode is electrically connected, and the second electrode of the second storage capacitor C2 receives the power supply voltage VDD.
  • the thin film transistor includes a third erasing thin film transistor T3, a fourth erasing thin film transistor T4, a fifth erasing thin film transistor T5, and a sixth erasing thin film transistor T6.
  • the first end of the third thin film transistor T3 is electrically connected to the second end of the switching thin film transistor T2, that is, the third thin film transistor T3 is also electrically connected to the first electrode of the first storage capacitor C1, and the driving thin film transistor T1.
  • the gate of the third eliminating thin film transistor T3 is electrically connected to the anode of the OLED, and the gate of the third eliminating thin film transistor T3 receives the n-1th scanning signal Scan(n-1).
  • the first end of the fourth thin film transistor T4 receives the reference voltage Vref, the reference voltage Vref is a low level, and the second end of the fourth thin film transistor T4 is also electrically connected to the second end of the switching thin film transistor T2.
  • the gate of the fourth erasing thin film transistor T4 receives the n-1th-th scan signal Scan(n-1).
  • the first end of the fifth thin film transistor receives the power supply voltage VDD
  • the second end of the fifth thin film transistor is electrically connected to the first electrode of the second storage capacitor C2, and the gate of the fifth thin film transistor receives the enable signal EM.
  • the first end of the sixth thin film transistor is electrically connected to the first electrode of the second storage capacitor C2, that is, the second end of the fifth thin film transistor and the first end of the sixth thin film transistor are electrically connected to the second storage capacitor C2
  • the first electrode, the second end of the sixth thin film transistor is electrically connected to the first end of the driving thin film transistor T1, and the gate thereof receives the reverse signal SC, wherein the reverse signal SC and the nth scanning signal Scan are simultaneously
  • the voltage of (n) is reversed. For example, at a time, the nth scanning signal Scan(n) is at a high level, and the reverse signal SC is at a low level.
  • the first end of the driving thin film transistor T1 receives the power supply voltage VDD via the sixth canceling thin film transistor T6 and the fifth eliminating thin film transistor T5.
  • the OLED illumination of the OLED driving circuit is periodic, and one cycle of the OLED driving circuit includes a reset period R, a threshold voltage capture period R, a writing period W, and a lighting period E, see FIG. 3.
  • the driving of the OLED driving circuit will be described below with reference to FIGS. 2 and 3.
  • the switching thin film transistor T2, the driving thin film transistor T1, the third erasing thin film transistor T3, the fourth erasing thin film transistor T4, the fifth erasing thin film transistor T5, and the sixth erasing thin film transistor T6 are all P-type thin film transistors.
  • the fifth thin film transistor before the reset period R and the threshold voltage capture period R, the fifth thin film transistor is turned on, and the first storage capacitor C1 and the second storage capacitor C2 are connected to store the power supply voltage VDD, that is, the map.
  • the voltage at node B in 2 is the power supply voltage VDD.
  • the fifth thin film transistor T5 is turned off from on, and the n-1th scan signal Scan(n-1) and the reverse signal SC are low,
  • the third thin film transistor T3, the fourth thin film transistor T4, and the sixth thin film transistor T6 are turned on, so that the voltage of the gate of the driving thin film transistor T1 is set to the reference voltage Vref and stored in the first of the first storage capacitor C1.
  • the voltage of the first end of the driving thin film transistor T1 is the same as the voltage between the first storage capacitor C1 and the second storage capacitor C2, that is, the driving thin film transistor The voltage at one end is equal to the voltage at node B, both of which are the supply voltage VDD.
  • the driving thin film transistor T1 is a P-type thin film transistor, in order to grasp the threshold voltage of the driving thin film transistor T1, the voltage between the gate and the first end of the driving thin film transistor T1 is smaller than that of the driving thin film transistor.
  • the threshold voltage Vth drives the thin film transistor T1 to be turned on, that is,
  • the threshold voltage Vth of the driving thin film transistor T1 is started to be grasped, and the driving thin film transistor T1 is turned on until the voltage between the gate and the first end of the driving thin film transistor is driven.
  • Vg-Vs Vth
  • Vs Vg-Vth
  • Vs Vref - Vth.
  • VB Vref-Vth, that is, the voltage between the first storage capacitor C1 and the second storage capacitor C2 is Vref-Vth.
  • the n-th scanning signal Scan(n) is at a low level, at which time the switching thin film transistor T2 is turned on, the other thin film transistors are turned off, and the gate and the driving of the thin film transistor T1 are driven.
  • the first electrode of a storage capacitor C1 receives the data voltage Vdata, and the voltage on the gate of the driving thin film transistor T1 and the first electrode of the first storage capacitor C1 is suddenly changed to the data voltage Vdata, according to the coupling effect of the capacitor and the series capacitor.
  • the voltage division principle, the voltage between the first storage capacitor C1 and the second storage capacitor C2 becomes:
  • C1 is the capacitance value of the first storage capacitor
  • C2 is the capacitance value of the second storage capacitor
  • the enable signal EM and the reverse signal SC are at a low level, so that the fifth erase thin film transistor T5 and the sixth erase thin film transistor T6 are turned on, because the fifth thin film transistor is turned on. Therefore, the voltage of the first terminal of the driving thin film transistor T1 is suddenly changed to the power supply voltage VDD, that is, the voltage at the node B in FIG. 2 is suddenly changed to the power supply voltage VDD, that is, between the first storage capacitor C1 and the second storage capacitor C2. The voltage is abruptly changed to the power supply voltage VDD. According to the coupling effect of the capacitor, the voltage at the first electrode of the first storage capacitor C1 is also abruptly changed, that is, the voltage at the node A in FIG. 2 is abruptly changed to:
  • the driving thin film transistor T1 is a P-type thin film transistor, thus, when When the driving thin film transistor T1 is turned on, the OLED emits light, and the driving current I OLED is calculated as:
  • K is the current amplification factor of the driving thin film transistor T1
  • Vdata is the data voltage
  • Vref is the reference voltage
  • the driving current I OLED is compared. Stable, so that the OLED brightness is relatively uniform, and the image quality of the AMOLED display panel is better.
  • the power supply voltage VDD is lowered, and the problem of IR drop does not occur, so that the driving current I OLED is more stable. Thereby the OLED emits light more evenly.
  • An embodiment of the present invention further provides an AMOLED display panel, including the OLED driving circuit described above.
  • the present invention has the following advantages:
  • the OLED driving circuit further includes a eliminating capacitor and eliminating a thin film transistor, it is for eliminating a variation of a driving current of the OLED due to a drift of a threshold voltage of the driving thin film transistor and a voltage drop of a power supply voltage. Due to the setting of the cancellation circuit, the threshold voltage of the driving thin film transistor is not calculated in the calculation formula of the driving current, so that the influence of the drift of the threshold voltage of the driving thin film transistor on the driving current can be eliminated, so that the driving current is relatively stable, and the luminance of the OLED is compared. Uniform, AMOLED display panel has better picture quality.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

本发明实施例公开了一种OLED驱动电路，包括OLED、驱动薄膜晶体管和开关薄膜晶体管；所述开关薄膜晶体管的第一端接收数据电压，第二端电连接到所述驱动薄膜晶体管的栅极，栅极接收第n级扫描信号，其中n为大于或等于2的整数，所述驱动薄膜晶体管的第一端接收电源电压，第二端电连接至所述OLED的正极，所述OLED的负极加载低电平电压；其中，所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管的阈值电压的漂移以及电源电压的压降而导致的所述OLED的驱动电流的变化。本发明实施例还公开了一种AMOLED显示面板。采用本发明，具有改善由于驱动薄膜晶体管阈值电压漂移以及电源电压的压降而导致OLED发光不均匀的问题。

Description

OLED驱动电路及AMOLED显示面板
本发明要求2017年11月15日递交的发明名称为“OLED驱动电路及AMOLED显示面板”的申请号201711130082.1的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示驱动技术领域，特别是涉及一种OLED驱动电路及AMOLED显示面板。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板因具有因为具备轻薄、节能、宽视角、色域广、对比度高等特性而备受人们的青睐，有机发光二极管显示面板分为被动式有机发光二极管显示面板(PMOLED)和主动式有机发光二极管显示面板(AMOLED)。其中AMOLED常用的OLED驱动电路如图1所示，所述OLED驱动电路用于驱动OLED，所述OLED驱动电路包括一个开关薄膜晶体管(Switch TFT)T2、一个驱动薄膜晶体管(Driver TFT)T1以及一个存储电容Cst，这种结构也被称为2T1C结构。所述开关薄膜晶体管T2的栅极接收第n级扫描信号Scan(n)，所述开关薄膜晶体管T2的漏极接收数据电压Vdata，所述开关薄膜晶体管T2的源极电连接至所述驱动薄膜晶体管T1的栅极。所述开关薄膜晶体管T2的源极和所述开关薄膜晶体管T2漏极在所述第n级扫描信号Scan(n)的控制下导通或者关闭。当所述开关薄膜晶体管T2的源极和所述开关薄膜晶体管T2漏极在所述第n级扫描信号Scan(n)的控制下导通时，所述数据电压Vdata被传输至所述驱动薄膜晶体管T1的栅极。所述驱动薄膜晶体管T1的源极电连接至一电源电压VDD，所述电源电压VDD为高电位电压，所述驱动薄膜晶体管T1的漏极电连接至OLED的正极。所述OLED的负极电连接至一低电位电压VSS。所述存储电容Cst的两端分别电连接至所述驱动薄膜晶体管T1的栅极及所述驱动薄膜晶体管T1的漏极。流经所述OLED的电流IOLED为：
IOLED＝k(Vgs-Vth)2。
其中，IOLED为流经所述OLED的电流，也称为所述OLED的驱动电流；k为所述驱动薄膜晶体管T1的电流放大系数，由所述驱动薄膜晶体管T1自身的特性决定；Vgs为所述驱动薄膜晶体管T1的栅极与源极之间的电压；Vth为所述驱动薄膜晶体管T1的阈值电压。由此可见，所述OLED的驱动电流与所述驱动薄膜晶体管T1的阈值电压Vth有关。由于所述驱动薄膜晶体管T1的阈值电压Vth容易漂移，从而导致所述OLED的驱动电流IOLED变动，所述OLED的驱动电流IOLED变动会导致所述OLED的发光亮度发生变化，进而影响所述AMOLED显示面板的画质。而且，电源电压VDD由于长距离的传输，会造成压降，从而导致流经所述OLED的驱动电流IOLED变动，这就是常说的IR drop的问题，也会导致所述OLED的发光亮度发生变化，进而影响所述OLED显示面板的画质。
发明内容
本发明实施例所要解决的技术问题在于，提供一种OLED驱动电路及AMOLED显示面板。可改善由于驱动薄膜晶体管阈值电压漂移以及电源电压的压降而导致OLED发光不均匀的问题。
为了解决上述技术问题，本发明第一方面实施例提供了一种OLED驱动电路，包括OLED、开关薄膜晶体管和驱动薄膜晶体管；所述开关薄膜晶体管的第一端接收数据电压，所述开关薄膜晶体管的第二端电连接到所述驱动薄膜晶体管的栅极，所述开关薄膜晶体管的栅极接收第n级扫描信号，其中n为大于或等于2的整数，所述驱动薄膜晶体管的第一端接收电源电压，所述驱动薄膜晶体管的第二端电连接至所述OLED的正极，所述OLED的负极加载低电平电压；其中，所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管的阈值电压的漂移以及电源电压的压降而导致的所述OLED的驱动电流的变化。
其中，所述消除电容包括第一存储电容和第二存储电容，所述第一存储电容和所述第二存储电容串联，所述第一存储电容的第一电极电连接驱动薄膜晶 体管的栅极，所述第一存储电容的第二电极电连接第二存储电容的第一电极，所述第二存储电容的第二电极接收电源电压。
其中，所述消除薄膜晶体管包括第三消除薄膜晶体管、第四消除薄膜晶体管、第五消除薄膜晶体管和第六消除薄膜晶体管，其中，所述第三消除薄膜晶体管的第一端电连接到开关薄膜晶体管的第二端，其第二端电连接到OLED的正极，其栅极接收第n-1级扫描信号，所述第四消除薄膜晶体管的第一端接收参考电压，其第二端电连接到开关薄膜晶体管的第二端，其栅极接收第n-1级扫描信号，所述第五消除薄膜晶体管的第一端接收电源电压，其第二端电连接第二存储电容的第一电极，所述第五消除薄膜晶体管的栅极接收使能信号，所述第六消除薄膜晶体管的第一端电连接到第二存储电容的第一电极，其第二端电连接到驱动薄膜晶体管的第一端，其栅极接收反向信号，其中，同时刻所述反向信号与第n级扫描信号的电压相反。
其中，所述OLED驱动电路的一个周期包括复位时间段、阈值电压抓取时间段、写入时间段、发光时间段，其中，
在复位时间段和阈值电压抓取时间段，第五薄膜晶体管由导通变为关闭，第三消除薄膜晶体管、第四消除薄膜晶体管、第六消除薄膜晶体管导通，所述驱动薄膜晶体管由导通直到驱动薄膜晶体管的栅极和第一端之间的电压与驱动薄膜晶体管的阈值电压相等而关闭；
在写入时间段，第四消除薄膜晶体管关闭，开关薄膜晶体管导通，数据电压输送给驱动薄膜晶体管的栅极并存储在第一存储电容中；
在发光时间段，第五消除薄膜晶体管、第六消除薄膜晶体管导通，驱动薄膜晶体管导通，所述OLED发光，且所述驱动电流IOLED的计算公式为：
Figure PCTCN2017114035-appb-000001
其中，K为驱动薄膜晶体管的电流放大系数，Vdata为数据电压，Vref为参考电压。
其中，所述开关薄膜晶体管、驱动薄膜晶体管、第三消除薄膜晶体管、第四消除薄膜晶体管、第五消除薄膜晶体管、第六消除薄膜晶体管均为N型薄膜晶体管。
其中，所述电源电压与参考电压的差大于驱动薄膜晶体管的阈值电压。
其中，在数据写入时间段，第一存储电容和第二存储电容之间的电压变为：
Figure PCTCN2017114035-appb-000002
其中，Vref为参考电压，Vth为驱动薄膜晶体管的阈值电压，C1位第一存储电容的电容值，C2位第二存储电容的电容值，Vdata为数据电压。
其中，在发光时间段，驱动薄膜晶体管的栅极电压由于第一存储电容耦合作用突变为：
Figure PCTCN2017114035-appb-000003
其中，C1为第一存储电容的电容值，C2为第二存储电容的电容值，Vdata为数据电压，Vref为参考电压，VDD为电源电压，Vth为驱动薄膜晶体管的阈值电压。
其中，所述第一端为源极，所述第二端为漏极；或者，所述第一端为漏极，所述第二端为源极。
本发明第二方面实施例提供了一种AMOLED显示面板，所述AMOLED显示面板包括上述的OLED驱动电路。
实施本发明实施例，具有如下有益效果：
由于所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管的阈值电压的漂移以及电源电压的压降而导致的所述OLED的驱动电流的变化。由于消除电路的设置，所述驱动电流的计算公式中没有驱动薄膜晶体管的阈值电压，从而可以消除驱动薄膜晶体管的阈值电压的漂移对驱动电流的影响，从而驱动电流比较稳定，OLED的发光亮度比较均匀，AMOLED显示面板的画质较好。而且，驱动电流的计算公式中也没有电源电压，从而，即使电源电压经过长距离传输而导致电源电压降低，也不会出现IR drop的问题，从而驱动电流更加稳定，从而OLED发光更加均匀。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术OLED驱动电路的示意图；
图2是本发明一实施例OLED驱动电路的示意图；
图3是本发明一实施例OLED驱动电路的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
本发明实施例提供一种OLED驱动电路，请参见图2，包括OLED、驱动薄膜晶体管T1和开关薄膜晶体管T2。在本实施例中，所述OLED用于发光；开关薄膜晶体管T2的第一端接收数据电压Vdata，开关薄膜晶体管T2的第二端电连接到驱动薄膜晶体管T1的栅极，开关薄膜晶体管T2的栅极接收第n级扫描信号Scan(n)，其中n为大于或等于2的整数，例如为2、3、4、5、6、7、8、9、10等；驱动薄膜晶体管T1的第一端接收电源电压VDD，在本实施例中，电源电压VDD为高电平电压，驱动薄膜晶体管T1的第二端电连接至OLED的正极，OLED的负极加载低电平电压VSS。在本实施例中，开关薄膜晶 体管T2、驱动薄膜晶体管T1的第一端为源极，第二端为漏极。在本发明的其他实施例中，开关薄膜晶体管、驱动薄膜晶体管的第一端为漏极，第二端为源极。
为了消除驱动薄膜晶体管T1的阈值电压Vth的漂移以及电源电压VDD长距离传输造成的压降对OLED的驱动电流的影响，造成OLED的发光亮度发生变化，造成亮度不均。在本实施例中，所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管T1的阈值电压的漂移以及电源电压VDD的压降而带来的所述OLED的驱动电流的变化。
具体说来，所述消除电容包括第一存储电容C1和第二存储电容C2，所述第一存储电容C1和所述第二存储电容C2串联，所述第一存储电容C1的第一电极电连接驱动薄膜晶体管T1的栅极，也即第一存储电容C1的第一电极还电连接开关薄膜晶体管T2的第二端，所述第一存储电容C1的第二电极与第二存储电容C2的第一电极电连接，所述第二存储电容C2的第二电极接收电源电压VDD。
在本实施例中，所述消除薄膜晶体管包括第三消除薄膜晶体管T3、第四消除薄膜晶体管T4、第五消除薄膜晶体管T5和第六消除薄膜晶体管T6。其中，第三消除薄膜晶体管T3的第一端电连接到开关薄膜晶体管T2的第二端，也即第三消除薄膜晶体管T3还电连接到第一存储电容C1的第一电极、驱动薄膜晶体管T1的栅极，第三消除薄膜晶体管T3的第二端电连接到OLED的正极，第三消除薄膜晶体管T3的栅极接收第n-1级扫描信号Scan(n-1)。第四消除薄膜晶体管T4的第一端接收参考电压Vref，所述参考电压Vref为低电平，所述第四消除薄膜晶体管T4的第二端也电连接到开关薄膜晶体管T2的第二端，所述第四消除薄膜晶体管T4的栅极接收第n-1级扫描信号Scan(n-1)。第五薄膜晶体管的第一端接收电源电压VDD，第五薄膜晶体管的第二端电连接第二存储电容C2的第一电极，第五薄膜晶体管的栅极接收使能信号EM。所述第六薄膜晶体管的第一端电连接到第二存储电容C2的第一电极，也即第五薄膜晶体管的第二端、第六薄膜晶体管的第一端均电连接第二存储电容C2的第一电极，第六薄膜晶体管的第二端电连接到驱动薄膜晶体管T1的第一端，其栅极接收反向信号S-C，其中，同时刻反向信号S-C与第n级扫描信号Scan (n)的电压相反，例如在一个时刻，第n级扫描信号Scan(n)为高电平，此时反向信号S-C为低电平，同样，在一个时刻，第n级扫描信号Scan(n)为低电平，此时反向信号S-C为高电平。从而，驱动薄膜晶体管T1的第一端经由第六消除薄膜晶体管T6、第五消除薄膜晶体管T5而接收电源电压VDD。
在本实施例中，OLED驱动电路的OLED发光呈周期性，OLED驱动电路的一个周期包括复位时间段R、阈值电压抓取时间段R、写入时间段W和发光时间段E，请参见图3，以下结合图2和图3描述OLED驱动电路的驱动。
在本实施例中，开关薄膜晶体管T2、驱动薄膜晶体管T1、第三消除薄膜晶体管T3、第四消除薄膜晶体管T4、第五消除薄膜晶体管T5、第六消除薄膜晶体管T6均为P型薄膜晶体管。
在本实施例中，在复位时间段R和阈值电压抓取时间段R之前，第五薄膜晶体管导通，第一存储电容C1和第二存储电容C2连接处存储了电源电压VDD，也即图2中节点B处的电压为电源电压VDD。在复位时间段R和阈值电压抓取时间段R，第五薄膜晶体管T5由导通变为关闭，第n-1级扫描信号Scan(n-1)和反向信号S-C为低电平，第三消除薄膜晶体管T3、第四消除薄膜晶体管T4和第六消除薄膜晶体管T6导通，从而，驱动薄膜晶体管T1的栅极的电压被置为参考电压Vref并存储在第一存储电容C1的第一电极中，而且，由于第六消除薄膜晶体管T6导通，从而驱动薄膜晶体管T1的第一端的电压与第一存储电容C1和第二存储电容C2之间的电压相同，也即驱动薄膜晶体管第一端处的电压等于节点B处的电压，均为电源电压VDD。在本实施例中，由于驱动薄膜晶体管T1为P型薄膜晶体管，为了抓取驱动薄膜晶体管T1的阈值电压，从而驱动薄膜晶体管T1的栅极与第一端之间的电压要小于驱动薄膜晶体管的阈值电压Vth，此时驱动薄膜晶体管T1导通，也即:
Vs-Vg＞丨Vth丨；从而，
VDD-Vref＞丨Vth丨；
由于驱动薄膜晶体管T1导通，从而B处的电压持续漏电，开始抓取驱动薄膜晶体管T1的阈值电压Vth，驱动薄膜晶体管T1导通直到驱动薄膜晶体管的栅极和第一端之间的电压与驱动薄膜晶体管T1的阈值电压相同，由于驱动薄膜晶体管T1为P型薄膜晶体管，从而Vgs＝Vth，从而抓取到驱动薄膜晶体 管T1的阈值电压Vth，此时驱动薄膜晶体管T1关闭，从而：
Vg-Vs＝Vth；
Vs＝Vg-Vth；
Vs＝Vref-Vth。
也即节点B处的电压经过漏电，最后为：VB＝Vref-Vth，也即第一存储电容C1和第二存储电容C2之间的电压为Vref-Vth。
在本实施例中，在写入时间段W，第n级扫描信号Scan(n)为低电平，此时开关薄膜晶体管T2导通，其他薄膜晶体管关闭，驱动薄膜晶体管T1的栅极和第一存储电容C1的第一电极接收到数据电压Vdata，此时驱动薄膜晶体管T1的栅极和第一存储电容C1的第一电极上的电压突变为数据电压Vdata，根据电容的耦合作用以及串联电容的分压原理，第一存储电容C1和第二存储电容C2之间的电压变为：
Figure PCTCN2017114035-appb-000004
其中，在上式中C1为第一存储电容的电容值，C2为第二存储电容的电容值。
也即节点B处的电压由Vref-Vth突变为
Figure PCTCN2017114035-appb-000005
在本实施例中，在发光时间段，使能信号EM和反向信号S-C为低电平，从而，第五消除薄膜晶体管T5、第六消除薄膜晶体管T6导通，由于第五薄膜晶体管导通，从而驱动薄膜晶体管T1的第一端的电压突变为电源电压VDD，也即图2中节点B处的电压突变为电源电压VDD，也即第一存储电容C1和第二存储电容C2之间的电压突变为电源电压VDD，根据电容的耦合作用，第一存储电容C1的第一电极处的电压也进行突变，也即图2中节点A处的电压突变为：
Figure PCTCN2017114035-appb-000006
从而，
Figure PCTCN2017114035-appb-000007
从而，Vgs的电压为
Figure PCTCN2017114035-appb-000008
由于驱动薄膜晶体管T1为P型薄膜晶体管，从而，当
Figure PCTCN2017114035-appb-000009
时，驱动薄膜晶体管T1导通，此时OLED发光，且所述驱动电流IOLED的计算公式为：
Figure PCTCN2017114035-appb-000010
其中，K为驱动薄膜晶体管T1的电流放大系数，Vdata为数据电压，Vref为参考电压。
从而，通过上面计算驱动电流IOLED的公式可知，由于公式中没有驱动薄膜晶体管T1的阈值电压Vth，从而可以消除驱动薄膜晶体管T1的阈值电压的漂移对驱动电流的影响，从而驱动电流IOLED比较稳定，从而OLED的发光亮度比较均匀，AMOLED显示面板的画质较好。而且，由于驱动电流IOLED的公式中也没有电源电压VDD，从而，即使电源电压VDD经过长距离传输而导致电源电压VDD降低，也不会出现IR drop的问题，从而驱动电流IOLED更加稳定，从而OLED发光更加均匀。
本发明实施例还提供一种AMOLED显示面板，包括上述的OLED驱动电路。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
通过上述实施例的描述，本发明具有以下优点：
由于所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管的阈值电压的漂移以及电源电压的压降而导致的所述OLED的驱动电流的变化。由于消除电路的设置，所述驱动电流的计算公式中没有驱动薄膜晶体管的阈值电压，从而可以消除驱动薄膜晶体管的阈值电压的漂移对驱动电流的影响，从而驱动电流比较稳定，OLED的发光亮度比较均匀，AMOLED显示面板的画质较好。而且，驱动电流的计算公式中也没有电源电压，从而，即使电源电压经过长距离传输而导致电源电压降低，也不会出现IR drop的问题，从而驱动电流更加稳定，从而OLED发光更加均匀。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (18)

  1. 一种OLED驱动电路，其中，包括OLED、开关薄膜晶体管和驱动薄膜晶体管；所述开关薄膜晶体管的第一端接收数据电压，所述开关薄膜晶体管的第二端电连接到所述驱动薄膜晶体管的栅极，所述开关薄膜晶体管的栅极接收第n级扫描信号，其中n为大于或等于2的整数，所述驱动薄膜晶体管的第一端接收电源电压，所述驱动薄膜晶体管的第二端电连接至所述OLED的正极，所述OLED的负极加载低电平电压；其中，所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管的阈值电压的漂移以及电源电压的压降而导致的所述OLED的驱动电流的变化。
  2. 如权利要求1所述的OLED驱动电路，其中，所述消除电容包括第一存储电容和第二存储电容，所述第一存储电容和所述第二存储电容串联，所述第一存储电容的第一电极电连接驱动薄膜晶体管的栅极，所述第一存储电容的第二电极电连接第二存储电容的第一电极，所述第二存储电容的第二电极接收电源电压。
  3. 如权利要求2所述的OLED驱动电路，其中，所述消除薄膜晶体管包括第三消除薄膜晶体管、第四消除薄膜晶体管、第五消除薄膜晶体管和第六消除薄膜晶体管，其中，所述第三消除薄膜晶体管的第一端电连接到开关薄膜晶体管的第二端，其第二端电连接到OLED的正极，其栅极接收第n-1级扫描信号，所述第四消除薄膜晶体管的第一端接收参考电压，其第二端电连接到开关薄膜晶体管的第二端，其栅极接收第n-1级扫描信号，所述第五消除薄膜晶体管的第一端接收电源电压，其第二端电连接第二存储电容的第一电极，所述第五消除薄膜晶体管的栅极接收使能信号，所述第六消除薄膜晶体管的第一端电连接到第二存储电容的第一电极，其第二端电连接到驱动薄膜晶体管的第一端，其栅极接收反向信号，其中，同时刻所述反向信号与第n级扫描信号的电压相反。
  4. 如权利要求3所述的OLED驱动电路，其中，所述OLED驱动电路的一个周期包括复位时间段、阈值电压抓取时间段、写入时间段、发光时间段，其中，
    在复位时间段和阈值电压抓取时间段，第五薄膜晶体管由导通变为关闭，第三消除薄膜晶体管、第四消除薄膜晶体管、第六消除薄膜晶体管导通，所述驱动薄膜晶体管由导通直到驱动薄膜晶体管的栅极和第一端之间的电压与驱动薄膜晶体管的阈值电压相等而关闭；
    在写入时间段，第四消除薄膜晶体管关闭，开关薄膜晶体管导通，数据电压输送给驱动薄膜晶体管的栅极并存储在第一存储电容中；
    在发光时间段，第五消除薄膜晶体管、第六消除薄膜晶体管导通，驱动薄膜晶体管导通，所述OLED发光，且所述驱动电流IOLED的计算公式为：
    Figure PCTCN2017114035-appb-100001
    其中，K为驱动薄膜晶体管的电流放大系数，Vdata为数据电压，Vref为参考电压。
  5. 如权利要求3所述的OLED驱动电路，其中，所述开关薄膜晶体管、驱动薄膜晶体管、第三消除薄膜晶体管、第四消除薄膜晶体管、第五消除薄膜晶体管、第六消除薄膜晶体管均为N型薄膜晶体管。
  6. 如权利要求4所述的OLED驱动电路，其中，所述电源电压与参考电压的差大于驱动薄膜晶体管的阈值电压。
  7. 如权利要求4所述的OLED驱动电路，其中，在数据写入时间段，第一存储电容和第二存储电容之间的电压变为：
    Figure PCTCN2017114035-appb-100002
    其中，Vref为参考电压，Vth为驱动薄膜晶体管的阈值电压，C1位第一存储电容的电容值，C2位第二存储电容的电容值，Vdata为数据电压。
  8. 如权利要求4所述的OLED驱动电路，其中，在发光时间段，驱动薄膜晶体管的栅极电压由于第一存储电容耦合作用突变为：
    Figure PCTCN2017114035-appb-100003
    其中，C1为第一存储电容的电容值，C2为第二存储电容的电容值，Vdata为数据电压，Vref为参考电压，VDD为电源电压，Vth为驱动薄膜晶体管的阈值电压。
  9. 如权利要求1所述的OLED驱动电路，其中，所述第一端为源极，所述第二端为漏极；或者，所述第一端为漏极，所述第二端为源极。
  10. 一种AMOLED显示面板，其中，包括OLED驱动电路，所述OLED驱动电路包括OLED、开关薄膜晶体管和驱动薄膜晶体管；所述开关薄膜晶体管的第一端接收数据电压，所述开关薄膜晶体管的第二端电连接到所述驱动薄膜晶体管的栅极，所述开关薄膜晶体管的栅极接收第n级扫描信号，其中n为大于或等于2的整数，所述驱动薄膜晶体管的第一端接收电源电压，所述驱动薄膜晶体管的第二端电连接至所述OLED的正极，所述OLED的负极加载低电平电压；其中，所述OLED驱动电路还包括消除电容和消除薄膜晶体管，其用于消除由于所述驱动薄膜晶体管的阈值电压的漂移以及电源电压的压降而导致的所述OLED的驱动电流的变化。
  11. 如权利要求10所述的AMOLED显示面板，其中，所述消除电容包括第一存储电容和第二存储电容，所述第一存储电容和所述第二存储电容串联，所述第一存储电容的第一电极电连接驱动薄膜晶体管的栅极，所述第一存储电容的第二电极电连接第二存储电容的第一电极，所述第二存储电容的第二电极接收电源电压。
  12. 如权利要求11所述的AMOLED显示面板，其中，所述消除薄膜晶体管包括第三消除薄膜晶体管、第四消除薄膜晶体管、第五消除薄膜晶体管和第六消除薄膜晶体管，其中，所述第三消除薄膜晶体管的第一端电连接到开关薄膜晶体管的第二端，其第二端电连接到OLED的正极，其栅极接收第n-1级扫描信号，所述第四消除薄膜晶体管的第一端接收参考电压，其第二端电连接到开关薄膜晶体管的第二端，其栅极接收第n-1级扫描信号，所述第五消除薄膜晶体管的第一端接收电源电压，其第二端电连接第二存储电容的第一电极，所述第五消除薄膜晶体管的栅极接收使能信号，所述第六消除薄膜晶体管的第一端电连接到第二存储电容的第一电极，其第二端电连接到驱动薄膜晶体管的第一端，其栅极接收反向信号，其中，同时刻所述反向信号与第n级扫描信号的电压相反。
  13. 如权利要求12所述的AMOLED显示面板，其中，所述OLED驱动电路的一个周期包括复位时间段、阈值电压抓取时间段、写入时间段、发光时间段，其中，
    在复位时间段和阈值电压抓取时间段，第五薄膜晶体管由导通变为关闭，第三消除薄膜晶体管、第四消除薄膜晶体管、第六消除薄膜晶体管导通，所述驱动薄膜晶体管由导通直到驱动薄膜晶体管的栅极和第一端之间的电压与驱动薄膜晶体管的阈值电压相等而关闭；
    在写入时间段，第四消除薄膜晶体管关闭，开关薄膜晶体管导通，数据电压输送给驱动薄膜晶体管的栅极并存储在第一存储电容中；
    在发光时间段，第五消除薄膜晶体管、第六消除薄膜晶体管导通，驱动薄膜晶体管导通，所述OLED发光，且所述驱动电流IOLED的计算公式为：
    Figure PCTCN2017114035-appb-100004
    其中，K为驱动薄膜晶体管的电流放大系数，Vdata为数据电压，Vref为参考电压。
  14. 如权利要求12所述的AMOLED显示面板，其中，所述开关薄膜晶 体管、驱动薄膜晶体管、第三消除薄膜晶体管、第四消除薄膜晶体管、第五消除薄膜晶体管、第六消除薄膜晶体管均为N型薄膜晶体管。
  15. 如权利要求13所述的AMOLED显示面板，其中，所述电源电压与参考电压的差大于驱动薄膜晶体管的阈值电压。
  16. 如权利要求13所述的AMOLED显示面板，其中，在数据写入时间段，第一存储电容和第二存储电容之间的电压变为：
    Figure PCTCN2017114035-appb-100005
    其中，Vref为参考电压，Vth为驱动薄膜晶体管的阈值电压，C1位第一存储电容的电容值，C2位第二存储电容的电容值，Vdata为数据电压。
  17. 如权利要求13所述的AMOLED显示面板，其中，在发光时间段，驱动薄膜晶体管的栅极电压由于第一存储电容耦合作用突变为：
    Figure PCTCN2017114035-appb-100006
    其中，C1为第一存储电容的电容值，C2为第二存储电容的电容值，Vdata为数据电压，Vref为参考电压，VDD为电源电压，Vth为驱动薄膜晶体管的阈值电压。
  18. 如权利要求10所述的AMOLED显示面板，其中，所述第一端为源极，所述第二端为漏极；或者，所述第一端为漏极，所述第二端为源极。
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