WO2019090893A1 - Hva焊垫共用结构 - Google Patents

Hva焊垫共用结构 Download PDF

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Publication number
WO2019090893A1
WO2019090893A1 PCT/CN2017/116276 CN2017116276W WO2019090893A1 WO 2019090893 A1 WO2019090893 A1 WO 2019090893A1 CN 2017116276 W CN2017116276 W CN 2017116276W WO 2019090893 A1 WO2019090893 A1 WO 2019090893A1
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Prior art keywords
clock
hva
pad
pads
potential
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PCT/CN2017/116276
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English (en)
French (fr)
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王添鸿
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/744,741 priority Critical patent/US10330996B2/en
Publication of WO2019090893A1 publication Critical patent/WO2019090893A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a HVA pad sharing structure.
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • notebooks because of their high image quality, power saving, thin body and wide application range.
  • each sub-pixel has a thin film transistor (TFT) whose gate is connected to a horizontal scanning line, a source is connected to a vertical data line, and a drain is connected to a drain.
  • TFT thin film transistor
  • Applying a sufficient voltage on the horizontal scanning line causes all the TFTs on the horizontal scanning line to be turned on.
  • the pixel electrodes on the horizontal scanning line are connected to the data lines in the vertical direction, thereby connecting the data lines.
  • the display signal voltage is written into the pixel, and the transmittance of different liquid crystals is controlled to achieve the effect of controlling the color.
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external chip (IC) of the panel, and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • IC external chip
  • Gate Driver On Array (GOA) technology which uses the existing thin film transistor liquid crystal display array (Array) process to fabricate the gate scan drive signal circuit on the Array substrate to realize the Gate on the Array substrate. The way the line scan is driven.
  • TFT-LCD display panels on the market can be classified into three types, namely, a twisted nematic (TN) or a super twisted nematic (STN) type, a planar conversion (IPS) type, and a vertical alignment (VA) type.
  • the VA type liquid crystal display has a very high contrast ratio with respect to other types of liquid crystal displays, and has a very wide application in a large-sized display such as a television.
  • the High Vertical Alignment (HVA) mode is an important branch of the VA mode.
  • the vertical electric field formed by the pixel electrode on the array substrate side and the common electrode on the color filter substrate side controls the rotation of the liquid crystal molecules of the liquid crystal layer.
  • the liquid crystal light alignment technology refers to the purpose of achieving liquid crystal alignment by causing a reaction of a monomer in a liquid crystal to cause a liquid crystal molecule to form a pretilt angle by applying ultraviolet light to a liquid crystal panel.
  • the product In the LCD production process, usually due to the yield factor, the product needs to be tested at a specific point in the process to find the existing problems, so as to repair the product to improve the product yield; For detection, it is necessary to power on the GOA circuit and the effective display area (AA). It is necessary to set a signal pad around the peripheral trace to energize the probe; in today's GOA products, for high resolution, large size, The need for high frequencies is growing, and to meet these needs, additional signals need to be added to the product design to share the RC loading so that the main-board can have enough thrust to maintain signal stability; In the GOA product, the four clock (CK) signals required for high definition (HD) resolution are changed to the 12 CK signals required for the ultra high definition (UD) trigate.
  • CK clock
  • the detection device need to add 8 probes for each set of probes to detect it; if a mask contains multiple chips on the production capacity, the process needs to be simultaneously Multiple chips Measure or align the liquid crystal, the existing design needs to increase the number of pads accordingly, resulting in the detection equipment needs to increase 8 ⁇ N (N is the number of chips on the substrate) probes, so that the product cost increases too much, at the same time, too much
  • N is the number of chips on the substrate
  • FIG. 1A it is a schematic diagram of a conventional normal HVA pad design; a plurality of sets of HVA pads 1 are disposed around the periphery of the wafer 4, and other such as an Array test pad 2 and A cell test pad 3 is formed.
  • FIG. 1B it is a schematic diagram of a specific pad type included in the existing HVA pad of FIG. 1A.
  • Each group of HVA pads 1 is used to detect or align the wafers 4 in the process.
  • a group of HVA pads 1 may include n clocks such as input clock signals.
  • Pad CK1...CKn color film substrate common voltage pad CFcom for inputting common voltage of color film substrate
  • array substrate common voltage pad Acom for inputting common voltage of array substrate, for inputting DC high voltage DC high
  • the voltage pad VGH, etc. each pad is connected according to the type and the corresponding position of the peripheral trace.
  • the specific pad type, quantity and the like included in each group of HVA pads 1 can be determined according to the detection of the wafer 4 or the liquid crystal alignment requirement.
  • each wafer 4 corresponds to a group of HVA pads 1; wherein, if a group of HVA pads 1 includes M pads, for N wafers 4, N x M pieces are normally required.
  • the solder pad makes the number of pads of a group of HVA pads 1 too much, resulting in tight layout and high cost; and if a group of HVA pads 1 simultaneously detects multiple wafers 4 or aligns the liquid crystals, once A short between signals within the wafer 4 may cause other wafers 4 to fail to detect or fail to align.
  • the present invention provides a HVA pad sharing structure comprising: a set of HVA pads for sharing, the set of HVA pads comprising n clock pads for inputting m high DC potentials a DC high potential pad for inputting a DC low potential pad of a DC low potential, and n clock conversion circuits respectively corresponding to the n clock pads; wherein m is a natural number greater than 1, indicating sharing of the group of HVA The number of wafers of the pad, n is a natural number: the n clock pads are respectively connected with the corresponding n clock conversion circuits to respectively input corresponding clock signals to the corresponding n clock conversion circuits, the m DC high potential welding a pad and a DC low potential pad are connected to each of the clock conversion circuits to input m DC high potentials and one DC low potential to each clock conversion circuit; when each clock conversion circuit inputs a corresponding clock signal and m DC high potentials and one When the DC is low, the respective clock conversion circuits are controlled by the corresponding clock signals to output
  • the m DC high potential pads input the same DC high potential.
  • the m-channel clock signal is a square wave
  • the DC high-potential is a high level of the square wave
  • the m-channel clock signal is a square wave
  • the DC low-potential is a low level of the square wave
  • Each of the clock conversion circuits includes m units, and the m units respectively correspond to the m DC high potential pads and m wafers to output a corresponding one-way clock signal to the corresponding chip, and each unit includes:
  • a first thin film transistor having a gate connected to a clock pad corresponding to a current clock conversion circuit, a source connected to a DC high potential pad corresponding to the current unit, and a drain connected to a wafer corresponding to the current unit;
  • the second thin film transistor has a signal input from a gate thereof inverted from a signal input from a gate of the first thin film transistor, a source connected to a wafer corresponding to the current cell, and a drain connected to the DC low potential pad.
  • the corresponding clock signal respectively input to the corresponding n clock conversion circuits via the clock pad is a square wave, and the DC high potential is equal to the high level of the square wave.
  • the DC low potential is equal to the low level of the square wave.
  • the HVA pad sharing structure is connected to the GOA circuit of the active LCD and the peripheral trace of the effective display area.
  • the set of HVA pads further comprises a color film substrate common voltage pad for inputting a common voltage of the color film substrate.
  • the set of HVA pads further comprises an array substrate common voltage pad for inputting the common voltage of the array substrate.
  • the invention also provides a HVA pad sharing structure, comprising: a set of HVA pads for sharing, the set of HVA pads comprising n clock pads for inputting DC high potential pads of DC high potential a DC low potential pad for inputting a DC low potential, and n clock conversion circuits respectively corresponding to the n clock pads; wherein m is a natural number greater than 1, indicating a wafer sharing the set of HVA pads
  • the number, n is a natural number: the n clock pads are respectively connected with the corresponding n clock conversion circuits to respectively input corresponding clock signals to the corresponding n clock conversion circuits, the m DC high potential pads and a DC low
  • the potential pads are connected to the respective clock conversion circuits to input m DC high potentials and one DC low potential to the respective clock conversion circuits; when the respective clock conversion circuits input corresponding clock signals and m DC high potentials and one DC low potential, Each clock conversion circuit is controlled by a corresponding clock signal to output m clock signals according to m DC high potentials and
  • the m DC high potential pads input the same DC high potential
  • Each of the clock conversion circuits includes m units, and the m units respectively correspond to the m DC high potential pads and m wafers to output a corresponding one-way clock signal to the corresponding chip, and each unit includes:
  • a first thin film transistor having a gate connected to a clock pad corresponding to a current clock conversion circuit, a source connected to a DC high potential pad corresponding to the current unit, and a drain connected to a wafer corresponding to the current unit;
  • a second thin film transistor wherein a signal input from a gate thereof is opposite to a signal input from a gate of the first thin film transistor, a source is connected to a wafer corresponding to the current unit, and a drain is connected to the DC low potential pad;
  • the HVA pad sharing structure is connected to the GOA circuit of the active LCD and the peripheral trace of the effective display area;
  • the set of HVA pads further comprises a color film substrate common voltage pad for inputting a common voltage of the color film substrate;
  • the set of HVA pads further comprises an array substrate common voltage pad for inputting the common voltage of the array substrate.
  • the HVA pad sharing structure of the present invention can use a set of HVA pads to simultaneously provide signals for multiple wafers to detect or align liquid crystals, reduce process time, reduce costs, ease design space constraints, and improve glass. Substrate utilization.
  • FIG. 1A is a schematic view showing the design of a conventional normal HVA pad
  • FIG. 1B is a schematic view showing a specific type of pad included in the conventional HVA pad of FIG. 1A;
  • FIG. 2 is a schematic structural view of a preferred embodiment of a shared structure of a HVA pad of the present invention
  • FIG. 3 is a schematic view showing the type of a specific pad included in the HVA pad of FIG. 2;
  • FIG. 4 is a schematic diagram of a clock conversion circuit of a preferred embodiment of the HVA pad sharing structure of the present invention.
  • FIG. 5 is a timing diagram of a preferred embodiment of a shared structure of an HVA pad of the present invention.
  • FIG. 6 is a schematic view showing the application of a preferred embodiment of the HVA pad sharing structure of the present invention.
  • the HVA pad sharing structure 60 of the present invention mainly comprises: a set of HVA pads 10 for sharing, the set of HVA pads 10 comprising at least n clock pads for inputting m high potentials V1...Vm a DC high potential pad 20 for inputting a DC low potential pad 30 of a DC low potential VGL, and n clock conversion circuits 40 respectively corresponding to the n clock pads; wherein m is a natural number greater than 1, indicating The number of the wafers 50 sharing the set of HVA pads 10, n is a natural number: the n clock pads are respectively connected to the corresponding n clock conversion circuits 40 to respectively input corresponding clock signals to the corresponding n clock conversion circuits 40.
  • the m DC high potential pads 20 and a DC low potential pad 30 are connected to the respective clock conversion circuits 40 to input m DC high potentials and one DC low potential to the respective clock conversion circuits 40; when the respective clock conversion circuits 40 When the corresponding clock signal and m DC high potentials and one DC low potential are input, the respective clock conversion circuits 40 are controlled by the corresponding clock signals to output m clock signals according to m DC high potentials and one DC low potential. M wafers 50 are supplied.
  • the invention only adds m+1 pads on the original set of HVA pads 10, m corresponds to the number of wafer patterns contained on the mask; clock switching is designed at the clock pads in the HVA pads 10.
  • the present invention is applicable to a GOA product in an active LCD, and the shared structure can be connected to the GOA circuit of the active LCD and the peripheral trace of the effective display area.
  • FIG. 3 it is a schematic diagram of a specific pad type included in the HVA pad of FIG. 2, and is only used to illustrate the present invention.
  • Each set of HVA pads 10 is used to detect or align the wafers 50 during processing.
  • a set of HVA pads 10 may include, for example, n clocks for inputting clock signals, depending on the particular GOA circuit structure on the wafer 50.
  • Pad CK1...CKn color film substrate common voltage pad CFcom for inputting common voltage of color film substrate, array substrate common voltage pad Acom for inputting common voltage of array substrate, low frequency clock for inputting low frequency clock signal Pads LC1, LC2, etc., each pad is connected according to the type and the corresponding position of the peripheral trace.
  • the specific pad type, quantity and the like included in a group of HVA pads 10 can be determined according to the detection of the wafer 50 or the liquid crystal alignment requirement.
  • the detecting device or the like connects the pads through the probe to provide a corresponding signal or voltage.
  • Each clock conversion circuit 40 includes m cells respectively corresponding to the m DC high potential pads 20 and m wafers 50 to output corresponding one clock signals to the corresponding wafer 50, each unit include:
  • the first thin film transistor T1 has a gate connected to the clock pad CKn corresponding to the current clock conversion circuit to input a corresponding clock signal CKn, and the source is connected to a DC high potential pad (one of V1 to Vm) corresponding to the current unit, and the drain Connecting the wafer corresponding to the current unit (one of the wafer 1 to the wafer m);
  • the second thin film transistor T2 has a signal XCKn input from the gate thereof and an inverted signal CKn input from the gate of the first thin film transistor, and a source connected to the wafer corresponding to the current cell (one of the wafer 1 to the wafer m), The drain is connected to the DC low potential pad VGL.
  • the design of the HVA pad sharing structure of the present invention includes a clock conversion circuit 40 that divides a clock (CK) signal into a plurality of branches, and the inter-branch clock signals do not interfere with each other.
  • the design can save (A-1) ⁇ m - (m + 1) pads.
  • (A-1) ⁇ m is the number of clock pads saved due to sharing
  • (m+1) is V1...Vm and the number of VGL signals
  • V1...Vm can be VGH signals, input the same DC height Potential.
  • the m-channel clock signal outputted to the wafer 50 via the clock conversion circuit 40 may be a square wave, with the DC high potential VGH being the high level of the square wave and the DC low potential VGL being the low level of the square wave.
  • FIG. 5 is a timing diagram of a preferred embodiment of the HVA pad sharing structure of the present invention.
  • the clock signal CKn is inverted from XCKn and is a square wave.
  • the corresponding clock signal CKn input to the corresponding n clock conversion circuits via the clock pad CKn is a square wave
  • the DC high potential VGH can be equal to the high level of the square wave CKn, DC.
  • the low potential VGL can be equal to the low level of the square wave CKn, that is, the clock signal CKn is converted by the clock conversion circuit 40 to output the same waveform.
  • FIG. 6 is a schematic diagram of the application of a preferred embodiment of the HVA pad sharing structure of the present invention.
  • the HVA pad sharing structure 60 of the present invention can be connected to the GOA circuit of the active LCD and the peripheral traces of the active display area.
  • a peripheral trace of the surrounding wafer 50 is provided with a set of HVA pad sharing structures 60, as well as other such as array test pads 70 and boxed test pads 80.
  • a detecting device or the like is connected to each of the pads through a probe to provide a corresponding signal or voltage.
  • the HVA pad sharing structure of the present invention can simultaneously provide signals for detecting or aligning liquid crystals by using a set of HVA pads, thereby reducing process time and reducing cost; alleviating tension in design layout space and improving glass Substrate utilization.

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Abstract

一种HVA焊垫共用结构（60），包括一组用于共用的HVA焊垫（10），该组HVA焊垫包含n个时钟焊垫，用于输入直流高电位（V1…Vm）的m个直流高电位焊垫(20)，用于输入直流低电位（VGL）的一个直流低电位焊垫（30），以及分别对应于该n个时钟焊垫的n个时钟转换电路（40）。其中m为大于1的自然数，表示共用该组HVA焊垫的晶片的数量，n为自然数。该n个时钟焊垫与对应的n个时钟转换电路分别连接以向对应的n个时钟转换电路分别输入相应的时钟信号。该m个直流高电位焊垫和一个直流低电位焊垫连接至各个时钟转换电路以向各个时钟转换电路输入m个直流高电位和一个直流低电位。采用一组HVA焊垫即可同时对多个晶片提供信号进行检测或对液晶进行配向，减少制程时间。

Description

HVA焊垫共用结构 技术领域
本发明涉及液晶显示器领域，尤其涉及一种HVA焊垫共用结构。
背景技术
液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
主动式液晶显示器中，每个子像素具有一个薄膜晶体管(TFT)，其栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得该条水平扫描线上的所有TFT打开，此时该条水平扫描线上的像素电极会与垂直方向上的数据线连通，从而将数据线上的显示信号电压写入像素，控制不同液晶的透光度进而达到控制色彩的效果。目前主动式液晶显示面板水平扫描线的驱动主要由面板外接的芯片(IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。阵列基板行驱动(Gate Driver On Array，简称GOA)技术，也就是利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式。
目前市场上的TFT-LCD显示面板可分为三种类型，分别是扭曲向列(TN)或超扭曲向列(STN)型，平面转换(IPS)型、及垂直配向(VA)型。其中VA型液晶显示器相对其他种类的液晶显示器具有极高的对比度，在大尺寸显示，如电视等方面具有非常广的应用。而高垂直排列(HVA)模式是VA模式中一个重要的分支。HVA型液晶显示面板工作时是由阵列基板侧的像素电极和彩膜基板侧的公共电极形成的垂直电场来控制液晶层的液晶分子的旋转。液晶光配向技术是指在给液晶面板施加电压的情况下，通过紫外光照射，促使液晶中的单体反应，使液晶分子形成预倾角，从而达到液晶配向的目的。
在LCD生产过程中，通常因良率因素考虑，会需要在制程中的特定某个环节对该产品进行检测，找到存在的问题，以便对其进行修复来提升产品良率；若需要对产品进行检测，则需要对GOA电路及有效显示区(AA) 进行通电，则需要环绕外围走线设置信号焊垫(pad)以便探针通电；在现如今GOA产品中，对高分辨率、大尺寸、高频率的需求日益旺盛，而要达到这些需求，在产品设计时需要增加额外的信号来分担阻容负载(RC loading)，以便主板(main-board)可以有足够的推力来维持信号稳定；举例来说，GOA产品中，从高清晰度(HD)分辨率所需要的4个时钟(CK)信号变为超高清晰度(UD)三栅极(Trigate)所需要的12个CK信号，这也使得检测设备需要每组探针新增8个探针以便对其进行检测；若从产能上考虑，一个光罩(mask)上包含多个晶片(chip)的图案，则制程中需要同时对多个chip进行检测或对液晶进行配向，现有设计需要相应增加焊垫数量，导致检测设备需要增加8×N(N为基板上chip个数)个探针，使得产品成本上增加太多，同时，过多的探针(pin)也导致产品设计上的排版空间紧张。
如图1A所示，其为现有正常(normal)HVA焊垫设计示意图；环绕晶片4的外围走线设置有多组HVA焊垫1，以及其他诸如阵列测试焊垫(Array test pad)2和成盒测试焊垫(cell test pad)3。
如图1B所示，其为图1A中现有HVA焊垫所包含的具体焊垫类型示意图。各组HVA焊垫1用于在制程中对晶片4进行检测或对液晶进行配向，根据晶片4上具体的GOA电路结构，一组HVA焊垫1可以包括诸如用于输入时钟信号的n个时钟焊垫CK1……CKn，用于输入彩膜基板公共电压的彩膜基板公共电压焊垫CFcom，用于输入阵列基板公共电压的阵列基板公共电压焊垫Acom，用于输入直流高电压的直流高电压焊垫VGH等，各焊垫根据类型与外围走线的相应位置连接，各组HVA焊垫1所包括的具体焊垫类型、数量等可根据晶片4的检测或液晶配向需求来确定。
现有正常HVA焊垫设计是每个晶片4对应一组HVA焊垫1；其中，一组HVA焊垫1若包括M个焊垫，对于N个晶片4，则正常情况下需要N×M个焊垫，使得一组HVA焊垫1的焊垫数目过多，造成排版紧张，成本升高；而若一组HVA焊垫1同时对多个晶片4进行检测或对液晶进行配向，一旦某个晶片4内信号间短路(short)则可能导致其他晶片4检测失败或者配向失败。
发明内容
因此，本发明的目的在于提供一种HVA焊垫共用结构，采用一组HVA焊垫即可同时对多个晶片提供信号。
为实现上述目的，本发明提供了一种HVA焊垫共用结构，包括：一组 用于共用的HVA焊垫，该组HVA焊垫包含n个时钟焊垫，用于输入直流高电位的m个直流高电位焊垫，用于输入直流低电位的一个直流低电位焊垫，以及分别对应于该n个时钟焊垫的n个时钟转换电路；其中m为大于1的自然数，表示共用该组HVA焊垫的晶片的数量，n为自然数：该n个时钟焊垫与对应的n个时钟转换电路分别连接以向对应的n个时钟转换电路分别输入相应的时钟信号，该m个直流高电位焊垫和一个直流低电位焊垫连接至各个时钟转换电路以向各个时钟转换电路输入m个直流高电位和一个直流低电位；当各个时钟转换电路输入相应的时钟信号以及m个直流高电位和一个直流低电位时，由相应的时钟信号控制各个时钟转换电路根据m个直流高电位和一个直流低电位输出m路时钟信号以分别供给m个晶片。
其中，所述m个直流高电位焊垫输入相同的直流高电位。
其中，所述m路时钟信号为方波，以所述直流高电位为该方波的高电平。
其中，所述m路时钟信号为方波，以所述直流低电位为该方波的低电平。
其中，每个时钟转换电路包括m个单元，该m个单元与所述m个直流高电位焊垫和m个晶片分别对应，以向对应的晶片输出对应的一路时钟信号，每个单元包括：
第一薄膜晶体管，其栅极连接当前时钟转换电路对应的时钟焊垫，源极连接当前单元对应的直流高电位焊垫，漏极连接当前单元对应的晶片；
第二薄膜晶体管，其栅极所输入的信号与该第一薄膜晶体管的栅极所输入的信号反相，源极连接当前单元对应的晶片，漏极连接该直流低电位焊垫。
其中，经所述时钟焊垫向对应的n个时钟转换电路分别输入的相应的时钟信号为方波，所述直流高电位与该方波的高电平相等。
其中，所述直流低电位与该方波的低电平相等。
其中，所述HVA焊垫共用结构连接至主动型LCD的GOA电路及有效显示区的外围走线。
其中，该组HVA焊垫还包含用于输入彩膜基板公共电压的彩膜基板公共电压焊垫。
其中，该组HVA焊垫还包含用于输入阵列基板公共电压的阵列基板公共电压焊垫。
本发明还提供一种HVA焊垫共用结构，包括：一组用于共用的HVA 焊垫，该组HVA焊垫包含n个时钟焊垫，用于输入直流高电位的m个直流高电位焊垫，用于输入直流低电位的一个直流低电位焊垫，以及分别对应于该n个时钟焊垫的n个时钟转换电路；其中m为大于1的自然数，表示共用该组HVA焊垫的晶片的数量，n为自然数：该n个时钟焊垫与对应的n个时钟转换电路分别连接以向对应的n个时钟转换电路分别输入相应的时钟信号，该m个直流高电位焊垫和一个直流低电位焊垫连接至各个时钟转换电路以向各个时钟转换电路输入m个直流高电位和一个直流低电位；当各个时钟转换电路输入相应的时钟信号以及m个直流高电位和一个直流低电位时，由相应的时钟信号控制各个时钟转换电路根据m个直流高电位和一个直流低电位输出m路时钟信号以分别供给m个晶片；
其中，所述m个直流高电位焊垫输入相同的直流高电位；
其中，每个时钟转换电路包括m个单元，该m个单元与所述m个直流高电位焊垫和m个晶片分别对应，以向对应的晶片输出对应的一路时钟信号，每个单元包括：
第一薄膜晶体管，其栅极连接当前时钟转换电路对应的时钟焊垫，源极连接当前单元对应的直流高电位焊垫，漏极连接当前单元对应的晶片；
第二薄膜晶体管，其栅极所输入的信号与该第一薄膜晶体管的栅极所输入的信号反相，源极连接当前单元对应的晶片，漏极连接该直流低电位焊垫；
其中，所述HVA焊垫共用结构连接至主动型LCD的GOA电路及有效显示区的外围走线；
其中，该组HVA焊垫还包含用于输入彩膜基板公共电压的彩膜基板公共电压焊垫；
其中，该组HVA焊垫还包含用于输入阵列基板公共电压的阵列基板公共电压焊垫。
综上，本发明的HVA焊垫共用结构采用一组HVA焊垫即可同时对多个晶片提供信号进行检测或对液晶进行配向，减少制程时间；降低成本；缓解设计排版空间紧张问题，提高玻璃基板利用率。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1A所示为现有正常HVA焊垫设计示意图；
图1B所示为图1A中现有HVA焊垫所包含的具体焊垫类型示意图；
图2为本发明HVA焊垫共用结构一较佳实施例的结构示意图；
图3为图2中HVA焊垫所包含的具体焊垫类型示意图；
图4为本发明HVA焊垫共用结构一较佳实施例的时钟转换电路示意图；
图5为本发明HVA焊垫共用结构一较佳实施例的时序示意图；
图6为本发明HVA焊垫共用结构一较佳实施例的应用示意图。
具体实施方式
参见图2，其为本发明HVA焊垫共用结构一较佳实施例的结构示意图。本发明的HVA焊垫共用结构60主要包括：一组用于共用的HVA焊垫10，该组HVA焊垫10至少包含n个时钟焊垫，用于输入直流高电位V1……Vm的m个直流高电位焊垫20，用于输入直流低电位VGL的一个直流低电位焊垫30，以及分别对应于该n个时钟焊垫的n个时钟转换电路40；其中m为大于1的自然数，表示共用该组HVA焊垫10的晶片50的数量，n为自然数：该n个时钟焊垫与对应的n个时钟转换电路40分别连接以向对应的n个时钟转换电路40分别输入相应的时钟信号，该m个直流高电位焊垫20和一个直流低电位焊垫30连接至各个时钟转换电路40以向各个时钟转换电路40输入m个直流高电位和一个直流低电位；当各个时钟转换电路40输入相应的时钟信号以及m个直流高电位和一个直流低电位时，由相应的时钟信号控制各个时钟转换电路40根据m个直流高电位和一个直流低电位输出m路时钟信号以分别供给m个晶片50。
本发明只在原先所需的一组HVA焊垫10上增加m+1个焊垫，m对应于光罩上所包含晶片图案个数；在HVA焊垫10中的时钟焊垫处设计时钟转换电路；本发明适用于主动型LCD中的GOA产品，共用结构可以连接至主动型LCD的GOA电路及有效显示区的外围走线。
如图3所示，其为图2中HVA焊垫所包含的具体焊垫类型示意图，仅用于对本发明进行举例说明。各组HVA焊垫10用于在制程中对晶片50进行检测或对液晶进行配向，根据晶片50上具体的GOA电路结构，一组HVA焊垫10可以包括诸如用于输入时钟信号的n个时钟焊垫CK1……CKn，用于输入彩膜基板公共电压的彩膜基板公共电压焊垫CFcom，用于输入阵列基板公共电压的阵列基板公共电压焊垫Acom，用于输入低频时钟信号的低频时钟焊垫LC1、LC2等，各焊垫根据类型与外围走线的相应位置连接，一组HVA焊垫10所包括的具体焊垫类型、数量等可根据晶片50的检测或液晶配向需求预先确定。制程中进行检测或液晶配向时，检测装置等通过 探针连接各焊垫以提供相应的信号或电压。
图4为本发明HVA焊垫共用结构一较佳实施例的时钟转换电路示意图。每个时钟转换电路40包括m个单元，该m个单元与所述m个直流高电位焊垫20和m个晶片50分别对应，以向对应的晶片50输出对应的一路时钟信号，每个单元包括：
第一薄膜晶体管T1，其栅极连接当前时钟转换电路对应的时钟焊垫CKn以输入相应的时钟信号CKn，源极连接当前单元对应的直流高电位焊垫(V1至Vm其中之一)，漏极连接当前单元对应的晶片(晶片1至晶片m其中之一)；
第二薄膜晶体管T2，其栅极所输入的信号XCKn与该第一薄膜晶体管的栅极所输入的信号CKn反相，源极连接当前单元对应的晶片(晶片1至晶片m其中之一)，漏极连接该直流低电位焊垫VGL。
本发明HVA焊垫共用结构的设计其中所包含的时钟转换电路40，将一个时钟(CK)信号分成多个分支，且分支间时钟信号互不干扰。假设GOA产品上时钟数目为A个，则本设计可以节省(A－1)×m－(m+1)个焊垫。其中，(A－1)×m为因共用而节省的时钟焊垫数量，(m+1)为V1…Vm以及一个VGL信号的数量；V1…Vm可以均为VGH信号，输入相同的直流高电位。经时钟转换电路40输出至晶片50的m路时钟信号可以为方波，以直流高电位VGH为该方波的高电平，以直流低电位VGL为该方波的低电平。
图5为本发明HVA焊垫共用结构一较佳实施例的时序示意图。时钟信号CKn与XCKn反相，均为方波。以时钟焊垫CKn为例，经时钟焊垫CKn向对应的n个时钟转换电路分别输入的相应的时钟信号CKn为方波，直流高电位VGH可以与该方波CKn的高电平相等，直流低电位VGL可以与该方波CKn的低电平相等，也就是使时钟信号CKn经时钟转换电路40转换后输出相同的波形。
参见图6，其为本发明HVA焊垫共用结构一较佳实施例的应用示意图。本发明的HVA焊垫共用结构60可以连接至主动型LCD的GOA电路及有效显示区的外围走线。环绕晶片50的外围走线设置有一组HVA焊垫共用结构60，以及其他诸如阵列测试焊垫70和成盒测试焊垫80。制程中进行检测或液晶配向时，检测装置等通过探针连接至各焊垫以提供相应的信号或电压。
综上，本发明的HVA焊垫共用结构采用一组HVA焊垫即可同时对多个晶片提供信号进行检测或对液晶进行配向，减少制程时间；降低成本； 缓解设计排版空间紧张问题，提高玻璃基板利用率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种HVA焊垫共用结构，包括：一组用于共用的HVA焊垫，该组HVA焊垫包含n个时钟焊垫，用于输入直流高电位的m个直流高电位焊垫，用于输入直流低电位的一个直流低电位焊垫，以及分别对应于该n个时钟焊垫的n个时钟转换电路；其中m为大于1的自然数，表示共用该组HVA焊垫的晶片的数量，n为自然数：该n个时钟焊垫与对应的n个时钟转换电路分别连接以向对应的n个时钟转换电路分别输入相应的时钟信号，该m个直流高电位焊垫和一个直流低电位焊垫连接至各个时钟转换电路以向各个时钟转换电路输入m个直流高电位和一个直流低电位；当各个时钟转换电路输入相应的时钟信号以及m个直流高电位和一个直流低电位时，由相应的时钟信号控制各个时钟转换电路根据m个直流高电位和一个直流低电位输出m路时钟信号以分别供给m个晶片。
  2. 如权利要求1所述的HVA焊垫共用结构，其中，所述m个直流高电位焊垫输入相同的直流高电位。
  3. 如权利要求2所述的HVA焊垫共用结构，其中，所述m路时钟信号为方波，以所述直流高电位为该方波的高电平。
  4. 如权利要求2所述的HVA焊垫共用结构，其中，所述m路时钟信号为方波，以所述直流低电位为该方波的低电平。
  5. 如权利要求1所述的HVA焊垫共用结构，其中，每个时钟转换电路包括m个单元，该m个单元与所述m个直流高电位焊垫和m个晶片分别对应，以向对应的晶片输出对应的一路时钟信号，每个单元包括：
    第一薄膜晶体管，其栅极连接当前时钟转换电路对应的时钟焊垫，源极连接当前单元对应的直流高电位焊垫，漏极连接当前单元对应的晶片；
    第二薄膜晶体管，其栅极所输入的信号与该第一薄膜晶体管的栅极所输入的信号反相，源极连接当前单元对应的晶片，漏极连接该直流低电位焊垫。
  6. 如权利要求1所述的HVA焊垫共用结构，其中，经所述时钟焊垫向对应的n个时钟转换电路分别输入的相应的时钟信号为方波，所述直流高电位与该方波的高电平相等。
  7. 如权利要求6所述的HVA焊垫共用结构，其中，所述直流低电位与该方波的低电平相等。
  8. 如权利要求1所述的HVA焊垫共用结构，其中，所述HVA焊垫共 用结构连接至主动型LCD的GOA电路及有效显示区的外围走线。
  9. 如权利要求1所述的HVA焊垫共用结构，其中，该组HVA焊垫还包含用于输入彩膜基板公共电压的彩膜基板公共电压焊垫。
  10. 如权利要求1所述的HVA焊垫共用结构，其中，该组HVA焊垫还包含用于输入阵列基板公共电压的阵列基板公共电压焊垫。
  11. 一种HVA焊垫共用结构，包括：一组用于共用的HVA焊垫，该组HVA焊垫包含n个时钟焊垫，用于输入直流高电位的m个直流高电位焊垫，用于输入直流低电位的一个直流低电位焊垫，以及分别对应于该n个时钟焊垫的n个时钟转换电路；其中m为大于1的自然数，表示共用该组HVA焊垫的晶片的数量，n为自然数：该n个时钟焊垫与对应的n个时钟转换电路分别连接以向对应的n个时钟转换电路分别输入相应的时钟信号，该m个直流高电位焊垫和一个直流低电位焊垫连接至各个时钟转换电路以向各个时钟转换电路输入m个直流高电位和一个直流低电位；当各个时钟转换电路输入相应的时钟信号以及m个直流高电位和一个直流低电位时，由相应的时钟信号控制各个时钟转换电路根据m个直流高电位和一个直流低电位输出m路时钟信号以分别供给m个晶片；
    其中，所述m个直流高电位焊垫输入相同的直流高电位；
    其中，每个时钟转换电路包括m个单元，该m个单元与所述m个直流高电位焊垫和m个晶片分别对应，以向对应的晶片输出对应的一路时钟信号，每个单元包括：
    第一薄膜晶体管，其栅极连接当前时钟转换电路对应的时钟焊垫，源极连接当前单元对应的直流高电位焊垫，漏极连接当前单元对应的晶片；
    第二薄膜晶体管，其栅极所输入的信号与该第一薄膜晶体管的栅极所输入的信号反相，源极连接当前单元对应的晶片，漏极连接该直流低电位焊垫；
    其中，所述HVA焊垫共用结构连接至主动型LCD的GOA电路及有效显示区的外围走线；
    其中，该组HVA焊垫还包含用于输入彩膜基板公共电压的彩膜基板公共电压焊垫；
    其中，该组HVA焊垫还包含用于输入阵列基板公共电压的阵列基板公共电压焊垫。
  12. 如权利要求11所述的HVA焊垫共用结构，其中，所述m路时钟信号为方波，以所述直流高电位为该方波的高电平。
  13. 如权利要求11所述的HVA焊垫共用结构，其中，所述m路时钟 信号为方波，以所述直流低电位为该方波的低电平。
  14. 如权利要求11所述的HVA焊垫共用结构，其中，经所述时钟焊垫向对应的n个时钟转换电路分别输入的相应的时钟信号为方波，所述直流高电位与该方波的高电平相等。
  15. 如权利要求14所述的HVA焊垫共用结构，其中，所述直流低电位与该方波的低电平相等。
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