Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5642—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/26—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
  • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
  • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits

Definitions

• the present invention relates to non- volatile memory devices
• Non- volatile memory devices are well known in the art.
• a split-gate memory cell is disclosed in U.S. Patent 5,029,130.
• This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions.
• Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region to determine the programming state of the floating gate).
• U.S. Patent 7,315,056 discloses a memory cell that additionally includes a program/erase gate over the source region.
• U.S. Patent 7,868,375 discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate.
• Fig. 1 illustrates a split gate memory cell 10 with spaced apart source and drain regions 14/16 formed in a silicon semiconductor substrate 12.
• a channel region 18 of the substrate is defined between the source/drain regions 14/16.
• a floating gate 20 is disposed over and insulated from a first portion of the channel region 18 (and partially over and insulated from the source region 14).
• a control gate (also referred to as a word line gate or select gate) 22 has a lower portion disposed over and insulated from a second portion of the channel region 18, and an upper portion that extends up and over the floating gate 20 (i.e., the control gate 22 wraps around an upper edge of the floating gate 20).
• Memory cell 10 can be erased by placing a high positive voltage on the control gate 22, and a reference potential on the source and drain regions 14/16. The high voltage drop between the floating gate 20 and control gate 22 will cause electrons on the floating gate 20 to tunnel from the floating gate 20, through the intervening insulation, to the control gate 22 by the well-known Fowler-Nordheim tunneling mechanism (leaving the floating gate 20 more positively charged - the erased state). Memory cell 10 can be programmed by applying a ground potential to drain region 16, a positive voltage on source region 14, and a positive voltage on the control gate 22.
• Electrons will then flow from the drain region 16 toward the source region 14, with some electrons becoming accelerated and heated whereby they are injected onto the floating gate 20 (leaving the floating gate negatively charged - the programmed state).
• Memory cell 10 can be read by placing ground potential on the drain region 16, a positive voltage on the source region 14 and a positive voltage on the control gate 22 (turning on the channel region portion under the control gate 22). If the floating gate is more positively charged (erased), the positive voltage on the control gate will at least partially couple to the floating gate to turn on the channel region portion under the floating gate, and electrical current will flow from source region 14 to drain region 16 (i.e. the memory cell 10 is sensed to be in its erased "1" state based on sensed current flow).
• the coupled voltage from the control gate 22 will not overcome the negative charge of the floating gate, and the channel region under the floating gate is weakly turned on or turned off, thereby reducing or preventing any current flow (i.e., the memory cell 10 is sensed to be in its programmed "0" state based on sensed low or no current flow).
• Fig. 2 illustrates an alternate split gate memory cell 30 with same elements as memory cell 10, but additionally with a program/erase (PE) gate 32 disposed over and insulated from the source region 14 (i.e. this is a three gate design).
• Memory cell 30 can be erased by placing a high voltage on the PE gate 32 to induce tunneling of electrons from the floating gate 20 to the PE gate 32.
• Memory cell 30 can be programmed by placing positive voltages on the control gate 22, PE gate 32 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20.
• Memory cell 30 can be read by placing positive voltages on the control gate 22 and drain region 16, and sensing current flow.
• FIG. 3 illustrates an alternate split gate memory cell 40 with same elements as memory cell 10, but additionally with an erase gate 42 disposed over and insulated from the source region 14, and a coupling gate 44 over and insulated from the floating gate 20.
• Memory cell 40 can be erased by placing a high voltage on the erase gate 42 (and optionally a negative voltage on the coupling gate 44) to induce tunneling of electrons from the floating gate 20 to the erase gate 42.
• Memory cell 40 can be programmed by placing positive voltages on the control gate 22, erase gate 42, coupling gate 44 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20.
• Memory cell 30 can be read by placing positive voltages on the control gate 22 and drain region 16 (and optionally on the erase gate 42 and/or the coupling gate 44), and sensing current flow.
• each memory cell can only store one bit of data (i.e., the cell has only two possible states). There is a need to program more than one bit of data in each memory cell. It is also known to operate the above described memory cells in an analog fashion so that the memory cell can store more than just two binary values (i.e., just one bit of information).
• the memory cells can be operated below their threshold voltage, meaning that instead of fully programming or fully erasing the memory cells, they can be only partially programmed or partially erased, and operated in an analog fashion below the threshold voltage of the memory cell. It is also possible to program the memory cells to one of multiple program states above the threshold voltage too. However, if discrete programming states are desired, it can be difficult to reliably program and read the memory cells because the read current values for the various states are so close together.
• a method of reading a memory device having a plurality of memory cells by reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current.
• a method of reading a memory device having a plurality of memory cells includes reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, generating a first voltage from the first read current, generating a second voltage from the second read current, applying a first offset value to the second voltage, and then combining the first and second voltages to form a third voltage, and then determining a program state using the third voltage.
• a memory device includes a semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate, and circuitry formed on the semiconductor substrate and configured to read a first memory cell of the plurality of memory cells to generate a first read current, read a second memory cell of the plurality of memory cells to generate a second read current, apply a first offset value to the second read current, and then combine the first and second read currents to form a third read current, and then determine a program state using the third read current.
• a memory device includes a semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate, and circuitry formed on the semiconductor substrate and configured to read a first memory cell of the plurality of memory cells to generate a first read current, read a second memory cell of the plurality of memory cells to generate a second read current, generate a first voltage from the first read current, generate a second voltage from the second read current, apply a first offset value to the second voltage, and then combine the first and second voltages to form a third voltage, and then determine a program state using the third voltage.
• Fig. 1 is a side cross sectional view of a first conventional split gate non-volatile memory cell.
• Fig. 2 is a side cross sectional view of a second conventional split gate nonvolatile memory cell.
• Fig. 3 is a side cross sectional view of a third conventional split gate non-volatile memory cell.
• Fig. 4 is a graph illustrating the current versus voltage characteristics for eight program states of a non- volatile memory cell.
• Figs. 5A-5B are graphs illustrating the current versus voltage characteristics for eight program states of two non-volatile memory cell.
• Figs. 6A-6B are graphs illustrating the current versus voltage characteristics for eight program states of two non-volatile memory cells, with the program states of the second cell shifted relative to those of the first.
• Figs. 6C is a graph illustrating collectively the current versus voltage
• Fig. 7 is a plan view of a memory device architecture.
• Fig. 8 is a schematic diagram illustrating the layout of an array of the memory cells.
• the present invention is directed to non-volatile memory devices capable of storing more than one bit of information in each memory cell. This can be done by operating the memory cells above and/or below their threshold voltage. For example, instead of fully programming or fully erasing the memory cells, they can be only partially programmed or partially erased, and operated in an analog fashion. The following description focuses on memory cells operating below the threshold voltage of the memory cell. However, it equally applies to memory cells operated above the threshold voltage of the memory cell as well.
• the memory cell represented by Fig. 4 can theoretically store multiple bits of information, because it can be programmed into 8 different states. By measuring the current at one or more specific control gate voltages, such as read voltage V R , the program state n can be determined.
• n program states As indicated in Fig. 4 is that the difference in read current for two adjacent program states can be too small (i.e., the program states are too close together) for reliable operation when the number of states n exceeds just a few.
• Program states too close together are susceptible to noise on the program and/or reading of the memory cells. For example, there would be a small range of variation in terms of how reliably the memory cell can be programmed into any given program state. Similarly, there would be a small range of variation in terms of how reliably the state of the cell can be read by measuring the read currents. Therefore, the n states cannot be located too close to each other, otherwise they could not reliably be distinguished from each other. This places a practical limit on the number of states n that can be programmed into a single memory cell, which means there is a practical limit on the number of states n that can be stored in the memory device.
• Figures 5A-5B illustrate a solution to the above described problem.
• the different states n can be stored over multiple memory cells.
• the same number of total states can be stored, but with twice the separation between adjacent program states for better reliability.
• twice as many states can be stored with a given separation between adjacent program states using two memory cells relative to using just a single cell.
• Implementing the offset X for cell 2 can be done using an adding circuit that adds a current offset X to the read current from cell 2 before the read current from cell 2 is added to the cell current from cell 1 (e.g., the adding circuit is part of the sense amplifier that is used to detect currents through the cells). Or, the adding circuit can add a voltage offset X to a voltage signal that is generated by the sense amplifier to reflect the current being detected through cell 2. In this case, it would be the voltages signals (corresponding to the detected current levels) that are added together before determining from the combined voltage signal which program state was read from the pair of memory cells.
• a multiplier circuit can be as part of, or downstream of, the sense amplifier to multiply the current or voltage signal for cell 2 before being added to the current/voltage signal for cell 1.
• the offset X whether it be a voltage offset or a current offset, could be stored in a reference cell (i.e., a memory cell in the memory cell array dedicated for this purpose), so that the proper amount of offset is reliably applied to the voltage or current signal for cell 2 for that given die.
• the architecture of an exemplary memory device is illustrated in Fig. 7.
• the memory device includes an array 50 of non-volatile memory cells, which can be segregated into two separate planes (Plane A 52a and Plane B 52b).
• the memory cells can be of the type shown in Figures 1-3, formed on a single chip, arranged in a plurality of rows and columns in the semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g. XDEC 54 (row decoder), SLDRV 56, YMUX 58 (column decoder), HVDEC 60) and a bit line controller (BLINHCTL 62), which are used to decode addresses and supply the various voltages to the various memory cell gates and regions during read, program, and erase operations for selected memory cells.
• Column decoder 58 includes sense amplifiers for measuring the voltages or currents on the bit lines during a read operation.
• Controller 66 controls the various device elements to implement each operation (program, erase, read) on target memory cells.
• Charge pump CHRGPMP 64 provides the various voltages used to read, program and erase the memory cells under the control of the controller 66.
• the offset X and signal adding can be implemented, for example, with circuitry in the controller 66. Alternately or additionally, the offset X and signal adding can be implemented with circuitry in the sense amplifier portion of the column decoder YMUX 58.
• Fig. 8 shows the array configuration for the two-gate memory cells of Fig. 1, where the memory cells are arranged in rows and columns. This array configuration equally applies to the memory cells of Figs. 2-3, whereby additional lines would be added for the additional gates.
• Word lines WL each connect to the control gates for one row of memory cells.
• Bit lines BL each connect to the drain regions for one column of memory cells.
• Source lines SL each connect to the source regions for one row of a pair of memory cells.
• each of cells having their read currents or voltages added together are disposed in different columns so the read process is faster. Therefore, for the example above where two memory cells are used, cell 1 would be in column 1 connected to bit line BLO, and cell 2 would be in column 2 connected to bit line BL1.
• the read current for cell 1 is detected on bit line BLO and the read current for cell 2 is detected on bit line BL1.
• Circuitry in the sense amplifiers or downstream from there will add the offset X to the read current on bit line BL1 (or the voltage corresponding thereto) and then add the read currents (or voltages) from both cells to each other and then determine from the combined read current/voltage what program state is programmed in the pair of memory cells.
• references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims.
• the invention is described with respect to sub-threshold operation of the memory cells, it could be implemented in memory cells operated above threshold (in which case the logarithmic relationship between the current and the voltage may no longer apply).
• programming a cell to its highest program state shown in the figures actually involves an erase operation where the highest program state is a fully erased memory cell. Applying offset X is disclosed above by adding to (increasing) the value of the current or voltage by the amount X.
• offset X could include a negative offset, which can be achieved by subtracting from (decreasing) the value of the current or voltage by the amount X.
• Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated.
• the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
• forming an element "over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.

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• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Read Only Memory (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)

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• 2018
  • 2018-10-01 US US16/148,304 patent/US10515694B2/en active Active
  • 2018-10-02 CN CN201880068646.XA patent/CN111344791B/zh active Active
  • 2018-10-02 JP JP2020524440A patent/JP6970826B2/ja active Active
  • 2018-10-02 WO PCT/US2018/053930 patent/WO2019089168A1/en not_active Ceased
  • 2018-10-02 EP EP18872824.0A patent/EP3704700B1/en active Active
  • 2018-10-02 KR KR1020207010818A patent/KR102199607B1/ko active Active
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