WO2019080304A1 - Goa电路 - Google Patents

Goa电路

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Publication number
WO2019080304A1
WO2019080304A1 PCT/CN2017/116271 CN2017116271W WO2019080304A1 WO 2019080304 A1 WO2019080304 A1 WO 2019080304A1 CN 2017116271 W CN2017116271 W CN 2017116271W WO 2019080304 A1 WO2019080304 A1 WO 2019080304A1
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WIPO (PCT)
Prior art keywords
node
signal output
source
drain
output point
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Ceased
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PCT/CN2017/116271
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English (en)
French (fr)
Inventor
石龙强
陈书志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/742,043 priority Critical patent/US10217429B1/en
Publication of WO2019080304A1 publication Critical patent/WO2019080304A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit.
  • the GOA Gate Driver on Array
  • the GOA is beneficial to the design and cost reduction of the narrow side frame of the display driver, and has been widely applied and studied.
  • the GOA circuit generally includes a plurality of cascaded GOA circuit units, and N is a natural number, and the Nth-level GOA circuit unit is connected to an Nth-level signal output point G (N). ), responsible for outputting the horizontal scan signal of the Nth line.
  • N Nth-level signal output point G
  • FIG. 2 shows the waveforms and voltage waveforms of the signals and important nodes required for the GOA circuit unit of Figure 1.
  • STV is the start signal for inputting the first stage of the GOA circuit unit to start;
  • CK, XCK is the high frequency alternating current with the opposite phase of the signal, the high and low potentials of these signals are 28V, -5V, respectively, when using forward and reverse scanning In the driving mode, the two opposite phase clock signals CK and XCK are respectively used;
  • VSS indicates a DC low potential, and a low voltage direct current is input, and the potential is -5V.
  • IGZO Indium Gallium Zinc Oxide
  • TFT Thin Film Transistor
  • the present invention provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein N is a natural number, and the Nth stage GOA circuit unit comprises a GOA circuit portion and a signal amplifying circuit portion, and the GOA circuit portion is provided An Nth internal signal output point is connected to the signal amplifying circuit portion through the internal signal output point, and the signal amplifying circuit portion includes:
  • a first amplifying circuit thin film transistor having a gate connected to a high DC potential, and a source and a drain connected to the first amplifying circuit node and a direct current high potential;
  • a second amplifying circuit thin film transistor having a gate connected to an Nth internal signal output point, wherein the source and the drain are respectively connected to the first amplifying circuit node and a DC low potential;
  • a third amplifying circuit thin film transistor having a gate connected to a high DC potential, and a source and a drain respectively connected to an Nth external signal output point and a DC high potential;
  • the fourth amplifying circuit thin film transistor has a gate connected to the first amplifying circuit node, and a source and a drain connected to the Nth external signal output point and the DC low potential, respectively.
  • the GOA circuit is manufactured based on IGZO-TFT.
  • the part of the GOA circuit includes:
  • a first thin film transistor having a gate connected to an N-1th internal signal output point, and a source and a drain connected to the first node and the N-1th internal signal output point, respectively;
  • a second thin film transistor having a gate connected to the first node, wherein the source and the drain are respectively connected to the clock signal and the Nth internal signal output point;
  • a third thin film transistor having a gate connected to an N+1th internal signal output point, and a source and a drain respectively connected to the Nth internal signal output point and a DC low potential;
  • a fourth thin film transistor having a gate connected to an N+1th internal signal output point, and a source and a drain respectively connected to the first node and a DC low potential;
  • a fifth thin film transistor having a gate connected to the second node, wherein the source and the drain are respectively connected to the Nth internal signal output point and the DC low potential;
  • a sixth thin film transistor having a gate connected to the second node, the source and the drain being respectively connected to the first node and a DC low potential;
  • a seventh thin film transistor having a gate connected to a clock signal, and a source and a drain respectively connected to the clock signal and the second node;
  • An eighth thin film transistor having a gate connected to the first node, a source and a drain respectively connected to the second node and a DC low potential;
  • the bootstrap capacitor has two ends connected to the first node and the Nth internal signal output point.
  • the DC low potential is -5 volts.
  • the DC high potential is 28 volts.
  • the present invention also provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein N is a natural number, the Nth stage GOA circuit unit comprises a GOA circuit portion and a signal amplifying circuit portion, and the GOA circuit portion is provided with an Nth stage An internal signal output point is connected to the signal amplifying circuit portion through the internal signal output point, and the signal amplifying circuit portion includes:
  • a first amplifying circuit thin film transistor having a gate connected to a high DC potential, and a source and a drain connected to the first amplifying circuit node and a direct current high potential;
  • a second amplifying circuit thin film transistor having a gate connected to an Nth internal signal output point, wherein the source and the drain are respectively connected to the first amplifying circuit node and a DC low potential;
  • a third amplifying circuit thin film transistor having a gate connected to a high DC potential, and a source and a drain respectively connected to the second amplifying circuit node and a DC high potential;
  • a fourth amplifying circuit thin film transistor having a gate connected to the second amplifying circuit node, a source and a drain The poles are respectively connected to the Nth external signal output point and the DC high potential;
  • a fifth amplifying circuit thin film transistor having a gate connected to the first amplifying circuit node, wherein the source and the drain are respectively connected to the Nth external signal output point and the DC low potential;
  • the amplifying circuit bootstrap capacitor has two ends connected to the second amplifying circuit node and the Nth external signal output point.
  • the GOA circuit is manufactured based on IGZO-TFT.
  • the part of the GOA circuit includes:
  • a first thin film transistor having a gate connected to an N-1th internal signal output point, and a source and a drain connected to the first node and the N-1th internal signal output point, respectively;
  • a second thin film transistor having a gate connected to the first node, wherein the source and the drain are respectively connected to the clock signal and the Nth internal signal output point;
  • a third thin film transistor having a gate connected to an N+1th internal signal output point, and a source and a drain respectively connected to the Nth internal signal output point and a DC low potential;
  • a fourth thin film transistor having a gate connected to an N+1th internal signal output point, and a source and a drain respectively connected to the first node and a DC low potential;
  • a fifth thin film transistor having a gate connected to the second node, wherein the source and the drain are respectively connected to the Nth internal signal output point and the DC low potential;
  • a sixth thin film transistor having a gate connected to the second node, the source and the drain being respectively connected to the first node and a DC low potential;
  • a seventh thin film transistor having a gate connected to a clock signal, and a source and a drain respectively connected to the clock signal and the second node;
  • An eighth thin film transistor having a gate connected to the first node, a source and a drain respectively connected to the second node and a DC low potential;
  • the bootstrap capacitor has two ends connected to the first node and the Nth internal signal output point.
  • the DC low potential is -5 volts.
  • the DC high potential is 28 volts.
  • the present invention also provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein N is a natural number, the Nth stage GOA circuit unit comprises a GOA circuit portion and a signal amplifying circuit portion, and the GOA circuit portion is provided with an Nth internal portion a signal output point and connected to the signal amplifying circuit portion through the internal signal output point, the signal amplifying circuit portion comprising:
  • a first amplifying circuit thin film transistor having a gate connected to a high DC potential, and a source and a drain connected to the first amplifying circuit node and a direct current high potential;
  • a second amplifying circuit thin film transistor having a gate connected to an Nth internal signal output point, wherein the source and the drain are respectively connected to the first amplifying circuit node and a DC low potential;
  • a third amplifying circuit thin film transistor having a gate connected to a high DC potential, and a source and a drain respectively connected to an Nth external signal output point and a DC high potential;
  • a fourth amplifying circuit thin film transistor having a gate connected to the first amplifying circuit node, wherein the source and the drain are respectively connected to the Nth external signal output point and the DC low potential;
  • the GOA circuit is manufactured based on IGZO-TFT
  • the part of the GOA circuit includes:
  • a first thin film transistor having a gate connected to an N-1th internal signal output point, and a source and a drain connected to the first node and the N-1th internal signal output point, respectively;
  • a second thin film transistor having a gate connected to the first node, wherein the source and the drain are respectively connected to the clock signal and the Nth internal signal output point;
  • a third thin film transistor having a gate connected to an N+1th internal signal output point, and a source and a drain respectively connected to the Nth internal signal output point and a DC low potential;
  • a fourth thin film transistor having a gate connected to an N+1th internal signal output point, and a source and a drain respectively connected to the first node and a DC low potential;
  • a fifth thin film transistor having a gate connected to the second node, wherein the source and the drain are respectively connected to the Nth internal signal output point and the DC low potential;
  • a sixth thin film transistor having a gate connected to the second node, the source and the drain being respectively connected to the first node and a DC low potential;
  • a seventh thin film transistor having a gate connected to a clock signal, and a source and a drain respectively connected to the clock signal and the second node;
  • An eighth thin film transistor having a gate connected to the first node, a source and a drain respectively connected to the second node and a DC low potential;
  • a bootstrap capacitor the two ends of which are respectively connected to the first node and the Nth internal signal output point;
  • the DC low potential is -5 volts
  • the DC high potential is 28 volts.
  • the GOA circuit of the present invention integrates the level shift function into the GOA circuit, which is advantageous for reducing the cost of the driver IC and improving the GOA gate output waveform (waveform rise time and waveform fall time) and power reduction. Consumption.
  • FIG. 1 is a schematic diagram of a primary GOA circuit unit of a conventional GOA circuit
  • FIG. 2 is a waveform diagram of waveforms and voltages of signals and important nodes required for the GOA circuit unit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a GOA circuit unit according to a preferred embodiment of the GOA circuit of the present invention.
  • FIG. 4 is a schematic diagram of a GOA circuit unit according to still another preferred embodiment of the GOA circuit of the present invention.
  • FIG. 5 is a waveform diagram showing waveforms and voltages of signals and important nodes required for the GOA circuit unit shown in FIGS. 3 and 4.
  • FIG. 3 is a schematic diagram of a GOA circuit unit according to a preferred embodiment of the GOA circuit of the present invention, comprising a GOA circuit and a signal amplifying circuit.
  • the signal amplifying circuit portion is composed of four TFTs (T1, T2, T3, T4).
  • T1, T2, T3, T4 TFTs
  • the GOA circuit portion of the preferred embodiment is for example only, and other suitable GOA circuit forms may be employed.
  • FIG. 5 is a waveform diagram showing waveforms and voltages of signals and important nodes required for the GOA circuit unit shown in FIG.
  • STV, CK, XCK, VGH, VSS are signals given by the system.
  • STV, CK, XCK high and low potential is 5V and -5V
  • STV is used for the start of the first stage of the GOA unit, when the forward and reverse scan drive mode is used, the two opposite phase clock signals CK and XCK
  • VGH DC high potential, is high voltage DC
  • potential can be 28V
  • VSS is DC low potential
  • potential can be -5V
  • G(N-1)_in, G(N)_in, G(N +1)_in respectively represent the output waveform of the gate of the inside of the GOA circuit portion of the N-1, N, N+1-level GOA circuit unit, which is a waveform that is not amplified by the signal, that is, the high and low potentials respectively It is 5V and -5V.
  • G(N)_out refers to the gate output waveform of the Nth stage GOA circuit unit outputted through the signal amplifying circuit portion.
  • the waveform is the waveform of the gate of the TFT that is normally driven to be driven, and the high and low potentials are respectively 28V, -5V. .
  • the GOA circuit of the preferred embodiment mainly includes a GOA circuit portion and a signal amplifying circuit portion, and the GOA circuit portion is provided with an Nth internal signal output point G(N)_in and passes through the internal signal output point.
  • G(N)_in is connected to the signal amplifying circuit portion, and the signal amplifying circuit portion comprises: a T1 gate connected to a DC high potential VGH, a source and a drain respectively connected to the node S(N) and a DC high potential VGH; and a T2 gate connection
  • the Nth internal signal output point G(N)_in, the source and the drain are respectively connected to the node S(N) and the DC low potential VSS
  • the T3 gate is connected to the DC high potential VGH, and the source and the drain are respectively connected to the Nth stage
  • the T4 gate connection node S(N), the source and the drain are respectively connected to the Nth external signal output point G(N)_out and the DC low potential VSS.
  • the GOA circuit portion includes: a T11 gate connected to the N-1th internal signal output point G(N-1)_in, and the source and the drain are respectively connected to the node Q(N) and the N-1th internal signal output point G (N -1)_in; T21 gate connection node Q(N), source and drain are respectively connected with clock signal CK and Nth internal signal output point G(N)_in; T31 gate is connected to N+1th internal signal The output point G(N+1)_in, the source and the drain are respectively connected to the Nth internal signal output point G(N)_in and the DC low potential VSS; the T41 gate is connected to the N+1th internal signal output point G ( N+1)_in, the source and the drain are respectively connected to the node Q(N) and the DC low potential VSS; the T32 gate is connected to the node P(N), and the source and the drain are respectively connected to the Nth internal signal output point G ( N)_in and DC low potential VSS; T42 gate connection node P(N), source
  • the GOA circuit of the present invention can be fabricated based on IGZO-TFT.
  • the invention integrates a level shifting unit on a display screen based on the IGZO-TFT, which can save the cost of driving the IC (chip).
  • FIG. 4 is a schematic diagram of a GOA circuit unit according to still another preferred embodiment of the GOA circuit of the present invention, including a GOA circuit and a signal amplifying circuit.
  • the signal amplifying circuit portion is composed of 5 TFTs and a bootstrap capacitor Cb1.
  • the GOA circuit portion of the preferred embodiment is for illustration only, in the same form as in Figure 3, and other suitable GOA circuit forms may be employed.
  • Fig. 5 is also a waveform diagram showing waveforms and voltages of signals and important nodes required for the GOA circuit unit shown in Fig. 4.
  • the GOA circuit of the preferred embodiment mainly includes a GOA circuit portion and a signal amplifying circuit portion, and the GOA circuit portion is provided with an Nth internal signal output point G(N)_in and passes through the internal signal output point.
  • G(N)_in is connected to the signal amplifying circuit portion, and the signal amplifying circuit portion comprises: a T1 gate connected to a DC high potential VGH, a source and a drain respectively connected to the node S(N) and a DC high potential VGH; and a T2 gate connection
  • the Nth internal signal output point G(N)_in, the source and the drain are respectively connected to the node S(N) and the DC low potential VSS
  • the T3 gate is connected to the DC high potential VGH, and the source and the drain are respectively connected to the node T ( N) and DC high potential VGH
  • T4 gate connection node T (N) The source and the drain are respectively connected to the Nth external signal output point G(N)_out and the DC high potential VGH
  • the T5 gate is connected to the node S(N), and the source and the drain are respectively connected to the Nth external signal output point G (N)_out and DC low potential VSS
  • the amplifying circuit bootstrap capacitor Cb1 is connected
  • the circuit of the preferred embodiment has a more stable voltage output.
  • the working principle of the preferred embodiment will be described below with reference to FIGS. 4 and 5.
  • T2 When G(N)_in is low at -5V, T2 is turned off. Since T1 and T3 are connected to VGH (28V), T1 and T3 are turned on, and the potential of S(N) is 28V. When turned on, the potential of T(N) is 28V, and T4 is turned on. Due to the voltage division of T4 and T5, G(N)_out outputs a low potential of -5V of VSS.
  • T2 When G(N)_in is 5V high, T2 is turned on. Since the gate of T1 is connected to VGH (28V), T1 is also turned on T3. Because of the voltage division of T1 and T2, S(N) The potential is -5V, so T5 is off; T(N) is 28V, T4 is on, and G(N)_out outputs VGH at a high potential of 28V.
  • the highly integrated gate drive circuit design provided by the present invention can be applied to LCD displays as well as to OLED displays.
  • the GOA circuit of the present invention integrates the level shift function on the GOA circuit based on the IGZO-TFT, which is advantageous for reducing the cost of the driver IC and improving the GOA gate output waveform (waveform rise time and The falling time of the waveform) and reduced power consumption.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路，GOA电路的第N级GOA电路单元的信号放大电路部分包括：第一放大电路薄膜晶体管（T1）栅极连接直流高电位（VGH），源极和漏极连接第一放大电路节点（S(N)）和直流高电位（VGH）；第二放大电路薄膜晶体管（T2）栅极连接第N级内部信号输出点（G(N)_in），源极和漏极连接第一放大电路节点（S(N)）和直流低电位（VSS）；第三放大电路薄膜晶体管（T3）栅极连接直流高电位（VGH），源极和漏极连接第N级外部信号输出点（G(N)_out）和直流高电位（VGH）；第四放大电路薄膜晶体管（T4）栅极连接第一放大电路节点（S(N)），源极和漏极连接第N级外部信号输出点（G(N)_out）和直流低电位（VSS），可以改善GOA栅极输出波形和降低功耗。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
背景技术
GOA(Gate Driver on Array，阵列基板行驱动)技术有利于显示屏行驱动(gate driver)侧窄边框的设计和成本的降低，得到广泛地应用和研究。
图1为现有一种GOA电路的一级GOA电路单元示意图，GOA电路一般包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元连接第N级信号输出点G(N)，负责输出第N行水平扫描信号。各级GOA电路单元所需信号是从系统端的电平移位(Level shift)单元给入。
图2所示为图1中GOA电路单元所需信号和重要节点的波形和电压的波形。STV是起始信号，用于输入最初一级的GOA电路单元进行启动；CK，XCK是信号相位完全相反的高频交流电，这些信号的高低电位分别是28V，﹣5V，当采用正反向扫描驱动方式时会分别用到此两个相位相反的时钟信号CK和XCK；VSS表示直流低电位，输入低压直流电，电位为-5V。
另一方面，目前的IGZO(铟镓锌氧化物)-TFT(薄膜晶体管)具有高的迁移率，和良好的器件稳定性等优点。
发明内容
因此，本发明的目的在于提供一种GOA电路，将电平移位功能集成到GOA电路上。
为实现上述目的，本发明提供了一种GOA电路，包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点并通过该内部信号输出点连接该信号放大电路部分，该信号放大电路部分包括：
第一放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第一放大电路节点和直流高电位；
第二放大电路薄膜晶体管，其栅极连接第N级内部信号输出点，源极和漏极分别连接第一放大电路节点和直流低电位；
第三放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第N级外部信号输出点和直流高电位；
第四放大电路薄膜晶体管，其栅极连接第一放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流低电位。
其中，所述GOA电路基于IGZO-TFT制造。
其中，所述GOA电路部分包括：
第一薄膜晶体管，其栅极连接第N－1级内部信号输出点，源极和漏极分别连接第一节点和第N－1级内部信号输出点；
第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接时钟信号和第N级内部信号输出点；
第三薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
第四薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第一节点和直流低电位；
第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电位；
第七薄膜晶体管，其栅极连接时钟信号，源极和漏极分别连接时钟信号和第二节点；
第八薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电位；
自举电容，其两端分别连接第一节点和第N级内部信号输出点。
其中，所述直流低电位为﹣5伏。
其中，所述直流高电位为28伏。
本发明还提供了一种GOA电路，包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点并通过该内部信号输出点连接该信号放大电路部分，该信号放大电路部分包括：
第一放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第一放大电路节点和直流高电位；
第二放大电路薄膜晶体管，其栅极连接第N级内部信号输出点，源极和漏极分别连接第一放大电路节点和直流低电位；
第三放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第二放大电路节点和直流高电位；
第四放大电路薄膜晶体管，其栅极连接第二放大电路节点，源极和漏 极分别连接第N级外部信号输出点和直流高电位；
第五放大电路薄膜晶体管，其栅极连接第一放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流低电位；
放大电路自举电容，其两端分别连接第二放大电路节点和第N级外部信号输出点。
其中，所述GOA电路基于IGZO-TFT制造。
其中，所述GOA电路部分包括：
第一薄膜晶体管，其栅极连接第N－1级内部信号输出点，源极和漏极分别连接第一节点和第N－1级内部信号输出点；
第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接时钟信号和第N级内部信号输出点；
第三薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
第四薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第一节点和直流低电位；
第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电位；
第七薄膜晶体管，其栅极连接时钟信号，源极和漏极分别连接时钟信号和第二节点；
第八薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电位；
自举电容，其两端分别连接第一节点和第N级内部信号输出点。
其中，所述直流低电位为﹣5伏。
其中，所述直流高电位为28伏。
本发明还提供一种GOA电路，包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点并通过该内部信号输出点连接该信号放大电路部分，该信号放大电路部分包括：
第一放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第一放大电路节点和直流高电位；
第二放大电路薄膜晶体管，其栅极连接第N级内部信号输出点，源极和漏极分别连接第一放大电路节点和直流低电位；
第三放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第N级外部信号输出点和直流高电位；
第四放大电路薄膜晶体管，其栅极连接第一放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流低电位；
其中，所述GOA电路基于IGZO-TFT制造；
其中，所述GOA电路部分包括：
第一薄膜晶体管，其栅极连接第N－1级内部信号输出点，源极和漏极分别连接第一节点和第N－1级内部信号输出点；
第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接时钟信号和第N级内部信号输出点；
第三薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
第四薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第一节点和直流低电位；
第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电位；
第七薄膜晶体管，其栅极连接时钟信号，源极和漏极分别连接时钟信号和第二节点；
第八薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电位；
自举电容，其两端分别连接第一节点和第N级内部信号输出点；
其中，所述直流低电位为﹣5伏；
其中，所述直流高电位为28伏。
综上，本发明的GOA电路将电平位移的功能集成到GOA电路上，有利于降低驱动IC成本的同时，可以改善GOA栅极输出波形(波形的上升时间和波形的下降时间)和降低功耗。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有一种GOA电路的一级GOA电路单元示意图；
图2为图1所示GOA电路单元所需信号和重要节点的波形和电压的波形示意图；
图3为本发明GOA电路一较佳实施例的GOA电路单元示意图；
图4为本发明GOA电路又一较佳实施例的GOA电路单元示意图；
图5为图3和图4所示GOA电路单元所需信号和重要节点的波形和电压的波形示意图。
具体实施方式
参见图3，其为本发明GOA电路一较佳实施例的GOA电路单元示意图，包括了GOA电路和信号放大电路两部分，信号放大电路部分由四颗TFT(T1，T2，T3，T4)组成，该较佳实施例中的GOA电路部分仅用于举例，也可以采用其他适合的GOA电路形式。
图5为图3所示GOA电路单元所需信号和重要节点的波形和电压的波形示意图。STV,CK，XCK，VGH，VSS是系统端给的信号。其中，STV，CK，XCK的高低电位是5V和-5V，STV用于最初一级GOA单元的启动，当采用正反向扫描驱动方式时会分别用到此两个相位相反的时钟信号CK和XCK；VGH为直流高电位，是高压直流电，电位可以为28V，VSS为直流低电位，是低压直流电，电位可以为-5V，G(N-1)_in，G(N)_in，G(N+1)_in分别代表第N-1，N，N+1级GOA电路单元的GOA电路部分的内部的栅极(gate)的输出波形，该波形是没有经过信号放大的波形，即高低电位分别为5V和-5V。G(N)_out是指第N级GOA电路单元经信号放大电路部分向外输出的栅极输出波形，该波形是经过放大，正常驱动像素TFT栅极的波形，高低电位分别为28V，-5V。
如图3所示，该较佳实施例的GOA电路主要包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点G(N)_in并通过该内部信号输出点G(N)_in连接该信号放大电路部分，该信号放大电路部分包括：T1栅极连接直流高电位VGH，源极和漏极分别连接节点S(N)和直流高电位VGH；T2栅极连接第N级内部信号输出点G(N)_in，源极和漏极分别连接节点S(N)和直流低电位VSS；T3栅极连接直流高电位VGH，源极和漏极分别连接第N级外部信号输出点G(N)_out和直流高电位VGH；T4栅极连接节点S(N)，源极和漏极分别连接第N级外部信号输出点G(N)_out和直流低电位VSS。
该GOA电路部分包括：T11栅极连接第N－1级内部信号输出点G(N－1)_in，源极和漏极分别连接节点Q(N)和第N－1级内部信号输出点G(N －1)_in；T21栅极连接节点Q(N)，源极和漏极分别连接时钟信号CK和第N级内部信号输出点G(N)_in；T31栅极连接第N+1级内部信号输出点G(N+1)_in，源极和漏极分别连接第N级内部信号输出点G(N)_in和直流低电位VSS；T41栅极连接第N+1级内部信号输出点G(N+1)_in，源极和漏极分别连接节点Q(N)和直流低电位VSS；T32栅极连接节点P(N)，源极和漏极分别连接第N级内部信号输出点G(N)_in和直流低电位VSS；T42栅极连接节点P(N)，源极和漏极分别连接节点Q(N)和直流低电位VSS；T51栅极连接时钟信号CK，源极和漏极分别连接时钟信号CK和节点P(N)；T52栅极连接节点Q(N)，源极和漏极分别连接节点P(N)和直流低电位VSS；自举电容Cb两端分别连接节点Q(N)和第N级内部信号输出点G(N)_in。
本发明的GOA电路可以基于IGZO-TFT制造。本发明在IGZO-TFT的基础上，将电平移位单元集成到显示屏上，这样可以节省驱动IC(芯片)的成本。
下面结合图3和图5说明该较佳实施例的工作原理：
(1)当G(N)_in为-5V低电位时，T2关闭，由于T1，T3的栅极接VGH(28V),所以，T1，T3打开，S(N)的电位为28V，T4也打开，由于T3，T4的分压作用，G(N)_out输出VSS的低电位-5V。
(2)当G(N)_in为5V高电位时，T2,打开，由于T1的栅极接VGH(28V),所以，T1也T3打开，由于T1，T2的分压作用，S(N)的电位为-5V，所以T4关闭；G(N)_out输出VGH的高电位28V。
参见图4，其为本发明GOA电路又一较佳实施例的GOA电路单元示意图，包括了GOA电路和信号放大电路两部分，信号放大电路部分由5个TFT和一个自举电容Cb1组成，该较佳实施例中的GOA电路部分仅用于举例，采用了与图3中相同的形式，也可以采用其他适合的GOA电路形式。图5也为图4所示GOA电路单元所需信号和重要节点的波形和电压的波形示意图。
如图4所示，该较佳实施例的GOA电路主要包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点G(N)_in并通过该内部信号输出点G(N)_in连接该信号放大电路部分，该信号放大电路部分包括：T1栅极连接直流高电位VGH，源极和漏极分别连接节点S(N)和直流高电位VGH；T2栅极连接第N级内部信号输出点G(N)_in，源极和漏极分别连接节点S(N)和直流低电位VSS；T3栅极连接直流高电位VGH，源极和漏极分别连接节点T(N)和直流高电位VGH；T4栅极连接节点T(N)， 源极和漏极分别连接第N级外部信号输出点G(N)_out和直流高电位VGH；T5栅极连接节点S(N)，源极和漏极分别连接第N级外部信号输出点G(N)_out和直流低电位VSS；放大电路自举电容Cb1，其两端分别连接节点T(N)和第N级外部信号输出点G(N)_out。
该较佳实施例的电路有更稳定电压输出。下面结合图4和图5说明该较佳实施例的工作原理：
(1)当G(N)_in为-5V低电位时，T2关闭，由于T1，T3的栅极接VGH(28V)，所以，T1，T3打开，S(N)的电位为28V，T5也打开，T(N)的电位为28V，T4打开，由于T4，T5的分压作用，G(N)_out输出VSS的低电位-5V。
(2)当G(N)_in为5V高电位时，T2,打开，由于T1的栅极接VGH(28V),所以，T1也T3打开，由于T1，T2的分压作用，S(N)的电位为-5V，所以T5关闭；T(N)为28V，T4打开，G(N)_out输出VGH的高电位28V。
该过程G(N)_out的电位有原来的-5V变为28V，由于Cb1电容效应，T(N)电位会由28V上升的更高，这样，T3打开的更好，VGH的高电位更快更好的传递到G(N)_out，所以该电路有更好的栅极输出波形而且电路更加稳定。
本发明所提供的高集成度的栅极驱动电路设计可运用于LCD显示，也可运用于OLED显示。
综上，本发明的GOA电路在IGZO-TFT的基础上，将电平位移的功能集成到GOA电路上，有利于降低驱动IC成本的同时，可以改善GOA栅极输出波形(波形的上升时间和波形的下降时间)和降低功耗。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种GOA电路，包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点并通过该内部信号输出点连接该信号放大电路部分，该信号放大电路部分包括：
    第一放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第一放大电路节点和直流高电位；
    第二放大电路薄膜晶体管，其栅极连接第N级内部信号输出点，源极和漏极分别连接第一放大电路节点和直流低电位；
    第三放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第N级外部信号输出点和直流高电位；
    第四放大电路薄膜晶体管，其栅极连接第一放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流低电位。
  2. 如权利要求1所述的GOA电路，其中，所述GOA电路基于IGZO-TFT制造。
  3. 如权利要求1所述的GOA电路，其中，所述GOA电路部分包括：
    第一薄膜晶体管，其栅极连接第N－1级内部信号输出点，源极和漏极分别连接第一节点和第N－1级内部信号输出点；
    第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接时钟信号和第N级内部信号输出点；
    第三薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
    第四薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第一节点和直流低电位；
    第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
    第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电位；
    第七薄膜晶体管，其栅极连接时钟信号，源极和漏极分别连接时钟信号和第二节点；
    第八薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电位；
    自举电容，其两端分别连接第一节点和第N级内部信号输出点。
  4. 如权利要求1所述的GOA电路，其中，所述直流低电位为﹣5伏。
  5. 如权利要求1所述的GOA电路，其中，所述直流高电位为28伏。
  6. 一种GOA电路，包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点并通过该内部信号输出点连接该信号放大电路部分，该信号放大电路部分包括：
    第一放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第一放大电路节点和直流高电位；
    第二放大电路薄膜晶体管，其栅极连接第N级内部信号输出点，源极和漏极分别连接第一放大电路节点和直流低电位；
    第三放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第二放大电路节点和直流高电位；
    第四放大电路薄膜晶体管，其栅极连接第二放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流高电位；
    第五放大电路薄膜晶体管，其栅极连接第一放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流低电位；
    放大电路自举电容，其两端分别连接第二放大电路节点和第N级外部信号输出点。
  7. 如权利要求6所述的GOA电路，其中，所述GOA电路基于IGZO-TFT制造。
  8. 如权利要求6所述的GOA电路，其中，所述GOA电路部分包括：
    第一薄膜晶体管，其栅极连接第N－1级内部信号输出点，源极和漏极分别连接第一节点和第N－1级内部信号输出点；
    第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接时钟信号和第N级内部信号输出点；
    第三薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
    第四薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第一节点和直流低电位；
    第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
    第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电位；
    第七薄膜晶体管，其栅极连接时钟信号，源极和漏极分别连接时钟信号和第二节点；
    第八薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电位；
    自举电容，其两端分别连接第一节点和第N级内部信号输出点。
  9. 如权利要求6所述的GOA电路，其中，所述直流低电位为﹣5伏。
  10. 如权利要求6所述的GOA电路，其中，所述直流高电位为28伏。
  11. 一种GOA电路，包括级联的多个GOA电路单元，设N为自然数，第N级GOA电路单元包括GOA电路部分和信号放大电路部分，该GOA电路部分设有第N级内部信号输出点并通过该内部信号输出点连接该信号放大电路部分，该信号放大电路部分包括：
    第一放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第一放大电路节点和直流高电位；
    第二放大电路薄膜晶体管，其栅极连接第N级内部信号输出点，源极和漏极分别连接第一放大电路节点和直流低电位；
    第三放大电路薄膜晶体管，其栅极连接直流高电位，源极和漏极分别连接第N级外部信号输出点和直流高电位；
    第四放大电路薄膜晶体管，其栅极连接第一放大电路节点，源极和漏极分别连接第N级外部信号输出点和直流低电位；
    其中，所述GOA电路基于IGZO-TFT制造；
    其中，所述GOA电路部分包括：
    第一薄膜晶体管，其栅极连接第N－1级内部信号输出点，源极和漏极分别连接第一节点和第N－1级内部信号输出点；
    第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接时钟信号和第N级内部信号输出点；
    第三薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
    第四薄膜晶体管，其栅极连接第N+1级内部信号输出点，源极和漏极分别连接第一节点和直流低电位；
    第五薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第N级内部信号输出点和直流低电位；
    第六薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第一节点和直流低电位；
    第七薄膜晶体管，其栅极连接时钟信号，源极和漏极分别连接时钟信 号和第二节点；
    第八薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和直流低电位；
    自举电容，其两端分别连接第一节点和第N级内部信号输出点；
    其中，所述直流低电位为﹣5伏；
    其中，所述直流高电位为28伏。
PCT/CN2017/116271 2017-10-25 2017-12-14 Goa电路 Ceased WO2019080304A1 (zh)

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