WO2019066987A1 - Empilement de matériaux multiples à tolérance de dimensions - Google Patents

Empilement de matériaux multiples à tolérance de dimensions Download PDF

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Publication number
WO2019066987A1
WO2019066987A1 PCT/US2017/054671 US2017054671W WO2019066987A1 WO 2019066987 A1 WO2019066987 A1 WO 2019066987A1 US 2017054671 W US2017054671 W US 2017054671W WO 2019066987 A1 WO2019066987 A1 WO 2019066987A1
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WIPO (PCT)
Prior art keywords
dies
die
encapsulation layer
interconnects
layer
Prior art date
Application number
PCT/US2017/054671
Other languages
English (en)
Inventor
Javier A. FALCON
Shawna M. LIFF
Preston T. Myers
Albert S. LOPEZ
Joe R. SAUCEDO
Adel A. ELSHERBINI
Johanna M. Swan
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/054671 priority Critical patent/WO2019066987A1/fr
Publication of WO2019066987A1 publication Critical patent/WO2019066987A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • Embodiments relate to semiconductor devices. More particularly, the embodiments relate to packaging small form factor (SFF) systems using a printed circuit board (PCB) in
  • the PCB may include plated pillars, multi-encapsulation layers, and double-sided interconnects.
  • the communication, processing, and sensing functions are implemented with low power systems that allow the use of small batteries (e.g. , thin film batteries) and small energy harvesting devices (e.g., solar and vibration).
  • small batteries e.g. , thin film batteries
  • small energy harvesting devices e.g., solar and vibration
  • the SFF systems are typically limited to silicon components (i.e., with few or no discrete devices such as capacitors or inductors) to minimize the overall volume of the systems. Additional, some systems use wirebonding or vertical stacking using through silicon vias (TSVs) to further minimize the overall volume.
  • TSVs through silicon vias
  • the connected components (or dies) are then overmolded or coated to protect the system from the environment.
  • Ultra SFF systems present several problems.
  • One major problem involved with packaging these SFF systems is debugging, programming, and testing the components due to their small size.
  • the SFF systems may add additional test pads for testing and programming purposes but this significantly increases their overall volume (e.g. , adding 10 test pads to a 1mm 3 system results in a volume increase of roughly 50%).
  • Adding test pads to the SFF systems also leads to other problems when the pads need to be sealed from the environment which may prevent their use in many applications (e.g., in applications where moisture may cause shorts from the test pads, or where the test pads may not be biocompatible for body implantation).
  • the energy harvester starts charging the battery as soon as it is connected to the battery. This requires the use of shorting wires or open wires on the energy harvester during the different assembly steps to avoid partially charging the battery and reducing its shelf life or performance after the high temperature assembly steps. The wires on the energy harvester are then broken or shorted after the manufacturing is completed. Due to the SFF of the system, the process of cutting or connecting the wires is extremely challenging and needs to be manually performed under a microscope or magnifying glass. Furthermore, techniques to deal with these issues and other challenges requires smart strategies to enable batch processes with multi-product configuration flexibility.
  • Figure 1 A is a cross-sectional view of a semiconductor package having one or more dies, one or more interconnects, and an encapsulation layer, according to one embodiment.
  • Figure IB is a cross-sectional view of a semiconductor package having one or more dies, one or more interconnects, an encapsulation layer, and a PCB with one or more pads, according to one embodiment.
  • Figure 1C is a cross-sectional view of a semiconductor package having one or more dies, one or more interconnects with through silicon vias (TSVs), and an encapsulation layer, according to one embodiment.
  • TSVs through silicon vias
  • Figure ID is a cross-sectional view of a semiconductor package having one or more dies, one or more interconnects with through mold vias (TMVs), and an encapsulation layer, according to one embodiment.
  • TSVs through mold vias
  • Figures 2A-2E are cross-sectional views of a process flow used to form a semiconductor package having one or more dies, one or more interconnects, an encapsulation layer, and a PCB with one or more pads, according to some embodiments.
  • Figures 3A-3H are cross-sectional views of a process flow used to form a semiconductor package having one or more dies, one or more interconnects, one or more encapsulation layers, and a PCB with one or more pads, according to some embodiments.
  • Figure 4 is a cross-sectional view of a semiconductor package having one or more dies suspended in a cavity of a PCB, according to one embodiment.
  • Figures 5 is a cross-sectional view of a semiconductor package having one or more dies embedded within a PCB that has a multi-level cavity, according to one embodiment.
  • Figures 6 is a cross-sectional view of a semiconductor package having one or more dies embedded on a PCB with a cavity, according to one embodiment.
  • Figure 7 is a cross-sectional view of a semiconductor package having one or more dies disposed on a first cavity of a PCB and a die disposed on a second cavity of the PCB, according to one embodiment.
  • Figure 8 is a top, perspective view of a PCB with a plurality of cavities that include a plurality of semiconductor packages, according to one embodiment.
  • Figure 9 is a top, perspective view of a PCB with one or more channels and a plurality of cavities that have a plurality of semiconductor packages, according to one embodiment.
  • Figure 10 is a process flow illustrating a method of forming a semiconductor package having a plurality of dies, one or more interconnects, and an encapsulation layer, according to one embodiment.
  • Figure 11 is a process flow illustrating a method of forming a semiconductor package having a plurality of dies, one or more interconnects, an encapsulation layer, and a substrate with one or more pads, according to one embodiment.
  • Figure 12 is a process flow illustrating a method of forming a package layer having a plurality of cavities, a plurality of device packages, and a plurality of interconnects, according to one embodiment.
  • Figures 13-14 are cross-sectional views of semiconductor packages having one or more dies, one or more interconnects, a PCB with a cavity, according to one embodiment.
  • Figures 15-16 are cross-sectional views of semiconductor packages having one or more dies, one or more interconnects, one or more encapsulation layers, and a PCB with a cavity, according to one embodiment.
  • Figures 17A-17E are cross-sectional views of a process flow used to form a
  • semiconductor package having one or more dies, one or more interconnects, and a PCB with a cavity, according to some embodiments.
  • Figures 18A-18D are cross-sectional views of a process flow used to form a
  • semiconductor package having one or more dies, one or more interconnects, one or more encapsulation layers, and a PCB with a cavity, according to some embodiments.
  • Figure 19 is a process flow illustrating a method of forming a semiconductor package having one or more dies, one or more interconnects, and a PCB with a cavity, according to one embodiment.
  • Figures 20A-20B are plan views of a process flow used to form a package layer having a plurality of device packages, a plurality of interconnects, and one or more encapsulation layers that are stacked, according to one embodiment.
  • Figures 20C-20H are corresponding plan and cross-sectional views of a process flow used to form a package layer having a plurality of device packages, a plurality of interconnects, and one or more encapsulation layers that are stacked, according to one embodiment.
  • Figure 21 is a process flow illustrating a method of forming a package layer having a plurality of device packages, a plurality of interconnects, and one or more encapsulation layers that are stacked, according to one embodiment.
  • Figures 22 is a cross-sectional view of a semiconductor package having one or more substrates, one or more interconnects, and one or more pillars, according to one embodiment.
  • Figure 23 is a process flow illustrating a method of forming a semiconductor package having one or more substrates, one or more interconnects, and one or more pillars, according to one embodiment.
  • Figures 24-27 are cross-sectional views of semiconductor packages having one or more substrates, one or more interconnects, and one or more pillars, according to some embodiments.
  • Figure 28 is a schematic block diagram illustrating a computer system that utilizes a semiconductor package, according to one embodiment.
  • Described herein are systems that include a semiconductor package and methods of forming such semiconductor packages. Specifically, ultra-small form factor systems are described below and methods of forming such ultra-small form factor systems using a printed circuit board (PCB) in combination with a sacrificial or permanent molding/encapsulation base. Note that these disclosed embodiments are not limited in application to ultra-small form factor systems. Additionally, according to some embodiments, a PCB embedded stack is described herein having plated pillars, multi-encapsulation layers, and/or double-sided interconnects. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.
  • an ultra-small form factor system includes one or more dies that are vertically stacked to minimize the overall volume of the system.
  • the one or more dies are stacked or disposed within or adjacent to the PCB (also referred to as a package or a substrate), where the PCB includes one or more exposed pads.
  • the PCB also referred to as a package or a substrate
  • the PCB includes one or more exposed pads.
  • vertically stacking the dies with wire bonds or through silicon vias (TSVs) and then adding one or more encapsulation layers over the dies and wire bonds/TSVs yields the ultra-small form factor.
  • the present embodiments enable automated testing during various manufacturing steps by using the exposed pads of the PCB.
  • the present embodiments help to facilitate the extraction of one or more semiconductor packages (also referred to as device packages) within the PCB using a cutting process, which provides individual packages for customers needing ultra-small form factor devices without the PCB.
  • the present embodiments also help to facilitate the extraction of additional semiconductor packages within the PCB using the cutting process, which provides individual packages for customers needing ultra-small form factor devices with the exposed pads of the PCB for debugging, testing, and/or programming.
  • the present embodiments further enhance packaging solutions for ultra-small form factors by embedding a PCB adjacent to the stacked dies before overmolding. This allows testing of the dies (or devices/components) at different assembly steps using exposed pads of the PCB - before and after overmolding.
  • the semiconductor packages can be tested and/or programmed during an intermediate testing step of the overall assembly process, as the PCB is used as an encapsulation dam (or overmolding dam) between different types of molds.
  • the present embodiments also provide an automated and precise sawing/cutting process that allows shorting wires of an energy harvester to be cut at the last assembly step.
  • the present embodiments enable device packages to be embedded in (or adjacent to) a PCB with pads and, therefore, provide automated testing of the device packages during different manufacturing steps - without increasing volume, cost, and total number of manufacturing steps.
  • the semiconductor package 100 has an encapsulation layer 102 and a plurality of dies 105-108 that are connected using one or more interconnects 103.
  • the semiconductor package 100 may have an ultra-small form factor that is implemented for wearables, temperature monitoring, imaging and motion detection, implantable medical monitoring, ingestibles, security, search and rescue, environmental monitoring, Internet of Things (IoTs), chemical and biological military sensors, smart devices (e.g., smart dust, mote, etc.), etc., and/or any system in package (SIP) having an ultra-small form factor.
  • IoTs Internet of Things
  • smart devices e.g., smart dust, mote, etc.
  • SIP system in package
  • an “ultra-small form factor” system may refer to a semiconductor (or device) package that has a total volume in the order of roughly several cubic millimeter ( ⁇ mm 3 ) or less (e.g., somewhere in the 1-100 mm3 depending on the functions).
  • the “ultra-small form factor” system refers to a low-power device with one or more miniaturized systems that integrate sensors, data processing, energy harvesting, energy storage and/or wireless data transmission.
  • an "ultra-small form factor" system may include a semiconductor package that utilizes at least one of (i) a power system with near threshold voltage (NTV) devices, solar cells, and thin film batteries; (ii) a packaging system with integrated antennas, all- silicon design, and minimal packaging assembly (i.e. , wire bonding, integrated antennas, and/or encapsulation); (iii) a modular system with multiple dies (or chips) having a common bus; and/or (iv) a PCB with one or more pads for improved electrical functionality and testing (as shown in further detail below in Figure IB).
  • NTV near threshold voltage
  • a packaging system with integrated antennas, all- silicon design, and minimal packaging assembly i.e. , wire bonding, integrated antennas, and/or encapsulation
  • a modular system with multiple dies (or chips) having a common bus and/or (iv) a PCB with one or more pads for improved electrical functionality and testing (as shown in further detail below in Figure IB).
  • the semiconductor package 100 may be formed adjacent to a substrate, a package, and a PCB (as shown in Figure IB), according to several embodiments.
  • the system may be a stand-alone device or a system in package (SiP) as part of a larger device.
  • the dies 105-108 are disposed (or assembled) on top of one another to form a stack (e.g., a vertical stack).
  • the dies 105-108 may be disposed on a rigid
  • each die 105-108 has a top surface 110 and a bottom surface 111 that is opposite from the top surface 110.
  • Each die 105-108 also has one or more die contacts 120-121 that are located on the top surface 110 of each die 105-108 (or on both sides of the dies for the case of stacking using TSVs).
  • the die contacts 120-121 are each electrically coupled to at least one other die contact of another die with one or more interconnects 103 (e.g., wire bonds, TSV, TMVs, flip-chip, 3D printing, inkjet, and anisotropic conductive film (ACF)).
  • interconnects 103 e.g., wire bonds, TSV, TMVs, flip-chip, 3D printing, inkjet, and anisotropic conductive film (ACF)
  • die 105 has two die contacts 120-121, die contact 120 of die 105 is electrically coupled to die contact 121 of die 106, and die contact 121 of die 105 is electrically coupled to a surface 104 of an encapsulation layer 102.
  • the encapsulation layer 102 (or an encapsulation layer) is disposed over and around the dies 105-108 and the one or more interconnects 103 and 113. As described herein, disposing/forming an encapsulation layer over the dies and interconnects may also be referred to as overmolding.
  • a semiconductor package may have two or more encapsulation layers (as shown in Figures 3A-H), where the encapsulation layers may include different type of materials for each encapsulation layer (e.g. , an opaque material for a first encapsulation layer and a transparent material for a second encapsulation layer).
  • the semiconductor package 100 has an interconnect 113 and an outer enclosure 101 formed from the encapsulation layer 102.
  • the interconnect 113 has a first end 113a and a second end 113b that is opposite from the first end 113a.
  • the first end 113a is connected to die contact 121 of die 105 and the second end 113b extends through the encapsulation layer 102 to the surface 104 of the encapsulation layer 102.
  • a semiconductor package can have one or more interconnects that connect to the surface of the encapsulation layer based on implementation and customer requirements.
  • Each of the one or more dies 105-108 may include, but is not limited to, a semiconductor die, an integrated circuit, a CPU, and a microprocessor.
  • the dies 105- 108 are formed of semiconductor components/devices (i.e., no discrete devices such as capacitors or inductors) to minimize the overall volume of the package (e.g., dies with thickness of approximately 50-150 ⁇ or less).
  • semiconductor components/devices i.e., no discrete devices such as capacitors or inductors
  • the overall volume of the package e.g., dies with thickness of approximately 50-150 ⁇ or less.
  • the dies in the stack have to be active semiconductor components/devices (i.e. , some dies or layers may be organic substrates, exclusively passive devices (e.g. , decoupling capacitors/power delivery inductors, antennas), micro-electromechanical systems (MEMS), or other types of components and/or sensors).
  • MEMS micro-electro
  • the dies 105-108 may further include, but are not limited to, a sensor (e.g., a temperature sensor, a pressure sensor, a motion detection/imaging sensor, etc.), a communication device (or chip), a radio, a battery, a decoupling capacitor, a battery control, a power stabilizer, a memory, an energy harvester (e.g., a solar cell, a photovoltaic (PV) cell), etc., and/or any combination thereof.
  • the semiconductor package 100 may have any possible variations of dies that are stacked.
  • the energy harvesting can be implemented using one or more dies (or devices), there can be more than one sensor (e.g. , light sensor, pressure sensor, temperature sensor, humidity sensor, temperature & humidity sensor, medical sensor, etc.), and there can be an additional energy management die(s).
  • die 105 may be a sensor
  • die 106 may be a microprocessor (or a processing device)
  • die 107 may be a battery (e.g. , a thin-film lithium (Li) battery)
  • die 108 may be an energy harvester.
  • the total number of dies for each package is not limited to a specific number of dies (i.e. , a package can have Nth number of dies based on a design or customer requirements).
  • a plurality of dies may be vertically stacked to minimize the overall volume and z-height, but the plurality of dies may also be arranged in any specified orientation to have any other desired configuration (e.g. , as shown in Figures 4 and 7).
  • a die may be directly disposed on another die with an adhesive layer (e.g. , a bond film, a one/double sided tape, an attach film, an electrically conductive attach film, an epoxy film, etc.), or with solder interconnects for TSV dies, on the bottom surface of the die to be placed/disposed on the other die.
  • an adhesive layer e.g. , a bond film, a one/double sided tape, an attach film, an electrically conductive attach film, an epoxy film, etc.
  • solder interconnects for TSV dies solder interconnects for TSV dies
  • each of the dies 105-108 may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium nitride, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.
  • germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium nitride, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials are described herein, any material that may serve as a foundation upon which a semiconductor device may be built falls within the scope of the present embodiments.
  • One or more dies may also be built on a non-semiconducting substrate (e.g., quartz, glass or ceramic) to provide passive functionality such as
  • each of the dies 105-108 has one or more die contacts 120-121 that are each electrically coupled to at least one other die contact 120-121 of another die 105-108 using one or more interconnects 103 (e.g. , wire bonds, TSV, TMVs, flip-chip, 3D printing, inkjet, and ACF).
  • each of the dies 105-108 is a wire-bonded semiconductor die. Additional embodiments may include dies 105-108 that are electrically coupled/interconnected with a TSV, a through mold interconnect (TMI), a flip-chip interconnect using plated pillars/TMIs, or any combination thereof.
  • each of the dies 105-108 may be a flip-chip semiconductor die.
  • Interconnects 103 electrically couple die contacts 120-121 of one die 105-108 to another die 105-108.
  • interconnects 103 and 113 are wire bonds.
  • the wire bonding structure of the semiconductor package 100 as shown in Figure 1 A may be substantially similar to those presently known in the art.
  • interconnects 103 and 113 may be wires that are ball-stitch bonded or wedge bonded from one die 105-108 to another die 105-108, one die 105-108 to a surface 104 on an encapsulation layer 102.
  • interconnects 103 and 113 may be any commonly used conductive material, such as copper, silver, gold, or alloys thereof. While wire-bonded semiconductor dies are illustrated in Figure 1A, it is to be appreciated that the semiconductor dies are not limited to wire-bonding, and other interconnect structures, such as flip-chip, 3D printing, inkjet, and anisotropic conductive film (ACF), are also within the scope of embodiments.
  • wire-bonded semiconductor dies are illustrated in Figure 1A, it is to be appreciated that the semiconductor dies are not limited to wire-bonding, and other interconnect structures, such as flip-chip, 3D printing, inkjet, and anisotropic conductive film (ACF), are also within the scope of embodiments.
  • ACF anisotropic conductive film
  • the die contacts 120-121 may include a conductive stack of materials, such as, but not limited to adhesion promoters, seed layers, copper, silver, gold, or alloys thereof, and oxidation inhibitors.
  • Each of the die contacts 120-121 is electrically coupled to another die contact 120-121 by an interconnect 103 (also referred to as an interconnect line).
  • the interconnects 103 are formed in a cascading pattern in order to allow for the interconnects to have flexibility, particularly in flexibility to change interconnect locations and avoid bending and damage.
  • an encapsulation layer 102 is deposited over and around the dies 105-108 and interconnects 103 and 113 to protect the semiconductor package 100 from the environment.
  • the encapsulation layer 102 is then cured.
  • Encapsulation layer 102 helps to protect and cover dies 105-108 from humidity, photons, corrosion and damage.
  • a semiconductor package e.g. , semiconductor package 100
  • the encapsulation layer 102 is made of an epoxy (e.g., a soft epoxy, a stiff epoxy, opaque epoxy, etc.) with one or more filler materials.
  • the one or more materials for the encapsulation layer 102 include, but are not limited to, ultra-compliant materials for pressure sensors, visible light, ultraviolet (UV) and infrared (IR) absorbing/reflective materials to block photons from the dies, stiff polymers to encapsulate the interconnects, and/or transparent materials on an energy harvest (e.g. , a solar cell).
  • the one or more multi-layered materials may also include visible light, UV and/or IR blocking agents or metals (e.g.
  • the encapsulation layer 102 may be formed with one or more encapsulant materials that are dispensed onto the package (e.g. , semiconductor package 100), rather than using injection, compression, or transfer mold processes.
  • the encapsulation layer 102 may form an outer enclosure 101 with a surface 104 that is coupled to an interconnect 113.
  • the interconnect 113 extends through the encapsulation layer 102 as the first end 113 is coupled to die contact 121 of die 105 and the second end 113b is exposed on surface 104 of the outer enclosure 101 of the encapsulation layer 102 (i.e., a surface of the second end of the interconnect is coplanar with the surface 104 of the encapsulation layer 102).
  • the second end 113b of the interconnect 113 is exposed on the surface 104 after the semiconductor package 100 is singulated along a saw fiducial (not shown).
  • interconnect 113 can be cut at the last assembly step during sawing in an automated and precise manner, which then provides individual packages to customers needing ultra-small form factor devices.
  • the surface 104 of the encapsulation layer 102 may be recessed to expose the second end 113b of the interconnect 113.
  • the encapsulation layer 102 may be recessed with an encapsulation grinding/polishing (also referred to as mold
  • the surface 104 may also have a coating (not shown) that electrically isolates the interconnect end 113b from the external environment.
  • the surface 122 of the encapsulation layer 102 may be recessed to disconnect the terminal 103b of the interconnect 103b.
  • the encapsulation layer 102 may be recessed with an encapsulation grinding/polishing to provide a flat, polished surface for interconnect end 103b.
  • the surface 122 may also have a coating (not shown) that electrically isolates the interconnect end 103b from the external environment.
  • the encapsulation layer 102 may have any arbitrary shape or texture to enable the desired packaging design or application, including hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.
  • the encapsulation layer 102 may have any arbitrary shape or texture to enable the desired packaging design or application, including hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.
  • the encapsulation layer 102 may have any arbitrary shape or texture to enable the desired packaging design or application, including hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.
  • the encapsulation layer 102 may have any arbitrary shape or texture to enable the desired packaging design or application, including hemispherical shape,
  • 102 may also serve one or more additional purposes, such as bio-compatible and/or hermetic sealing.
  • the semiconductor package 100 may include fewer or additional packaging components based on the desired packaging design.
  • Figure IB illustrates a cross-sectional view of a semiconductor package 150 having an encapsulation layer 102, a plurality of dies 105-108 connected with one or more interconnects
  • semiconductor package 150 of Figure IB is similar to semiconductor package 100 of Figure 1A, except that the
  • semiconductor package 150 includes the PCB 160 with the one or more pads 161 to provide improved electrical functionality and testing.
  • the one or more PCB pads 161 allow customers to debug, test, program, and/or develop the semiconductor package 150 using standard probe technology.
  • the semiconductor package 150 has the dies 105-108 disposed on top of one another to form a stack.
  • each die 105-108 has a top surface 110 and a bottom surface 111 that is opposite from the top surface 110.
  • Each die 105- 108 also has one or more die contacts 120-121 that are located on the top surface 110 of each die 105-108.
  • the die contacts 120-121 are each electrically coupled to at least one other die contact of another die with one or more interconnects 103.
  • the dies 105-108 are stacked and disposed adjacent to the PCB 160 (or substrate/package).
  • a PCB may refer to a base PCB that may be one or more smaller PCB(s) that are placed adjacent to or under the system components (e.g., the dies), as shown in Figures 1-7.
  • a "PCB” may also refer to an
  • the encapsulation PCB may be a large PCB with one or more cavities (and one or more encapsulation channels), where the system components and one or more encapsulation layers may be disposed into the one or more cavities.
  • the encapsulation PCB (as shown in Figures 8-9) may be used at the packaging-level (or panel-level) to assemble a plurality of semiconductor packages, where the semiconductor packages may be singulated into individual units with or without the PCB.
  • the units may be of the same configuration and shape or of multiple unique shapes and configurations.
  • the dies 105-108 may be placed adjacent to the PCB 160.
  • each of the dies 105-108 may be disposed in a cavity or a cut-out (not shown) of the PCB 160 (e.g. , as shown in Figures 8-9), suspended within the cavity of the PCB 160 (e.g., as shown in Figure 4), embedded in the PCB 160 (e.g. , as shown in Figure 5 illustrating a PCB with multilevel cavities), and embedded and on the PCB 160 (e.g. , as shown in Figure 6).
  • dies 106-108 may be disposed on a top cavity (not shown) of the PCB 160
  • die 105 e.g., a sensitive pressure sensor or a MEMS device
  • die 105 may be disposed on a bottom cavity (not shown) of the PCB 160 that is connected to the top cavity with solder bumps and one or more vias (e.g., as shown in Figure 7).
  • the PCB 160 has a first set of pads 162 on a top surface 160a and a second set of pads 161 on a bottom surface 160b.
  • the encapsulation layer 102 is deposited over and around the dies 105-108, the interconnects 103 and 113, and the first set of pads 162 of the PCB 160, as the second set of pads 161 on the bottom surface 160b are exposed.
  • the encapsulation layer 102 is then cured.
  • the exposed second set of pads 161 on the bottom surface 160b of the PCB 160 can be used for debugging, testing, programing, and/or developing the dies 105-108 of the semiconductor package 150.
  • a first end 113a of interconnect 113 is electrically coupled to one of the die contacts 121 of die 105, and a second end 113b of interconnect 113 extends through the encapsulation layer 102 and is electrically coupled to at least one pad of the first set of pads 162 of the PCB 160.
  • a semiconductor package e.g. , semiconductor package 150
  • the PCB 160 is made of an FR-4 glass epoxy base with thin copper foil laminated on both sides (not shown).
  • a multilayer PCB can be used, with pre-preg and copper foil (not shown) used to make additional layers.
  • the multilayer PCB may include one or more dielectric layers, where each dielectric layer can be a photosensitive dielectric layer (not shown).
  • the surface 122 of the encapsulation layer 102 may be recessed to disconnect the terminal 103b of the interconnect 103b.
  • the encapsulation layer 102 may be recessed with an encapsulation grinding/polishing to provide a flat, polished surface for interconnect end 103b.
  • the surface 122 may also have a coating (not shown) that electrically isolates the interconnect end 103b from the external environment.
  • a plurality of cavities may be formed in the PCB 160 (e.g., as shown in Figures 8-9).
  • the PCB 160 may also include conductive copper traces, vias, metallic pads, and holes (not shown).
  • Figures 1C and ID illustrates cross-sectional views of a semiconductor package 170 having TSV stacked dies and a semiconductor package 180 having the stacked dies with through mold vias (TMVs), accordingly. Note that Figures 1C and ID show other embodiments that may be used as a vertical interconnect for the stacked dies. For some embodiments, the
  • semiconductor packages 170 and 180 of Figures 1C and ID are similar to semiconductor packages 100 and 150 of Figures 1A and IB, except that theses semiconductor package 170 and 180 implement alternative interconnects, such as TSVs and TMVs respectively, to interconnect the stacked dies rather than using wire bond interconnects. Also note that each interconnect (e.g. , wire bond, TSV, TMV, etc.) may have advantages based on the desired design of the semiconductor package.
  • the semiconductor package 170 has dies 105-108 electrically coupled with a plurality of TSVs 175 and a plurality of solder bumps 171.
  • the semiconductor package 170 has an enclosure 151 formed with an
  • the semiconductor package 170 may use the TSV interconnects 175 to stack the dies 105-108 directly above each other.
  • a plurality of TSVs 175 may be formed in die 105, where a bottom surface 111 of die 105 may be exposed.
  • a plurality of solder bumps 171 may be disposed on the plurality of TSVs 175 to attach and electrically couple to a plurality of TSVs 175 formed in die 106.
  • the same process is used to dispose the remaining dies 107-108 until the stack is completed.
  • the semiconductor package 180 has dies 105-108 electrically coupled with a plurality of TSVs 175, a plurality of TMVs 185, and a plurality of solder bumps 171.
  • the semiconductor package 180 has an enclosure 151 formed with an encapsulation layer (as shown in Figures 1 A and IB) that may be above a top surface 110 of die 108.
  • the semiconductor package 180 may use the TMVs interconnects 185 and TSV interconnects 175 to stack the dies 105-108 directly above each other.
  • a plurality of TSVs 175 may be formed in die 105, where a bottom surface 111 of die 105 may be exposed.
  • a plurality of solder bumps 171 may be disposed on the plurality of TSVs 175 to attach and electrically couple to a plurality of TSVs 175 formed in die 106. Then, a plurality of solder bumps 171 may be disposed on the plurality of TSVs 175 to attach and electrically couple an encapsulation layer 132 with an embedded die 107 and a plurality of TMVs 185. That is, the TMV interconnects 185 are disposed in between dies 108 and 106 using the plurality of solder bumps 171, as embedded die 107 is electrically coupled to die 108 with solder bumps 171.
  • PCB embedded stack e.g., as shown in Figures 1-9
  • PCB embedded stack provides various advantages, especially advantages over testing individual components then wireless programming/testing of the overall system.
  • semiconductor packages may be programmed simultaneously, and the packages may then be verified (or tested) for correct programing during the assembly process to significantly reduce the overall time of the verification process (e.g. , an alternative verification process can be completed after the assembly process using wireless programming on a standard encapsulation strip size ( ⁇ 240 x 74-95 mm) that can have up to a few thousand devices, and therefore the verification process can take an extremely long time due to probe collisions between packets coming from the thousands of different devices.); (ii) one or more semiconductor packages may be tested intermediately to reduce an overall yield loss of packages (e.g.
  • wireless programming requires that the packages (or dies) be completely assembled, which prevents intermediate testing and can result in a high yield loss due to assembling top dies on non-working bottom dies.); and (iii) one or more semiconductor packages may be tested without using additional components to wirelessly transmit to test device (e.g. , analog-to-digital converters (ADCs)) and connections between the dies, thereby reducing overall costs and volume (e.g., analog signals typically need to be tested (eye diagrams, voltage levels, current levels, etc.) and sending such signals wirelessly requires additional components and connections between the dies - increasing the overall volume of the systems and costs for signals that may only be used for testing.).
  • test device e.g. , analog-to-digital converters (ADCs)
  • ADCs analog-to-digital converters
  • semiconductor package 150 may include fewer or additional packaging components based on the desired packaging design.
  • Figures 2A-E are cross-sectional views of a process flow 200 used to form a semiconductor package (e.g., semiconductor packages 250-251 of Figures 2D-E) with an encapsulation layer (e.g., encapsulation layer 202 of Figure 2B).
  • a semiconductor package e.g., semiconductor packages 250-251 of Figures 2D-E
  • an encapsulation layer e.g., encapsulation layer 202 of Figure 2B
  • the process flow 200 for forming a semiconductor package without and with a PCB e.g. , semiconductor packages 250-251 of Figures 2D-E, respectively
  • Figures 2A-E is illustrated in Figures 2A-E.
  • FIGS 2A-E may be used to form a semiconductor package without a PCB similar to the device illustrated in Figure 1 A, a semiconductor package with a PCB similar to the device illustrated in Figure IB, a semiconductor package with two or more encapsulation layers either similar to the device illustrated in Figure 3F or Figure 3H, or a plurality of semiconductor packages stacked and embedded in a plurality of cavities of a PCB similar to devices illustrates in Figures 8-9.
  • the package layer may include a plurality of dies 205-208 and a PCB 260 disposed over a carrier 210.
  • the dies 205-208 and the PCB 260 of Figures 2A-E are similar to the dies 105-108 and the PCB 160 of Figure IB.
  • the carrier 210 may be a glass carrier or a rigid carrier, which can be made from stainless steel or ceramic or even copper clad core.
  • the plurality of dies 205-208 are disposed on the carrier 210 and adjacent to the PCB 260.
  • the dies 205-208 are stacked or assembled adjacent to or within a cavity (not shown) of the PCB 260 before overmolding (as shown in Figure 2B).
  • each of the dies 205-208 is each electrically coupled to at least one other die using one or more interconnects 203 and 213.
  • the interconnect 213 may be electrically coupled to at least one pad of the PCB 260.
  • the package layer shows the dies 205-208 stacked adjacently to the PCB 260, but the package layer may have the dies 205-208 disposed on the PCB 260 in one or more
  • connection 213 is between the bottom die and the PCB but in actual applications different dies may be connected to the PCB not necessarily a single die.
  • an encapsulation layer 202 may be deposited (or formed) over and around the die 205-208 and the interconnects 203 and 213.
  • the encapsulation layer 202 may then be cured and thus forms the enclosure 201 to surround and protect the package layer.
  • the encapsulation layer 202 is made of an epoxy (e.g. , a soft epoxy, a stiff, opaque epoxy, etc.) with one or more filler materials.
  • the package layer may include more than two or more encapsulant layers with different materials (e.g., as shown in Figures 3A-H) or two layers (or rounds) of the same encapsulation layer.
  • some of the dies may be initially stacked (e.g., dies 205-206 are first stacked on the carrier 210) and then a first layer (not shown) of encapsulation layer 202 may be deposited over and around these initially stacked dies.
  • the remaining other dies are subsequently stacked (e.g. , dies 207-208 are subsequently stacked on the carrier 210) and then a second layer (not shown) of the encapsulation layer 202 may also be deposited over and around these remaining stacked dies.
  • the enclosure 201 formed with the encapsulation layer 202 may have any desired shape.
  • the enclosure 201 may have a rounded shaped or rounded angles (e.g., a hill-shaped enclosure with a plateaued top surface) or any designed shape (e.g., hemispherical shape, capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.).
  • a compression plunger may be used to flatten a top surface of the enclosure 201 if needed.
  • the carrier 210 is removed from the package layer.
  • the package layer now has one or more exposed pads 261 on the bottom surface of the PCB 260.
  • the one or more pads 261 of the PCB 260 allow for the dies 205-208 to be tested, debugged, verified, and/or programmed (e.g. , to verify that each of the interconnects was not damaged and the dies are correctly programmed).
  • the package layer is singulated to provide one or more semiconductor packages 250-251.
  • each of the packages 250-251 may be diced along a plurality of fiducial lines to extract each of the packages 250-251 from the package layer.
  • Figure 2D illustrates one or more semiconductor packages 250 that are singulated without the PCB 260.
  • the semiconductor packages 250 have one or more surfaces 204 that may also have a coating (not shown) that electrically isolates the interconnect ends 213 from the external environment. These packages 250 may be used as units for customers needing ultra-small form factor devices.
  • Figure 2E illustrates the semiconductor package 251 that includes the PCB 260 with the one or more pads 261. This package 251 may be used as unit(s) for customers needing debugging, additional programming/testing, and/or developmental devices.
  • While the illustrated process flow in Figures 2A-E produces a semiconductor package 250 with an interconnect 213 extending to a surface 204 of an encapsulation layer 202 (without including a PCB with one or more pads) and a semiconductor package 251 with an interconnect 213 electrically coupling a plurality of dies 205-208 to a PCB 260 with one or more pads 261 that are formed in a single package layer, embodiments are not limited to such configurations.
  • the package layer illustrated in the process flow of Figures 2A-E may be used to exclusively produce either a first plurality of semiconductor packages with a PCB or a second plurality of semiconductor packages without a PCB based on design (or customer) requirements.
  • a semiconductor package with a PCB may also be formed with two or more encapsulation layers to allow intermediate testing of a plurality of dies.
  • a process flow for forming such a semiconductor package is described in detail with respect to Figures 3A-H.
  • semiconductor packages 250-251 may include fewer or additional packaging components based on the desired packaging design.
  • Figures 3A-H are cross-sectional views of a process flow 300 used to form a semiconductor package (e.g., semiconductor packages 350-351 of Figures 3G-H) with two encapsulation layers (e.g. , encapsulation layer 312 of Figure 3B and encapsulation layer 302 of Figure 3E).
  • a semiconductor package e.g., semiconductor packages 350-351 of Figures 3G-H
  • two encapsulation layers e.g. , encapsulation layer 312 of Figure 3B and encapsulation layer 302 of Figure 3E.
  • the process flow 300 for forming a semiconductor package without and with a PCB e.g. , semiconductor packages 350-351 of Figures 3G-H, respectively
  • Figures 3A-H is illustrated in Figures 3A-H.
  • FIG. 3A-H may be used to form a semiconductor package without a PCB similar to the device illustrated in Figure 1A, a semiconductor package with a PCB similar to the device illustrated in Figure IB, or a plurality of semiconductor packages stacked and embedded in a plurality of cavities of a PCB similar to devices illustrates in Figures 8-9.
  • the overmolding of the package layer may be deposited in two or more encapsulation layers using different materials (e.g., a soft epoxy, a stiff, opaque epoxy, a transparent material, etc.), as illustrated in Figures 3A-H. Having the overmolding formed in two or more assembly steps additionally allows an intermediate testing and programming of the package layer at different assembly steps.
  • different materials e.g., a soft epoxy, a stiff, opaque epoxy, a transparent material, etc.
  • the package layer may include one or more dies 305-306 and a PCB 360 disposed over a carrier 310.
  • the dies 305-306 and the PCB 360 of Figures 3A-H are similar to the dies 105-108 and the PCB 160 of Figure IB.
  • the carrier 210 may be a glass carrier or a rigid carrier, which can be made from stainless steel or copper clad core or ceramic.
  • the dies 305-306 are disposed on the carrier 310 and adjacent to the PCB 360.
  • the dies 305-306 are stacked or assembled adjacent to or within a cavity (not shown) of the PCB 360 before a first overmolding step (as shown in Figure 3B).
  • each of the dies 305-306 is each electrically coupled to at least one other dies 305-306 using one or more interconnects 303 and 313.
  • the interconnect 313 may be electrically coupled to at least one pad of the PCB 360.
  • the package layer shows the dies 305-306 stacked adjacently to the PCB 360, but the package layer may have dies 305-306 disposed on the PCB 360 in one or more configurations (e.g., as shown in Figures 4-7).
  • a first encapsulation layer 312 may be deposited (or formed) over and around the dies 305-306 and the interconnects 303 and 313.
  • the first encapsulation layer 312 may be an opaque encapsulation layer based on the encapsulation requirements of the dies 305-306.
  • the first encapsulation layer 312 of the package layer may then be cured.
  • the first encapsulation layer 312 is formed of one or more first materials (e.g., a soft epoxy, a stiff, opaque epoxy, etc.), which may be different than the materials used for a second encapsulation layer (as shown in Figure 3E).
  • the PCB 360 may be used as an encapsulation dam (or an overmolding dam) between two or more layers of encapsulation (e.g. , an encapsulation dam between a first encapsulation layer and a second encapsulation layer).
  • the PCB surface and sides may be treated to result in different encapsulation angles near the PCB (e.g., the PCB may be treated to repel or attract the encapsulation material).
  • the package layer now has one or more exposed pads 361 on the top surface of the PCB 360.
  • the one or more pads 361 of the PCB 360 allow for the dies 305-306 to be tested, debugged, verified, and/or programmed (e.g. , to verify that each of the interconnects was not damaged and the dies are correctly programmed).
  • the interconnects 303 and 313, the dies 305-306, and/or the PCB 350 may be verified (i.e., tested, debugged, and/or programmed) to determine whether each of the components has an operational status (i.e.
  • each of the interconnects and dies are properly working). This intermediate testing facilitates in an overall decrease in yield loss by testing and verifying that the dies 305-306 are functioning correctly prior to stacking additional dies (e.g. , dies 307-308 of Figure 3D) on the package layer.
  • one or more dies 307-308 are disposed on the dies 305-306 of the package layer.
  • one or more interconnects 303 may be assembled to electrically couple the dies 307-308 with the other dies 305-306 and the PCB 360.
  • the dies 307-308 may be disposed on the carrier 310 and adjacent to the PCB 360.
  • the dies 305-308 are now interconnected with the pads 361 of the PCB using the interconnects 303 and 313, which allows the package layer to be additionally tested/programmed if needed prior to depositing a second encapsulation layer.
  • a second encapsulation layer 302 may be deposited over and around the dies 306-308, the interconnects 303 and 313, the first encapsulation layer 312, and the PCB 360.
  • the second encapsulation layer 302 may be a transparent encapsulation layer based on the encapsulation requirements of either of the dies 307-308 (e.g. , die 308 may be an energy harvesting device that needs light).
  • the second encapsulation layer 302 of the package layer may then be cured, forming enclosure 301 to surround and protect the package layer.
  • the PCB 360 may be used as an encapsulation dam between the first encapsulation layer 312 and the second encapsulation layer 302.
  • the encapsulation layer 302 may have any desired shape.
  • the enclosure 301 may have a rounded shaped or rounded angles (e.g., a hill-shaped enclosure with a plateaued top surface, a hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.).
  • a compression plunger may be used to flatten a top surface of the enclosure 301 if needed.
  • the carrier 310 is removed from the package layer.
  • the package layer now has one or more exposed pads 361 on the bottom surface of the PCB 360.
  • the one or more pads 361 of the PCB 360 allow for the dies 305-308 to be tested, debugged, verified, and/or programmed.
  • the package layer is singulated to provide one or more semiconductor packages 350-351 with two encapsulation layers 302 and 312.
  • each of the packages 350-351 may be diced along a plurality of fiducial lines to extract each of the packages 350-351 from the package layer.
  • Figure 3G illustrates a semiconductor package 350 that is singulated without the PCB 360.
  • the semiconductor package 350 has a surface 304 that may also have a coating (not shown) that electrically isolates the interconnect end 313 from the external environment.
  • Figure 3H illustrates a semiconductor package 351 that includes the PCB 360 with the one or more pads 361.
  • While the illustrated process flow in Figures 3A-H produces a semiconductor package 350 with an interconnect 313 extending to a surface 304 of an encapsulation enclosure 301 (without including a PCB with one or more pads) and a semiconductor package 351 with an interconnect 313 electrically coupling a plurality of dies 305-308 to a PCB 360 with one or more pads 361 that are formed in a single package layer, embodiments are not limited to such configurations.
  • the package layer illustrated in the process flow of Figures 2A-E may be used to exclusively produce either a first plurality of semiconductor packages with a PCB or a second plurality of semiconductor packages without a PCB based on design (or customer) requirements.
  • the PCB (or the test PCB) can be tabbed cut (or removed) so that the PCB can be disposed of later for the final product.
  • the test PCB can be removed with a paddle cut, a routed laser machined, etc.
  • semiconductor packages 350-351 may include fewer or additional packaging components based on the desired packaging design.
  • Figures 4-7 illustrate cross-sectional views of semiconductor packages having one or more configurations based on a plurality of dies and a PCB.
  • the dies, the interconnects, the encapsulation layer, and the PCB of Figures 4-7 are similar to the dies 105-108, the interconnects 103 and 113, the encapsulation layer 102, and the PCB 160 of Figure IB, however each package layer has a different configuration (or orientation) for disposing the dies on the PCB.
  • the present embodiments are not limited to such configurations.
  • Figure 4 is a cross-sectional view of a semiconductor package 400 having an encapsulation layer 402, a PCB 460 with a cavity 440 and one or more pads 461, and a plurality of dies 405-408 that are suspended on the cavity 440 of the PCB 460, according to some embodiments.
  • the semiconductor package 400 has the die 405 disposed within the cavity 440 of the PCB 460 using an adhesive layer 471 (e.g., a bond film) to attach the top surface of die 405 with the bottom surface of die 406.
  • the dies 405-408 are disposed on top of one another to form a stack.
  • Each die 405-408 may have one or more die contacts that are each electrically coupled to at least one other die contact of another die with one or more
  • interconnects 103 may be electrically coupled to one or more pads 461 of the PCB 460.
  • the package layer also has the encapsulation layer 402 formed over and around the dies 406-408, the interconnects 403, and the PCB 460.
  • the PCB 460 After overmolding, the PCB 460 has a set of pads 461 on the bottom surface of the PCB 460 that are exposed and may be used for testing, programming, and debugging. Note that suspending a die 405 inside a cavity 440 of a PCB 460 allows a die (e.g. , a sensor die or any other type of dies) to be protected from the encapsulation process if needed.
  • the stack of dies 405-408 may be assembled together initially and then the package layer is overmolded.
  • the stack of dies 406-408 may be disposed on the cavity 440 with the adhesive layer 471 and then the die 405 (or the cavity die) may be attached afterwards to the bottom surface of die 406 with the adhesive layer 471.
  • the die 406 may leverage backside interconnects such as TSVs or TMIs.
  • semiconductor package 400 may include fewer or additional packaging components based on the desired packaging design.
  • Figures 5 is a semiconductor package 500 having an encapsulation layer 502, a PCB 560 with a multi-level cavity 540a-b and one or more pads 561, and a plurality of dies 505-508 that are embedded in at least one of the cavities 540a-b of the PCB 560, according to some embodiments.
  • the semiconductor package 500 has a plurality of dies 505-508 embedded within the cavities 540a-b of the PCB 560.
  • the PCB 560 may have any desired number of cavity levels.
  • the dies 505-508 are disposed on top of one another to form a stack.
  • Each die 505-508 may have one or more die contacts that are each electrically coupled to at least one other die contact of another die with one or more interconnects 503.
  • one or more interconnects 503 may be electrically coupled to one or more pads 561 of the PCB 560.
  • the package layer has the encapsulation layer 502 formed over and around the dies 505-508, the interconnects 503, and the PCB 560.
  • the PCB 560 has a set of pads 561 on the top and bottom surfaces of the PCB 560 that are exposed and may be used for testing, programming, and debugging. Note that embedding die 505-508 in a multi-level cavity 540a-b of a PCB 560 allows for additional pads 561 on both sides of the PCB 560, and thus avoids needing to remove a carrier to test/program during some of the assembly steps. This also allows for a simpler testing with light exposed on the energy harvester die (e.g., die 508).
  • semiconductor package 500 may include fewer or additional packaging components based on the desired packaging design.
  • Figure 6 is a semiconductor package 600 having an encapsulation layer 602, a PCB 660 with a cavity 640 and one or more pads 661, and a plurality of dies 605-608 that are embedded in the cavity 640 of the PCB 660, according to some embodiments.
  • the semiconductor package 600 is similar to semiconductor package 500 of Figure 5, but the semiconductor package 600 has the dies 605-608 disposed on the top surface the cavities 640 of the PCB 660 (i.e. , the bottom surface of die 605 is not exposed as compared to Figure 5). This provides a lower manufacturing cost as the bottom surface of die 605 does not have to be exposed to the environment (e.g. , a temperature sensor die for food packaging).
  • semiconductor package 600 may include fewer or additional packaging components based on the desired packaging design.
  • Figure 7 is a cross-sectional view of a semiconductor package 700 having one or more encapsulation layers 702, a PCB 760 with one or more cavities 740a-b and one or more pads 761, and a plurality of dies 706-708 that are disposed on the cavity 740a of the PCB 760 and a die 705 disposed on the cavity 740b of the PCB 760, according to some embodiments.
  • the stack of dies 706-708 may be embedded in cavity 740a and disposed on the top surface of the PCB 760a.
  • the die 705 may be embedded in cavity 740b and disposed on the bottom surface of the PCB 760b.
  • the die 705 may be coupled to the PCB 760 and the other dies 706-708 with solder bumps 771 and one or more interconnects such as TSVs or TMIs or flip chip interconnects via redistribution layer.
  • the semiconductor package 700 allows a sensor die (e.g., die 705) to be attached without modification to the bottom surface of another die (e.g., die 406 as shown in Figure 4).
  • the semiconductor package 700 also allows for the compartmentalizing of two or more encapsulation layers if needed, particularly if the encapsulation specifications are unique. Also note that the semiconductor package 700 may include fewer or additional packaging components based on the desired packaging design.
  • Figure 8 is a top, perspective view of a package layer 800 that has a PCB 860 with a plurality of cavities 840 and a plurality of semiconductor packages 845, according to some embodiments.
  • the semiconductor packages 845 may be similar to the packages 100 and 150 of Figures 1A-B, the packages 250-251 of Figures 2D-E, the packages 350-351 of Figures 3G-H, the packages 400, 500, 600, and 700 of Figures 4-7, and the packages 945 of Figure 9.
  • the package layer 800 may be the PCB 860 having the one or more cavities 840, according to one embodiment.
  • the PCB 860 may be formed to have the one or more cavities 840 and then the system components (e.g., the dies, the interconnects, etc.) may be disposed within the one or more cavities 840.
  • the package layer 800 may further include a top surface 860a with pads 861 and a bottom surface 860b with pads 862.
  • the pads 861-862 may be similar the pads in Figures 2-7, which may be used for testing, debugging, verifying, and/or programming.
  • an encapsulation layer (not shown) may be deposited over the one or more PCB cavities 840 to enclose the plurality of semiconductor packages 845.
  • the PCB 860 may be used at the panel-level to assemble the plurality of semiconductor packages 845, where each of the semiconductor packages 845 may be singulated after the overmolding process into individual units without or with the PCB (as shown in Figures 1A-B).
  • the system components are assembled together prior to disposing the components into the cavities 840 of the PCB 860.
  • the system components and the encapsulation layers may be formed and deposited at different stages of the assembly process to allow for intermediate testing.
  • a PCB with cavities may be leveraged to include a portion of the wire bond stack of integrated circuits (ICs).
  • this PCB may be used to redistribute signals and enable further signal conditioning or functioning on the package (e.g., by adding a radio-frequency (RF) antenna into the PCB).
  • the PCB can also be leveraged to protect the die sensors that have special requirements, such as pressure sensors which must have low, symmetric stresses around the four sides.
  • the PCB e.g., PCB 860
  • the PCB also enables double-sided processing and may separate mixed encapsulate requirements and interaction issues.
  • the PCB (as described herein and illustrated in Figures 1-9) improves the overall architectural or configurational flexibility of the package with minimal impact to the overall volumetric form factor (i.e. , maintaining an ultra-small form factor for the package).
  • package layer 800 may include fewer or additional packaging components based on the desired packaging design.
  • Figure 9 is a top, perspective view of a PCB 960 with a plurality of cavities 940 and one or more channels 941, according to one embodiment.
  • the PCB 960 also includes a plurality of semiconductor packages 945 disposed on the one or more cavities 940 of the PCB 960.
  • the semiconductor packages 945 may be similar to the packages 100 and 150 of Figures 1A-B, the packages 250-251 of Figures 2D-E, the packages 350-351 of Figures 3G-H, the packages 400, 500, 600, and 700 of Figures 4-7, and the packages 845 of Figure 8.
  • the plurality of units (packages) in the PCB 960 can be different from each other having varying sizes, shapes, etc. (i.e. , the packages do not have to be identical).
  • the package layer 900 is similar to the package layer 800 of Figure 8, but the package layer 900 includes the one or more channels 941 that may be used to allow an encapsulation overflow between the package units and account for component size tolerance. Additionally, depending on the overmolding process, it might be preferable to have the one or more channels 941 between each of the packages 945. This enables volumetric control consistent with typical high volume manufacturing (HVM) tools rather than the precision volumes required for single units at one time.
  • HVM high volume manufacturing
  • package layer 900 may include fewer or additional packaging components based on the desired packaging design.
  • Figure 10 is a process flow 1000 illustrating a method of forming a semiconductor package having a plurality of dies, one or more interconnects, an encapsulation layer, and a substrate with one or more pads, according to one embodiment.
  • Figure 10 illustrates a process flow 1000 of forming a semiconductor package as shown in Figure 1 A.
  • the process flow 1000 may be similar to the method of forming a semiconductor package as shown in Figures 2A-E.
  • the process flow 1000 may be used to form a semiconductor package as shown in Figure 3G.
  • the process flow 1000 electrically couples a die contact of a die to a pad on a substrate with an interconnect, where the substrate is adjacent to the die (as shown in Figure 2A).
  • a package layer may electrically couple at least one die contact of a die from a plurality of dies to a pad on a substrate with at least one interconnect from one or more interconnects, where the substrate is adjacent to the plurality of dies.
  • the process flow 1000 disposes a plurality of dies on top of one another to form a stack (note that this may include the die from block 1005), where each die has a top surface and a bottom surface, where each die has one or more die contacts on the top surface and/or the bottom surface that are each electrically coupled to at least one die contact of another die with one or more interconnects (as shown in Figure 2A).
  • the plurality of dies may have contacts on one surface only or on both surface (e.g. , TSVs).
  • the process flow 1000 may be assembled in any configuration needed and is not limited to the sequential order of blocks 1005 and 1010 (i.e.
  • the step of block 1010 may be implemented first, and then the step of block 1005 is assembled - or vice-versa). For example, for some embodiments, a process flow may dispose the substrate first and then the dies may be disposed on the substrate using the substrate pattern as fiducials. Also note that steps 1005 and 1010 maybe repeated for different sets of dies to enable testing during the manufacturing rather than at the last step.
  • the process flow 1000 form an encapsulation layer over and around the plurality of dies, the one or more interconnects, and the substrate (as shown in Figure 2B).
  • the process flow 1000 severs the encapsulation layer and the interconnect to the pad on the substrate to form one or more semiconductor packages (as shown in Figure 2D), where some of the semiconductor packages include the substrate and some packages do not include the substrate.
  • the process flow may sever the interconnect to form a surface on the encapsulation layer (as shown in Figure 2D) (e.g. , the surface may be coplanar to one of the surfaces of the encapsulation layer).
  • the process flow 1000 may also include two or more encapsulation layers and any other configuration for the dies, the interconnects, and the substrate.
  • Figure 11 is a process flow 1100 illustrating a method of forming a semiconductor package having a plurality of dies, one or more interconnects, and one or more encapsulation layers, according to one embodiment.
  • Figure 11 illustrates a process flow 1100 of forming a semiconductor package as shown in Figure IB.
  • the process flow 1100 may be similar to the method of forming a semiconductor package as shown in Figures 2A-E. Note that the process flow 1100 may be used to form a semiconductor package as shown in Figure 3H.
  • the process flow 1100 disposes a first set of dies on top of one another to form a stack, wherein each die has a top surface and a bottom surface that is opposite from the top surface, wherein each die has one or more die contacts on the top surface that are each electrically coupled to at least one die contact of another die with one or more interconnects (as shown in Figure 2A).
  • the process flow 1100 disposes a substrate adjacent to the plurality of dies, wherein the substrate includes a first set of pads on a top surface and a second set of pads on a bottom surface that are opposite from the top surface (as shown in Figure 2A).
  • the process flow 1200 electrically couples at least one die contact to at least one pad of the first set of pads of the substrate with at least one of the interconnects (as shown in Figure 2A).
  • the process flow 1 100 forms an encapsulation layer over and around the plurality of dies, the one or more interconnects, and the substrate, wherein the second set of pads on the bottom surface of the substrate are exposed (as shown in Figure 2C). Furthermore, after overmolding, a carrier may be removed to expose the second set of pads on the bottom surface of the substrate, according to one embodiment.
  • the encapsulation layer may include a first encapsulation layer and a second encapsulation layer.
  • the first encapsulation layer may be initially deposited over and around one or more of the dies and one or more of the interconnects, and then the second encapsulation layer may be deposited over and around the first encapsulation layer, the remaining dies, and the remaining interconnects, according to some embodiments.
  • the process flow may test the first set of pads of the substrates to determine whether each of the dies and interconnects have an operational status. Note that the process flow 1 100 may also include any other configuration for the dies, interconnects, and the substrate.
  • Figure 12 is a process flow 1200 illustrating a method of forming a package layer having a plurality of cavities, a plurality of device packages, and a plurality of interconnects, according to one embodiment.
  • Figure 12 illustrates a process flow 1200 of forming a package layer as shown in Figures 8-9.
  • the process flow 1200 disposing a substrate having a plurality of cavities, a first set of pads, and a second set of pads on the substrate (as shown in Figure 8-9).
  • the process flow may place the substrate on a carrier.
  • the process flow disposes a plurality of device packages on the plurality of cavities of the substrate (as shown in Figures 8-9).
  • the plurality of device packages may be similar to the semiconductor packages of Figures 1A-B.
  • the process flow 1200 forms a plurality of interconnects on the plurality of device packages, where each of the device packages is electrically coupled to at least one pad of the first set of pads by one of the interconnects (as shown in Figures 8-9). Note that each of the device packages may have similar or
  • the process flow 1200 may dispose a plurality of channels on the substrate, where the plurality of channels are coupled to the plurality of cavities (as shown in Figure 9).
  • the process flow 1200 may form the first set of pads on a top surface of the substrate and the second set of pads on a bottom surface of the substrate (as shown in Figure 8-9).
  • the process flow 1200 may deposit an encapsulation layer over and around the plurality device packages, the plurality of interconnects, and the plurality of cavities and the plurality of channels of the substrate, where the second set of pads on the bottom surface of the substrate may be exposed.
  • the process flow 1200 may also include two or more encapsulation layers and any other configuration for the dies and the substrate.
  • Figures 13-14 illustrate cross-sectional views of semiconductor packages 1300 and 1400, respectively, having a plurality of dies, one or more interconnects, and a PCB (or embedded PCB).
  • the semiconductor package 1300 of Figure 13 is similar to the semiconductor package 1400 of Figure 14, however a PCB 1360 of Figure 13 has a through-cut cavity 1361 as a PCB 1460 of Figure 14 has a cavity 1461 with a specified depth (or z-height).
  • the semiconductor packages 1300 and 1400 use the embedded PCB (e.g.
  • PCB 1360 and 1460 for added functionality of the ultra-small form factor systems, such as reducing the overall z- height and volume by including/embedding a portion of the wire bond stacked dies and interconnects (e.g. , dies 1305 and 1405 and interconnects 1313 and 1413 of Figures 13-14).
  • the semiconductor package 1300 includes the PCB 1360 having the cavity 1361 with a through-cut.
  • the through-cut of cavity 1361 may refer to a cavity that has exposed top and bottom surfaces (i.e., the depth of the cavity is roughly equal to the z-height of the PCB).
  • the PCB 1360 has one or more pads 1340 on a top surface 1360a of the PCB 1360.
  • a first die 1305 may be embedded in the cavity 1360 of the PCB 1360.
  • the cavity 1360 may have a through-cut or a specified depth (as shown in Figure 14).
  • Each stacked die of the semiconductor package 1300 has a top surface 1310 and a bottom surface 1311 that is opposite from the top surface 1310 (note that each surface is not shown to avoid confusion).
  • the die 1305 may have one or more die contacts (not shown), where at least one of the die contacts of die 1305 is electrically coupled to the pads 1340 with an interconnect 1313 (e.g. , as shown in Figure 17C).
  • a soft encapsulant material (not shown) may be formed and cured around the edges of the die 1305 or air may be maintained around each of the four edges between the cavity walls and the die 1305.
  • a second die 1306 may have an adhesive layer 1330 on the bottom surface 1311 of the second die 1306 (i.e. , the backside of die 1306).
  • the second die 1306 with the adhesive layer 1330 on its backside may be disposed on the first die 1305 and the top surface 1360a of the PCB 1360.
  • the adhesive layer 1330 of the die 1306 is used to seal the die 1305 to the top surface 1360a of the PCB 1360.
  • the adhesive layer 1330 may have a deformation layer to accommodate the electrical contact topology on the PCB's top surface 1360a and any interconnects (e.g. , interconnect 1313).
  • the die 1305 may need to be shielded from interference as such an electrically conductive adhesive layer may be used to electrically couple to a ground (not shown) on the PCB 1360.
  • the semiconductor package 1300 has a plurality of dies 1307- 1309 disposed on top of one another to form a stack above the second die 1306.
  • Each of the dies 1305-1309 may have one or more die contacts 1320 on the top surface 1310 of each die 1305- 1309.
  • the one or more die contacts 1320 of each die 1305-1309 may be electrically coupled to at least one of the die contacts 1320 of another die 1305-1309 and/or the pads 1340 of the PCB 1360 using the interconnects 1303 and 1313.
  • the semiconductor package 1300 may have a sealant formed on the pads 1340 of the PCB 1360 and the one or more interconnects 1303 and 1313 that are coupled to the pads 1340.
  • the die 1305 may be a pressure sensor
  • the die 1306 may be a battery
  • the die 1307 may be a decoupling capacitor
  • the die 1308 may be a radio
  • the die 1309 may be a solar cell (or any other energy harvest).
  • the total number of dies for each package is not limited to a specific number of dies (i.e. , a package can have Nth number of dies based on a design or customer requirements).
  • a plurality of dies may be vertically stacked to minimize the overall volume and z-height, but the plurality of dies may also be arranged in any specified orientation to have any other desired configuration (e.g., as shown in Figures 15 and 16).
  • the PCB 1360 includes the cavity 1361 to embed a portion of the interconnects 1313 and the interconnected stack of dies 1305-1309 (i.e. , die 1305 is embedded, however more than one die may be embedded in the cavity).
  • the PCB 1360 thus allows the overall volume of the semiconductor package 1300 to be reduced, while also providing redistribution of signals and enabling further signal conditioning or functionality for the PCB 1360.
  • the PCB 1360 may also include one or more antennas 1370 (e.g. , radio frequency (RF) antennas) to enhance the signal conditioning and functionality of the semiconductor package 1300.
  • RF radio frequency
  • the one or more antennas 1370 may be disposed on the bottom surface 1360b of the PCB 1360, however the antennas may be disposed on any surface (or intermediate layer(s)) of the PCB (e.g. , as shown in Figures 14 and 15) pending directionality & frequency sensitivity required for transmit and/or receive.
  • the embedded PCB 1360 can also be leveraged to protect dies (or sensors) that have special requirements, such as a pressure sensor that needs low, symmetric stresses around the four sides of the sensor.
  • the embedded PCB 1360 further (i) enables double-sided processing on both surfaces 1360a-b (and any other layers formed within the PCB) and (ii) facilitates separate encapsulant requirements and interaction issues (e.g., die 1305 may be encapsulated with air, while dies 1306-1309 may be encapsulated with one or more
  • the 1400 includes the PCB 1460 that has cavity 1461 with a specified depth.
  • the cavity 1461 may refer to a cavity that has either an exposed top surface or bottom surface with the depth needed to embed a desired die (i.e. , the depth of the cavity is roughly equal to the z-height of the die).
  • the PCB 1460 has one or more pads 1440 on a top surface 1460a of the PCB 1460.
  • a first die 1405 may be embedded in the cavity 1460 of the PCB 1460.
  • the through-cut of cavity 1361 may refer to a cavity that has exposed top and bottom surfaces (i.e. , the depth of the cavity is roughly equal to the z-height of the PCB).
  • Each stacked die of the semiconductor package 1400 has a top surface 1410 and a bottom surface 1411 that is opposite from the top surface 1410 (note that each surface is not shown to avoid confusion).
  • the die 1405 may have one or more die contacts (not shown), where at least one of the die contacts of die 1405 is electrically coupled to the pads 1440 with an interconnect 1413 (e.g. , as shown in Figure 17C).
  • a soft encapsulant material (not shown) may be formed and cured around the edges of the die 1405 or air may be maintained around each of the four edges between the cavity walls and the die 1405.
  • a second die 1406 may have an adhesive layer 1430 on the bottom surface 1411 of the second die 1406 (i.e. , the backside of die 1406).
  • the second die 1406 with the adhesive layer 1330 on its backside may be disposed on the first die 1405 and the substrate 1460.
  • the adhesive layer 1430 of the die 1306 is used to seal the die 1405 to the top surface 1460a of the PCB 1460.
  • the adhesive layer 1430 may have a deformation layer to accommodate the electrical contact topology on the PCB's top surface 1460a and any interconnects (e.g., interconnect 1413).
  • the die 1405 may need to be shielded from interference as such an electrically conductive adhesive layer may be used to electrically couple to a ground (not shown) on the PCB 1460.
  • the semiconductor package 1400 has a plurality of dies 1407- 1409 disposed on top of one another to form a stack above the second die 1406.
  • Each of the dies 1405-1409 may have one or more die contacts 1420 on the top surface 1410 of each die 1405- 1409.
  • the one or more die contacts 1420 of each die 1405-1409 may be electrically coupled to at least one of the die contacts 1420 of another die 1405-1409 and/or the pads 1440 of the PCB 1460 using the interconnects 1403 and 1413.
  • the semiconductor package 1400 may have a sealant formed on the pads 1440 of the PCB 1460 and the one or more interconnects 1403 and 1413 that are coupled to the pads 1440.
  • the die 1405 may be an accelerometer
  • the die 1406 may be a battery
  • the die 1407 may be a decoupling capacitor
  • the die 1408 may be a radio
  • the die 1409 may be a solar cell (or any other energy harvest).
  • the PCB 1460 may also include one or more antennas 1470 disposed on the top surface 1460a of the PCB 1460, however the antennas may be disposed on any surface (or intermediate layer(s)) of the PCB (e.g. , as shown in Figures 13 and 15).
  • the semiconductor packages 1300 and 1400 of Figures 13-14 may include fewer or additional packaging components based on the desired packaging design.
  • the semiconductor packages 1300 and 1400 may include one or more encapsulation layers (as shown in Figures 15-16) and any other configuration (or orientation) for the dies, interconnects, cavities, and PCB.
  • Figures 15-16 illustrate cross-sectional views of semiconductor packages 1500 and 1600, respectively, having a plurality of dies, one or more interconnects, one or more encapsulation layers, and a PCB.
  • the semiconductor packages 1500 and 1600 of Figures 15-16 are similar to the semiconductor packages 1300 and 1400 of Figures 13-14, however these semiconductor packages 1500 and 1600 have one or more encapsulation layers and one or more stacks using double-sided interconnects.
  • the semiconductor package 1500 includes the PCB 1560 having the cavity 1561 with a through-cut.
  • the PCB 1560 has one or more pads 1540a on a top surface 1560a of the PCB 1560 and one or more pads 1540b on a bottom surface 1560b of the PCB 1560.
  • a first die 1505 may be embedded in the cavity 1560 of the PCB 1560.
  • the die 1505 may have one or more die contacts (not shown), where at least one of the die contacts of die 1505 is electrically coupled to the pads 1540a (or pads 1540b) with an interconnect 1513 (e.g. , as shown in Figure 17C).
  • a soft encapsulant material (not shown) may be formed and cured around the edges of the die 1505 or air may be maintained around each of the four edges between the cavity walls and the die 1505.
  • a second die 1506 may have an adhesive layer 1530 on a bottom surface 1511 of the second die 1506 (i.e. , the backside of die 1506).
  • the second die 1506 with the adhesive layer 1530 on its backside may be disposed on the top surface 1510 of the first die 1505 and the top surface 1560a of the substrate 1560.
  • a third die 1509 may have an adhesive layer 1531 on the bottom surface 1511 of the third die 1509.
  • the third die 1509 with the adhesive layer 1531 on its backside may be disposed on the bottom surface 1511 of the first die 1505 and the bottom surface 1560b of the substrate 1560.
  • the adhesive layers 1530-1531 of the dies 1506 and 1509 may be used to seal the die 1505 to the top and bottom surfaces 1560a-b of the PCB 1560.
  • the semiconductor package 1500 has a first stack of dies 1506-1508 disposed on the top surface 1560a of the PCB 1560, and a die 1509 (or a second stack of dies as shown in Figure 16) disposed on the bottom surface 1560b of the PCB 1560.
  • Each of the dies 1505-1509 may have one or more die contacts 1520 on the top surface 1510 of each die 1505-1509.
  • the one or more die contacts 1520 of each die 1505-1509 may be electrically coupled to at least one of the die contacts 1520 of another die 1505-1509 and/or the pads 1540a-b of the PCB 1560 using the interconnects 1503 and 1513.
  • the semiconductor package 1500 may have a sealant formed on the pads 1540a-b of the PCB 1560 and the one or more interconnects 1503 and 1513 that are coupled to the pads 1540a-b.
  • the die 1505 may be an accelerometer
  • the die 1506 may be a battery
  • the die 1507 may be a decoupling capacitor
  • the die 1508 may be a radio
  • the die 1509 may be a solar cell (or any other energy harvest).
  • the PCB 1560 may also include one or more antennas 1570 to enhance the signal conditioning and functionality of the semiconductor package 1500.
  • the one or more antennas 1570 may be disposed on any layer of the PCB 1560, including any surface (or intermediate layer(s)) of the PCB (e.g., as shown in Figures 13 and 15).
  • the antennas 1570 may be disposed on the PCB with side-radiating
  • an encapsulation layer 1502 may be formed over and around the dies 1506-1508 (note that this may include the adhesive layer 1530), the
  • interconnects 1503 and 1513, and the pads 1540a and top surface 1560a of the PCB 1560 may be exposed or covered with the encapsulation layer.
  • an encapsulation layer 1512 may be formed over and around the die 1509 (note that this may include the adhesive layer 1531), the interconnects 1503 and die contacts 1520, and the pads 1540b and bottom surface 1560b of the PCB 1560.
  • the die 1509 may be a solar cell as such the encapsulation layer 1512 may be formed of an UV -Visible (UV-Vis) transmittable material, while the encapsulation layer 1502 may be formed of an epoxy material (i.e., encapsulation layers 1502 and 1512 may be formed from different materials).
  • UV-Vis UV -Visible
  • the encapsulation layer 1502 may be formed of an epoxy material (i.e., encapsulation layers 1502 and 1512 may be formed from different materials).
  • the semiconductor package 1600 includes the PCB 1660 having the cavity 1661 with a through-cut.
  • the PCB 1660 has one or more pads 1640a on a top surface 1660a of the PCB 1560 and one or more pads 1540b on a bottom surface 1560b of the PCB 1560.
  • a first die 1605 may be embedded in the cavity 1660 of the PCB 1660.
  • the die 1605 may have one or more die contacts (not shown) on a top surface 1610a and/or a bottom surface 1611a, where at least one of the die contacts of die 1605 is electrically coupled to the pads 1640a and/or pads 1640b with one or more interconnects 1613a-b.
  • a soft encapsulant material (not shown) may be formed and cured around the edges of the die 1605 or air may be maintained around each of the four edges between the cavity walls and the die 1605.
  • a second die 1606a may have an adhesive layer 1630 on a bottom surface 161 la of the second die 1606a (i.e., the backside of die 1606).
  • the second die 1606a with the adhesive layer 1630 on its backside may be disposed on the top surface 1610a of the first die 1605 and the top surface 1660a of the substrate 1660.
  • a third die 1606b may have an adhesive layer 1631 on the bottom surface 161 lb of the third die 1606b.
  • the third die 1606b with the adhesive layer 1631 on its backside may be disposed on the bottom surface 161 la of the first die 1605 and the bottom surface 1660b of the substrate 1660.
  • the adhesive layers 1630-1631 of the dies 1606a-b may be used to seal the die 1605 to the top and bottom surfaces 1660a-b of the PCB 1660.
  • the semiconductor package 1600 has a first stack of dies 1606a- 1609a disposed on the top surface 1660a of the PCB 1660, and a second stack of dies 1606b- 1609b disposed on the bottom surface 1560b of the PCB 1660.
  • the semiconductor package 1600 is similar to the semiconductor package 1300 of Figure 13, but this package 1600 has two sets of stacked dies 1606a- 1609a and 1606b- 1609b and multiple encapsulation layers 1602a-b and 1612a-b.
  • Each of the dies 1606a- 1609a and 1606b- 1609b may have one or more die contacts
  • the one or more die contacts 1620a-b of each die 1606a-1609a and 1606b- 1609b may be electrically coupled to at least one of the die contacts 1620a-b of another die 1606a- 1609a and 1606b- 1609b and/or the pads 1640a-b of the PCB 1660 using the interconnects 1603a-b and 1613a-b.
  • the semiconductor package 1600 may have a sealant formed on the pads 1640a-b of the PCB 1660 and the one or more interconnects 1603a-b and 1613a-b that are coupled to the pads 1640a-b.
  • the die 1605 may be a pressure sensor
  • the dies 1606a-b may be batteries
  • the dies 1607a-b may be decoupling capacitors
  • the dies 1608a-b may be radios
  • the dies 1609a-b may be solar cells (or any other energy harvests).
  • the dies e.g., dies 1606a-b
  • the dies may be the same dies or different dies (i.e., die 1606a may be a battery, while 1606b is a decoupling capacitor)
  • the stacked dies e.g. , 1606a-1609a and 1606b- 1609b) may have the same configuration or any, different orientation/configuration that is needed.
  • the PCB 1660 may also include one or more antennas (not shown) to enhance the signal conditioning and functionality of the semiconductor package 1600. As shown in Figures 13-16, the one or more antennas (not shown) may be disposed on any layer of the PCB 1660.
  • an encapsulation layer 1602a may be formed over and around the dies 1606a-1608a (note that this may include the adhesive layer 1630), the interconnects 1603a and 1613a, and the pads 1640a and top surface 1660a of the PCB 1660.
  • an encapsulation layer 1602b may be formed over and around the dies 1606b-1608b (note that this may include the adhesive layer 1631), the interconnects 1603b and 1613b, and the pads 1640b and bottom surface 1660b of the PCB 1660.
  • the encapsulation layer 1602a-b may formed of the same material (e.g., an epoxy) or one or more different materials.
  • an encapsulation layer 1612a may be formed over and around the die 1609a, the interconnects 1603a and die contacts 1620a, and the encapsulation layer 1602a.
  • the die 1609a may be a solar cell as such the encapsulation layer 1612a may be formed of a UV- Vis transmittable material, while the encapsulation layer 1602a may be formed of an epoxy material (i.e. , encapsulation layers 1502 and 1512 may be formed from different materials with different encapsulant requirements for the respective embedded dies).
  • an encapsulation layer 1612b may be formed over and around the die 1609b, the interconnects 1603b and die contacts 1620b, and the encapsulation layer 1602b.
  • the encapsulation layer 1612a-b may formed of the same material (e.g. , a transparent material) or one or more different materials.
  • the semiconductor packages 1500 and 1600 of Figures 15-16 may include fewer or additional packaging components based on the desired packaging design.
  • the semiconductor packages 1500 and 1600 may include additional encapsulation layers and any other the dies, interconnects, cavities, and PCB.
  • the semiconductor packages may enable various, different layouts of the interconnected (or wire bond) stack as interconnects may be routed to the PCB (e.g., PCB 1360) rather than the exposed die pads (e.g., die contacts 1320);
  • additional functionality may be added to the PCB (e.g., an antenna (such as antennas 1370) may be routed with prescribed directionality, integrated passives may be designed in the layers of the PCB, and surface-mount devices (SMDs) may be added as needed);
  • the PCB may be made of traditional materials or new alternatives (e.g.
  • liquid crystal polymer LCP
  • polyimide PI
  • PET polyethylene terephthalate
  • MIS MIS
  • pre- preg organic build-up, polyurethanes, polydimethylsiloxane (PDMS), etc.
  • devices or components/features may be added to the PCB (or package) to enable interconnections to other sub-modules with different functionality or connectorizations of specific shells or add-ons
  • the integrated dies (or circuits) e.g., dies 1305-1309
  • the integrated dies may have different material encapsulant requirements and may thus be separated from top-to-bottom to reduce the risk of interfacial adhesion delamination
  • NTV ICs or dies
  • NTV ICs may be covered with photon-absorbing material, sputter coated with aluminum (Al) or similar reflector material, spray coated with a black artificial substance (e.g.
  • pressure sensors e.g. , die 1305
  • pressure sensors may be embedded including a soft encapsulation layer formed around the four sides of the pressure sensor if needed to help ensure pressure sensor stability or air around the four sides of the pressure sensor if an adhesive layer (e.g. , adhesive layer 1330) is used on the interconnects (e.g. , interconnects 1303 and 1313);
  • adhesive layer e.g. , adhesive layer 1330
  • one or more stacks of dies may be encompassed in the same design (e.g. , semiconductor package 1600 of Figure 16); and
  • panel -lev el manufacturing is enabled with redistribution without the increased cost of embedded wafer-level ball grid array (eWLB) or fan-out approaches.
  • eWLB embedded wafer-level ball grid array
  • Figures 17A-17E are cross-sectional views of a process flow 1700 used to form a semiconductor package (e.g., semiconductor package 1750 of Figure 17E) having one or more dies (e.g., dies 1705-1708F), one or more interconnects (e.g., interconnects 1703 and 1713), and a PCB 176 with a cavity 1761, according to some embodiments.
  • Figures 17A-17E illustrate cross-sectional views of the process flow 1700 used to form a semiconductor package (e.g. , semiconductor package 1750 of Figure 17E) having an embedded stack of dies - without an encapsulation layer(s).
  • a process flow 1800 of Figures 18A-D implements a semiconductor package similar to the semiconductor package 1750 of Figures 17E to further illustrate forming one or more encapsulation layers on the semiconductor package (e.g., the semiconductor package 1750 of Figure 17E).
  • the processing illustrated in Figures 17A-17E may be used to form a semiconductor package similar to the devices illustrated in Figures 13 and 14, the devices illustrated in Figures 15 and 16, and the devices illustrated in Figures 18C and 18D.
  • the package layer may include forming a PCB 1760 with a through-cut cavity 1761 and one or more pads 1740 formed on a top surface 1760a of the PCB 1760.
  • the PCB 1760 may be formed (or disposed) on a temporary carrier (not shown) during the assembly process.
  • the PCB 1760 may have a cavity 1761 or more than one cavity (not shown) if needed.
  • the cavity 1761 may have a through-cut (as shown) or any specified depth (e.g., as shown with cavity 1461 of Figure 14).
  • the PCB 1760 may provide any redistribution of signals and embedding of signals or components.
  • pads 1740 may be used to redistribute and/or electrically couple signals and components within the PCB 1760.
  • any routing of the PCB 1760 may be included through the thickness or along the cross-section of the PCB 1760 to enable broad functionality, such as integrated passives, antennas, etc.
  • the package layer may include disposing a die 1705 in the cavity 1761 of the PCB 1760.
  • the die 1705 may be a pressure sensor that is placed on the cavity 1761 of the PCB 1760 with a diaphragm (not shown) onto the temporary carrier (not shown).
  • the die 1705 has one or more die contacts 1720 on a top surface 1710 of the die 1705.
  • the die 1705 may also have die contacts on a bottom surface of the die 1705 (not shown).
  • a soft encapsulant material (not shown) may be deposited and cured between the four walls of the cavity 1761 and the four sides of the die 1705.
  • the cavity 1761 may have air surround the four sides of the die 1705.
  • the package layer may include electrically coupling at least one or more of the die contacts 1720 and the pads 1740 of the PCB 1760 with interconnects 1713.
  • the interconnects 1713 may be wires that are ball-stitch bonded (wire bonds) from the die contacts 1720 of the die 1705 to the pads 1740 of the PCB 1760.
  • the interconnects 1713 may be wire bonds, TSVs, TMIs, or a combination thereof, or any other desired type of interconnects.
  • a die 1706 may be disposed on the die 1705 and the top surface 1760a of the PCB (note that this may include a portion of the pads 1740 and interconnects 1713).
  • the die 1706 may have an adhesive layer 1730 on a bottom surface 1711 of the die 1706 (i.e. , the backside of die 1706).
  • the die 1706 with the adhesive layer 1730 on its backside may be disposed on the die 1705 and the top surface 1710 of the PCB 1760.
  • the adhesive layer 1730 of the die 1706 is used to seal the die 1705 to the top surface 1760a of the PCB 1760.
  • the adhesive layer 1730 may have a deformation layer to accommodate the electrical contact topology on the PCB's top surface 1760a, such as a portion of the pads 1740 and interconnects 1713.
  • the die 1705 may need to be shielded from interference as such an electrically conductive adhesive layer may be used to electrically couple to a ground (not shown) on the PCB 1760.
  • the package layer may have a sealant formed on the pads 1740 of the PCB 1760 and the one or more interconnects 1703 and 1713 that are coupled to the pads 1740.
  • the package layer may include stacking dies 1707-1708F above the die 1706 and interconnecting the dies 1705-1708F to each other or to the PCB 1760 to ultimately form a PCB embedded stack 1750 (also referred to as a package embedded stack).
  • the remaining dies 1707-1708F may then be attached and interconnected based on the design arrangement that is needed (i.e. , forming the dies and die contacts in any specified orientation and location).
  • the interconnects 1703 and 1713 may be electrically coupled (or interconnected) from one die 1705-1708F to another die 1705-1708F or one die 1705-1708F to the PCB 1760.
  • Each of the dies 1705-1708F may have one or more die contacts 1720 on the top surface 1710 of each die 1705-1708F.
  • the one or more die contacts 1720 of each die 1705-1708F may be electrically coupled to at least one of the die contacts 1720 of another die 1705-1708F and/or the pads 1740 of the PCB 1760 using the interconnects 1703 and 1713.
  • the PCB 1760 may also include one or more antennas (not shown) that may be disposed on any surface (or intermediate layer(s)) of the PCB (e.g. , as shown in Figures 13-15).
  • the PCB embedded stack 1750 is then formed and may further include a spacer and a solar cell die (e.g., dies 1809B and 1809 A, respectively, as shown in Figures 18C- D) and one or more encapsulation layers (e.g. , encapsulation layers 1802 and 1812 as shown in Figures 18C-D) to separate the encapsulant requirements of the dies.
  • a spacer and a solar cell die e.g., dies 1809B and 1809 A, respectively, as shown in Figures 18C- D
  • encapsulation layers e.g. , encapsulation layers 1802 and 1812 as shown in Figures 18C-D
  • the total number of dies for each package is not limited to a specific number of dies (i.e.
  • a package can have Nth number of dies based on a design or customer requirements), nor is the shape of the unit (or individual package) limited to a rectangular prism, for example, any arbitrary 3D shape is feasible (e.g., hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.).
  • a plurality of dies may be vertically stacked to minimize the overall volume and z- height, but the plurality of dies may also be arranged in any specified orientation to have any other desired configuration.
  • the process flow 1700 and the semiconductor package 1750 may include fewer or additional packaging components based on the desired packaging design.
  • Figures 18A-18D illustrate cross-sectional views of a process flow 1800 used to form a semiconductor package (e.g., semiconductor packages 1850-1851 of Figures 18C and 18D) having an embedded stack of dies (e.g. , dies 1806-1809A) with one or more encapsulation layers (e.g., encapsulation layers 1802 and 1812).
  • a semiconductor package e.g., semiconductor packages 1850-1851 of Figures 18C and 18D
  • an embedded stack of dies e.g. , dies 1806-1809A
  • encapsulation layers e.g., encapsulation layers 1802 and 1812
  • a process flow 1800 of Figures 18A-D uses a semiconductor package similar to the semiconductor package 1750 of Figures 17E, omitting some steps to focus on the overmolding process.
  • the processing illustrated in Figures 18A-18D may be used to form a semiconductor package similar to the devices illustrated in Figures 15 and 16 and the device illustrated in Figure 17E. Note that for simplicity a process flow for one instantiation is provided on a unit-level flow, however it is to be appreciated that the processing illustrated in Figures 18A-18D may be implemented on a panel-level to enable a plurality of semiconductor packages with singulation as a last step.
  • a package layer includes a stack of dies 1806-1808F (note that an additional die may be embedded in the PCB 1860) disposed on the PCB 1860.
  • the package layer further includes forming an encapsulation layer 1802 (e.g., an epoxy) over and around the dies 1806-1808F (note that this may include an adhesive layer if needed on the backside of die 1806), one or more interconnects (not shown) and one or more pads (not shown) of the PCB 1860, and a top surface 1860a of the PCB 1860. Note that the top surface 1810 of die 1808F may be exposed or covered with the encapsulation layer 1802.
  • an encapsulation layer 1802 e.g., an epoxy
  • the top surface 1810 of die 1808F may be exposed or covered with the encapsulation layer 1802.
  • the overmolding process may be implemented in batches (if needed) with or without an exposed top surface of the top die (e.g., die 1808F), where exposing the top surface of the top die may be facilitated with any known process such as laser raster, wet blast, grind, etch, etc.
  • the package layer may form TMIs to one or more dies or to the PCB using a laser ablate with a filling process (i.e. , depositing a conductive material to fill the laser ablated openings to form the TMIs).
  • the package layer may include an interconnect loop (e.g. , interconnects 1803) formed through the package prior to forming/depositing the encapsulation layer and then after molding use a grinding process to expose one or more contacts 1804 of any interconnect (e.g., interconnects 1803) that was enabled.
  • the interconnect loop may a wire bonds, a TSV, a TMV, a flip- chip, a 3D printing, an inkjet, and an ACF.
  • the package layer may further include disposing dies 1809A-B on the top surface 1810 of the die 1808F (or a top surface of the encapsulation layer 1802).
  • the dies 1809A-B may be a spacer and a solar cell die that are added to finalize the stack.
  • the stack of semiconductor package 1850 is assembled and then encapsulated with an encapsulation layer 1812, which may include an alternate material (e.g., an UV-Vis material) from the encapsulation layer 1802 (e.g. , an epoxy material).
  • the encapsulation layer 1812 may be formed over and around the dies 1809A-B, one or more interconnects 1803, one or more die contacts 1820, and the encapsulation layer 1802.
  • the top dies 1809A-B may be electrically coupled to the rest of the package 1850 either with the exposed contacts (e.g., contacts 1804 as shown in Figure 18B) of the interconnects 1803 or an alternate side (e.g. , the bottom surface 1860b) of the PCB 1860 (as shown in Figure 18D).
  • the package layer may have stacked the dies 1806-1809B and electrically coupled the dies 1806-1809B and the PCB 1860 with the interconnects 1803, and then formed the encapsulation layers (e.g., encapsulation layers 1802 and 1812) when the stack was assembled.
  • the package layer may dispose dies 1809A-B on the bottom surface 1860b of the PCB 1860, such as a PCB embedded stack with double-sided interconnects.
  • the stack of semiconductor package 1851 is assembled and then encapsulated with an encapsulation layer 1812, which may include an alternate material from the encapsulation layer 1802.
  • the encapsulation layer 1812 may be formed over and around the dies 1809A-B, one or more interconnects 1803, one or more die contacts 1820 on the top surface 1810b of the dies 1809A-B, and the bottom surface 1860b of the PCB 1860.
  • the dies 1809A-B may be electrically coupled to the rest of the package 1851 using the bottom surface 1860b of the PCB 1860.
  • the package layer may have stacked both set of dies 1806-1808F and 1809A-B and electrically coupled the dies 1806-1809B and the PCB 1860 with the interconnects 1803, and then formed the encapsulation layers (e.g. , encapsulation layers 1802 and 1812) when the stacks were assembled.
  • the process flow 1800 of Figures 18A-18D may include fewer or additional packaging components based on the desired packaging design.
  • the semiconductor packages e.g., semiconductor packages 1300, 1400, 1500, and 1600 of Figures 13-16, andl 850-1851 of Figures 18C-D
  • the semiconductor packages may include components such as: (i) antennas on any surface or layer of a PCB, (ii) integrated passives (e.g.
  • inductors inductors, resistors, capacitors, and any other circuits
  • SMDs surface-mount devices
  • a PCB that may be formed of a wide variety of materials and does not have to be planar, (v) multiple cavities or thru-cuts may be made in a PCB, (vi) alternate sensors, cameras, light-emitting diodes (LEDs), or photo-detectors may be disposed on a PCB, and (vii) at least one side of a PCB may include interconnects that may socket, anisotropic conductive film (ACF), or reflow attach to other modules or systems (or packages).
  • ACF anisotropic conductive film
  • Figure 19 is a process flow 1900 illustrating a method of forming a semiconductor package having one or more dies, one or more interconnects, and a PCB with a cavity, according to one embodiment.
  • Figure 19 illustrates a process flow 1900 of forming a semiconductor package as shown in Figure 18C.
  • the process flow 1900 may be similar to the method of forming semiconductor packages as shown in Figures 13-16 and 17E.
  • the process flow disposes a substrate having a cavity and one or more pads on at least one of a top surface and a bottom surface that is opposite from the top surface (as shown in Figure 17A).
  • a package layer may dispose a substrate (e.g. , a PCB) with a through-cut cavity and one or more pads formed on a top surface of the substrate.
  • the substrate may be disposed on a temporary carrier during the assembly process.
  • the process flow embeds a first die in the cavity of the substrate (as shown in Figure 17B).
  • a package layer may dispose the first die in the cavity of the substrate, where the first die may be a pressure sensor.
  • the first die may have one or more die contacts on a top surface and/or a bottom surface of the first die.
  • a soft encapsulant material (not shown) may be deposited and cured between the four walls of the cavity and the edges of the first die, or the cavity may have air surround the four walls of the cavity and the edges of the first die.
  • the process flow disposes a second die having an adhesive layer on a bottom surface of the second die, where the second die and the adhesive layer are disposed on the first die and the substrate (as shown in Figure 17D).
  • the second die may have the adhesive layer on its backside, and the package layer may dispose the second die with the adhesive layer on the first die and/or the top surface of the substrate (note that this may include a portion of the pads and one or more interconnects).
  • the adhesive layer and the second die may be used to seal the first die to the top surface of the substrate.
  • the process flow disposes a plurality of dies disposed on the second die and on top of one another to form a stack, wherein each die has a top surface and a bottom surface that is opposite from the top surface, wherein each die has one or more die contacts on the top surface and/or bottom surface that are each electrically coupled to at least one of the die contacts of another die and the pads of the substrate with one or more interconnects (as shown in Figure 17E).
  • a package layer may stack the plurality of dies on the second die. Then, continuing with the above example, the package layer may electrically couple at least one or more of the die contacts from one die to another die or from one die to the pads of the substrate using interconnects (e.g., wire bonds, TSVs, TMIs, direct write interconnects via 3d printing or inkjet printing etc.).
  • interconnects e.g., wire bonds, TSVs, TMIs, direct write interconnects via 3d printing or inkjet printing etc.
  • the process flow forms an encapsulation layer over and around the plurality of dies, the one or more interconnects, the one or more pads of the substrate, and the top surface of the substrate (as shown in Figures 15 and 18C).
  • the package layer may deposit the encapsulation layer over the plurality of dies (note that this includes the second die and/or the adhesive layer), the interconnects, the pads, and the top surface of the substrate.
  • the encapsulation layer may further includes a first encapsulation layer and a second encapsulation layer, where the first encapsulation layer may be initially deposited over and around one or more of the dies, one or more of the interconnects, the pads, and the top surface of the substrate, and the second layer encapsulation layer may then be deposited over and around the remaining dies, the remaining interconnects, and the top surface of the first encapsulation layer.
  • the process flow 1900 may form a semiconductor package that may include fewer or additional packaging components based on the desired packaging design.
  • the semiconductor package may include any configuration needed, including additional encapsulation layers and any other the dies, interconnects, cavities, and PCB.
  • Figures 20A-20H are plan views and corresponding plan and cross-sectional views of a process flow used to form the package layer 2000 having a plurality of device packages, a plurality of interconnects, and one or more encapsulation layers that are stacked (also referred to as a multi-material stack), according to one embodiment.
  • Figures 20A-20H illustrate the package layer 2000 used to form a semiconductor package (e.g., semiconductor package 2050 of Figure 20H) having a plurality of stacked dies (e.g., dies 2005-2009 of Figure 20H), one or more interconnects (e.g. , interconnects 2003), and one or more encapsulation layers (e.g. ,
  • Figures 20C-20H illustrate two corresponding views of the package layer 200, a plan view of the package layer (as shown on the left) and a cross-sectional view of the respective package layer in an individual unit-level (as shown on the right), where the individual unit is one of a plurality of semiconductor packages/units.
  • the package layer 2000 illustrated in Figures 20A-20H enables a dimension tolerant, low-cost, and multi-material stack.
  • the package layer 2000 may utilize a batch process that relies on large material volume control rather than tight tolerance encapsulation/mold collaterals, materials applications, or grind control.
  • Some of the advantages of these embodiments are cost-efficient, accelerated stock keeping unit (SKU) adjustment, and custom build on demand with minimal manufacturing change or cost.
  • the package layer 2000 may facilitate lowered volume for the overall packages as overmolding is dispensed or paste printed to control the overall z- height of the packages.
  • the one or more encapsulation layers may include, but are not limited to, ultra-compliant materials for pressure sensors, visible light, UV and IR
  • the one or more encapsulation layers as described herein may also include visible light, UV and/or IR blocking agents or metals (e.g. , aluminum to block light) that are selectively sputtered on the packages.
  • a package layer 2000 may have a panel 2001 (or a temporary carrier) with a first set of fiducials 2005 that are covered with an adhesive layer 2030, according to one embodiment.
  • the package layer 2000 illustrates forming the adhesive layer 2030 on the panel 2001 that has the first set of fiducials 2005.
  • the adhesive layer 2030 may include a bond film, a one/double sided tape, a thermal tape, an attach film, or any other type of adhesive.
  • the first set of fiducials 2005 may be used to align an encapsulation dam (as shown in Figure 20B) or accommodate to any package design.
  • the package layer 2000 may include disposing a dam 2010 with a cavity 2061 on the adhesive layer 2030, according to one embodiment.
  • the dam 2010 is disposed on the adhesive layer forming the cavity 2061 with the bottom surface covered with the adhesive layer, while the top surface is exposed.
  • the package layer 2000 may form a set second of fiducials 2015 with a laser to denote singulation patterns.
  • the second set of fiducials 2015 may be formed on the adhesive layer 2030 and adjacent to an outer surface 2010a of the dam 2010, where the second set of fiducials 2015 may be formed outside of the dam 2010 and aligned adjacently to at least two outer-edge walls (e.g., aligned on the x-y axis) of the dam 2010.
  • the second set of fiducials 2015 may be used to form a plurality of compartments (e.g. , a plurality of
  • compartments 2055 of Figure 20H that house a plurality of semiconductor packages (e.g., a plurality of semiconductor packages 2045 of Figure 20H) and align with the saw fiducials (e.g., fiducial lines 2025 of Figure 20H) during the singulation process and formed with any configuration.
  • the exact location and placement of the second set of fiducials 2015 is illustrative (i.e. , the fiducials as shown in Figures 20B - 20H may not be to scale) and may be changed based on the desired number of semiconductor packages and requirements.
  • the package layer 2000 illustrates disposing a first plurality of dies 2005 in the cavity 2061 of the dam 2010 formed on the adhesive layer 2030, according to one embodiment.
  • the first plurality of dies 2005 are disposed on the adhesive layer 2030 using the second set of fiducials 2015 to align each die within one of the compartments 2055 (i.e. , within a prescribed array having the lines/boundaries formed by the fiducials 2015 and/or the dam 2010).
  • the first plurality of dies 2005 may be pressure sensors.
  • one of the first dies 2005 is illustrated having a top surface 2020 and a bottom surface 2021 that is opposite of the top surface 2020. Note that a few components may be omitted for simplicity (e.g. , the adhesive layer and the panel formed below the die).
  • the package layer 2000 includes forming a first encapsulation layer 2002 around the first plurality of dies 2005, according to one embodiment.
  • the first encapsulation layer 2002 e.g., a soft epoxy
  • the dam 2010 filling up to a plurality of top surfaces 2020 of the first plurality of dies 2005 and then the first encapsulation layer 2002 is cured.
  • the package layer 2000 illustrates the first die 2005 having the first encapsulation layer 2002 formed around the edges of the first die 2005.
  • a top surface 2002a of first encapsulation layer 2002 may not be planar as the top surface 2002a curtails based on one or more factors (e.g. , coefficient of thermal expansion (CTE) mismatch, z-height of the adjacent die, pressure created by stacking additional encapsulation layers, material properties of the encapsulation layers, etc.).
  • the top surface 2002a may have a rounded shape or rounded angles (e.g.
  • the package layer 2000 may form the first encapsulation layer 2002 to have any desired shape (e.g., hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.).
  • any desired shape e.g., hemispherical shape, a capsule-like shape, a honeycombed shape to increase surface area, a round shape, one or more dimples to fit in certain devices, etc.
  • the package layer 2000 illustrates disposing a second plurality of dies 2006-2008 on the top surfaces 2020 of the first plurality of dies 2005, according to one embodiment.
  • the second plurality of dies 2006-2008 may include one or more different dies.
  • dies 2006 may be batteries
  • dies 2007 may be decoupling capacitors
  • dies 2008 may be radios.
  • each of the stacked dies 2005-2008 may be interconnected in a batch or one at a time, according to some embodiments.
  • each of the stacked dies 2005-2008 may have one or more die contacts (not shown) on the top surface 2020 and/or the bottom surface 2021 that are each electrically coupled to at least one die contact of another die 2005-2008 with one or more interconnects 2003.
  • the interconnects 2003 may be wire bonds, TSVs, through mold vias (TMVs), inkjet printed interconnects, three-dimensional (3D) printed interconnects, and/or anisotropic conductive film (ACF).
  • the package layer 2000 shows the second dies 2006-2008 disposed on the top surface 2020 of the first die 2005, where each of the dies 2005-208 are electrically coupled with interconnects 2003.
  • the package layer 2000 includes forming a second encapsulation layer 2012 around the second plurality of dies 2006-2008 and on the top surface 2002a of the first encapsulation layer 2002 (note that this may include portions of the top surfaces of the first plurality of dies 2005), according to one embodiment.
  • the second encapsulation layer 2012 e.g. , a stiff, opaque epoxy to protect the interconnects 2003
  • the dam 2010 filling up to a plurality of top surfaces 2020 of the top dies 2008 and then the second encapsulation layer 2012 is cured.
  • the package layer 2000 illustrates the second encapsulation layer 2012 formed around and over the edges of the second dies 2006-2008, interconnects 2003, and on the top surface 2002a of the first encapsulation layer 2002 (note that this may include portions of the top surface of the first die 2005).
  • the rounded angles (e.g., hill-shaped) of the top surface 2012a of the second encapsulation layer 2012 may increase and end (or plateau) at the top surface 2020 of the topmost die 2008 of the second plurality of dies 2006- 2008.
  • the package layer 2000 illustrates disposing a third plurality of dies 2009 on the top surfaces 2020 of the topmost dies 2008, according to one embodiment.
  • the third plurality of dies 2009 may be solar cells.
  • each of the third plurality of dies 2009 may be electrically coupled to the other stacked dies 2005-2008 with interconnects 2003, according to one embodiment.
  • the package layer 2000 shows the third die 2009 disposed above the second encapsulation layer 2012 and on the top surface 2020 of the die 2008.
  • the package layer 2000 includes forming a third encapsulation layer 2022 over and around the third plurality of dies 2009 and on the top surface 2012a of the second encapsulation layer 2012 (note that this may include portions of the top surfaces of the dies 2008), according to one embodiment.
  • the third encapsulation layer 2022 e.g., a transparent material to facilitate the third dies 2009
  • the dam 2010 filling up above the top surfaces 2020 of the third dies 2009 - but below the top level/height of the dam - and then the third encapsulation layer 2022 is cured.
  • the top surface 2022a of the third encapsulation layer 2022 may be compressed with a compression plunger (not shown) to flatten the top surface 2022a if needed. Note, however, that even if the top surface 2022a is compressed, the top surface 2022a may have a similar hill-shaped angle as the other encapsulation layers (e.g. , top surfaces 2002a and 2012a of the encapsulation layers 2002 and 2012). As such, after the third encapsulation layer 2022 is deposited, the package layer 2000 has formed a plurality of semiconductor packages 2045, according to some embodiments.
  • the package layer 2000 may have fiducial lines 2025 (shown as dashed lines) formed based on the set second of fiducials 2015 to facilitate the singulation of each of the plurality of semiconductor packages 2045 (e.g. , as an individual unit shown with the semiconductor package 2050).
  • the fiducial lines 2025 on the package layer 2000 form a plurality of individual semiconductor packages that were assembled (e.g., forty-eight individual semiconductor packages/units may be singulated, where each unit may be illustrated as semiconductor package 2050).
  • the semiconductor package 2050 may have the third encapsulation layer 2022 formed over and around the third die 2009, interconnects 2003, and on the top surface 2012a of the second encapsulation layer 2012 (note that this may include portions of the top surfaces of the die 2008).
  • the top surface 2022a of the third encapsulation layer 2022 may be compressed to flatten the top surface above the die 2009, but all of the surface 2022a of the third encapsulation layer 2022 may not be planar (i.e. , angled as the other top surfaces 2002a and 2012a of the encapsulation layers 2002 and 2012).
  • each of the semiconductor packages may now be singulated along the fiducials 2025 (shown with the dashed lines) to form each individual package.
  • the adhesive layer 2030 and the panel 2001 may then be removed (in either order), where the die 2005 may have an exposed bottom surface 2021, according to some embodiments.
  • surface treatments such as plasma
  • the resulting multi-material stack may have a meniscus atypical of molding (or encapsulation).
  • each of the encapsulation layers may rescind and form a curved upper surface (as shown with surface 2002a and 2012a of Figure 20F) and the upper encapsulation layers may have a larger curved upper surface than the lower curved upper surface (as shown with surface 2012a of Figure 20F compared to surface 2002a of Figure 20F), according to some embodiments.
  • a meniscus encapsulation shape for each of the encapsulation layers is unlike the flatten surface that is formed with a typical encapsulation process.
  • the process flow, as described above in Figures 20A - 20H, may also be leveraged by adding one or more packaging components, such as the PCB (e.g. , PCB 160 of Figure IB and/or the PCB of Figures 13 - 18), and/or the one or more antennas (e.g., antennas 1370, 1470, and 1570 of Figures 13 - 15) to re-distribute the signals or enable further features on the package.
  • the process flow illustrated in Figures 20A-20H may include fewer or additional packaging components based on the desired packaging design, including any combination and number of dies, interconnects, encapsulation layers, and encapsulation materials.
  • a plurality of dies e.g. , the first plurality of dies, the second plurality of dies, and the third plurality of dies
  • Figure 21 is a process flow illustrating a method of forming a package layer having a plurality of device packages, a plurality of interconnects, and one or more encapsulation layers that are stacked, according to one embodiment.
  • Figure 21 illustrates the process flow used to form a semiconductor package (e.g., semiconductor package 2050 of Figure 20H) with a dimension tolerant, multi-material stack, according to one embodiment.
  • the process flow 2100 may be similar to the method of forming a package layer (e.g., package layer 2000) having a plurality of semiconductor packages as shown in Figures 20A-H.
  • the process flow forms a panel with a first set of fiducials that are covered with an adhesive layer (as shown in Figure 20A).
  • the process flow disposes a dam on the adhesive layer and forms a set second of fiducials with a laser to denote singulation patterns (as shown in Figure 20B).
  • the process flow disposes a first plurality of dies on the adhesive layer (as shown in Figure 20C). For example, the first plurality of dies are disposed on the adhesive layer using the second set of fiducials to align each die within a prescribed array within the dam.
  • the process flow forms a first encapsulation layer around the first plurality of dies, where the first encapsulation layer is formed within the dam filling the dam up to a plurality of top surfaces of the first plurality of dies (as shown in Figure 20D).
  • the process flow disposes a second plurality of dies on the top surfaces of the first plurality of dies, where each of the dies may have one or more die contacts on a top surface and/or a bottom surface that are each electrically coupled to at least one die contact of another die with one or more interconnects (as shown in Figure 20E).
  • the second plurality of dies may include one or more different dies.
  • each of the stacked dies may be interconnected in a batch or one at a time, according to some embodiments.
  • the process flow forms a second encapsulation layer around the second plurality of dies and on the top surface of the first encapsulation layer, where the second encapsulation layer is formed within the dam filling the dam up to a plurality of top surfaces of the second plurality of dies (as shown in Figure 20F).
  • the process flow disposes a third plurality of dies on the top surfaces of the topmost dies of the second plurality of dies, where each of the third plurality of dies may be electrically coupled to the other stacked dies with the interconnects (as shown in Figure 20G).
  • the process flow forms a third encapsulation layer over and around the third plurality of dies and on the top surface of the second encapsulation layer, where here the third encapsulation layer is formed within the dam filling the dam over the top surfaces of the third plurality of dies but below the top level of the dam (as shown in Figure 20H).
  • the process flow singulates the plurality of semiconductor packages along one or more fiducial lines to form an individual semiconductor package. Note that at block 2145, the process flow may further remove the adhesive layer and the panel (in either order), where each of the first plurality of dies may have an exposed bottom surface, according to some embodiments.
  • the process flow 2100 may form a semiconductor package that may include fewer or additional packaging components based on the desired packaging design.
  • the semiconductor package may include any configuration needed, including additional encapsulation layers and any combination and/or number of dies, interconnects, and
  • Figures 22 illustrates a cross-sectional view of a semiconductor package 2200 having one or more substrates 2201-2210, one or more interconnects 2250, and one or more pillars 2230, according to one embodiment.
  • the semiconductor package 2200 includes stacked substrates 2201-2210 that may be formed vertically using interconnects 2250 and pillars 2230 - without using, for example, wire bonds, through silicon vias (TSVs), or through mold vias.
  • TSVs through silicon vias
  • the semiconductor package 2200 may implement a TSV-less die stacking of substrates 2201-2210 with pillars 2230 (also referred to as plated pillars), adhesive layers 2271, and interconnects 2250 for added
  • ultra-small form factor systems such as reducing the overall z-height and volume by circumventing TSV and/or wire bond stacked dies and interconnects.
  • the semiconductor package 2200 may implement a flip-chip process with interconnects 2250 along with one or more plated pillars 2230 to interconnect the various layers of substrates 2201 -2210, where the plated pillars 2230 are disposed on the periphery of two or more substrates 2201-2210 (e.g. , one plated pillar 2230 is formed at the periphery edges of substrates 2201 and 2204 as shown in Figure 22).
  • a "pillar" (or plated pillar) may refer to a conductive via formed to electrically couple one or more substrates/layers without the need for wire bonding or TSVs.
  • these longer pillars (e.g., pillars 2230 of Figure 22) help to connect the various layers/substrates of a semiconductor package.
  • the "pillar" may be formed using a copper pillar(s), where a photoresist layer is spun onto a wafer and
  • photolithography is then used to create arrays of wells/molds as the copper is then electroplated to form these longer pillars (e.g., reaching aspect ratios as high as 6: 1).
  • pillars 2230 may be formed to interconnect two or more substrates 2201-2210 having one pillar joined with another pillar with a solder bump 2235.
  • substrates 2201-2210 are stacked in layers with adhesive layers 2271 in between one or more substrates 2201-2210 (e.g., substrate 2202 is joined with substrate 2203 with adhesive layer 2271).
  • interconnects 2250 may be formed with two or more pads 2215 of two substrates 2201-2210 joined by a solder bump 2235.
  • substrate 2201 may be joined to substrate 2201 with four interconnects 2250 as substrate 2201 is then joined with substrate 2204 with pillars 2230.
  • substrates 2201-2210 may include, but are not limited to, semiconductor dies (e.g., processors, sensors, etc.), organic substrates (e.g. , PCBs), passive devices (e.g. , decoupling capacitors/power delivery inductors), MEMS devices, or any other types of components/devices.
  • semiconductor dies e.g., processors, sensors, etc.
  • organic substrates e.g., PCBs
  • passive devices e.g. , decoupling capacitors/power delivery inductors
  • MEMS devices e.g., MEMS devices
  • solder bumps 2235 may formed with solder, controlled collapse chip connection (C4) bumps, ACF, or other conductive layers/materials.
  • adhesive layers 2271 may be die-attach film or any other adhesive material.
  • the semiconductor package 2200 may have ten substrates 2201-2210 that are vertically attached with four pillars 2230 and a plurality of interconnects 2250 and four adhesive layers 2271.
  • the plurality of interconnects 2250 may include a plurality of pads 2215 and a plurality of solder bumps 2235.
  • the plurality of solder bumps 2235 may be used to interconnect the plurality of die pads 2215 (i.e., forming interconnects 2250) and the one or more pillars 2230.
  • each of the substrates 2201-2210 may have a top surface 2220 and a bottom surface 2221, where for example substrate 2202 may have a plurality of pads 2210 on the bottom surface 2221 of the substrate 2202 that are electrically coupled to a plurality of pads 2210 on the top surface 2220 of the substrate 2201, and an adhesive layer 2271 on the top surface 2220 of substrate 2202 that is attached to the bottom surface 2221 of substrate 2203.
  • pillars 2230 may be formed to interconnect substrate 2201 to substrate 2204, substrate 2203 to substrate 2206, substrate 2205 to substrate 2208, and substrate 2207 to substrate 2210. Note that each of the pillars 2230 may be used to interconnect more than two substrates.
  • adhesive layers 2271 may be formed between substrates 2202-2203, 2204-2205, 2206-2207, and 2208-2209. Also note that each substrate 2201-2210 may have interconnects 2250 on both surfaces, however to reduce the overall z-height of the package 2200, pads 2215 are only located on one of the surfaces of each substrate 2201-2210.
  • the method of forming the semiconductor package 2200 may be simplified and reduce the cost of the wafer manufacturing process. That is, by circumventing wire bonding, the semiconductor package 220 may enable more robust architecture(s) (without having to worry about damaging wires) and increase the number of interconnects per given volume. As shown in Figure 22, the semiconductor package 2200 using a flip-chip process allows the use of more of the substrate area for interconnects without having to grow the size of the substrate. Also, for some embodiments, only a few substrates (e.g., substrates 2201-2210) may need an increased number of interconnects (e.g.
  • interconnects may need a relatively small number of interconnects (e.g., 2-3 interconnects may be needed for an energy harvester or a battery, and 5-6 interconnects may be needed for sensors).
  • some of the additional advantages of using TSV-less die stacking with plated pillars are: (i) a lowered manufacturing cost as the use of TSVs in manufacturing of dies may increase cost; (ii) a reduction of manufacturing steps (i.e.
  • a reduction in complexity and difficulty) as the use of wire bonding are fragile and may need to be protected carefully to ensure they are not bent (which may cause shorts) or damaged (which may cause opens); (iii) a lowered overall volume of the package as the use of wire bonds, for example, increase the volume of the system by requiring the substrates to be offset from one another to accommodate the wire bond pads and, if more connections are needed, more wire bond pads must be added also increasing the volume of the package; and (iv) applicable for systems needing very low power systems as the use of wire bonds, for example, may likely have higher resistance and inductance.
  • the semiconductor package 2200 may include fewer or additional packaging components based on the desired packaging design, including any combination and number of substrates (dies, MEMS, and/or organic substrates), adhesive layers, interconnects, solder (or ACF), and pillars.
  • substrates dies, MEMS, and/or organic substrates
  • adhesive layers interconnects
  • solder or ACF
  • Figure 23 is a process flow 2300 illustrating a method of forming a semiconductor package having one or more substrates, one or more interconnects, and one or more pillars, according to one embodiment.
  • the process flow 2300 may be used to form a semiconductor package as shown in Figure 22 and 24-27.
  • the process flow 2300 may be implemented to form a TSV-less die stacking package with plated pillars, after the wafer has been grinded and the pillars have been formed to have a desired height(s).
  • the process flow forms a wafer on an adhesive layer (e.g., a die attach film (DAF)).
  • the process flow may form the wafer with DAF on a temporary carrier (e.g., a temporary adhesive, such as a UV release dicing tape).
  • a temporary carrier e.g., a temporary adhesive, such as a UV release dicing tape.
  • the process flow singulates the wafer into a plurality of substrates (layers or dies), where each substrate may have one or more pads formed on at least one of the surfaces of the substrate.
  • the process flow disposes a second substrate on a first substrate, where a first set of interconnects is formed to electrically couple the second substrate to the first substrate.
  • the process flow may use solder bumps or ACF to form the first set of interconnects between the pads of the first and second substrates to initialize the stack.
  • the process flow disposes a third substrate with the adhesive layer on the second substrate, where the adhesive layer attaches a bottom surface of the third substrate to a top surface of second substrate.
  • the process flow disposes a fourth substrate on the third substrate, where a second set of interconnects is formed to electrically couple the fourth substrate to the third substrate, where a first pillar is disposed between the fourth substrate and the first substrate.
  • the process flow may repeat (or return back to) the steps at blocks 2320 and 2325 one or more times to form additional, subsequent substrates on the existing stack of substrates (i.e. , the first to fourth substrates of the semiconductor package).
  • the semiconductor package of Figure 23 sets forth one embodiment used to form a TSV-less substrate stacking.
  • the semiconductor package formed by Figure 23 may include fewer or additional packaging components based on a desired packaging design, including any combination and number of substrates (dies, MEMS, and/or organic substrates), adhesive layers, interconnects, solder (or ACF), and pillars.
  • Figures 24-27 are cross-sectional views of semiconductor packages having one or more substrates, one or more interconnects, and one or more pillars, according to some embodiments.
  • the semiconductor packages 2400, 2500, 2600, and 2700 of Figures 24-27 are similar to the semiconductor package 2200 of Figure 22, however these semiconductor packages 2400, 2500, 2600, and 270 have one or more alternative configurations for each TSV-less substrate stacking using platted pillars.
  • a semiconductor packages (as shown below in Figures 24-27) may have a stack of semiconductor dies and organic substrates, a stack interconnected with ACF, and a stack interconnects with adhesive layers (e.g., DAFs) and a smaller number of interconnects.
  • adhesive layers e.g., DAFs
  • a semiconductor package 2400 may have one or more substrates 2401-2404, a plurality of interconnects 2450, and platted pillars 2430.
  • the semiconductor package 2400 may have four substrates (or any number of substrates), where the substrate 2401 is a first die, the substrate 2402 is a second die, the substrate 2403 is an organic substrate, and the substrate 2404 is a MEMs device.
  • the semiconductor packages may include a combination of dies, organic substrates, MEMs devices, and any other type of components that may serve a variety of purposes.
  • the substrates 2402-2403 may be attached with an adhesive layer 2471 , while the other substrates are interconnected with the plurality of interconnects 2450 and the platted pillars 2430.
  • the interconnects 2450 may include a plurality of solder bumps 2435 formed in between one or more pads 2415.
  • a semiconductor package 2500 may have one or more substrates 2501-2504, a plurality of interconnects 2550, and platted pillars 2530.
  • the semiconductor package 2500 may have four substrates (or any number of substrates), where the substrate 2501 is an organic substrate and the substrates 2502-2504 are dies.
  • the semiconductor package 2500 does not have to be a stand-alone system. That is, for example, the semiconductor package 2500 may be attached to an organic substrate and then surface-mounted to a board or any other system with a plurality of solder bumps 2545.
  • the semiconductor package 2500 may have the stack be embedded into an organic substrate either as standalone or with interconnects 2513 within the organic substrate.
  • the substrates 2502-2503 may be attached with an adhesive layer 2571 , while the other substrates are interconnected with the plurality of interconnects 2550 and the plated pillars 2530.
  • the interconnects 2550 may include a plurality of solder bumps 2535 formed in between one or more pads 2515.
  • a semiconductor package 2600 may have one or more substrates 2601 -2604, one or more interconnects 2655, and plated pillars 2630.
  • the semiconductor package 2600 may have four substrates (or any number of substrates), where each of the substrates 2601-2604 are dies (note that the substrate may also be organic substrates and MEMs devices).
  • the semiconductor package 2600 may have one or more interconnects 2655 formed between the pads 2715 and the substrates 2601 -2602 and 2603-2604 using ACF (or any other materials).
  • each of these interconnects 2655 may be formed with two or more pads of two substrates coupled with an ACF layer (rather than using a solder bump).
  • these systems may generally only need very few interconnects at very low powers ( ⁇ 10) as the interconnects tend to carry very low currents.
  • the substrates 2602-2603 may be attached with an adhesive layer 2671, while the other substrates 2601 and 2604 are interconnect with the platted pillars 2630 that may have a solder pump 2635 formed between (or joining) the pillars 2630.
  • a semiconductor package 2700 may have one or more substrates 2701-2704, one or more interconnects 2750, and plated pillars 2730.
  • the semiconductor package 2700 may have four substrates (or any number of substrates), where each of the substrates 2701-2704 are dies (note that the substrate may also be organic substrates, MEMs devices, sensors, LEDs and/or solar cells, etc.).
  • the semiconductor package 2700 may have a small number of interconnects 2750 as such it may be possible to use one or more adhesive layers 2771 (e.g., DAFs) as the main attach and use the pillars 2730 as the sole interconnects.
  • adhesive layers 2771 e.g., DAFs
  • the substrates 2701-2704 may be stacked/formed with one or more adhesive layers 2771 in between the substrates using one or more solder bumps 2735 to interconnect the one or more interconnects 2750 and pillars 2730.
  • the interconnects 2750 may include solder bumps 2735 formed in between one or more pads 2715.
  • semiconductor packages 2400, 2500, 2600, and 2700 of Figures 24-27 may include fewer or additional packaging components based on the desired packaging design, including any combination and number of substrates (dies, MEMS, and/or organic substrates), adhesive layers, interconnects, solder (or ACF), and pillars.
  • substrates dies, MEMS, and/or organic substrates
  • adhesive layers interconnects
  • solder or ACF
  • Figure 28 is a schematic block diagram illustrating a computer system that utilizes a device package, as described herein.
  • Figure 28 illustrates an example of computing device 2800.
  • Computing device 2800 houses motherboard 2802.
  • Motherboard 2802 may include a number of components, including but not limited to processor 2804, device package 2810 (e.g. , semiconductor packages of Figures 1-27), and at least one communication chip 2806.
  • Processor 2804 is physically and electrically coupled to motherboard 2802.
  • at least one communication chip 2806 is also physically and electrically coupled to motherboard 2802.
  • at least one communication chip 2806 is part of processor 2804.
  • computing device 2800 may include other components that may or may not be physically and electrically coupled to motherboard 2802. These other components include, but are not limited to, volatile memory (e.g. , DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g. , DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna,
  • At least one communication chip 2806 enables wireless communications for the transfer of data to and from computing device 2800.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • At least one communication chip 2806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • Computing device 2800 may include a plurality of communication chips 2806.
  • a first communication chip 2806 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 2806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • Processor 2804 of computing device 2800 includes an integrated circuit die packaged within processor 2804.
  • Device package 2810 may be, but is not limited to, silicon dies (e.g., dies with an ultra-small form factor), a packaging substrate, and/or a printed circuit board.
  • Device package 2810 may include dies and interconnects that are adjacent to a PCB, where the device package 2810 further includes one or more encapsulation layers over the dies, interconnects, and the PCB.
  • the device package 2810 may be an ultra-small form factor (SFF) system using a printed circuit board (PCB) as an encapsulation base, where the PCB may include plated pillars, multi-encapsulation layers, and double-sided interconnects (as shown in Figures 1-27).
  • SFF ultra-small form factor
  • PCB printed circuit board
  • device package 2810 may be a single component or a subset of components of the computing device 2800, or the device package 2810 may be an entire stand-alone system that operates
  • the integrated circuit die may be packaged with one or more devices on the device package 2810 that include a thermally stable RFIC and antenna for use with wireless communications.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • At least one communication chip 2806 also includes an integrated circuit die packaged within the communication chip 2806.
  • the integrated circuit die of the communication chip may be packaged with one or more devices on the device package 2810, as described herein.
  • Example 1 is a method of forming a package layer, comprising disposing a first plurality of dies in a cavity of a dam formed on the adhesive layer, wherein each die has a top surface and a bottom surface that is opposite from the top surface; forming a first encapsulation layer around the first plurality of dies in the cavity of the dam, wherein the first encapsulation layer is formed below the top surfaces of the first plurality of dies; disposing a second plurality of dies on the top surfaces of the first plurality of dies, wherein each of the dies may have one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of another die with one or more interconnects; forming a second encapsulation layer around the second plurality of dies, the one or more interconnects, and on a top surface of the first encapsulation layer in the cavity of the dam, wherein the second encapsulation layer is formed below the top surfaces of the topmost dies of the
  • example 2 the subject matter of example 1 can optionally include that prior to disposing the first plurality of dies, further comprising: disposing the dam with the cavity on the adhesive layer; and forming one or more fiducials on the adhesive layer and adjacent to an outer surface of the dam, wherein the one or more fiducials are aligned to form a plurality of compartments within the cavity.
  • any of examples 1-2 can optionally include that after the third over encapsulation layer is formed, further comprising: severing the encapsulation layers along the compartments within the cavity to form a plurality of semiconductor packages; and removing the adhesive layer.
  • any of examples 1-3 can optionally include the one or more interconnects comprising wire bonds, through silicon vias, through mold vias, inkjet printed, three-dimensional (3D) printed, and anisotropic conductive film (ACF).
  • the one or more interconnects comprising wire bonds, through silicon vias, through mold vias, inkjet printed, three-dimensional (3D) printed, and anisotropic conductive film (ACF).
  • any of examples 1-4 can optionally include prior to severing the encapsulation layers, further comprising: compressing a top surface of the third encapsulation layer in the cavity of the dam; and forming a coating on the top surface of the third encapsulation layer to electrically isolate the top surface of the third encapsulation layer.
  • any of examples 1-5 can optionally include the top surface of each of the encapsulation layers has a curved shape.
  • any of examples 1-6 can optionally include the first encapsulation layer formed with a first set of materials, the second encapsulation layer formed with a second set of materials, and the third encapsulation layer formed with a third set of materials.
  • any of examples 1-7 can optionally include the first set of materials, the second set of materials, and the third set of materials are different from each other, and wherein each of the encapsulation layers may have one or more different shapes, including a hemispherical shape, a capsule-like shape, a honeycombed shape, a round shape, and a dimple shape.
  • each of the first plurality of dies has an exposed bottom surface.
  • any of examples 1-9 can optionally include the plurality of dies comprising a semiconductor die, a memory, a processor, a decoupling capacitor, a radio device, an energy harvesting device, a battery, and a sensor.
  • the subject matter of any of examples 1-10 can optionally include the third encapsulation layer is a transparent encapsulation layer.
  • Example 12 is a device package, comprising a plurality of dies disposed on top of one another to form a stack, wherein each die has a top surface and a bottom surface that is opposite from the top surface, wherein each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of another die with one or more interconnects; and one or more encapsulation layers deposited over and around the plurality of dies and the one or more interconnects, wherein each of the one or more encapsulation layers are formed with a different set of materials.
  • example 13 the subject matter of example 12 can optionally include that prior to disposing the first plurality of dies, further comprising a dam with a cavity is disposed on the adhesive layer; and one or more fiducials are formed on the adhesive layer and adjacent to an outer surface of the dam, wherein the one or more fiducials are aligned to form a plurality of compartments within the cavity.
  • any of examples 12-13 can optionally include the one or more encapsulation layers having a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, wherein the first encapsulation layer is formed around the first plurality of dies in the cavity of the dam, wherein the first encapsulation layer is formed below the top surfaces of the first plurality of dies, wherein the second encapsulation layer is formed around the second plurality of dies, the one or more interconnects, and on a top surface of the first encapsulation layer in the cavity of the dam, wherein the second encapsulation layer is formed below the top surfaces of the topmost dies of the second plurality of dies, and wherein the third encapsulation layer is formed over and around the third plurality of dies, the one or more remaining interconnects, and a top surface of the second encapsulation layer in the cavity of the dam.
  • any of examples 12-14 can optionally include the one or more interconnects formed with wire bonds, through silicon vias, through mold vias, inkjet printed, three-dimensional (3D) printed, and anisotropic conductive film (ACF).
  • ACF anisotropic conductive film
  • any of examples 12-15 can optionally include that after depositing the third encapsulation layer, further comprising a coating is formed on the top surface of the third encapsulation layer to electrically isolate the top surface of the third encapsulation layer.
  • the top surface of the third encapsulation layer is compressed.
  • any of examples 12-16 can optionally include the top surface of each of the encapsulation layers has a curved shape.
  • any of examples 12-17 can optionally include the first encapsulation layer formed with a first set of materials, the second encapsulation layer formed with a second set of materials, and the third encapsulation layer formed with a third set of materials.
  • the first set of materials, the second set of materials, and the third set of materials are different from each other.
  • the third encapsulation layer is a transparent encapsulation layer.
  • each of the first plurality of dies has an exposed bottom surface.
  • any of examples 12-19 can optionally include the plurality of dies comprising a semiconductor die, a memory, a processor, a decoupling capacitor, a radio device, an energy harvesting device, a battery, and a sensor.
  • Example 21 is a package layer, comprising a dam with a cavity formed on an adhesive layer; a plurality of device packages disposed on the cavity of the dam, wherein each of the device packages includes a plurality of dies disposed on top of one another to form a stack, wherein each die has a top surface and a bottom surface that is opposite from the top surface, and wherein each die has one or more die contacts on at least one of the top surface and the bottom surface; a plurality of interconnects electrically coupling the one or more die contacts of each die to at least one die contact of another die; and one or more encapsulation layers deposited over and around the plurality device packages, the plurality of interconnects, and the adhesive layer.
  • example 22 the subject matter of example 21 can optionally include the plurality of dies of each device package having a bottommost die, a set of dies, and topmost die, wherein each of the dies are stacked having the set of dies disposed between the bottommost die and the topmost die.
  • any of examples 21 -22 can optionally include the one or more encapsulation layers having a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer is formed around the bottommost dies in the cavity of the dam.
  • the first encapsulation layer is formed below the top surfaces of the bottommost dies.
  • the second encapsulation layer is formed around the set of dies, one or more interconnects, and on a top surface of the first encapsulation layer in the cavity of the dam.
  • the second encapsulation layer is formed below the top surfaces of the topmost dies of the set of dies.
  • the third encapsulation layer is formed over and around the topmost dies, the one or more remaining interconnects, and a top surface of the second encapsulation layer in the cavity of the dam.
  • any of examples 21 -23 can optionally include the one or more interconnects comprising wire bonds, through silicon vias, through mold vias, inkjet printed, three-dimensional (3D) printed, and anisotropic conductive film (ACF).
  • the one or more interconnects comprising wire bonds, through silicon vias, through mold vias, inkjet printed, three-dimensional (3D) printed, and anisotropic conductive film (ACF).
  • each of the encapsulation layers has a curved shape.
  • the first encapsulation layer is formed with a first set of materials
  • the second encapsulation layer is formed with a second set of materials
  • the third encapsulation layer is formed with a third set of materials.
  • the first set of materials, the second set of materials, the third set of materials are different from each other, and wherein the third encapsulation layer is a transparent encapsulation layer.
  • Each of the encapsulation layers may have one or more different shapes, including a hemispherical shape, a capsule-like shape, a honeycombed shape, a round shape, and a dimple shape.

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Abstract

L'invention concerne un procédé de formation d'une couche de boîtier consistant à disposer des matrices dans une cavité d'un barrage formé sur la couche adhésive, à former une première couche d'encapsulation autour des matrices dans la cavité du barrage, la première couche d'encapsulation étant formée sous les surfaces supérieures des premières matrices, et à disposer des deuxièmes matrices sur les surfaces supérieures des premières matrices. Le procédé consiste en outre à former une deuxième couche d'encapsulation autour des deuxièmes matrices, les interconnexions, et sur une surface supérieure de la première couche d'encapsulation dans la cavité, la deuxième couche d'encapsulation étant formée sous les surfaces supérieures des matrices situées le plus en haut parmi les deuxièmes matrices, à disposer des troisièmes matrices sur les surfaces supérieures des matrices situées le plus en haut des deuxièmes matrices, et à former une troisième couche d'encapsulation sur les troisièmes matrices, sur les interconnexions restantes, et sur une surface supérieure de la deuxième couche d'encapsulation, et autour de ceux-ci, dans la cavité.
PCT/US2017/054671 2017-09-30 2017-09-30 Empilement de matériaux multiples à tolérance de dimensions WO2019066987A1 (fr)

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IT202000002758A1 (it) 2020-02-12 2021-08-12 Getters Spa Getter distribuibile ad alta capacità
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11749576B2 (en) 2018-03-27 2023-09-05 Analog Devices International Unlimited Company Stacked circuit package with molded base having laser drilled openings for upper package
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

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US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US11749576B2 (en) 2018-03-27 2023-09-05 Analog Devices International Unlimited Company Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
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