WO2019061779A1 - 一种阵列基板、掩膜板及阵列基板制作方法 - Google Patents

一种阵列基板、掩膜板及阵列基板制作方法 Download PDF

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Publication number
WO2019061779A1
WO2019061779A1 PCT/CN2017/112849 CN2017112849W WO2019061779A1 WO 2019061779 A1 WO2019061779 A1 WO 2019061779A1 CN 2017112849 W CN2017112849 W CN 2017112849W WO 2019061779 A1 WO2019061779 A1 WO 2019061779A1
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layer
array substrate
grid
insulating layer
bump
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PCT/CN2017/112849
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English (en)
French (fr)
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刘兴华
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武汉华星光电技术有限公司
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Priority to US15/740,267 priority Critical patent/US20190096918A1/en
Publication of WO2019061779A1 publication Critical patent/WO2019061779A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the invention belongs to the technical field of flat panel display, and particularly relates to an array substrate, a mask panel and a method for fabricating an array substrate.
  • Low temperature poly-silicon (LTPS) thin film transistor liquid crystal display uses excimer laser as a heat source in the packaging process. After the laser light passes through the projection system, a laser beam with uniform energy distribution is generated and projected onto the amorphous silicon. On the glass substrate of the structure, when the amorphous silicon structure glass substrate absorbs the energy of the excimer laser, it will be transformed into a polysilicon structure. Its biggest advantage is that it is ultra-thin, light in weight, low in power consumption, and can provide more brilliant colors and more. Clear image.
  • the closed structure of the LTPS display in the industry usually includes a flat layer covering the source/drain, the flat layer photoresist film is 2.5 um thick, and the uniformity of the flat photoresist film after baking is within 10%, which can ensure the transmittance requirement.
  • the uniformity of the flat photoresist film after baking is within 10%, which can ensure the transmittance requirement.
  • optical standards due to the planar structure design of the flat layer, the reflectivity of the inner surface facing the backlight is low, the demand for backlight is large, and the cost is high.
  • the outer surface of the flat layer designed by the planar structure is likely to cause reflection and affect the viewing screen effect.
  • the present invention provides an array substrate.
  • the specific technical solutions are as follows:
  • An array substrate comprising a substrate, a thin film transistor layer disposed on the substrate, and a planar layer disposed above the thin film transistor layer;
  • the flat layer is formed with a bump on a side surface away from the thin film transistor layer.
  • the bump is one or more of a hemispherical shape, a semi-elliptical shape, and a tetrahedral shape.
  • the hemispherical bumps have a diameter of 5-6 ⁇ m.
  • the bumps are formed with regular concave and convex surfaces, and the subsequent layers maintain a regular concave and convex surface.
  • the concave and convex surfaces form a diffuse reflection layer, thereby improving the light reflectance, reducing the backlight requirement, and also weakening the surface.
  • the display surface is reflective and the viewing effect is better.
  • the thin film transistor layer comprises:
  • a buffer layer disposed on the substrate
  • An active layer disposed on the buffer layer
  • a gate insulating layer disposed on the buffer layer and covering the active layer
  • An interlayer insulating layer provided on the gate insulating layer and covering the gate, and a metal source/drain provided on the interlayer insulating layer.
  • a surface of the flat layer away from a side of the thin film transistor layer is further formed with a pit, and the pit and the bump are alternately disposed.
  • the pits and the bumps are excessively connected by a curve.
  • the spacing between the bumps is smaller than the width of the bumps.
  • the height from the lowest point of the pit to the highest point of the bump is 0.7-1.3 ⁇ m.
  • the present invention also provides a mask comprising an opaque region and a permeable region, wherein the opaque region and the permeable region are periodically spaced apart from each other, the permeable region It is a light transmitting area or a semi-light transmitting area.
  • the opaque region and the permeable region are distributed in an approximately honeycomb structure
  • the approximate honeycomb structure comprises a black grid
  • the black grid is separated by a white edge
  • the black grid is an opaque region.
  • the white edge is the region where the light transmissive region is located
  • the black grid is a square with a side length of 5-7 ⁇ m, and the width of the white edge is smaller than the side length of the black grid.
  • the opaque region and the permeable region are arranged in a checkerboard structure
  • the checkerboard structure comprises a black grid and a white grid
  • the black grid and the white grid are alternately arranged at intervals, and the black grid is not In the region where the light transmitting region is located
  • the white grid is the region where the light transmissive region is located
  • the black grid is a square with a side length of 5-7 ⁇ m
  • the white grid is a square with a side length of 5-7 ⁇ m.
  • the invention also provides a method for fabricating an array substrate, the method comprising the steps of:
  • a bump formed by the reticle method and the mask method adopts the mask plate described above, and the mask plate is placed above the flat layer, and is formed by a yellow light and an etching process. The bump.
  • the active layer is formed by depositing an amorphous silicon layer on the buffer layer, then converting the amorphous silicon layer into a polysilicon layer and patterning to form a polysilicon segment, and forming source/drain contact regions at both ends of the polysilicon segment.
  • the flat layer of the product is formed into a regular uneven surface so that the subsequent layers maintain a regular uneven surface.
  • it can effectively improve the diffuse reflection of light, reduce the requirement of backlight under the light intensity; reduce the energy consumption, effectively improve the endurance of the product, prolong the service life of the backlight component, and reduce the cost of the backlight component.
  • the light of the backlight illuminates the opposite side of the uneven layer of the flat layer, the light of the backlight will reflect and refract on the opposite side of the bump, thereby increasing the brightness of the light, thereby reducing the backlight requirement.
  • 1 is a schematic view of an array substrate according to a first embodiment of the present invention; wherein 1 is a substrate, 2 is a buffer layer, 3 is a gate insulating layer, 4 is an interlayer insulating layer, 5 is a flat layer, and 51 is a flat layer.
  • the upper bumps, 52 are edge grooves on the flat layer, 61 is a polysilicon segment, 62 is a gate, 63 is a metal source/drain, 64 is a metal line, and 65 is a source/drain contact region.
  • FIG. 2 is a schematic diagram of a diffuse reflection path of light rays irradiated to the array substrate of FIG. 1 by external light.
  • FIG. 3 is a schematic diagram of a mask design for fabricating the array substrate shown in FIG. 1, wherein 70 is a mask, 71 is a black grid, and 72 is a white edge.
  • FIG. 4 is a representation of the product produced according to the mask design of FIG. 3, wherein 51 is a bump and 52 is an edge groove.
  • FIG. 5 is a schematic diagram of a light diffusing emission path of an array substrate according to a second embodiment of the present invention, wherein 8 denotes a flat layer, 51 denotes a bump, and 82 denotes a pit.
  • FIG. 6 is a schematic diagram showing the design of a mask for fabricating the array substrate shown in FIG. 5, wherein 91 is a black grid and 92 is a white grid.
  • Figure 7 is a representation of the product produced according to the mask design of Figure 6, wherein 51 is a bump and 82 is a pit.
  • Figure 8 is a flow chart of manufacturing an array substrate of the present invention.
  • FIG. 1 is an array substrate according to a first embodiment of the present invention.
  • the array substrate includes a substrate 1, a thin film transistor layer (not shown) disposed on the substrate 1, and a planar layer 5 disposed above the thin film transistor layer, wherein the planar layer 5 is away from the thin film transistor layer A bump 51 is formed on one surface.
  • the thin film transistor layer includes: a buffer layer 2 disposed on the substrate 1, an active layer (not shown) disposed on the buffer layer 1, and an active layer included in the The buffer layer 2 faces away from the polysilicon segment 61 on the surface of the substrate 1 and the source/drain contact regions 65 disposed on the buffer layer 2 at opposite ends of the polysilicon segment 61.
  • the array substrate further includes a gate insulating layer 3 disposed on the surface of the buffer layer 2 facing away from the substrate 1 and covering the active layer, and disposed on the surface of the gate insulating layer 3 facing away from the buffer layer 2
  • the gate electrode 62 and the interlayer insulating layer 4 provided on the surface of the gate insulating layer 3 facing away from the buffer layer 2 and covering the gate electrode 62.
  • the array substrate further includes a metal source/drain 63 disposed on the surface of the interlayer insulating layer 4 facing away from the gate insulating layer 3, and a surface of the interlayer insulating layer 4 facing away from the gate insulating layer 3 and coated with a metal source/ The flat layer 5 of the drain 63.
  • the buffer layer 2 further includes a device light shielding layer, and the device light shielding layer is located under the active layer to protect the active layer from being irradiated by the backlight for a long time. The problem that can be reduced.
  • the metal source/drain 63 is electrically connected to the source/drain 65 by a metal line 64 passing through the interlayer insulating layer 4.
  • the polysilicon section 61, the source/drain contact region 65, the gate electrode 62, and the metal source/drain 63 together constitute a driving TFT.
  • the flat layer 5 is bent away from the surface of the interlayer insulating layer 4 to form a bump 51 so that the surface of the flat layer 5 has an uneven surface.
  • the uneven surface formed by the bump 51 diffuses the external light, and at the same time, when the light emitted by the backlight B passes through
  • the inside of the uneven surface formed by the bumps 51 diffuses the light emitted from the backlight to improve the backlight light reflection.
  • the rate in this way, while reducing the backlight demand, it also weakens the reflective surface of the display screen, and the viewing effect is better.
  • the bumps 51 are hemispherical, and the two adjacent bumps 51 are spaced apart from each other. As shown in FIG. 4, adjacent to the two bumps 51 along the X-axis direction or the Y-axis direction. The separation distance is smaller than the width of the bump 51.
  • the bumps described in the present invention may be regular patterns such as a semi-elliptical shape and a tetrahedral shape. As long as they are arranged in a regular manner, they may be alternately arranged in a semi-elliptical shape, a tetrahedral shape, or a mixture of different shapes. For example, in the X-axis direction or the Y-axis direction, the semi-elliptical bumps and the four-sided pyramid-shaped bumps are alternately arranged.
  • the bumps 51 are periodically and uniformly distributed to make the light passing through the flat layer 5 and the light scattered through the flat layer 5 more uniform, thereby obtaining a better viewing effect (as shown in FIG. 2).
  • the second embodiment provided by the present invention is a further improvement based on the first embodiment. Specifically, in order to make the external light and the light emitted by the backlight form a substantially equivalent scattering effect, A concave portion 82 is formed in a substantially hemispherical shape between the adjacent two bumps 51.
  • the bumps 51 When viewed from the side of the flat layer 5 away from the interlayer insulating layer 4, the bumps 51 form a periodically distributed convex surface and the pits 82 form a periodically distributed concave surface; when approaching the interlayer insulating layer 4 from the planar layer 5 When viewed from one side, the pits 82 form a periodically distributed convex surface and the bumps 51 form a concave surface having a periodic facet, thus forming a regular uneven surface.
  • the bumps 51 and the pits 82 are excessively joined by a curve.
  • the pit 82 has a hemispherical shape that is recessed downward. It is to be understood that the pit 82 is not limited to a hemisphere, and may be one or more of a semi-elliptical sphere and a tetrahedral cone.
  • the hemispherical shape of the bump 51 has a diameter of 5-6 ⁇ m. According to the current size specification of each pixel, it is a preferred technical solution to make the hemispherical diameter of the bump 51 into the above specifications.
  • the height from the lowest point of the pit 82 to the highest point of the bump is 0.7-1.3 ⁇ m.
  • the present invention also provides a mask 70.
  • the mask 30 includes an opaque region and a permeable region, and the opaque region and the permeable region are periodically spaced apart from each other.
  • the light transmissive area is a light transmissive area or a semi-transmissive area.
  • a first mask 70 is provided, wherein the opaque region and the permeable region of the mask 70 are distributed in an approximately honeycomb structure.
  • the approximate honeycomb structure includes a black grid 71, the black grid 71 is spaced apart by a white edge 72, the black grid 71 is the area where the opaque region is located, and the white edge 72 is the region where the light permeable region is located;
  • the black grid 71 is a square having a side length of 5-7 ⁇ m, and the width of the white edge 72 is smaller than the side length of the black grid.
  • the mask of the present embodiment adopts an arrangement of an approximately honeycomb structure, so that the target product adopts the concave and convex surface of the mask plate which is formed by the reticle process.
  • the present invention provides a method for fabricating a first array substrate, comprising the following steps:
  • S4 forming a source/drain contact region 65 at both ends of the polysilicon segment 61, and subsequently forming a gate insulating layer 3, a gate electrode 62, an interlayer insulating layer 4, a metal source/drain 63, and a flat layer 5;
  • a bump 5 is formed on the side of the flat layer 5 away from the metal source/drain 63 by a photomask method.
  • the bump 5 is hemispherical; the photomask method adopts the first mask 70 described above, and the mask 70 is placed above the flat layer 5
  • the yellow light and the etching process form the bump 51 and the edge groove 52 of the spacer bump 51.
  • the array substrate as described in FIG. 1 is prepared by the method.
  • a second mask 90 is provided.
  • the opaque region and the permeable region of the mask 90 are arranged in a checkerboard structure.
  • the checkerboard structure includes a black grid 91 and a white grid 92, wherein the black grid 91 and the white grid 92 are spaced apart from each other, the black grid 91 is the area where the opaque zone is located, and the white grid 92 is the area where the permeable zone is located;
  • the black grid 91 is a square having a side length of 5-7 ⁇ m, and the white grid 92 is a square having a side length of 5-7 ⁇ m.
  • the mask of the embodiment adopts a checkerboard structure to enable the target product to adopt the mask to perform the mask process to form the uneven surface of the unevenness.
  • the present invention provides a method for fabricating a second array substrate, which is substantially the same as the method for fabricating the first array substrate, except that the photomask method in the step S5 is in this embodiment.
  • the reticle method is to use the second mask 90 described above, and the mask 90 is placed above the flat layer 5, and the bumps 51 and the pits 82 are formed by a yellow light or etching process. .
  • An array substrate comprising the flat layer structure as described in FIG. 5 is prepared by the method.

Abstract

提供一种阵列基板，包括基板（1）、设置基板（1）上的薄膜晶体管层以及设于薄膜晶体管层上方的平坦层（5）；平坦层（5）远离薄膜晶体管层的一侧表面形成有凸点（51）。通过设置凸点（51），通过平坦层（5）表面的凸点（51）形成漫反射层，可以弱化反光现象和降低背光需求。还提供一种掩膜板以及利用该掩膜板来制备阵列基板的方法。

Description

一种阵列基板、掩膜板及阵列基板制作方法
本发明要求2017年9月27日递交的发明名称为“一种阵列基板、掩膜板及阵列基板制作方法”的申请号201710892062.1的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明属于平板显示技术领域，具体涉及一种阵列基板、掩膜板及阵列基板制作方法。
背景技术
低温多晶硅(Low Temperature Poly-silicon；简称LTPS)薄膜晶体管液晶显示器是在封装过程中，利用准分子镭射作为热源，镭射光经过投射系统后，会产生能量均匀分布的镭射光束，投射于非晶硅结构的玻璃基板上，当非晶硅结构玻璃基板吸收准分子镭射的能量后，会转变成为多晶硅结构，它的最大优势在于超薄、重量轻、低耗电，可以提供更艳丽的色彩和更清晰的影像。业内LTPS显示器的封闭结构通常包括一用于覆盖源/漏极的平坦层，平坦层光阻膜厚2.5um，烘烤后平坦光阻膜厚均一性在10％以内，可保证穿透率需求，从而满足光学标准。在目前LTPS技术下，因平坦层采用平面结构设计，导致面向背光源的内表面反射率偏低，需求背光量大，成本较高。与此同时，在外部光线比较强的情况下，采用平面结构设计的平坦层的外表面很容易造成反光而影响观看视屏效果。
发明内容
为解决现有显示屏平面结构而造成反射率偏低、反光等问题，本发明提供一种阵列基板，具体技术方案如下：
一种阵列基板，包括基板、设在所述基板上的薄膜晶体管层以及设于所述薄膜晶体管层上方的平坦层；
所述平坦层远离所述薄膜晶体管层的一侧表面形成有凸点。
优选的，所述凸点为半球形、半椭圆形、四面锥形中的一种或者多种。
优选的，所述半球形的凸点的直径大小为5-6μm。
上述凸点形成有规则性凹凸面，后续各层保持规则的凹凸面，当外界光线照射在显示屏上时，凹凸面形成漫反射层，从而提高光线反射率，降低背光需求，同时也弱化了显示屏面反光现象，观看效果更佳。
优选的，所述薄膜晶体管层包括：
设于所述基板上的缓冲层；
设于所述缓冲层上的有源层；
设于所述缓冲层上并包覆所述有源层的栅极绝缘层；
设于所述栅极绝缘层上的栅极；
设于所述栅极绝缘层上并包覆所述栅极的层间绝缘层，以及设于层间绝缘层上的金属源/漏极。
优选的，所述平坦层远离所述薄膜晶体管层的一侧的表面还形成有凹点，所述凹点和所述凸点交替设置。
优选的，所述凹点与所述凸点之间通过曲线过度衔接。
优选的，所述凸点之间的间距小于所述凸点的宽度。
优选的，所述凹点的最低点到所述凸点最高点的高度为0.7-1.3μm。
本发明还提供一种掩膜板，所述掩膜板包括不透光区和可透光区，所述不透光区和可透光区相互间隔呈周期性布置，所述可透光区为透光区或者半透光区。
优选的，所述不透光区和可透光区呈近似蜂窝状结构分布，所述近似蜂窝状结构包括黑色格，所述黑色格通过白色边缘间隔开，所述黑色格为不透光区所在区域，所述白色边缘为可透光区所在区域；所述黑色格为边长为5-7μm的方格，所述白色边缘的宽度小于黑色格的边长。
优选的，所述不透光区和可透光区呈棋盘式结构分布，所述棋盘式结构包括黑色格和白色格，所述黑色格和白色格相互间隔交错设置，所述黑色格为不透光区所在区域，所述白色格为可透光区所在区域；所述黑色格为边长为5-7μm的方格，所述白色格为边长为5-7μm的方格。
本发明还提供一种阵列基板的制作方法，该方法包括步骤：
提供基板；依次在基板上沉积缓冲层、有源层，后续依次形成栅极绝缘层、栅极、层间绝缘层、金属源/漏极、平坦层，在所述平坦层远离金属源/漏极的一面上通过光罩法做成有凸点，所述光罩法是采用了上面所述的掩膜板，将所述掩膜板置于平坦层的上方，通过黄光、蚀刻制程形成所述凸点。
优选的，所述有源层是在缓冲层沉积非晶硅层，然后使非晶硅层转变成多晶硅层并图案化形成多晶硅段，并在多晶硅段两端形成源/漏极接触区。
本发明的有益效果：
(1)将产品平坦层做成有规则的凹凸面，从而使后续各层保持规则的凹凸面。在规定视角内可有效提高光线漫反射，降低在光强下背光量的需求；降低能耗，针对产品可有效提高产品电源续航能力，延长背光部件使用寿命，并降低背光部件成本等。当背光源的光线会照射的平坦层凹凸点的反面时，背光源的光线在凹凸点的反面会有反射和折射现象，从而增加了光线亮度，进而降低了背光需求。
(2)改善显示屏表面在外部光线比较强的情况下反光严重的问题，使显示屏图像更清晰，观看效果更佳。
(3)且采用凹凸点排列方式更易做出漫反射镜面，工艺上更易实现。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施例中的阵列基板的示意图；其中，1为基板，2为缓冲层，3为栅极绝缘层，4为层间绝缘层，5为平坦层，51为平坦层上的凸点，52为平坦层上的边缘凹槽，61为多晶硅段，62为栅极，63为金属源/漏极，64为金属线，65为源/漏极接触区。
图2为外界光线照射到图1中的阵列基板的光线漫反射路线示意图。
图3为制作图1所示的阵列基板的掩膜板设计图形简图，其中70为掩膜板，71为黑色格，72为白色边缘。
图4为根据图3中的掩膜板设计制作得到的产品呈现图，其中51为凸点，52为边缘凹槽。
图5为本发明第二实施例中的阵列基板的光线漫发射路线示意图，其中8表示平坦层，51表示凸点，82为凹点。
图6为制作图5所示阵列基板的掩膜板设计图形简图，其中91为黑色格，92位白色格。
图7为根据图6中的掩膜板设计制作得到的产品呈现图，其中51为凸点，82为凹点。
图8为本发明制造阵列基板的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1为本发明第一实施例提供的一种阵列基板。该阵列基板包括基板1、设在所述基板1上的薄膜晶体管层(图中未示出)以及设于薄膜晶体管层上方的平坦层5，在所述平坦层5远离所述薄膜晶体管层的一侧表面形成有凸点51。
进一步的实施例，所述薄膜晶体管层包括：设于所述基板1上的缓冲层2、设于缓冲层1上的有源层(图中未示出)，有源层包括设于所述缓冲层2背向基板1的表面上的多晶硅段61和设于所述缓冲层2上且位于所述多晶硅段61相对两端的源/漏极接触区65。该阵列基板还包括设于所述缓冲层2背向基板1的表面上并包覆有源层的栅极绝缘层3、设于所述栅极绝缘层3背向缓冲层2的表面上的栅极62、及设于所述栅极绝缘层3背向缓冲层2的表面且包覆栅极62的层间绝缘层4。该阵列基板还包括设于层间绝缘层4背向栅极绝缘层3表面的金属源/漏极63、以及设于层间绝缘层4背向栅极绝缘层3表面且包覆金属源/漏极63的平坦层5。
进一步的实施例，所述缓冲层2中还包括器件遮光层，所述器件遮光层处于正对于有源层的下方，用来保护有源层，避免长时间被背光源照射而导致性 能下降的问题。
所述金属源/漏极63借由穿过层间绝缘层4的金属线64电连接于源/漏极65。上述多晶硅段61、源/漏极接触区65、栅极62和金属源/漏极63共同构成驱动TFT。
所述平坦层5远离层间绝缘层4的表面向上凸点形成凸点51，以使平坦层5表面呈凹凸表面。如图2所示，当外界光线沿A方向照射在显示屏上到达到平坦层5时，凸点51形成的凹凸表面对外界光进行漫反射，与此同时，当背光源B发出的光经基板1、缓冲层2、栅极绝缘层3、层间绝缘层4后照射至平坦层5时，凸点51形成的凹凸表面的内侧对背光源发出的光进行漫反射从而提高背光源光线反射率，如此，在降低背光需求的同时，也弱化了显示屏面反光现象，观看效果更佳。
在本实施例中，所述凸点51为半球形，且相邻两个凸点51之间间隔设置，如图4所示，沿X轴方向或Y轴方向，相邻两个凸点51之间间隔距离小于凸点51的宽度。可以理解的是，本发明所述的凸点可以是半椭圆形、四面锥形等规则性图形。只要成规则性排列，可以为半椭圆形、四面锥形、或者不同形状结构混合交替设置，例如，沿X轴方向或Y轴方向，半椭圆形凸点和四面锥形凸点交替设置。
优选地，上述凸点51周期性均匀分布，以使通过平坦层5的光以及经平坦层5散射的光更加均匀，从而得到更好的观看效果(如图2所示)。
如图5所示，本发明提供的第二个实施例为在第一个实施例基础上的进一步改进，具体地，为了使外界光和背光源发出的光均能形成大致相当的散射效果，相邻两个凸点51之间内凹形成大致呈半球形的凹点82。当从平坦层5远离层间绝缘层4的一侧观看时，凸点51形成周期性分布的凸起面而凹点82形成周期性分布的凹面；当从平面层5靠近层间绝缘层4的一侧观看时，凹点82形成周期性分布的凸起面而凸点51形成周期性分面的凹面，如此，形成有规则性凹凸面。
进一步的实施例，所述凸点51与凹点82通过曲线过度衔接。所述凹点82呈向下凹陷的半球形。可以理解的是凹点82不限于半球形，还可以是半椭圆球形、四面锥形中的一种或多种。
进一步的实施例，所述凸点51的半球形的直径大小为5-6μm。根据目前每一个像素点的大小规格，将凸点51的半球形的直径大小做成上述规格的属于优选的技术方案。
进一步的实施例，所述凹点82的最低点到所述凸点最高点的高度为0.7-1.3μm。
本发明还提供一种掩膜板70，如图3所示，所述掩膜板30包括不透光区和可透光区，所述不透光区和可透光区相互间隔呈周期性布置，所述可透光区为透光区或者半透光区。
请参阅图3和图4，在本发明第三实施例中，提供第一种掩膜板70，所述掩膜板70中的不透光区和可透光区呈近似蜂窝状结构分布，所述近似蜂窝状结构包括黑色格71，所述黑色格71通过白色边缘72间隔开，所述黑色格71为不透光区所在区域，所述白色边缘72为可透光区所在区域；所述黑色格71为边长为5-7μm的方格，所述白色边缘72的宽度小于黑色格的边长。本实施例掩膜板采用近似蜂窝状结构的设置可以使目标产品采用该掩膜板的在经光罩法制程后形成凹凸点间隔的凹凸面。
请参阅图3、图4和图8，本发明提供第一种阵列基板的制作方法，包括以下步骤：
S1：提供一基板1；
S2：在基板1上沉积形成缓冲层2以及非晶硅层；
S3：使非晶硅层转变成多晶硅层并图案化形成多晶硅段61；
S4：在多晶硅段61两端形成源/漏极接触区65，后续依次形成栅极绝缘层3、栅极62、层间绝缘层4、金属源/漏极63、平坦层5；
S5：在所述平坦层5远离金属源/漏极63的一面上通过光罩法做成有凸点5。在本实施例中，所述凸点5为半球形；所述光罩法是采用上面所述的第一种掩膜板70，将所述掩膜板70置于平坦层5的上方，通过黄光、蚀刻制程形成所述凸点51以及间隔凸点51的边缘凹槽52。采用本方法制备得到如图1所述的阵列基板。
请参阅图6和图7，在本发明第四实施例中，提供第二种掩膜板90，所述掩膜板90中的不透光区和可透光区呈棋盘式结构分布，所述棋盘式结构包括 黑色格91和白色格92，所述黑色格91和白色格92相互间隔交错设置，所述黑色格91为不透光区所在区域，所述白色格92为可透光区所在区域；所述黑色格91为边长为5-7μm的方格，所述白色格92为边长为5-7μm的方格。该实施例掩膜板采用棋盘式结构的设置可以使目标产品采用该掩膜板进行光罩法制程后形成凹凸点间隔的凹凸面。
请参阅图5-8，本发明提供第二种阵列基板的制作方法，该制作方法与第一种阵列基板的制作方法大致相同，不同的是在S5步骤中的光罩法，在本实施例中的光罩法是采用上面所述的第二种掩膜板90，将所述掩膜板90置于平坦层5的上方，通过黄光、蚀刻制程形成所述凸点51和凹点82。采用本方法制备得到包括如图5所述平坦层结构的阵列基板。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也是为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其中，包括基板、设在所述基板上的薄膜晶体管层以及设于所述薄膜晶体管层上方的平坦层；
    所述平坦层远离所述薄膜晶体管层的一侧表面形成有凸点。
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管层包括：
    设于所述基板上的缓冲层；
    设于所述缓冲层上的有源层；
    设于所述缓冲层上并包覆所述有源层的栅极绝缘层；
    设于所述栅极绝缘层上的栅极；
    设于所述栅极绝缘层上并包覆所述栅极的层间绝缘层，以及设于层间绝缘层上的金属源/漏极。
  3. 根据权利要求1所述的阵列基板，其中，所述平坦层远离所述薄膜晶体管层的一侧的表面还形成有凹点，所述凹点和所述凸点交替设置。
  4. 根据权利要求3所述的阵列基板，其中，所述凹点与所述凸点之间通过曲线过度衔接。
  5. 根据权利要求1所述的阵列基板，其中，所述凸点之间的间距小于所述凸点的宽度。
  6. 根据权利要求3所述的阵列基板，其中，所述凹点的最低点到所述凸点最高点的高度为0.7-1.3μm。
  7. 一种掩膜板，其中，所述掩膜板包括不透光区和可透光区，所述不透光区和可透光区相互间隔呈周期性布置，所述可透光区为透光区或者半透光区。
  8. 根据权利要求7所述的掩膜板，其中，所述不透光区和可透光区呈近似蜂窝状结构分布，所述近似蜂窝状结构包括黑色格，所述黑色格通过白色边缘间隔开，所述黑色格为不透光区所在区域，所述白色边缘为可透光区所在区域；所述黑色格为边长为5-7μm的方格，所述白色边缘的宽度小于黑色格的边长。
  9. 根据权利要求7所述的掩膜板，其中，所述不透光区和可透光区呈棋盘式结构分布，所述棋盘式结构包括黑色格和白色格，所述黑色格和白色格相互间隔交错设置，所述黑色格为不透光区所在区域，所述白色格为可透光区所在区域；所述黑色格为边长为5-7μm的方格，所述白色格为边长为5-7μm的方格。
  10. 一种阵列基板的制作方法，其中，该方法包括步骤：
    提供基板；依次在基板上沉积缓冲层、有源层，后续依次形成栅极绝缘层、栅极、层间绝缘层、金属源/漏极、平坦层，在所述平坦层远离金属源/漏极的一面上通过光罩法做成有凸点，所述光罩法是采用了权利要求7所述的掩膜板，将所述掩膜板置于平坦层的上方，通过黄光、蚀刻制程形成所述凸点。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054040A (zh) * 2021-03-05 2021-06-29 中国科学院苏州纳米技术与纳米仿生研究所 用于光导开关的衬底以及具有该衬底的光导开关

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109256052B (zh) * 2018-09-21 2020-06-02 京东方科技集团股份有限公司 电子设备、显示面板、驱动背板及其制造方法
CN109378345A (zh) * 2018-10-11 2019-02-22 深圳市华星光电技术有限公司 薄膜晶体管及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0899369A (ja) * 1994-09-30 1996-04-16 Casio Comput Co Ltd マイクロレンズアレイ
CN1530718A (zh) * 2003-03-12 2004-09-22 统宝光电股份有限公司 反射式液晶显示器及周边电路的制造方法
CN1637546A (zh) * 2003-12-26 2005-07-13 Lg.菲利浦Lcd株式会社 透射反射型液晶显示器件的阵列基板及其制造方法
CN101158794A (zh) * 2007-11-20 2008-04-09 友达光电股份有限公司 半透射半反射液晶显示面板及其显示阵列基板、像素结构
US20090283807A1 (en) * 2008-05-14 2009-11-19 International Business Machines Corporation Anti-Reflection Structures For CMOS Image Sensors
CN104733456A (zh) * 2015-03-23 2015-06-24 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039352B (zh) * 2017-04-12 2019-09-10 深圳市华星光电半导体显示技术有限公司 Tft基板的制作方法及tft基板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0899369A (ja) * 1994-09-30 1996-04-16 Casio Comput Co Ltd マイクロレンズアレイ
CN1530718A (zh) * 2003-03-12 2004-09-22 统宝光电股份有限公司 反射式液晶显示器及周边电路的制造方法
CN1637546A (zh) * 2003-12-26 2005-07-13 Lg.菲利浦Lcd株式会社 透射反射型液晶显示器件的阵列基板及其制造方法
CN101158794A (zh) * 2007-11-20 2008-04-09 友达光电股份有限公司 半透射半反射液晶显示面板及其显示阵列基板、像素结构
US20090283807A1 (en) * 2008-05-14 2009-11-19 International Business Machines Corporation Anti-Reflection Structures For CMOS Image Sensors
CN104733456A (zh) * 2015-03-23 2015-06-24 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054040A (zh) * 2021-03-05 2021-06-29 中国科学院苏州纳米技术与纳米仿生研究所 用于光导开关的衬底以及具有该衬底的光导开关

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