WO2019056912A1 - 一种otn支路板卡的时钟处理装置及方法 - Google Patents

一种otn支路板卡的时钟处理装置及方法 Download PDF

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Publication number
WO2019056912A1
WO2019056912A1 PCT/CN2018/102157 CN2018102157W WO2019056912A1 WO 2019056912 A1 WO2019056912 A1 WO 2019056912A1 CN 2018102157 W CN2018102157 W CN 2018102157W WO 2019056912 A1 WO2019056912 A1 WO 2019056912A1
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clock
processing module
alarm
service port
module
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PCT/CN2018/102157
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English (en)
French (fr)
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毛晓波
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烽火通信科技股份有限公司
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Publication of WO2019056912A1 publication Critical patent/WO2019056912A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted

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  • the present invention relates to the field of optical communication application technologies, and in particular to a clock processing apparatus and method for an OTN (Optical Transport Network) tributary board.
  • OTN Optical Transport Network
  • each OTN tributary board extracts a clock from a port on the client side according to the user configuration, and outputs the clock to the clock unit of the system after being divided; the clock unit of the system is from each OTN branch.
  • the clock extracted by the board card locks one clock as a clock source, and then distributes the 8K clock signal of the clock source to each OTN branch board of the system, thereby realizing the synchronization function of the entire network clock.
  • the object of the present invention is to overcome the deficiencies of the above background art, and provide a clock processing apparatus and method for an OTN tributary board, which can not only realize timely switching of a clock source when a locked clock source is lost, but also can be in 1 ms.
  • the response process is performed within the system to meet the system TIE requirements and the user experience is good.
  • the present invention provides a clock processing apparatus for an OTN tributary board, which is disposed in each OTN tributary board, and includes an FPGA, a Framer chip, and a clock chip connected to each other.
  • the clock chip includes a clock processing module for receiving an 8K clock distributed by a clock unit of the system;
  • the FPGA includes an FPGA processing module for locking the 8K clock;
  • the Framer chip includes an SFP module and an 8K clock processing module connected to the SFP module.
  • the SFP module is connected to the FPGA processing module through the LOS pin, and the 8K clock processing module is connected to the FPGA processing module and the clock processing module through the INTB pin and the PGMRCLK pin respectively;
  • the 8K clock processing module is configured to: receive and respond to user configuration, extract a clock from a user service port designated by the user to a clock unit of the system; and when the OTN tributary board is used as a clock source, monitor the customer service port in real time, once monitored To the fault alarm, the interrupt level signal is output to the FPGA processing module through the INT pin of the INTB pin or the SFP module, and the clock source switching signal is sent to the clock unit of the system;
  • the FPGA processing module closes the channel for extracting the clock by the 8K clock processing module when receiving the interrupt level signal; after receiving the clock source switching signal, the clock unit of the system performs switching of the clock source and redistributes the new clock source. 8K clock to each OTN branch board.
  • the invention also provides a clock processing method for an OTN branch board, the method comprising the following steps:
  • the 8K clock processing module of each OTN tributary board receives and responds to the user configuration, and extracts a clock from the user service port designated by the user to the clock unit of the system;
  • the clock unit of the system selects one clock from the clocks extracted by each OTN branch board as a clock source lock, and distributes the 8K clock signal of the clock source to the clock processing module of each OTN branch board;
  • the FPGA processing module of each OTN branch board locks the 8K clock signal from the clock processing module
  • the 8K clock processing module of the OTN tributary board as the clock source monitors the customer service port in real time. Once the fault alarm is detected, the interrupt level signal is output to the FPGA processing module through the INT pin of the INTB pin or the SFP module. At the same time, the clock source switching signal is sent to the clock unit of the system; after receiving the interrupt level signal, the FPGA processing module closes the channel for extracting the clock by the 8K clock processing module; after receiving the clock source switching signal, the clock unit of the system performs the clock source. Switch and redistribute the 8K clock of the new clock source to each OTN tributary board.
  • the invention adds an 8K clock processing module to the Framer chip of each OTN branch board.
  • the 8K clock processing module can receive and respond to the user configuration, and extract the clock from the user-specified customer service port to the clock unit of the system; when the OTN tributary board of the 8K clock processing module is used as the clock source, the client service can be monitored in real time.
  • the port once the fault alarm is detected, outputs an interrupt level signal to the FPGA processing module through the INT pin of the INTB pin or the SFP module, and simultaneously issues a clock source switching signal to the clock unit of the system.
  • the FPGA processing module After receiving the interrupt level signal, the FPGA processing module will close the channel for extracting the clock from the 8K clock processing module; after receiving the clock source switching signal, the clock unit of the system will switch the clock source and redistribute the new clock source.
  • the 8K clock is connected to each OTN tributary board, so that the clock source can be switched in time to ensure the synchronization of the entire network clock.
  • the present invention can not only perform timely switching of the clock source when the locked clock source is lost, but also perform response processing within 1 ms to ensure the whole network system when the synchronization function of the entire network clock is realized.
  • the clock TIE jitter is within 80 ns, which meets the system TIE requirements and effectively improves the user experience.
  • FIG. 1 is a structural block diagram of a clock processing apparatus of an OTN tributary board in an embodiment of the present invention
  • FIG. 2 is a flowchart of a clock processing method of an OTN tributary board in an embodiment of the present invention
  • FIG. 3 is a specific flowchart of step S4 in the embodiment of the present invention.
  • an embodiment of the present invention provides a clock processing device for an OTN tributary board, which is disposed in each OTN tributary board, and includes an FPGA (Field Programmable Gate Array). ), Framer (frame) chip and clock chip.
  • the clock chip includes a clock processing module for receiving an 8K clock distributed by a clock unit of the system; the FPGA includes an FPGA processing module for locking an 8K clock received by the clock processing module; and the Framer chip includes a Small Form-factor Pluggables (SFP).
  • the module can be connected to the 8K clock processing module connected to the SFP module.
  • the SFP module is connected to the FPGA processing module through the LOS (Loss of Signal) pin.
  • the 8K clock processing module passes the INTB (Interrupt).
  • B, interrupt B) pin, PGMRCLK (Programmable Recovered Clocks) pins are connected to the FPGA processing module and the clock processing module.
  • the 8K clock processing module is configured to: receive and respond to a user configuration, extract a clock from a user service port designated by the user to a clock unit of the system; and when the OTN tributary board is used as a clock source, monitor the customer service port in real time, once When the fault alarm is detected, the interrupt level signal is output to the FPGA processing module through the INT pin of the INTB pin or the SFP module, and the clock source switching signal is sent to the clock unit of the system.
  • the FPGA processing module receives the interrupt level signal, it closes the channel for which the 8K clock processing module extracts the clock. After receiving the clock source switching signal, the clock unit of the system will switch the clock source and redistribute the 8K clock of the new clock source to each OTN tributary board.
  • the 8K clock processing module includes a configuration processing module, an alarm interrupt configuration module, a fault real-time monitoring module, and an interrupt processing module.
  • the configuration processing module is configured to: receive and respond to the user configuration, and extract a clock from the user service port specified by the user to the clock unit of the system;
  • the alarm interruption configuration module is configured to: configure the corresponding alarm interruption working mode according to the type of the service port of the customer;
  • the fault real-time monitoring module is configured to: perform real-time monitoring on the customer service port according to the configured alarm interruption working mode, and if the fault alarm is detected, output an interrupt level signal to the FPGA processing module through the corresponding LOS pin or the INTB pin.
  • the clock source switching signal is sent to the clock unit of the system through the interrupt processing module.
  • the user configuration includes SSM (Synchronization Status Message) information.
  • SSM Synchronization Status Message
  • the configuration processing module of each OTN tributary card receives and responds to the user configuration, the SSM information in the user configuration is sent to the clock unit of the system.
  • the clock unit of the system will select the SSM information and the extracted clock sent by the processing module of each OTN tributary board, select one of the clocks as the clock source lock, and distribute the 8K clock signal of the clock source to each OTN branch.
  • the clock processing module of the board will select the SSM information and the extracted clock sent by the processing module of each OTN tributary board, select one of the clocks as the clock source lock, and distribute the 8K clock signal of the clock source to each OTN branch.
  • the customer service port includes a GE (Gigabit Ethernet) service port, and an SDH/OTU (Synchronous Digital Hierarchy/Optical Transport Unit)
  • the service port; the fault alarm includes a LOS alarm, a linkdown (link interruption) alarm, and an LOF alarm.
  • the specific process of configuring the alarm interrupt working mode according to the type of the customer service port is as follows:
  • the alarm interrupt mode is set to: When the LOS alarm is detected on the GE service port, the LOS pin of the SFP module outputs an interrupt level signal to the FPGA processing module. If the linkdown alarm occurs on the service port, the interrupt level signal is output to the FPGA processing module through the INTB pin.
  • the alarm interrupt mode is set to: when the LOS alarm is detected on the SDH/OTU service port, the LOS pin of the SFP module outputs an interrupt level signal to the FPGA processing module.
  • the interrupt level signal is output to the FPGA processing module through the INTB pin.
  • the fault real-time monitoring module performs real-time monitoring on the customer service port according to the configured alarm interruption working mode
  • the interrupt level signal is cancelled by the interrupt processing module.
  • the FPGA processing module will open the channel for the 8K clock processing module to extract the clock.
  • an embodiment of the present invention further provides a clock processing method for an OTN tributary board based on the foregoing apparatus, including the following steps:
  • Step S1 The 8K clock processing module of each OTN tributary board receives and responds to the user configuration, and extracts a clock from the user service port designated by the user to the clock unit of the system.
  • Step S2 The clock unit of the system selects one clock from the clocks extracted by each OTN branch board as a clock source lock, and distributes the 8K clock signal of the clock source to the clock processing module of each OTN branch board.
  • Step S3 The FPGA processing module of each OTN branch board locks the 8K clock signal from the clock processing module.
  • Step S4 The 8K clock processing module of the OTN tributary board as the clock source monitors the customer service port in real time. Once the fault alarm is detected, the interrupt level signal is output to the FPGA through the INB pin or the LOS pin of the SFP module. Processing the module and simultaneously issuing a clock source switching signal to the clock unit of the system; when receiving the interrupt level signal, the FPGA processing module will close the channel for extracting the clock by the 8K clock processing module; after receiving the clock source switching signal, the clock unit of the system The clock source will be switched and the 8K clock of the new clock source will be redistributed to each OTN tributary board.
  • step S4 when the clock unit of the system performs the switching of the clock source, among the clocks extracted from the remaining OTN branch boards, one clock is selected as the new clock source to be locked.
  • the 8K clock processing module includes a configuration processing module, an alarm interrupt configuration module, a fault real-time monitoring module, and an interrupt processing module.
  • the configuration processing module of the 8K clock processing module receives and responds to the user configuration, and extracts the clock from the user service port designated by the user to the clock unit of the system.
  • step S4 specifically includes the following process:
  • Step S401 The alarm interrupt configuration module of the OTN tributary board as a clock source performs configuration of the corresponding alarm interrupt working mode according to the type of the service port of the customer;
  • Step S402 The fault real-time monitoring module of the OTN branch board as a clock source performs real-time monitoring on the customer service port according to the configured alarm interrupt working mode. If the fault alarm is detected, the fault is output through the corresponding LOS pin or the INTB pin. Interrupting the level signal to the FPGA processing module, and issuing a clock source switching signal to the clock unit of the system through the interrupt processing module;
  • Step S403 the FPGA processing module of the OTN tributary board as the clock source closes the channel for extracting the clock by the configuration processing module after receiving the interrupt level signal output by the fault real-time monitoring module through the LOS pin or the INTB pin;
  • Step S404 After receiving the clock source switching signal sent by the interrupt processing module, the clock unit of the system performs switching of the clock source and redistributes the 8K clock of the new clock source to each OTN branch board.
  • the user configuration includes SSM information.
  • step S1 when the configuration processing module of each OTN tributary card receives and responds to the user configuration, the SSM information in the user configuration is sent to the clock unit of the system.
  • step S2 the clock unit of the system will select the SSM information and the extracted clock sent by the configuration processing module of each OTN tributary board, select one of the clocks as the clock source lock, and distribute the 8K clock signal of the clock source to Clock processing module for each OTN branch board.
  • the customer service port includes a GE service port and an SDH/OTU service port; and the fault alarm includes a LOS alarm, a linkdown alarm, and an LOF alarm.
  • the specific process of configuring the corresponding alarm interrupt working mode according to the type of the customer service port is as follows:
  • the alarm interrupt mode is set to: when the LOS alarm is detected on the GE service port, the LOS pin of the SFP module outputs an interrupt level signal to the FPGA processing module. If the linkdown alarm occurs on the service port, the interrupt level signal is output to the FPGA processing module through the INTB pin.
  • the alarm interrupt mode is set to: when the LOS alarm is detected on the SDH/OTU service port, the LOS pin of the SFP module outputs an interrupt level signal to the FPGA processing module.
  • the interrupt level signal is output to the FPGA processing module through the INTB pin.
  • the step S402 further includes the following operations: the fault real-time monitoring module of the OTN tributary board as a clock source performs real-time monitoring on the customer service port according to the configured alarm interruption working mode, if monitoring When the fault alarm disappears, the output of the interrupt level signal is cancelled by the interrupt processing module, and the FPGA processing module opens the channel for extracting the clock from the 8K clock processing module, and ends step S4.
  • the clock processing method of the OTN tributary board of the present invention realizes the synchronization function of the whole network clock, not only can the clock source be switched in time when the locked clock source is lost, but also the response processing can be performed within 1 ms to ensure the response processing.
  • the TIE of the whole network system clock is within 80 ns, which meets the requirements of the system TIE index, which effectively improves the user experience.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
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Abstract

本发明公开了一种OTN支路板卡的时钟处理装置及方法，涉及光通信应用技术领域。该装置的Framer芯片包括SFP模块和与SFP模块相连的8K时钟处理模块。该8K时钟处理模块能从用户指定的客户业务端口提取时钟到系统的时钟单元，并当所在OTN支路板卡作为时钟源时实时监测客户业务端口，一旦监测到故障告警，则输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号。该装置的FPGA处理模块收到中断电平信号后，将关闭时钟提取通道，系统的时钟单元收到时钟源切换信号后，则进行时钟源的切换。本发明不但能在时钟源发生故障丢失时进行及时切换，而且能在1ms以内进行响应，达到了系统TIE指标要求，用户体验好。

Description

一种OTN支路板卡的时钟处理装置及方法 技术领域
本发明涉及光通信应用技术领域，具体来讲是一种OTN(Optical Transport Network，光传送网)支路板卡的时钟处理装置及方法。
背景技术
目前，在光通信应用领域，尤其是在全网时钟同步功能要求的网络应用场景中，为了实现全网时钟的同步功能，通常会需要各OTN支路板卡及系统的时钟单元共同来进行时钟同步的处理。
现有的OTN支路板卡时钟处理方式通常是：各OTN支路板卡根据用户配置从客户侧某个端口提取时钟，分频后输出给系统的时钟单元；系统的时钟单元从各OTN支路板卡提取的时钟中锁定一路时钟作为时钟源，再分发该时钟源的8K时钟信号给系统的各个OTN支路板卡使用，从而实现全网时钟的同步功能。
但是，实际应用中，一旦作为时钟源的客户侧接入的业务信号发生中断，就会使得锁定的时钟源丢失。而系统的时钟单元通常无法及时感知这一事件，所以仍然会锁定这一路客户侧的时钟，从而导致系统时钟不同步。而即使系统的时钟单元感知到了锁定时钟源的丢失，也无法在1ms以内进行响应处理，从而无法达到系统锁定时钟源TIE(Time Interval Error时间间隔误差)指标，而使得时钟同步功能状态不稳定，影响客户体验。
发明内容
本发明的目的是为了克服上述背景技术的不足，提供一种OTN 支路板卡的时钟处理装置及方法，不但能在锁定的时钟源发生故障丢失时实现时钟源的及时切换，而且能在1ms以内进行响应处理，达到系统TIE指标要求，用户体验好。
为达到以上目的，本发明提供一种OTN支路板卡的时钟处理装置，该装置设于各OTN支路板卡内，包括相互连接的FPGA、Framer芯片和时钟芯片。所述时钟芯片包括用于接收系统的时钟单元分发的8K时钟的时钟处理模块；FPGA包括用于锁定8K时钟的FPGA处理模块；Framer芯片包括SFP模块和与SFP模块相连的8K时钟处理模块，所述SFP模块通过LOS管脚与FPGA处理模块相连，8K时钟处理模块分别通过INTB管脚、PGMRCLK管脚与FPGA处理模块、时钟处理模块相连；
所述8K时钟处理模块用于：接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；当所在OTN支路板卡作为时钟源时，实时监测客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号；
所述FPGA处理模块在收到中断电平信号时，关闭8K时钟处理模块提取时钟的通道；系统的时钟单元在收到时钟源切换信号后，进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。本发明还提供一种OTN支路板卡的时钟处理方法，该方法包括以下步骤：
S1、各OTN支路板卡的8K时钟处理模块接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；
S2、系统的时钟单元从各OTN支路板卡提取的时钟中选择一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支 路板卡的时钟处理模块；
S3、各OTN支路板卡的FPGA处理模块从时钟处理模块中锁定8K时钟信号；
S4、作为时钟源的OTN支路板卡的8K时钟处理模块实时监测客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号；FPGA处理模块收到中断电平信号后，关闭8K时钟处理模块提取时钟的通道；系统的时钟单元收到时钟源切换信号后，进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
本发明的有益效果在于：
本发明在各OTN支路板卡的Framer芯片中增设有一个8K时钟处理模块。该8K时钟处理模块能够接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；当该8K时钟处理模块所在OTN支路板卡作为时钟源时，还能实时监测客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号。FPGA处理模块在收到中断电平信号后，将关闭8K时钟处理模块提取时钟的通道；系统的时钟单元在收到时钟源切换信号后，将进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡，从而实现时钟源的及时切换，保证了全网时钟的同步。
与现有技术相比，本发明在实现全网时钟的同步功能时，不但能在锁定的时钟源发生故障丢失时进行时钟源的及时切换，而且能在1ms以内进行响应处理，确保全网系统时钟TIE跳动在80ns以内，达到了系统TIE指标要求，有效提升了用户体验。
附图说明
图1为本发明实施例中OTN支路板卡的时钟处理装置的结构框图；
图2为本发明实施例中OTN支路板卡的时钟处理方法的流程图；
图3为本发明实施例中步骤S4的具体流程图。
具体实施方式
下面结合附图及具体实施例对本发明作进一步的详细描述。
参见图1所示，本发明实施例提供一种OTN支路板卡的时钟处理装置，该装置设于各OTN支路板卡内，包括相互连接的FPGA(Field Programmable Gate Array现场可编程门阵列)、Framer(成帧)芯片和时钟芯片。其中，时钟芯片包括用于接收系统的时钟单元分发的8K时钟的时钟处理模块；FPGA包括用于锁定时钟处理模块接收的8K时钟的FPGA处理模块；Framer芯片包括SFP(Small Form-factor Pluggables，小型可拔插光模块)模块和与SFP模块相连的8K时钟处理模块，所述SFP模块通过LOS(Loss of Signal，光信号丢失)管脚与FPGA处理模块相连，8K时钟处理模块分别通过INTB(Interrupt B，中断B)管脚、PGMRCLK(Programmable Recovered Clocks，可编程恢复时钟)管脚与FPGA处理模块、时钟处理模块相连。
所述8K时钟处理模块用于：接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；当所在OTN支路板卡作为时钟源时，实时监测该客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号。所述FPGA处理模块在收到中断电平信号时，会关闭8K时钟处理模块提取时钟的通道。系统的时钟单元在收到时钟源切换信号后，将进行时钟源的 切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
参见图1所示，所述8K时钟处理模块包括配置处理模块、告警中断配置模块、故障实时监测模块和中断处理模块。配置处理模块用于：接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；告警中断配置模块用于：根据客户业务端口的类型进行相应的告警中断工作模式的配置；故障实时监测模块用于：按照配置的告警中断工作模式对客户业务端口进行实时监测，若监测到故障告警，则通过相应的LOS管脚或INTB管脚输出中断电平信号给FPGA处理模块，并通过中断处理模块向系统的时钟单元发出时钟源切换信号。
进一步地，在一种实施方式中，所述用户配置中包含SSM(Synchronization Status Message，同步状态消息)信息。各OTN支路板卡的配置处理模块接收并响应用户配置时，会将用户配置中的SSM信息发送至系统的时钟单元。系统的时钟单元将根据各OTN支路板卡的配置处理模块发来到的SSM信息和提取的时钟，选择其中一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支路板卡的时钟处理模块。
进一步地，在一种实施方式中，所述客户业务端口包括GE(Giga Bit Ethernet，千兆以太网)业务端口、SDH/OTU(Synchronous Digital Hierarchy/Optical Transport Unit，同步数字体系/光传送单元)业务端口；所述故障告警包括LOS告警、linkdown(链路中断)告警和LOF告警。告警中断配置模块根据客户业务端口的类型进行相应的告警中断工作模式的配置的具体流程如下：
若客户业务端口的类型为GE业务端口，则配置告警中断工作模式为：监测到GE业务端口出现LOS告警，则通过SFP模块的LOS 管脚输出中断电平信号给FPGA处理模块；监测到GE业务端口出现linkdown告警，则通过INTB管脚输出中断电平信号给FPGA处理模块；
若客户业务端口的类型为SDH/OTU业务端口，则配置告警中断工作模式为：监测到SDH/OTU业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到SDH/OTU业务端口出现LOF告警，则通过INTB管脚输出中断电平信号给FPGA处理模块。
进一步地，在一种实施方式中，所述故障实时监测模块按照配置的告警中断工作模式对客户业务端口进行实时监测时，若监测到故障告警消失，则通过中断处理模块取消中断电平信号的输出。此时，FPGA处理模块将会打开8K时钟处理模块提取时钟的通道。
参见图2所示，本发明实施例还提供一种基于上述装置的OTN支路板卡的时钟处理方法，包括以下步骤：
步骤S1、各OTN支路板卡的8K时钟处理模块接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元。
步骤S2、系统的时钟单元从各OTN支路板卡提取的时钟中选择一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支路板卡的时钟处理模块。
步骤S3、各OTN支路板卡的FPGA处理模块从时钟处理模块中锁定8K时钟信号。
步骤S4、作为时钟源的OTN支路板卡的8K时钟处理模块实时监测该客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号；FPGA处理模块收到中断电平信号 时，将关闭8K时钟处理模块提取时钟的通道；系统的时钟单元在收到时钟源切换信号后，将进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
可以理解的是，步骤S4中，系统的时钟单元进行时钟源的切换时，是从其余的OTN支路板卡提取的时钟中，选择一路时钟作为新时钟源锁定。
进一步地，在一种实施方式中，所述8K时钟处理模块包括配置处理模块、告警中断配置模块、故障实时监测模块和中断处理模块。在此基础上，步骤S1中，是通过8K时钟处理模块的配置处理模块来接收并响应用户配置，并从用户指定的客户业务端口提取时钟到系统的时钟单元。并且，参见图3所示，步骤S4具体包括以下流程：
步骤S401、作为时钟源的OTN支路板卡的告警中断配置模块根据客户业务端口的类型进行相应的告警中断工作模式的配置；
步骤S402、作为时钟源的OTN支路板卡的故障实时监测模块按照配置的告警中断工作模式对客户业务端口进行实时监测，若监测到故障告警，则通过相应的LOS管脚或INTB管脚输出中断电平信号给FPGA处理模块，并通过中断处理模块向系统的时钟单元发出时钟源切换信号；
步骤S403、作为时钟源的OTN支路板卡的FPGA处理模块在收到故障实时监测模块通过LOS管脚或INTB管脚输出的中断电平信号后，关闭配置处理模块提取时钟的通道；
步骤S404、系统的时钟单元在收到中断处理模块发出的时钟源切换信号后，将进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
进一步地，在一种实施方式中，所述用户配置中包含SSM信息。 在此基础上，步骤S1中，各OTN支路板卡的配置处理模块接收并响应用户配置时，会将用户配置中的SSM信息发送至系统的时钟单元。步骤S2中，系统的时钟单元将根据各OTN支路板卡的配置处理模块发来到的SSM信息和提取的时钟，选择其中一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支路板卡的时钟处理模块。
进一步地，在一种实施方式中，所述客户业务端口包括GE业务端口、SDH/OTU业务端口；所述故障告警包括LOS告警、linkdown告警和LOF告警。在此基础上，步骤S401中，作为时钟源的OTN支路板卡的告警中断配置模块根据客户业务端口的类型进行相应的告警中断工作模式的配置的具体流程如下：
若客户业务端口的类型为GE业务端口，则配置告警中断工作模式为：监测到GE业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到GE业务端口出现linkdown告警，则通过INTB管脚输出中断电平信号给FPGA处理模块；
若客户业务端口的类型为SDH/OTU业务端口，则配置告警中断工作模式为：监测到SDH/OTU业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到SDH/OTU业务端口出现LOF告警，则通过INTB管脚输出中断电平信号给FPGA处理模块。
更进一步地，在一种实施方式中，步骤S402中还包括以下操作：作为时钟源的OTN支路板卡的故障实时监测模块按照配置的告警中断工作模式对客户业务端口进行实时监测，若监测到故障告警消失，则通过中断处理模块取消中断电平信号的输出，且FPGA处理模块将 打开8K时钟处理模块提取时钟的通道，结束步骤S4。
利用本发明的OTN支路板卡的时钟处理方法实现全网时钟的同步功能时，不但能在锁定的时钟源发生故障丢失时进行时钟源的及时切换，而且能在1ms以内进行响应处理，确保全网系统时钟TIE跳动在80ns以内，达到了系统TIE指标要求，有效提升了用户体验。
本发明不局限于上述实施方式，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围之内。
本说明书中未作详细描述的内容属于本领域专业技术人员公知的现有技术。

Claims (10)

  1. 一种OTN支路板卡的时钟处理装置，该装置设于各OTN支路板卡内，包括相互连接的FPGA、Framer芯片和时钟芯片，其特征在于：所述时钟芯片包括用于接收系统的时钟单元分发的8K时钟的时钟处理模块；FPGA包括用于锁定8K时钟的FPGA处理模块；Framer芯片包括SFP模块和与SFP模块相连的8K时钟处理模块，所述SFP模块通过LOS管脚与FPGA处理模块相连，8K时钟处理模块分别通过INTB管脚、PGMRCLK管脚与FPGA处理模块、时钟处理模块相连；
    所述8K时钟处理模块用于：接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；当所在OTN支路板卡作为时钟源时，实时监测客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号；
    所述FPGA处理模块在收到中断电平信号时，关闭8K时钟处理模块提取时钟的通道；系统的时钟单元在收到时钟源切换信号后，进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
  2. 如权利要求1所述的OTN支路板卡的时钟处理装置，其特征在于：所述用户配置中包含SSM信息；各OTN支路板卡的8K时钟处理模块接收并响应用户配置时，会将用户配置中的SSM信息发送至系统的时钟单元；系统的时钟单元将根据各OTN支路板卡的8K时钟处理模块发来到的SSM信息和提取的时钟，选择其中一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支路板卡的时钟处理模块。
  3. 如权利要求1所述的OTN支路板卡的时钟处理装置，其特征 在于：所述8K时钟处理模块包括配置处理模块、告警中断配置模块、故障实时监测模块和中断处理模块；
    所述配置处理模块用于：接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；
    所述告警中断配置模块用于：根据客户业务端口的类型进行相应的告警中断工作模式的配置；
    所述故障实时监测模块用于：按照配置的告警中断工作模式对客户业务端口进行实时监测，若监测到故障告警，则通过相应的LOS管脚或INTB管脚输出中断电平信号给FPGA处理模块，并通过中断处理模块向系统的时钟单元发出时钟源切换信号。
  4. 如权利要求3所述的OTN支路板卡的时钟处理装置，其特征在于：所述客户业务端口包括GE业务端口、SDH/OTU业务端口；所述故障告警包括LOS告警、linkdown告警和LOF告警；
    在此基础上，所述告警中断配置模块根据客户业务端口的类型进行相应的告警中断工作模式的配置的具体流程如下：
    若客户业务端口的类型为GE业务端口，则配置告警中断工作模式为：监测到GE业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到GE业务端口出现linkdown告警，则通过INTB管脚输出中断电平信号给FPGA处理模块；
    若客户业务端口的类型为SDH/OTU业务端口，则配置告警中断工作模式为：监测到SDH/OTU业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到SDH/OTU业务端口出现LOF告警，则通过INTB管脚输出中断电平信号给FPGA处理模块。
  5. 如权利要求3所述的OTN支路板卡的时钟处理装置，其特征在于：所述故障实时监测模块按照配置的告警中断工作模式对客户业务端口进行实时监测时，若监测到故障告警消失，则通过中断处理模块取消中断电平信号的输出。
  6. 一种基于权利要求1所述装置的OTN支路板卡的时钟处理方法，其特征在于，该方法包括以下步骤：
    S1、各OTN支路板卡的8K时钟处理模块接收并响应用户配置，从用户指定的客户业务端口提取时钟到系统的时钟单元；
    S2、系统的时钟单元从各OTN支路板卡提取的时钟中选择一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支路板卡的时钟处理模块；
    S3、各OTN支路板卡的FPGA处理模块从时钟处理模块中锁定8K时钟信号；
    S4、作为时钟源的OTN支路板卡的8K时钟处理模块实时监测客户业务端口，一旦监测到故障告警，则通过INTB管脚或SFP模块的LOS管脚输出中断电平信号给FPGA处理模块，同时向系统的时钟单元发出时钟源切换信号；FPGA处理模块收到中断电平信号后，关闭8K时钟处理模块提取时钟的通道；系统的时钟单元收到时钟源切换信号后，进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
  7. 如权利要求6所述的OTN支路板卡的时钟处理方法，其特征在于：所述用户配置中包含SSM信息；在此基础上，步骤S1中，各OTN支路板卡的8K时钟处理模块接收并响应用户配置时，会将用户配置中的SSM信息发送至系统的时钟单元；步骤S2中，系统的时钟单元将根据各OTN支路板卡的8K时钟处理模块发来到的SSM信息 和提取的时钟，选择其中一路时钟作为时钟源锁定，并分发该时钟源的8K时钟信号给各OTN支路板卡的时钟处理模块。
  8. 如权利要求6所述的OTN支路板卡的时钟处理方法，其特征在于：所述8K时钟处理模块包括配置处理模块、告警中断配置模块、故障实时监测模块和中断处理模块；
    在此基础上，步骤S1中，通过8K时钟处理模块的配置处理模块接收并响应用户配置，并从用户指定的客户业务端口提取时钟到系统的时钟单元；且步骤S4具体包括以下流程：
    S401、作为时钟源的OTN支路板卡的告警中断配置模块根据客户业务端口的类型进行相应的告警中断工作模式的配置；
    S402、故障实时监测模块按照配置的告警中断工作模式对客户业务端口进行实时监测，若监测到故障告警，则通过相应的LOS管脚或INTB管脚输出中断电平信号给FPGA处理模块，并通过中断处理模块向系统的时钟单元发出时钟源切换信号；
    S403、FPGA处理模块在收到故障实时监测模块通过LOS管脚或INTB管脚输出的中断电平信号后，关闭配置处理模块提取时钟的通道；
    S404、系统的时钟单元在收到中断处理模块发出的时钟源切换信号后，进行时钟源的切换并重新分发新时钟源的8K时钟至各OTN支路板卡。
  9. 如权利要求8所述的OTN支路板卡的时钟处理方法，其特征在于：所述客户业务端口包括GE业务端口、SDH/OTU业务端口；所述故障告警包括LOS告警、linkdown告警和LOF告警；
    在此基础上，步骤S401中，作为时钟源的OTN支路板卡的告警中断配置模块根据客户业务端口的类型进行相应的告警中断工作模 式的配置的具体流程如下：
    若客户业务端口的类型为GE业务端口，则配置告警中断工作模式为：监测到GE业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到GE业务端口出现linkdown告警，则通过INTB管脚输出中断电平信号给FPGA处理模块；
    若客户业务端口的类型为SDH/OTU业务端口，则配置告警中断工作模式为：监测到SDH/OTU业务端口出现LOS告警，则通过SFP模块的LOS管脚输出中断电平信号给FPGA处理模块；监测到SDH/OTU业务端口出现LOF告警，则通过INTB管脚输出中断电平信号给FPGA处理模块。
  10. 如权利要求8所述的OTN支路板卡的时钟处理方法，其特征在于：步骤S402中还包括以下操作：作为时钟源的OTN支路板卡的故障实时监测模块按照配置的告警中断工作模式对客户业务端口进行实时监测，若监测到故障告警消失，则通过中断处理模块取消中断电平信号的输出，且FPGA处理模块将打开8K时钟处理模块提取时钟的通道。
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