WO2019056508A1 - 一种扫描goa电路 - Google Patents

一种扫描goa电路 Download PDF

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Publication number
WO2019056508A1
WO2019056508A1 PCT/CN2017/109116 CN2017109116W WO2019056508A1 WO 2019056508 A1 WO2019056508 A1 WO 2019056508A1 CN 2017109116 W CN2017109116 W CN 2017109116W WO 2019056508 A1 WO2019056508 A1 WO 2019056508A1
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Prior art keywords
thin film
film transistor
gate
drain
capacitor
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PCT/CN2017/109116
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English (en)
French (fr)
Inventor
刘婕
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武汉华星光电半导体显示技术有限公司
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Publication of WO2019056508A1 publication Critical patent/WO2019056508A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scanning GOA circuit.
  • the GOA Gate Driver on Array
  • IC integrated circuit
  • STV scan start signal
  • Phase 1 CK (clock signal) is L (low level), XCK (inverted clock signal) is H (high level), STV (scanning enable signal) is L (low level), M3, M4, M5 M10, M11, M12 are turned on, the gate voltage of the thin film transistor M1 is L+Vth, Vth is the threshold voltage of M2, and the gate voltage of the thin film transistor M3 is L, so M1 and M3 are turned on, and the gate voltage of M2 is H. So M2 is off.
  • the OUT output of the output terminal is XCK, which is high level.
  • Phase 2 CK is H, XCK is L, STV is H, thin film transistors M10, M11, M12, M6, M7 are turned on, and M3, M4, M5, M8 are turned off. Because of the action of capacitors C1, C2, the gate voltages of M1 and M2 maintain the previous phase voltage state. When one end of C1 is connected to the gate of M1 and the other end is connected to VGH, at stage 2, the output terminal OUT should output XCK signal, but since the gate voltage of M1 is L+Vth, M1 has the risk of incomplete opening. , easy to cause output The output voltage of the terminal OUT is greater than L, so that the normal XCK signal cannot be completely output.
  • the output terminal OUT of the first-level GOA circuit outputs an abnormal waveform signal, which may cause the subsequent GOA circuit to fail to output the waveform, thereby causing the subsequent GOA circuit output to malfunction.
  • the signal output from the output terminal OUT changes from H to L.
  • the gate voltage of M2 is pulled low due to the parasitic capacitance effect of M2, so that M2 and M9 are turned on by mistake, and M2 is turned on to cause the output of M2 to output high power.
  • the signal VGH is flat, causing an output OUT error at the output; M9 is turned on, causing the potential at the PD in Figure 1 to be pulled high, thereby turning M1 off, causing the output of the output OUT to fail.
  • Stage 3 CK is L, XCK is H, STV is H, M7, M8, M9, M12 are turned on, so that the gate voltage of M2 is L+Vth, the gate voltage of M1 is H, then M2 is turned on, and M1 is turned off.
  • the OUT terminal outputs VGH, which is high.
  • the STV signal of the first stage GOA circuit is connected as shown in FIG. 2, and the gate of M4 in the next stage GOA circuit is connected to the output terminal OUT of the upper stage GOA circuit.
  • the first stage GOA circuit cannot output the correct SCAN (scanning signal) waveform, because in stage 2, the voltage of the PD point cannot be pulled lower, so that the CK or XCK signal waveform cannot be completely output.
  • the present invention provides a scanning GOA circuit, which can ensure that its output terminal outputs a normal signal without failure.
  • the invention provides a scanning GOA circuit, comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a first capacitor;
  • the first end of the first thin film transistor is connected to the inverted clock signal, and the second end of the first thin film transistor is connected to the first end of the second thin film transistor and serves as an output end;
  • a gate of the third thin film transistor is connected to a scan enable signal, a first end of the third thin film transistor is connected to a gate of the second thin film transistor, and a second end of the third thin film transistor is The second end of the second thin film transistor is connected and connected to a high level signal;
  • the gate and the source of the fourth thin film transistor are connected and connected to a scan enable signal, and the drain and the drain a gate connection of the first thin film transistor;
  • Two ends of the first capacitor are respectively connected to a gate of the first thin film transistor and a second end of the first thin film transistor;
  • the first end is a source
  • the second end is a drain, or the first end is a drain, and the second end is a source.
  • the method further includes: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and an eighth thin film transistor;
  • a gate and a source of the sixth thin film transistor are connected to each other and an inverted clock signal is connected, and a drain of the sixth thin film transistor is respectively connected to a gate of the seventh thin film transistor and a fifth thin film transistor First end connection;
  • a gate of the eighth thin film transistor is connected to the first end of the seventh thin film transistor and is connected to a clock signal, and a first end of the eighth thin film transistor is connected to a second end of the seventh thin film transistor, The second end of the eighth thin film transistor is connected to the first end of the third thin film transistor;
  • a gate of the fifth thin film transistor is connected to a gate of the third thin film transistor and a scan enable signal is connected, and a second end of the fifth thin film transistor is connected to a second end of the second thin film transistor.
  • the method further includes: a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a second capacitor, and a third capacitor;
  • a drain of the fourth thin film transistor is connected to a gate of the first thin film transistor and a first end of the twelfth thin film transistor through the tenth thin film transistor;
  • a gate of the tenth thin film transistor is connected to a scan enable signal, a first end of the tenth thin film transistor is connected to a drain of the fourth thin film transistor, and a second end of the tenth thin film transistor is a gate of the first thin film transistor and a first end of the twelfth thin film transistor are connected;
  • a gate of the twelfth thin film transistor is connected to a low level signal, and another end of the source and the drain of the twelfth thin film transistor is connected to a first end of the ninth thin film transistor, the a second end of the nine thin film transistor is connected to a second end of the second thin film transistor, and a gate of the ninth thin film transistor is connected to a gate of the second thin film transistor;
  • a gate of the eleventh thin film transistor is connected to a low level signal, a first end of the eleventh thin film transistor is connected to a scan enable signal, and a second end of the eleventh thin film transistor is opposite to the third Thin a gate connection of the film transistor;
  • Two ends of the second capacitor are respectively connected to a gate of the ninth thin film transistor and a second end of the ninth thin film transistor;
  • Both ends of the third capacitor are respectively connected to the source and the drain of the ninth thin film transistor.
  • a fourth capacitor is further included;
  • Both ends of the fourth capacitor are respectively connected to the source and the drain of the fifth thin film transistor.
  • a gate of the thirteenth thin film transistor is respectively connected to a gate of the first thin film transistor, and a first end of the thirteenth thin film transistor is connected to a high level signal, and the thirteenth thin film transistor is The two ends are connected to the gate of the second thin film transistor.
  • the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, and the thirteenth thin film transistor are all P-type MOS transistors.
  • the high level signal and the low level signal are both direct current signals.
  • the scan enable signal is at a low level at the start time
  • the clock signal is at a low level during the first half cycle
  • the start time corresponds to the first half cycle
  • the present invention also provides a scan GOA circuit comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor , the eighth thin film transistor;
  • the first end of the first thin film transistor is connected to the inverted clock signal, and the second end of the first thin film transistor is connected to the first end of the second thin film transistor and serves as an output end;
  • a gate of the third thin film transistor is connected to a scan enable signal, a first end of the third thin film transistor is connected to a gate of the second thin film transistor, and a second end of the third thin film transistor is The second end of the second thin film transistor is connected and connected to a high level signal;
  • the gate and the source of the fourth thin film transistor are connected and connected to a scan enable signal, and the drain is connected to the gate of the first thin film transistor;
  • Two ends of the first capacitor are respectively connected to a gate of the first thin film transistor and a second end of the first thin film transistor;
  • a gate and a source of the sixth thin film transistor are connected to each other and an inverted clock signal is connected, and a drain of the sixth thin film transistor is respectively connected to a gate of the seventh thin film transistor and a fifth thin film transistor First end connection;
  • a gate of the eighth thin film transistor is connected to the first end of the seventh thin film transistor and is connected to a clock signal, and a first end of the eighth thin film transistor is connected to a second end of the seventh thin film transistor, The second end of the eighth thin film transistor is connected to the first end of the third thin film transistor;
  • a gate of the fifth thin film transistor is connected to a gate of the third thin film transistor and a scan enable signal is connected, and a second end of the fifth thin film transistor is connected to a second end of the second thin film transistor;
  • the first end is a source
  • the second end is a drain, or the first end is a drain, and the second end is a source
  • the scan enable signal is at a low level at a start time
  • the clock signal is in a first half cycle It is low
  • the startup time corresponds to the first half cycle
  • the method further includes: a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a second capacitor, and a third capacitor;
  • a drain of the fourth thin film transistor is connected to a gate of the first thin film transistor and a first end of the twelfth thin film transistor through the tenth thin film transistor;
  • a gate of the tenth thin film transistor is connected to a scan enable signal, a first end of the tenth thin film transistor is connected to a drain of the fourth thin film transistor, and a second end of the tenth thin film transistor is a gate of the first thin film transistor and a first end of the twelfth thin film transistor are connected;
  • a gate of the twelfth thin film transistor is connected to a low level signal, and another end of the source and the drain of the twelfth thin film transistor is connected to a first end of the ninth thin film transistor, the a second end of the nine thin film transistor is connected to a second end of the second thin film transistor, and a gate of the ninth thin film transistor is connected to a gate of the second thin film transistor;
  • a gate of the eleventh thin film transistor is connected to a low level signal, a first end of the eleventh thin film transistor is connected to a scan enable signal, and a second end of the eleventh thin film transistor is opposite to the third a gate connection of the thin film transistor;
  • Two ends of the second capacitor are respectively connected to a gate of the ninth thin film transistor and a second end of the ninth thin film transistor;
  • Both ends of the third capacitor are respectively connected to the source and the drain of the ninth thin film transistor.
  • a fourth capacitor is further included;
  • Both ends of the fourth capacitor are respectively connected to the source and the drain of the fifth thin film transistor.
  • the scanning GOA circuit of claim 10 further comprising a thirteenth thin film transistor
  • a gate of the thirteenth thin film transistor is respectively connected to a gate of the first thin film transistor, and a first end of the thirteenth thin film transistor is connected to a high level signal, and the thirteenth thin film transistor is The two ends are connected to the gate of the second thin film transistor.
  • the high level signal and the low level signal are both direct current signals.
  • the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, and the thirteenth thin film transistor are all P-type MOS transistors.
  • the present invention also provides a scan GOA circuit comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor , the eighth thin film transistor;
  • the first end of the first thin film transistor is connected to the inverted clock signal, and the second end of the first thin film transistor is connected to the first end of the second thin film transistor and serves as an output end;
  • a gate of the third thin film transistor is connected to a scan enable signal, a first end of the third thin film transistor is connected to a gate of the second thin film transistor, and a second end of the third thin film transistor is The second end of the second thin film transistor is connected and connected to a high level signal;
  • the gate and the source of the fourth thin film transistor are connected and connected to a scan enable signal, and the drain is connected to the gate of the first thin film transistor;
  • Two ends of the first capacitor are respectively connected to a gate of the first thin film transistor and a second end of the first thin film transistor;
  • the first end is a source
  • the second end is a drain, or the first end is a drain, and the second end is a source
  • the gate and the source of the sixth thin film transistor are connected and in reversed a clock signal, a drain of the sixth thin film transistor is respectively connected to a gate of the seventh thin film transistor and a first end of the fifth thin film transistor
  • a gate of the eighth thin film transistor is connected to the first end of the seventh thin film transistor Entering a clock signal, a first end of the eighth thin film transistor is connected to a second end of the seventh thin film transistor, and a second end of the eighth thin film transistor is connected to a first end of the third thin film transistor;
  • a gate of the fifth thin film transistor is connected to a gate of the third thin film transistor and a scan enable signal is connected, and a second end of the fifth thin film transistor is connected to a second end of the second thin film transistor;
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor are all P-type MOS transistors.
  • the method further includes: a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a second capacitor, and a third capacitor;
  • a drain of the fourth thin film transistor is connected to a gate of the first thin film transistor and a first end of the twelfth thin film transistor through the tenth thin film transistor;
  • a gate of the tenth thin film transistor is connected to a scan enable signal, a first end of the tenth thin film transistor is connected to a drain of the fourth thin film transistor, and a second end of the tenth thin film transistor is a gate of the first thin film transistor and a first end of the twelfth thin film transistor are connected;
  • a gate of the twelfth thin film transistor is connected to a low level signal, and another end of the source and the drain of the twelfth thin film transistor is connected to a first end of the ninth thin film transistor, the a second end of the nine thin film transistor is connected to a second end of the second thin film transistor, and a gate of the ninth thin film transistor is connected to a gate of the second thin film transistor;
  • a gate of the eleventh thin film transistor is connected to a low level signal, a first end of the eleventh thin film transistor is connected to a scan enable signal, and a second end of the eleventh thin film transistor is opposite to the third a gate connection of the thin film transistor;
  • Two ends of the second capacitor are respectively connected to a gate of the ninth thin film transistor and a second end of the ninth thin film transistor;
  • Both ends of the third capacitor are respectively connected to the source and the drain of the ninth thin film transistor.
  • a fourth capacitor is further included;
  • Both ends of the fourth capacitor are respectively connected to the source and the drain of the fifth thin film transistor.
  • a gate of the thirteenth thin film transistor is respectively connected to a gate of the first thin film transistor, and a first end of the thirteenth thin film transistor is connected to a high level signal, and the thirteenth thin film transistor is The second end is connected to the gate of the second thin film transistor.
  • the second thin film transistor and the thirteenth thin film transistor are both P-type MOS transistors;
  • Both the high level signal and the low level signal are DC signals.
  • the scan enable signal is at a low level at the start time
  • the clock signal is at a low level during the first half cycle
  • the start time corresponds to the first half cycle
  • the present invention has the following beneficial effects: two ends of the first capacitor are respectively connected to the gate of the first thin film transistor and the second end of the first thin film transistor. Because the first capacitor is directly connected in parallel to the gate of the first thin film transistor and the second end of the first thin film transistor, in the phase 2 shown in FIG. 2, the first capacitor can maintain the voltage state of the previous stage, that is, the phase 1.
  • the low level L, plus the parasitic capacitance of the first thin film transistor, the gate voltage of the first thin film transistor is less than 2L, so that the first thin film transistor is completely turned on, and the output terminal outputs a low level signal corresponding to the inverted clock signal.
  • the first capacitor is directly connected in parallel to the gate of the first thin film transistor and the second end of the first thin film transistor, and when the output terminal changes from the high level H to the low level L, the parasitic capacitance is prevented from being lowered.
  • the gate voltage is turned on to pull up the potential at the PD, and the first thin film transistor is turned off. Therefore, the output of the GOA circuit can output signals normally.
  • FIG. 1 is a circuit diagram of a GOA in the background art provided by the present invention.
  • FIG. 2 is a waveform diagram of a clock signal, an inverted clock signal, and a scan enable signal provided by the present invention.
  • FIG. 3a is a simulation result diagram of the output of the 1-4 level GOA circuit obtained after the GOA circuits in the 20 background technologies are connected in series according to the present invention.
  • FIG. 3b is a simulation result diagram of the output of the 16-20 stage GOA circuit obtained after the GOA circuits in the 20 background technologies are connected in series according to the present invention.
  • FIG. 4 is a circuit diagram of a scanning GOA provided by the present invention.
  • FIG. 5a is a simulation result diagram of the output of the 1-4 level GOA circuit obtained by selecting 20 scanning GOA circuits connected in series according to the present invention.
  • FIG. 5b is a simulation result diagram of the output of the 16-20 stage GOA circuit obtained by selecting 20 scanning GOA circuits connected in series according to the present invention.
  • the present invention provides a scanning GOA circuit.
  • the scanning GOA circuit includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, and a first capacitor C1.
  • the first end of the first thin film transistor M1 is connected to the inverted clock signal XCK, and the second end of the first thin film transistor M1 is connected to the first end of the second thin film transistor M2 and serves as an output terminal.
  • the gate of the third thin film transistor M3 is connected to the scan enable signal STV, the first end of the third thin film transistor M3 is connected to the gate of the second thin film transistor M2, and the second end of the third thin film transistor M3 is connected to the second thin film transistor M2.
  • the second end of the connection is connected to the high level signal VGH.
  • the gate and the source of the fourth thin film transistor M4 are connected to each other and are connected to the scan enable signal STV, and the drain is connected to the gate of the first thin film transistor M1.
  • Both ends of the first capacitor C1 are respectively connected to the gate of the first thin film transistor M1 and the second end of the first thin film transistor M1.
  • the first end is a source of the thin film transistor
  • the second end is a drain of the thin film transistor, or the first end is a drain of the thin film transistor, and the second end is a source of the thin film transistor.
  • the first capacitor C1 Since the first capacitor C1 is directly connected in parallel to the gate of the first thin film transistor M1 and the second end of the first thin film transistor M1, in the phase 2 shown in FIG. 2, the first capacitor C1 can maintain the previous stage, that is, the stage 1
  • the voltage state is a low level L, plus the parasitic capacitance of the first thin film transistor M1, the gate voltage of the first thin film transistor M1 is less than 2L, so that the first thin film transistor M1 is completely opened, and the output terminal OUT outputs an inverted clock.
  • the low level signal corresponding to the signal XCK.
  • the first capacitor C1 is directly connected in parallel to the gate of the first thin film transistor M1 and the second end of the first thin film transistor M1, and is prevented from being M2 due to the output terminal OUT being changed from the high level H to the low level L.
  • the parasitic capacitance pulls down the gate voltage of M2, turns on M9 and pulls up the potential at PD, turning off M1. Therefore, the output terminal OUT of the GOA circuit can output a signal normally.
  • the scan GOA circuit further includes: a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and an eighth thin film transistor M8.
  • the gate of the sixth thin film transistor M6 is connected to the source and is connected to the inverted clock signal XCK.
  • the drain of the sixth thin film transistor M6 is respectively connected to the gate of the seventh thin film transistor M7 and the first end of the fifth thin film transistor M5. connection.
  • the gate of the eighth thin film transistor M8 is connected to the first end of the seventh thin film transistor M7 and is connected to the clock signal CK.
  • the first end of the eighth thin film transistor M8 is connected to the second end of the seventh thin film transistor M7, and the eighth film is connected.
  • the second end of the transistor M8 is connected to the first end of the third thin film transistor M3.
  • the gate of the fifth thin film transistor M5 is connected to the gate of the third thin film transistor M3 and is connected to the scan enable signal STV, and the second end of the fifth thin film transistor M5 is connected to the second end of the second thin film transistor M2.
  • the scan GOA circuit further includes: a ninth thin film transistor M9, a tenth thin film transistor M10, an eleventh thin film transistor M11, a twelfth thin film transistor M2, a second capacitor C2, and a third capacitor C3.
  • the drain of the fourth thin film transistor M4 is connected to the gate of the first thin film transistor M1 and the first end of the twelfth thin film transistor M12 through the tenth thin film transistor M10.
  • the gate of the tenth thin film transistor M10 is connected to the scan enable signal STV, the first end of the tenth thin film transistor M10 is connected to the drain of the fourth thin film transistor M4, and the second end of the tenth thin film transistor M10 is connected with the first thin film transistor M1.
  • the gate electrode and the first end of the twelfth thin film transistor M12 are connected.
  • the gate of the twelfth thin film transistor M12 is connected to the low level signal VGL, and the other end of the source and the drain of the twelfth thin film transistor M12 is connected to the first end of the ninth thin film transistor M9, and the ninth thin film transistor M9 The second end is connected to the second end of the second thin film transistor M2, and the gate of the ninth thin film transistor M9 is connected to the gate of the second thin film transistor M2.
  • the gate of the eleventh thin film transistor M11 is connected to the low level signal VGL, and the first end of the eleventh thin film transistor M11 is connected to the scan enable signal STV, and the second end of the eleventh thin film transistor M11 and the third thin film transistor M3 The gate is connected.
  • Both ends of the second capacitor C2 are respectively connected to the gate of the ninth thin film transistor M9 and the second end of the ninth thin film transistor M9.
  • the second capacitor C2 can be avoided in stage 2 because of the second film
  • the parasitic capacitance inside the transistor M2 causes the gate voltages of the second thin film transistor M2 and the ninth thin film transistor M9 to be pulled low, thereby causing the second thin film transistor M2 and the ninth thin film transistor M9 to be erroneously turned on, when the ninth thin film transistor M9 When it is turned on, the voltage at the PD is pulled high, thereby turning off the first thin film transistor M1, causing an output failure.
  • the second capacitor C2 can maintain the gate voltages of the second thin film transistor M2 and the ninth thin film transistor M9 to be stable, thereby preventing the first thin film transistor M1 from being erroneously turned off, and maintaining the normal output of the output terminal OUT.
  • Both ends of the third capacitor C3 are respectively connected to the source and the drain of the ninth thin film transistor M9.
  • the third capacitor C3 can store the charge released by the leakage current of the ninth thin film transistor M9, and maintain the potential of the connection point between the ninth thin film transistor M9 and the twelfth thin film transistor M12.
  • the scan GOA circuit further includes a fourth capacitor C4. Both ends of the fourth capacitor C4 are respectively connected to the source and the drain of the fifth thin film transistor M5.
  • the scanning GOA circuit further includes a thirteenth thin film transistor M13.
  • the purpose of the fourth capacitor C4 is to maintain the gate voltage of the seventh thin film transistor M7 stable, and to prevent the inverted clock signal XCK from changing (from H to L), because the parasitic capacitance of the sixth thin film transistor M6 leads to the The gate voltage of the seven thin film transistor M7 is lowered, and is thus accidentally turned on, causing an output failure of the GOA circuit.
  • the gate of the thirteenth thin film transistor M13 is respectively connected to the gate of the first thin film transistor M1, the first end of the thirteenth thin film transistor M13 is connected to the high level signal VGH, and the second end of the thirteenth thin film transistor M13 is The gate of the second thin film transistor M2 is connected.
  • the thirteenth thin film transistor M13 prevents the second thin film transistor M2 from being erroneously opened in order to ensure that the PD is at a low potential, thereby ensuring the output of the GOA circuit is stable.
  • the ninth thin film transistor M9, the tenth thin film transistor M10, the eleventh thin film transistor M11, the twelfth thin film transistor M12, and the thirteenth thin film transistor M13 are all P-type MOS transistors.
  • the high level signal VGH and the low level signal VGL are both direct current signals.
  • the scan enable signal STV is at a low level at the start time
  • the clock signal CK is at a low level during the first half cycle
  • the start time corresponds to the first half cycle.
  • the startup time is shown in Figure 2.
  • Stage 1 shown in .
  • the potential of the inverted clock signal XCK is opposite to the potential of the clock signal CK.
  • the action process of the GOA circuit structure of the present invention is:
  • Phase 1 CK is L XCK is H, STV is L, M3, M4, M5, M10, M11, M12 are open, the gate voltage of M1 is L+Vth, the Vth is the threshold voltage of M2, M1 is open, M2 The gate voltage is H and M2 is off.
  • the output of the OUT terminal is XCK, which is high.
  • Stage 2 CK is H, XCK is L, STV is H, M10, M11, M12, M13, M6, M7 are open, and M4, M3, M5, M8 are closed. Because M13 is turned on at this time, the gate voltage of M2 is guaranteed to be H, and M2 and M9 are not accidentally turned on due to the parasitic capacitance of M2, resulting in an output error. At the same time, since the first capacitor C1 maintains the potential of the phase 1, and because of the parasitic capacitance of M1, the gate voltage of M1 is less than 2L, so that M1 is fully opened, and the output of the OUT terminal is XCK, which is a low level L.
  • Stage 3 CK is L, XCK is H, STV is H, M12, M9, M8, M7 are open, so that the gate voltage of M2 is L+Vth, where Vth is the threshold voltage of M2, and M9 is turned on, so that M1 The gate voltage is H, then M2 is turned on, M1 is turned off, and OUT is outputted as VGH, which is high level.
  • the STV signal shown in Fig. 2 is input to the STV input terminal of the first stage GOA circuit, and the CK signal and the XCK signal shown in Fig. 2 are input to the CK input terminal and the XCK input terminal of each stage of the GOA circuit.
  • the simulation results of the final output of the 1st to 4th GOA circuits are shown in Figure 5a.
  • the simulation results of the 16-20th GOA circuit output are shown in Figure 5b.
  • the 20th level GOA circuit can also be seen.
  • the potential of the PU point and the PD point It can be seen that the corresponding GOA circuit can output a normal waveform.
  • the GOA circuit of the present invention connects one end of C1 to the output terminal OUT, and also adds M13 and C4, and the output can be more stable during the multi-stage transfer process. Avoid the false opening and false closing of the thin film transistor due to the parasitic capacitance effect of the thin film transistor, causing the OUT terminal to output an error.

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Abstract

一种扫描GOA电路，其包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容；第一薄膜晶体管的第一端接入反相时钟信号，第二端与第二薄膜晶体管的第一端连接，作为输出端；第三薄膜晶体管的栅极接入扫描启动信号，且第三薄膜晶体管的第一端与第二薄膜晶体管的栅极连接，第三薄膜晶体管的第二端与第二薄膜晶体管的第二端连接且接入高电平信号；第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与第一薄膜晶体管的栅极连接；第一电容并联在与第一薄膜晶体管的栅极以及第一薄膜晶体管的第二端，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极。该GOA电路能够保证输出端正常输出信号。

Description

一种扫描GOA电路
本申请要求于2017年9月21日提交中国专利局、申请号为201710860740.6、发明名称为“一种扫描GOA电路”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种扫描GOA电路。
背景技术
GOA(Gate Driver on Array，阵列基板行驱动)技术能让栅极驱动电路集成在显示面板上，这样可以省去提供栅极电位信号的IC(integrated circuit，集成电路)。对于柔性OLED显示器，由于需要补偿薄膜晶体管的阈值电压和mobility，因而需要更多栅极信号，这样，从外部IC提供栅极信号变得非常困难。同时GOA的稳定性对于显示面板来说也是十分重要。为了改善显示画质，各公司提出来多种GOA电路，图1为已公布的一种GOA电路，图2为CK(时钟信号)、XCK(反相时钟信号)、STV(扫描启动信号)的波形图，该GOA电路的运作过程如下：
阶段1：CK(时钟信号)为L(低电平)，XCK(反相时钟信号)为H(高电平)，STV(扫描启动信号)为L(低电平)，M3、M4、M5、M10、M11、M12打开，薄膜晶体管M1的栅极电压为L+Vth，Vth为M2的阈值电压，薄膜晶体管M3的栅极电压为L，因此M1、M3打开，M2的栅极电压为H，因此M2关闭。输出端OUT输出为XCK，为高电平。
阶段2：CK为H，XCK为L，STV为H，薄膜晶体管M10、M11、M12、M6、M7打开，M3、M4、M5、M8关闭。因为电容C1、C2的作用，M1和M2的栅极电压保持上一阶段电压状态。C1的一端与M1的栅极相连，另一端与VGH相连时，在阶段2时，输出端OUT应输出XCK信号，但由于M1的栅极电压为L+Vth，因此M1有打开不完全的风险，容易造成输出 端OUT输出电压大于L，从而无法完整输出正常的XCK信号。并且在GOA级传过程中，一级GOA电路的输出端OUT输出不正常的波形信号，会导致后续的GOA电路无法输出波形，从而导致后续的GOA电路输出发生故障。同时，输出端OUT输出的信号从H变为L，会因为M2的寄生电容效应，导致M2的栅极电压被拉低，使得M2和M9被误打开，M2打开导致M2的输出端输出高电平信号VGH，从而造成输出端OUT输出错误；M9被打开，造成图1中PD处的电位被拉高，从而将M1关闭，导致输出端OUT的输出发生故障。
阶段3：CK为L，XCK为H，STV为H，M7、M8、M9、M12打开，使得M2的栅极电压为L+Vth，M1的栅极电压为H，则M2打开，M1关闭，OUT端输出VGH，为高电平。
将上述的GOA电路串联使用时，第1级GOA电路接入的STV信号如图2所示，下一级GOA电路中的M4的栅极与上一级GOA电路的输出端OUT连接。从图3a、3b上可以看出第1级GOA电路无法输出正确的SCAN(扫描信号)波形，因为在阶段2，PD点的电压无法被拉更低，使CK或者XCK信号波形无法完整输出。同时当M2的寄生电容较大时，会因为寄生电容效应使得PU点在阶段2时被拉低，M9打开，使得PD点电压被拉高，M1栅极电压过高，致使无法输出正常SCAN波形。
发明内容
为解决上述技术问题，本发明提供一种扫描GOA电路，能够保证其输出端正常输出信号，不发生故障。
本发明提供的一种扫描GOA电路，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容；
所述第一薄膜晶体管的第一端接入反相时钟信号，所述第一薄膜晶体管的第二端与所述第二薄膜晶体管的第一端连接，并作为输出端；
所述第三薄膜晶体管的栅极接入扫描启动信号，所述第三薄膜晶体管的第一端与所述第二薄膜晶体管的栅极连接，所述第三薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接且接入高电平信号；
所述第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与所 述第一薄膜晶体管的栅极连接；
所述第一电容的两端分别与所述第一薄膜晶体管的栅极以及所述第一薄膜晶体管的第二端连接；
其中，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极。
优选地，还包括：第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管；
所述第六薄膜晶体管的栅极和源极相连接且接入反相时钟信号，所述第六薄膜晶体管的漏极分别与所述第七薄膜晶体管的栅极、所述第五薄膜晶体管的第一端连接；
所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的第一端连接且接入时钟信号，所述第八薄膜晶体管的第一端与所述第七薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端与所述第三薄膜晶体管的第一端连接；
所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极连接且接入扫描启动信号，所述第五薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接。
优选地，还包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第二电容、第三电容；
所述第四薄膜晶体管的漏极通过所述第十薄膜晶体管与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
所述第十薄膜晶体管的栅极接入扫描启动信号，所述第十薄膜晶体管的第一端与所述第四薄膜晶体管的漏极连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
所述第十二薄膜晶体管的栅极接入低电平信号，且所述第十二薄膜晶体管的源极和漏极的另一端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接，所述第九薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；
所述第十一薄膜晶体管的栅极接入低电平信号，所述第十一薄膜晶体管的第一端接入扫描启动信号，所述第十一薄膜晶体管的第二端与所述第三薄 膜晶体管的栅极连接；
所述第二电容的两端分别与所述第九薄膜晶体管的栅极，以及所述第九薄膜晶体管的第二端连接；
所述第三电容的两端分别与所述第九薄膜晶体管的源极和漏极连接。
优选地，还包括第四电容；
所述第四电容的两端分别与所述第五薄膜晶体管的源极和漏极连接。
优选地，还包括第十三薄膜晶体管；
所述第十三薄膜晶体管的栅极分别与所述第一薄膜晶体管的栅极连接，所述第十三薄膜晶体管的第一端接入高电平信号，所述第十三薄膜晶体管的第二端与所述第二薄膜晶体管的栅极连接。
优选地，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管均为P型MOS管。
优选地，高电平信号和低电平信号均为直流信号。
优选地，扫描启动信号在启动时间为低电平，时钟信号在第一个半周期为低电平，且所述启动时间和所述第一个半周期对应。
本发明还提供一种扫描GOA电路，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管；
所述第一薄膜晶体管的第一端接入反相时钟信号，所述第一薄膜晶体管的第二端与所述第二薄膜晶体管的第一端连接，并作为输出端；
所述第三薄膜晶体管的栅极接入扫描启动信号，所述第三薄膜晶体管的第一端与所述第二薄膜晶体管的栅极连接，所述第三薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接且接入高电平信号；
所述第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与所述第一薄膜晶体管的栅极连接；
所述第一电容的两端分别与所述第一薄膜晶体管的栅极以及所述第一薄膜晶体管的第二端连接；
所述第六薄膜晶体管的栅极和源极相连接且接入反相时钟信号，所述第六薄膜晶体管的漏极分别与所述第七薄膜晶体管的栅极、所述第五薄膜晶体管的第一端连接；
所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的第一端连接且接入时钟信号，所述第八薄膜晶体管的第一端与所述第七薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端与所述第三薄膜晶体管的第一端连接；
所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极连接且接入扫描启动信号，所述第五薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接；
其中，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极；扫描启动信号在启动时间为低电平，时钟信号在第一个半周期为低电平，且所述启动时间和所述第一个半周期对应。
优选地，还包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第二电容、第三电容；
所述第四薄膜晶体管的漏极通过所述第十薄膜晶体管与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
所述第十薄膜晶体管的栅极接入扫描启动信号，所述第十薄膜晶体管的第一端与所述第四薄膜晶体管的漏极连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
所述第十二薄膜晶体管的栅极接入低电平信号，且所述第十二薄膜晶体管的源极和漏极的另一端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接，所述第九薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；
所述第十一薄膜晶体管的栅极接入低电平信号，所述第十一薄膜晶体管的第一端接入扫描启动信号，所述第十一薄膜晶体管的第二端与所述第三薄膜晶体管的栅极连接；
所述第二电容的两端分别与所述第九薄膜晶体管的栅极，以及所述第九薄膜晶体管的第二端连接；
所述第三电容的两端分别与所述第九薄膜晶体管的源极和漏极连接。
优选地，还包括第四电容；
所述第四电容的两端分别与所述第五薄膜晶体管的源极和漏极连接。
12、根据权利要求10所述的扫描GOA电路，其中，还包括第十三薄膜晶体管；
所述第十三薄膜晶体管的栅极分别与所述第一薄膜晶体管的栅极连接，所述第十三薄膜晶体管的第一端接入高电平信号，所述第十三薄膜晶体管的第二端与所述第二薄膜晶体管的栅极连接。
优选地，高电平信号和低电平信号均为直流信号。
优选地，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管均为P型MOS管。
本发明还提供一种扫描GOA电路，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管；
所述第一薄膜晶体管的第一端接入反相时钟信号，所述第一薄膜晶体管的第二端与所述第二薄膜晶体管的第一端连接，并作为输出端；
所述第三薄膜晶体管的栅极接入扫描启动信号，所述第三薄膜晶体管的第一端与所述第二薄膜晶体管的栅极连接，所述第三薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接且接入高电平信号；
所述第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与所述第一薄膜晶体管的栅极连接；
所述第一电容的两端分别与所述第一薄膜晶体管的栅极以及所述第一薄膜晶体管的第二端连接；
其中，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极；所述第六薄膜晶体管的栅极和源极相连接且接入反相时钟信号，所述第六薄膜晶体管的漏极分别与所述第七薄膜晶体管的栅极、所述第五薄膜晶体管的第一端连接；
所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的第一端连接且接 入时钟信号，所述第八薄膜晶体管的第一端与所述第七薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端与所述第三薄膜晶体管的第一端连接；
所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极连接且接入扫描启动信号，所述第五薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接；
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管均为P型MOS管。
优选地，还包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第二电容、第三电容；
所述第四薄膜晶体管的漏极通过所述第十薄膜晶体管与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
所述第十薄膜晶体管的栅极接入扫描启动信号，所述第十薄膜晶体管的第一端与所述第四薄膜晶体管的漏极连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
所述第十二薄膜晶体管的栅极接入低电平信号，且所述第十二薄膜晶体管的源极和漏极的另一端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接，所述第九薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；
所述第十一薄膜晶体管的栅极接入低电平信号，所述第十一薄膜晶体管的第一端接入扫描启动信号，所述第十一薄膜晶体管的第二端与所述第三薄膜晶体管的栅极连接；
所述第二电容的两端分别与所述第九薄膜晶体管的栅极，以及所述第九薄膜晶体管的第二端连接；
所述第三电容的两端分别与所述第九薄膜晶体管的源极和漏极连接。
优选地，还包括第四电容；
所述第四电容的两端分别与所述第五薄膜晶体管的源极和漏极连接。
优选地，还包括第十三薄膜晶体管；
所述第十三薄膜晶体管的栅极分别与所述第一薄膜晶体管的栅极连接，所述第十三薄膜晶体管的第一端接入高电平信号，所述第十三薄膜晶体管的 第二端与所述第二薄膜晶体管的栅极连接。
19、根据权利要求18所述的扫描GOA电路，其中，所述第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管均为P型MOS管；
高电平信号和低电平信号均为直流信号。
优选地，扫描启动信号在启动时间为低电平，时钟信号在第一个半周期为低电平，且所述启动时间和所述第一个半周期对应。
实施本发明，具有如下有益效果：第一电容的两端分别与第一薄膜晶体管的栅极以及第一薄膜晶体管的第二端连接。因为第一电容直接并联在第一薄膜晶体管的栅极以及第一薄膜晶体管的第二端上，在图2所示的阶段2时，第一电容可以维持上一阶段即阶段1的电压状态，为低电平L，再加上第一薄膜晶体管的寄生电容，第一薄膜晶体管的栅极电压小于2L，使得第一薄膜晶体管完全打开，输出端输出反相时钟信号对应的低电平信号。同时，第一电容直接并联在第一薄膜晶体管的栅极以及第一薄膜晶体管的第二端上，在输出端由高电平H变为低电平L时，防止因为的寄生电容拉低的栅极电压，打开而拉高PD处电位，关闭第一薄膜晶体管。因此，GOA电路的输出端可以正常输出信号。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的背景技术中的GOA电路图。
图2是本发明提供的时钟信号、反相时钟信号、扫描启动信号的波形图。
图3a是本发明提供的选取20个背景技术中的GOA电路进行串联连接后，得到的1～4级GOA电路输出的仿真结果图。
图3b是本发明提供的选取20个背景技术中的GOA电路进行串联连接后，得到的16～20级GOA电路输出的仿真结果图。
图4是本发明提供的扫描GOA电路图。
图5a是本发明提供的选取20个扫描GOA电路进行串联连接后，得到的1～4级GOA电路输出的仿真结果图。
图5b是本发明提供的选取20个扫描GOA电路进行串联连接后，得到的16～20级GOA电路输出的仿真结果图。
具体实施方式
本发明提供一种扫描GOA电路，如图4所示，该扫描GOA电路包括：第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第一电容C1。
第一薄膜晶体管M1的第一端接入反相时钟信号XCK，第一薄膜晶体管M1的第二端与第二薄膜晶体管M2的第一端连接，并作为输出端。
第三薄膜晶体管M3的栅极接入扫描启动信号STV，第三薄膜晶体管M3的第一端与第二薄膜晶体管M2的栅极连接，第三薄膜晶体管M3的第二端与第二薄膜晶体管M2的第二端连接且接入高电平信号VGH。
第四薄膜晶体管M4的栅极和源极连接且接入扫描启动信号STV，漏极与第一薄膜晶体管M1的栅极连接。
第一电容C1的两端分别与第一薄膜晶体管M1的栅极以及第一薄膜晶体管M1的第二端连接。
其中，第一端为薄膜晶体管的源极，第二端为薄膜晶体管的漏极，或者第一端为薄膜晶体管的漏极，第二端为薄膜晶体管的源极。
因为第一电容C1直接并联在第一薄膜晶体管M1的栅极以及第一薄膜晶体管M1的第二端上，在图2所示的阶段2时，第一电容C1可以维持上一阶段即阶段1的电压状态，为低电平L，再加上第一薄膜晶体管M1的寄生电容，第一薄膜晶体管M1的栅极电压小于2L，使得第一薄膜晶体管M1完全打开，输出端OUT输出反相时钟信号XCK对应的低电平信号。同时，第一电容C1直接并联在第一薄膜晶体管M1的栅极以及第一薄膜晶体管M1的第二端上，在输出端OUT由高电平H变为低电平L时，防止因为M2的寄生电容拉低M2的栅极电压，打开M9而拉高PD处电位，关闭M1。因此，GOA电路的输出端OUT可以正常输出信号。
进一步地，该扫描GOA电路还包括：第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8。
第六薄膜晶体管M6的栅极和源极相连接且接入反相时钟信号XCK，第六薄膜晶体管M6的漏极分别与第七薄膜晶体管M7的栅极、第五薄膜晶体管M5的第一端连接。
第八薄膜晶体管M8的栅极与第七薄膜晶体管M7的第一端连接且接入时钟信号CK，第八薄膜晶体管M8的第一端与第七薄膜晶体管M7的第二端连接，第八薄膜晶体管M8的第二端与第三薄膜晶体管M3的第一端连接。
第五薄膜晶体管M5的栅极与第三薄膜晶体管M3的栅极连接且接入扫描启动信号STV，第五薄膜晶体管M5的第二端与第二薄膜晶体管M2的第二端连接。
进一步地，该扫描GOA电路还包括：第九薄膜晶体管M9、第十薄膜晶体管M10、第十一薄膜晶体管M11、第十二薄膜晶体管M2、第二电容C2、第三电容C3。
第四薄膜晶体管M4的漏极通过第十薄膜晶体管M10与第一薄膜晶体管M1的栅极，以及第十二薄膜晶体管M12的第一端连接。
第十薄膜晶体管M10的栅极接入扫描启动信号STV，第十薄膜晶体管M10的第一端与第四薄膜晶体管M4的漏极连接，第十薄膜晶体管M10的第二端与第一薄膜晶体管M1的栅极，以及第十二薄膜晶体管M12的第一端连接。
第十二薄膜晶体管M12的栅极接入低电平信号VGL，且第十二薄膜晶体管M12的源极和漏极的另一端与第九薄膜晶体管M9的第一端连接，第九薄膜晶体管M9的第二端与第二薄膜晶体管M2的第二端连接，第九薄膜晶体管M9的栅极与第二薄膜晶体管M2的栅极连接。
第十一薄膜晶体管M11的栅极接入低电平信号VGL，第十一薄膜晶体管M11的第一端接入扫描启动信号STV，第十一薄膜晶体管M11的第二端与第三薄膜晶体管M3的栅极连接。
第二电容C2的两端分别与第九薄膜晶体管M9的栅极，以及第九薄膜晶体管M9的第二端连接。第二电容C2可以避免在阶段2，因为第二薄膜 晶体管M2内部的寄生电容，导致第二薄膜晶体管M2和第九薄膜晶体管M9的栅极电压被拉低，从而导致第二薄膜晶体管M2和第九薄膜晶体管M9被误打开，当第九薄膜晶体管M9被打开时，会造成PD处的电压被拉高，从而关闭第一薄膜晶体管M1，引发输出故障。因此，第二电容C2可以维持第二薄膜晶体管M2和第九薄膜晶体管M9的栅极电压稳定，进而避免第一薄膜晶体管M1被误关闭，维持了输出端OUT的正常输出。
第三电容C3的两端分别与第九薄膜晶体管M9的源极和漏极连接。第三电容C3可以储存第九薄膜晶体管M9的漏电流释放的电荷，维持第九薄膜晶体管M9和第十二薄膜晶体管M12之间连接点的电位稳定。
进一步地，该扫描GOA电路还包括第四电容C4。第四电容C4的两端分别与第五薄膜晶体管M5的源极和漏极连接。
进一步地，该扫描GOA电路还包括第十三薄膜晶体管M13。第四电容C4的目的是维持第七薄膜晶体管M7的栅极电压稳定，避免反相时钟信号XCK在变化(从H变为L)的过程中，因为第六薄膜晶体管M6的寄生电容，导致第七薄膜晶体管M7的栅极电压降低，进而被误打开，造成GOA电路的输出故障。
第十三薄膜晶体管M13的栅极分别与第一薄膜晶体管M1的栅极连接，第十三薄膜晶体管M13的第一端接入高电平信号VGH，第十三薄膜晶体管M13的第二端与第二薄膜晶体管M2的栅极连接。第十三薄膜晶体管M13为了保证在PD处的处于低电位时，防止第二薄膜晶体管M2被误打开，从而保证了GOA电路的输出稳定。
进一步地，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8、第九薄膜晶体管M9、第十薄膜晶体管M10、第十一薄膜晶体管M11、第十二薄膜晶体管M12、第十三薄膜晶体管M13均为P型MOS管。
进一步地，高电平信号VGH和低电平信号VGL均为直流信号。
进一步地，扫描启动信号STV在启动时间为低电平，时钟信号CK在第一个半周期为低电平，且启动时间和第一个半周期对应。即启动时间为图2 中所示的阶段1。反相时钟信号XCK的电位与时钟信号CK的电位对应相反。
本发明的GOA电路结构的动作过程是：
阶段1：CK为L XCK为H，STV为L，M3、M4、M5、M10、M11、M12打开，M1的栅极电压为L+Vth，该Vth为M2的阈值电压，M1打开，M2的栅极电压为H，M2关闭。OUT端的输出为XCK，为高电平。
阶段2：CK为H，XCK为L，STV为H，M10、M11、M12、M13、M6、M7打开，M4、M3、M5、M8关闭。因为此时M13打开，保证M2的栅极电压为H，不会因为M2的寄生电容而导致M2和M9被误打开，致使输出错误。同时，因为第一电容C1维持了阶段1的电位，并且因为M1的寄生电容，因此M1的栅极电压小于2L，使得M1完全打开，OUT端输出为XCK，为低电平L。
阶段3：CK为L，XCK为H，STV为H，M12、M9、M8、M7打开，使得M2的栅极电压为L+Vth，该处Vth为M2的阈值电压，打开M9，从而使M1的栅极电压为H，则M2打开，M1关闭，OUT端输出VGH，为高电平。
将20个上述的GOA电路结构进行串联连接，上一级GOA电路的输出端OUT作为下一级GOA电路的STV输入端，即与下一级GOA电路的M4的栅极连接。在第1级GOA电路的STV输入端输入图2中所示的STV信号，在每一级GOA电路的CK输入端和XCK输入端输入图2中所示的CK信号和XCK信号。
最终得到的1～4级GOA电路输出的仿真结果图如图5a所示，16～20级GOA电路输出的仿真结果图如图5b所示，图5b中还可以看到第20级GOA电路中PU点和PD点的电位。可以看出对应的GOA电路都能输出正常的波形。
本发明的GOA电路将C1的一端接到输出端OUT，还添加M13、C4，在多级传递过程中，可以保证输出更稳定。避免因为薄膜晶体管的寄生电容效应导致薄膜晶体管的误开和误关，致使OUT端输出错误。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的 普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (20)

  1. 一种扫描GOA电路，其中，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容；
    所述第一薄膜晶体管的第一端接入反相时钟信号，所述第一薄膜晶体管的第二端与所述第二薄膜晶体管的第一端连接，并作为输出端；
    所述第三薄膜晶体管的栅极接入扫描启动信号，所述第三薄膜晶体管的第一端与所述第二薄膜晶体管的栅极连接，所述第三薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接且接入高电平信号；
    所述第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与所述第一薄膜晶体管的栅极连接；
    所述第一电容的两端分别与所述第一薄膜晶体管的栅极以及所述第一薄膜晶体管的第二端连接；
    其中，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极。
  2. 根据权利要求1所述的扫描GOA电路，其中，还包括：第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管；
    所述第六薄膜晶体管的栅极和源极相连接且接入反相时钟信号，所述第六薄膜晶体管的漏极分别与所述第七薄膜晶体管的栅极、所述第五薄膜晶体管的第一端连接；
    所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的第一端连接且接入时钟信号，所述第八薄膜晶体管的第一端与所述第七薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端与所述第三薄膜晶体管的第一端连接；
    所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极连接且接入扫描启动信号，所述第五薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接。
  3. 根据权利要求2所述的扫描GOA电路，其中，还包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第二电容、第三电容；
    所述第四薄膜晶体管的漏极通过所述第十薄膜晶体管与所述第一薄膜 晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
    所述第十薄膜晶体管的栅极接入扫描启动信号，所述第十薄膜晶体管的第一端与所述第四薄膜晶体管的漏极连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
    所述第十二薄膜晶体管的栅极接入低电平信号，且所述第十二薄膜晶体管的源极和漏极的另一端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接，所述第九薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；
    所述第十一薄膜晶体管的栅极接入低电平信号，所述第十一薄膜晶体管的第一端接入扫描启动信号，所述第十一薄膜晶体管的第二端与所述第三薄膜晶体管的栅极连接；
    所述第二电容的两端分别与所述第九薄膜晶体管的栅极，以及所述第九薄膜晶体管的第二端连接；
    所述第三电容的两端分别与所述第九薄膜晶体管的源极和漏极连接。
  4. 根据权利要求3所述的扫描GOA电路，其中，还包括第四电容；
    所述第四电容的两端分别与所述第五薄膜晶体管的源极和漏极连接。
  5. 根据权利要求4所述的扫描GOA电路，其中，还包括第十三薄膜晶体管；
    所述第十三薄膜晶体管的栅极分别与所述第一薄膜晶体管的栅极连接，所述第十三薄膜晶体管的第一端接入高电平信号，所述第十三薄膜晶体管的第二端与所述第二薄膜晶体管的栅极连接。
  6. 根据权利要求5所述的扫描GOA电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管均为P型MOS管。
  7. 根据权利要求5所述的扫描GOA电路，其中，高电平信号和低电平信号均为直流信号。
  8. 根据权利要求6所述的扫描GOA电路，其中，扫描启动信号在启动 时间为低电平，时钟信号在第一个半周期为低电平，且所述启动时间和所述第一个半周期对应。
  9. 一种扫描GOA电路，其中，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管；
    所述第一薄膜晶体管的第一端接入反相时钟信号，所述第一薄膜晶体管的第二端与所述第二薄膜晶体管的第一端连接，并作为输出端；
    所述第三薄膜晶体管的栅极接入扫描启动信号，所述第三薄膜晶体管的第一端与所述第二薄膜晶体管的栅极连接，所述第三薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接且接入高电平信号；
    所述第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与所述第一薄膜晶体管的栅极连接；
    所述第一电容的两端分别与所述第一薄膜晶体管的栅极以及所述第一薄膜晶体管的第二端连接；
    所述第六薄膜晶体管的栅极和源极相连接且接入反相时钟信号，所述第六薄膜晶体管的漏极分别与所述第七薄膜晶体管的栅极、所述第五薄膜晶体管的第一端连接；
    所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的第一端连接且接入时钟信号，所述第八薄膜晶体管的第一端与所述第七薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端与所述第三薄膜晶体管的第一端连接；
    所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极连接且接入扫描启动信号，所述第五薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接；
    其中，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极；扫描启动信号在启动时间为低电平，时钟信号在第一个半周期为低电平，且所述启动时间和所述第一个半周期对应。
  10. 根据权利要求9所述的扫描GOA电路，其中，还包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第二电容、第三电容；
    所述第四薄膜晶体管的漏极通过所述第十薄膜晶体管与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
    所述第十薄膜晶体管的栅极接入扫描启动信号，所述第十薄膜晶体管的第一端与所述第四薄膜晶体管的漏极连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
    所述第十二薄膜晶体管的栅极接入低电平信号，且所述第十二薄膜晶体管的源极和漏极的另一端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接，所述第九薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；
    所述第十一薄膜晶体管的栅极接入低电平信号，所述第十一薄膜晶体管的第一端接入扫描启动信号，所述第十一薄膜晶体管的第二端与所述第三薄膜晶体管的栅极连接；
    所述第二电容的两端分别与所述第九薄膜晶体管的栅极，以及所述第九薄膜晶体管的第二端连接；
    所述第三电容的两端分别与所述第九薄膜晶体管的源极和漏极连接。
  11. 根据权利要求9所述的扫描GOA电路，其中，还包括第四电容；
    所述第四电容的两端分别与所述第五薄膜晶体管的源极和漏极连接。
  12. 根据权利要求10所述的扫描GOA电路，其中，还包括第十三薄膜晶体管；
    所述第十三薄膜晶体管的栅极分别与所述第一薄膜晶体管的栅极连接，所述第十三薄膜晶体管的第一端接入高电平信号，所述第十三薄膜晶体管的第二端与所述第二薄膜晶体管的栅极连接。
  13. 根据权利要求10所述的扫描GOA电路，其中，高电平信号和低电平信号均为直流信号。
  14. 根据权利要求12所述的扫描GOA电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管均为P型MOS管。
  15. 一种扫描GOA电路，其中，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管；
    所述第一薄膜晶体管的第一端接入反相时钟信号，所述第一薄膜晶体管的第二端与所述第二薄膜晶体管的第一端连接，并作为输出端；
    所述第三薄膜晶体管的栅极接入扫描启动信号，所述第三薄膜晶体管的第一端与所述第二薄膜晶体管的栅极连接，所述第三薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接且接入高电平信号；
    所述第四薄膜晶体管的栅极和源极连接且接入扫描启动信号，漏极与所述第一薄膜晶体管的栅极连接；
    所述第一电容的两端分别与所述第一薄膜晶体管的栅极以及所述第一薄膜晶体管的第二端连接；
    其中，第一端为源极，第二端为漏极，或者第一端为漏极，第二端为源极；所述第六薄膜晶体管的栅极和源极相连接且接入反相时钟信号，所述第六薄膜晶体管的漏极分别与所述第七薄膜晶体管的栅极、所述第五薄膜晶体管的第一端连接；
    所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的第一端连接且接入时钟信号，所述第八薄膜晶体管的第一端与所述第七薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端与所述第三薄膜晶体管的第一端连接；
    所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极连接且接入扫描启动信号，所述第五薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接；
    所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管均为P型MOS管。
  16. 根据权利要求15所述的扫描GOA电路，其中，还包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第二电容、第三电容；
    所述第四薄膜晶体管的漏极通过所述第十薄膜晶体管与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
    所述第十薄膜晶体管的栅极接入扫描启动信号，所述第十薄膜晶体管的第一端与所述第四薄膜晶体管的漏极连接，所述第十薄膜晶体管的第二端与所述第一薄膜晶体管的栅极，以及所述第十二薄膜晶体管的第一端连接；
    所述第十二薄膜晶体管的栅极接入低电平信号，且所述第十二薄膜晶体管的源极和漏极的另一端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第二薄膜晶体管的第二端连接，所述第九薄膜晶体管的栅极与所述第二薄膜晶体管的栅极连接；
    所述第十一薄膜晶体管的栅极接入低电平信号，所述第十一薄膜晶体管的第一端接入扫描启动信号，所述第十一薄膜晶体管的第二端与所述第三薄膜晶体管的栅极连接；
    所述第二电容的两端分别与所述第九薄膜晶体管的栅极，以及所述第九薄膜晶体管的第二端连接；
    所述第三电容的两端分别与所述第九薄膜晶体管的源极和漏极连接。
  17. 根据权利要求15所述的扫描GOA电路，其中，还包括第四电容；
    所述第四电容的两端分别与所述第五薄膜晶体管的源极和漏极连接。
  18. 根据权利要求16所述的扫描GOA电路，其中，还包括第十三薄膜晶体管；
    所述第十三薄膜晶体管的栅极分别与所述第一薄膜晶体管的栅极连接，所述第十三薄膜晶体管的第一端接入高电平信号，所述第十三薄膜晶体管的第二端与所述第二薄膜晶体管的栅极连接。
  19. 根据权利要求18所述的扫描GOA电路，其中，所述第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管均为P型MOS管；
    高电平信号和低电平信号均为直流信号。
  20. 根据权利要求16所述的扫描GOA电路，其中，扫描启动信号在启动时间为低电平，时钟信号在第一个半周期为低电平，且所述启动时间和所述第一个半周期对应。
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