WO2019052566A1 - 功率放大器和电子设备 - Google Patents

功率放大器和电子设备 Download PDF

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WO2019052566A1
WO2019052566A1 PCT/CN2018/106093 CN2018106093W WO2019052566A1 WO 2019052566 A1 WO2019052566 A1 WO 2019052566A1 CN 2018106093 W CN2018106093 W CN 2018106093W WO 2019052566 A1 WO2019052566 A1 WO 2019052566A1
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Prior art keywords
mos transistor
deep
well
amplifier
resistor
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PCT/CN2018/106093
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English (en)
French (fr)
Inventor
邵逸高
檀聿麟
戴思特
冯海刚
张宁
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深圳锐越微技术有限公司
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Priority to US16/628,994 priority Critical patent/US11057008B2/en
Publication of WO2019052566A1 publication Critical patent/WO2019052566A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
    • H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45188—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
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    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/534—Transformer coupled at the input of an amplifier
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    • H03F2200/537—A transformer being used as coupling element between two amplifying stages
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    • H03F2200/541—Transformer coupled at the output of an amplifier
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21103—An impedance adaptation circuit being added at the input of a power amplifier stage
    • H—ELECTRICITY
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    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21142—Output signals of a plurality of power amplifiers are parallel combined to a common output
    • H—ELECTRICITY
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45301—Indexing scheme relating to differential amplifiers there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
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    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45374—Indexing scheme relating to differential amplifiers the AAC comprising one or more discrete resistors
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    • H03F2203/45621—Indexing scheme relating to differential amplifiers the IC comprising a transformer for phase splitting the input signal
    • H—ELECTRICITY
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    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45731—Indexing scheme relating to differential amplifiers the LC comprising a transformer

Definitions

  • the present application relates to the field of integrated circuits and electronic devices, and in particular, to a power amplifier chip and an electronic device.
  • the power amplifier integrated with the power amplifier will become difficult to design with the power node; especially the advanced process nodes (such as 65nm or less), because of the tolerance of voltage swing and current swing. Poor capacity, designing high power power amplifiers on the top will face challenges.
  • the amplifier in Figure 1, 1 represents the input transformer, 2 represents the intermediate stage power splitter, 3 represents the output stage 2 (same as the first stage), 4 represents the power combiner; in Figure 2, 5 represents the input power split 6, 6 represents the intermediate level matching, and 7 represents the output stage power combiner; as can be seen from FIG. 1 and FIG. 2, the existing structure uses more inductors, has a large use area, is high in cost, and has a small tuning bandwidth.
  • r is the bandwidth reduction ratio, which is defined as the ratio of the bandwidth (Hz) after ⁇ f system cascading to the ⁇ f single single-stage bandwidth (Hz); n represents the number of cascades;
  • a system is the gain of the system after cascading; f t is the transition frequency, which is related to the bias condition and system properties.
  • the two-stage power amplifier, input matching, intermediate matching and output matching in Figure 1 and Figure 2 are tuned at the same frequency point, gain, band selectivity, in-band group delay, gain smoothness, system Efficiency These indicators are highly coupled.
  • the transition frequency is different, the design space becomes narrow, and complex trade-offs are required. Often we optimize the gain distribution and bias conditions for efficiency. Bandwidth is severely limited.
  • the main purpose of the present application is to propose a power amplifier designed to ensure that the signal gains within the bandwidth, achieves group delay flatness, improves signal quality, reduces the use area, and increases reliability and efficiency.
  • the present application provides a power amplifier including a staggered tuning circuit and a power combining circuit including two pseudo differential pair amplifiers, wherein the output of the staggered tuning circuit is connected to an input end of the power synthesizing circuit;
  • the staggered tuning circuit splits the pre-matching network and its input matching into a cascaded tuning circuit, and sets the central frequency of the parallel resonant network of different stages to be at different values offset by the set relationship, and after driving One stage power synthesis circuit;
  • the power synthesis circuit outputs power through two pseudo differential pair amplifiers and synthesizes the final synthesized power amplification signal.
  • the staggered tuning circuit includes an input matching network, a first amplifier, a second amplifier, a first intermediate level matching network, and a second intermediate level matching network, where an output of the input matching network is connected to the An input of an amplifier, an output of the first amplifier is coupled to an input of the first intermediate stage matching network, and an output of the first intermediate stage matching network is coupled to an input of the second amplifier, An output of the second amplifier is coupled to an input of the second intermediate stage matching network.
  • the staggered tuning circuit includes a first amplifier, a second amplifier, a first intermediate stage matching network, and a second intermediate stage matching network, and an output of the first amplifier is coupled to the first intermediate stage matching An input of the network, an output of the first intermediate stage matching network is coupled to an input of the second amplifier, and an output of the second amplifier is coupled to an input of the second intermediate stage matching network.
  • the setting relationship is specifically: multiplying or dividing by the preset frequency value and the coordination coefficient to obtain a central frequency of the parallel resonant network of different stages, where the preset frequency value is the center of the power amplifier working passband Frequency, the coordination factor is obtained based on the required system bandwidth and its in-band flatness.
  • the power synthesis circuit includes a third amplifier, a fourth amplifier, and a power synthesis resonant network, the third amplifier is connected in parallel with the fourth amplifier, and the output of the third amplifier and the fourth amplifier The outputs are connected to the input of the power synthesis resonant network.
  • the third amplifier and the fourth amplifier are a three-layer cascaded pseudo differential pair; the third amplifier and the fourth amplifier have the same internal structure, and each includes a first deep N-well N-MOS a tube, a second deep N-well N-MOS transistor, a third deep N-well N-MOS transistor, a fourth deep N-well N-MOS transistor, a first N-MOS transistor, a second N-MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein the deep N-well of the first deep N-well N-MOS transistor is connected to the first One end of the resistor, the other end of the first resistor is connected to one end of the second resistor and connected to a power supply voltage, and the other end of the second resistor is connected to the deep N-well of the second deep N-well N-MOS transistor The body end of the first deep N-MOS
  • the first deep N-well N-MOS transistor and the second deep N-well N-MOS transistor are both deep N-well normal voltage threshold thick gate oxide layer N-MOS transistors.
  • the third deep N-well N-MOS transistor and the fourth deep N-well N-MOS transistor are both deep N-well low voltage threshold thin gate oxide layer N-MOS transistors.
  • the first N-MOS transistor and the second N-MOS transistor are both low voltage threshold thin gate oxide layer N-MOS transistors.
  • the present application also proposes an electronic device comprising a power amplifier comprising a staggered tuning circuit and a power combining circuit comprising two pseudo differential pair amplifiers, wherein the output of the staggered tuning circuit is connected An input of a power synthesis circuit;
  • the staggered tuning circuit splits the pre-matching network and its input matching into a cascaded tuning circuit, and sets the central frequency of the parallel resonant network of different stages to be at different values offset by the set relationship, and after driving One stage power synthesis circuit;
  • the power synthesis circuit outputs power through two pseudo differential pair amplifiers and synthesizes the final synthesized power amplification signal.
  • the staggered tuning circuit includes an input matching network, a first amplifier, a second amplifier, a first intermediate level matching network, and a second intermediate level matching network, where an output of the input matching network is connected to the An input of an amplifier, an output of the first amplifier is coupled to an input of the first intermediate stage matching network, and an output of the first intermediate stage matching network is coupled to an input of the second amplifier, An output of the second amplifier is coupled to an input of the second intermediate stage matching network.
  • the staggered tuning circuit includes a first amplifier, a second amplifier, a first intermediate stage matching network, and a second intermediate stage matching network, and an output of the first amplifier is coupled to the first intermediate stage matching An input of the network, an output of the first intermediate stage matching network is coupled to an input of the second amplifier, and an output of the second amplifier is coupled to an input of the second intermediate stage matching network.
  • the setting relationship is specifically: multiplying or dividing by the preset frequency value and the coordination coefficient to obtain a central frequency of the parallel resonant network of different stages, where the preset frequency value is the center of the power amplifier working passband Frequency, the coordination factor is obtained based on the required system bandwidth and its in-band flatness.
  • the power synthesis circuit includes a third amplifier, a fourth amplifier, and a power synthesis resonant network, the third amplifier is connected in parallel with the fourth amplifier, and the output of the third amplifier and the fourth amplifier The outputs are connected to the input of the power synthesis resonant network.
  • the third amplifier and the fourth amplifier are a three-layer cascaded pseudo differential pair; the third amplifier and the fourth amplifier have the same internal structure, and each includes a first deep N-well N-MOS a tube, a second deep N-well N-MOS transistor, a third deep N-well N-MOS transistor, a fourth deep N-well N-MOS transistor, a first N-MOS transistor, a second N-MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein the deep N-well of the first deep N-well N-MOS transistor is connected to the first One end of the resistor, the other end of the first resistor is connected to one end of the second resistor and connected to a power supply voltage, and the other end of the second resistor is connected to the deep N-well of the second deep N-well N-MOS transistor The body end of the first deep N-MOS
  • the first deep N-well N-MOS transistor and the second deep N-well N-MOS transistor are both deep N-well normal voltage threshold thick gate oxide layer N-MOS transistors.
  • the third deep N-well N-MOS transistor and the fourth deep N-well N-MOS transistor are both deep N-well low voltage threshold thin gate oxide layer N-MOS transistors.
  • the first N-MOS transistor and the second N-MOS transistor are both low voltage threshold thin gate oxide layer N-MOS transistors.
  • the technical solution of the present application adopts the first-stage power amplifier architecture of the first staggered tuning and the power synthesis.
  • the present application splits the front stage and its input matching drive into cascaded staggered tuning, so that the center frequency is at the frequency point 1 and At frequency 2, the last stage is tuned to frequency 3. Because the staggered tuning of the previous stage expands the bandwidth, even if the last level of the tuning network reduces the bandwidth, it will not diminish too much; at the advanced process nodes (eg 65nm or less), the power of the architecture is integrated.
  • the amplifier chip compared to the known architecture, with the same number of transformers (same area), in-band signal quality and band filtering, would be better; due to its in-band flatness, this architecture is especially suitable for carrier aggregation communication applications.
  • 1 is a schematic structural view of a first known amplifier
  • FIG. 2 is a schematic structural view of a second known amplifier
  • FIG. 3 is a schematic diagram of functional modules of a power amplifier of the present application.
  • FIG. 4 is a schematic structural diagram of a first stage embodiment of a power amplifier of the present application including an input stage matching staggered tuning circuit;
  • FIG. 5 is a schematic structural diagram of a second embodiment of a power amplifier of the present application, which does not include an input stage matching staggered tuning circuit;
  • FIG. 6 is a schematic diagram of a power combining circuit of a third embodiment of a power amplifier of the present application.
  • FIG. 7 is a schematic diagram of an internal amplifier circuit of a power combining circuit according to a fourth embodiment of the power amplifier of the present application.
  • FIG. 8 is a schematic diagram of a power amplifier structure of a fifth embodiment of the power amplifier of the present application without input stage matching;
  • FIG. 9 is a schematic structural diagram of a power amplifier with input stage matching according to a sixth embodiment of the power amplifier of the present application.
  • FIG. 10 is a schematic diagram of frequency response of a power amplifier of the present application without input matching type staggered tuning
  • FIG. 11 is a schematic diagram of a frequency response of a power amplifier of the present application with input matching type staggered tuning;
  • Figure 12 is a schematic diagram of the frequency response during overlap tuning.
  • the directional indication is only used to explain in a certain posture (as shown in the drawing)
  • first”, “second”, etc. in the embodiments of the present application, the description of "first”, “second”, etc. is used for descriptive purposes only, and is not to be construed as an Its relative importance or implicit indication of the number of technical features indicated.
  • features defining “first” and “second” may include at least one of the features, either explicitly or implicitly.
  • the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. Nor is it within the scope of protection required by this application.
  • the application proposes a power amplifier.
  • the power amplifier proposed by the present application includes a staggered tuning circuit 100 and a power combining circuit 200 including two pseudo differential pair amplifiers, wherein the output of the staggered tuning circuit 100 is connected to the input of the power combining circuit 200. end;
  • the staggered tuning circuit 100 splits the pre-matching network and its input matching into a cascaded tuning circuit, and sets the central frequencies of the parallel resonant networks of different stages to be at different values offset by the set relationship, and drives a power synthesis circuit 200 of the latter stage;
  • the power combining circuit 200 outputs power through two pseudo differential pair amplifiers and synthesizes the final synthesized power amplified signal.
  • This application uses a two-stage power amplifier architecture with first staggered tuning and power synthesis. Compared with the known architecture, it is better to use the same number of transformers (same area), in-band signal quality and band filtering; due to its in-band flatness it is good.
  • the staggered tuning circuit 100 described herein is divided into input level matching and no input level matching.
  • the staggered tuning circuit 100 includes an input matching network M 1, a first amplifier A 1, the second amplifier A 2, a first inter-stage matching network and the second intermediate M 2 M. 3-matching network, said input matching network is connected to an output terminal of M input of the first amplifier a 1, the output of the first amplifier a 1 is connected to a first intermediate stage M input matching network 2, a first M inter-stage matching network 2 is connected to the output terminal of the second input terminal of the amplifier a 2, the output of the second amplifier a 2 is connected to an input terminal of the second inter-stage matching network of M 3.
  • the central frequency of the first intermediate level matching network M 2 and the second intermediate level matching network M 3 are set at different values staggered in a set relationship, specifically: the first intermediate level matching network M 2 is tuned at f 0 /alpha
  • the second intermediate level matching network M 3 is tuned at f 0 ⁇ alpha, generally f 0 is at the center frequency of the power amplifier, and the parameter alpha is a dimensionless design parameter, according to the required system bandwidth and its in-band flatness.
  • the driver of the preceding stage and its input matching is split into cascaded staggered tunings such that the center frequency is at frequency 1 and frequency 2, and the last stage is tuned to frequency 3. Because the staggered tuning of the previous stage expands the bandwidth, even if the last level of the tuning network reduces the bandwidth, it will not diminish too much.
  • the staggered tuning circuit 100 includes a first amplifier A 1 , a second amplifier A 2 , a first intermediate level matching network M 2 , and a second intermediate level matching network M 3 .
  • a first output terminal of the amplifier a 1 is connected to a first intermediate stage M input matching network 2
  • the output terminal of the first inter-stage matching network is connected to an input terminal of M 2 a 2 of the second amplifier
  • the second amplifier a 2 an input terminal connected to the output of the second inter-stage matching network of M 3.
  • the central frequency of the first intermediate level matching network M 2 and the second intermediate level matching network M 3 are set at different values staggered in a set relationship, specifically: the first intermediate level matching network M 2 is tuned at f 0 /alpha
  • the second intermediate level matching network M 3 is tuned at f 0 ⁇ alpha; where: f 0 is the center frequency of the power amplifier working passband, and the parameter alpha is a dimensionless design parameter, according to the required system bandwidth and its band
  • the inner flatness is selected; in this embodiment, the driving of the front stage and its input matching is split into the staggered tuning of the cascade, so that the central frequency is at the frequency point 1 and the frequency point 2, and then the last stage is tuned at the frequency point 3. . Because the staggered tuning of the previous stage expands the bandwidth, even if the last level of the tuning network reduces the bandwidth, it will not diminish too much.
  • the power combiner circuit 200 includes a third amplifier A 3, A 4 and the fourth amplifier power combiner resonant network, said third amplifier and a fourth amplifier A 3 A 4 In parallel, the output of the third amplifier and the output of the fourth amplifier are connected to the input of the power synthesis resonant network.
  • This implementation connects two amplifiers in parallel to the power synthesis resonant network, saving the number of transformers used.
  • the third amplifier A 3 and the fourth amplifier A 4 described in the present application are a three-layer cascaded pseudo differential pair; referring to FIG. 7, the third amplifier A 3 and the fourth amplifier A 4 have the same internal structure, and each includes a first deep N.
  • the first deep N-well N-MOS transistor M 3m and the second deep N-well N-MOS transistor M 3p are deep N-well normal voltage threshold thick gate oxide layer N-MOS transistor
  • the 6-port device is a tube, through which a large deep N-well resistor (R 3m2, R 3p2) biased at high voltage supply; end thereof through which a large resistor (R 3m1, R 3p1, 10Kohm ) are received Your own source.
  • the gate level is biased at a higher voltage such that the high voltage swing across p m , p p does not exceed its drain-gate tolerance.
  • the third deep N-well N-MOS transistor M 2m and the fourth deep N-well N-MOS transistor M 2p are deep N-well low voltage threshold thin gate oxide layer N-MOS transistors, and deep N-well low voltage threshold thin
  • the gate oxide layer NMOS which is a 6-port device; its deep N-well is biased at a higher voltage by a large resistor (R 2m2 , R 2p2 ). Its body end is connected to its own source through a large resistor (R 2m1 , R 2p1 , 10Kohm).
  • the first N-MOS transistor M 1m and the second N-MOS transistor M 1p are low voltage threshold thin gate oxide layer N-MOS transistors, which are 4-port devices;
  • the threshold voltages of the first N-MOS transistor M 1m , the second N-MOS transistor M 1p , the third deep N-well N-MOS transistor M 2m and the fourth deep N-well N-MOS transistor M 2p are arranged for
  • the on-resistance R on is lowered to lower the knee voltage V knee ; since R on , V knee and the maximum current I max have the following relationship:
  • the on-chip power synthesis approach also improves efficiency over designs that use a matching network with a larger conversion ratio to transmit power without the use of synthesis; as shown in the following equation:
  • ⁇ tf is the transformer power transmission efficiency
  • Q 2 ind is its quality factor
  • r is the impedance conversion ratio
  • One end of the resistor R 3p2 is connected to V dd
  • the other end of the second resistor R 3p2 is connected to the deep N well of the second deep N-well N-MOS transistor M 3p
  • the first deep N-well N-MOS transistor M 3m end of the third resistor connected to bulk terminal R 3m1, the other end of the third resistor R 3m1 connected to the source of the first N-MOS deep N-well tube and the source M 3m deep N-well connected to the drain of the third N-MOS tube of M 2m
  • end body deep N-well of the second N-MOS is connected to one end of the tube M 3p R 3p2 of the fourth resistor, the other end of the fourth resistor R 3p2 is connected to the second deep N-well
  • all of the amplifiers of the present application are biased in the deep class AB, the setting of the tube parameters, and the setting of the bias voltage should be such that deep class AB operation is achieved.
  • the transformer in the present application refers to both a Planar Spiral Transformer and a Stacked Spiral Transformer which are commonly used in CMOS radio frequency integrated circuits.
  • the design should be based on the application and area constraints, choose the appropriate k (mutual inductance), L 1 (the main coil self-inductance value), L 2 (the secondary coil self-inductance value), R, C, to design enough gain, enough
  • the resonant transformer network needs to be designed to meet the matching requirements.
  • the optimal output power matching (Optimal Power Matching) for output saturation power Psat needs to be designed; for Txfmr 1 and Txfmr 2
  • the resonant network needs to be designed to meet the staggered tuning bandwidth flatness requirements and achieve a power ratio a.
  • the overall circuit structure connecting the staggered tuning circuit 100 and the power combining circuit 200 of the present application is as follows:
  • V dd is the supply voltage
  • Vcg1 is the bias voltage
  • a 1 , A 2 , A 3 and A 4 are amplifiers.
  • C 0 and C 2 are tuning capacitors
  • C 1 It plays the role of even harmonic and common mode component suppression.
  • C 3 , C 4 , C 5 , C 6 , C 7 , C 8 and C 9 are tuning capacitors , which can be used to cope with process variations .
  • Programming switched capacitor array implementations, and should be covered by this patent; in Figure 8, C 10 and C 11 are AC coupling capacitors; Txfmr 0 , Txfmr 1 , Txfmr 2 transformers have central taps for the primary and secondary coils, It is a 6-port device.
  • the RC series array should be added to the center tap of the main-stage coil to suppress self-excitation and supply voltage regulation.
  • the center tap of the secondary coil can be optionally added with capacitance to ground to suppress even harmonics.
  • Mode drift; Txfmr 3 , Txfmr 4 transformer secondary coil has no center tap; R 3 , R 4 are the secondary coil's termination resistance, according to the required design of the system bandwidth and its in-band flatness; R 1 R 2 is a bias resistor and generally has a large resistance of >10 kOhm.
  • a power synthesis resonant network including an input matching type staggered tuning architecture, Txfmr 3 , Txfmr 4 , and C 7 , C 8 , and C 9 needs to be designed to satisfy the optimal output power matching of the output saturation power Psat (Optimal). Power Matching); an input stage matching M 1 for Txfmr 0 , C 0 , C 1 , C 2 and R 1 , and a resonant network M 2 and Txfmr 2 and C for Txfmr 1 and C 3 , C 4 , R 3 5.
  • the resonant network M 3 composed of C 6 and R 4 needs to be designed to satisfy the staggered tuning of the bandwidth flatness and to achieve the power ratio a.
  • This embodiment integrates the amplifier chip of the architecture at an advanced process node, compares the known architecture, uses the same number of transformers (same area), in-band signal quality and band filtering, which is better; due to its in-band flatness Therefore, this architecture is especially suitable for carrier aggregation communication occasions.
  • FIG. 10 which is a frequency response diagram without input matching type staggered tuning
  • FIG. 11 is a schematic diagram of frequency response with input matching type staggered tuning.
  • the horizontal axis is the frequency (Hz)
  • the vertical axis is the frequency response.
  • line 8 is the frequency response curve of the system input to output ( Figure 8 corresponds to Figure 10, Figure 9 corresponds to Figure 11);
  • Line 9 is the frequency response of A 1 + M 1 , which is the frequency of tuning At f 0 /alpha
  • line 10 is the frequency effect of A 2 +M 2 , the frequency response of the tuned frequency f 0 ⁇ alpha
  • line 11 is the M 1 +A 0 frequency response diagram, which assumes that the input match is Driven by A 0 , it is assumed that the A 0 is a drive amplifier that is added as appropriate, and is not drawn in the circuit (Fig. 9 or Fig. 8).
  • FIG. 11 is a schematic diagram of the frequency response during overlap tuning.
  • the line 9 is the frequency response of the amplifier tuned to the center frequency of 2.4G.
  • the frequency response of the system is as follows. As shown by the green line, it can be seen that the bandwidth is reduced and the in-band gain response flatness is deteriorated. Comparing Fig. 10 and Fig. 11 with Fig. 12, it can be seen that the bands in Fig. 10 and Fig. 11 are flat and the bandwidth is increased. Out-of-band suppression without sacrificing.
  • the present application also proposes an electronic device comprising the power amplifier, the electronic device comprising all the embodiments of the power amplifier described above, and therefore having the same technical effects as the embodiments of the power amplifier, here No longer.

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Abstract

一种功率放大器及电子设备，采用先参差调谐再功率合成这种两级功率放大器架构，此外，把前级以及其输入匹配的驱动拆成级联的参差调谐，使其中央频率处在小于设计频道的频点1和大于设计频点的频点2，再把最后功率合成级调谐在设计频点。在先进的CMOS工艺节点（比如：65nm或以下），集成该架构的放大器芯片，对比已知架构，用同样数量的变压器（面积一样），带内信号质量和带外过滤效果会更好，可靠性更高；而由于其带内平坦性好，因此，此架构尤其适合载波聚合通讯场合。

Description

功率放大器和电子设备 技术领域
本申请涉及集成电路与电子设备技术领域，特别涉及一种功率放大器芯片和电子设备。
背景技术
现有技术中，集成功率放大器的射频芯片随着工艺节点的缩小，功率放大器设计也会变得困难；尤其是先进的工艺节点(比如：65nm或以下)，因为容忍电压摆幅、电流摆幅能力较差，在上面设计高功率功率放大器会面临挑战。
参考图1(D.Chowdhury,C.D.Hull,O.B.Degani,Y.Wang,and A.M.Niknejad,“A fully integrated dual-mode highly linear 2.4Ghz CMOS power amplifier”,IEEE J.Solid-State Circuits,vol.43,no.3,pp.600-609,Mar.2009)和图2(Y.Tan,H,Xu.(2016)CMOS power amplifier design for wireless connectivity applications:a highly linear WLAN power amplifier in advanced SoC CMOS,In RF and mm-wave Power Generation in Silicon(pp.61-pp.87).Elsevier Inc..DOI:10.1016/B978-0-12-408052-2.00008-6)，为现有技术中常用的两种构架的放大器，图1中，1表示输入变压器，2表示中间级功率拆分器，3表示输出级2(跟第一级一样)，4表示功率合并器；图2中，5表示输入功率拆分器，6表示中间级匹配，7表示输出级功率合并器；从图1和图2中可知，现有构架中电感的使用比较多，使用面积大，成本高且调谐带宽比较小。
在先进的CMOS工艺节点(比如：65nm或以下)，参差调谐射频技术配合功率合成技术，会使得功率放大器达到较优的性能以及较低的面积成本。
理论上，若n个带宽相同的单调谐放大器调谐在同一个频点，有：
Figure PCTCN2018106093-appb-000001
其中，r表示带宽缩小率，它被定义为Δf system级联之后的带宽(Hz)与Δf single单级的带宽(Hz)之比；n表示级联的个数；
令每级增益相等，我们可以看到系统增益、系统带宽的限制条件
Figure PCTCN2018106093-appb-000002
其中，A system是级联后系统的增益；f t是跃迁频率，与偏置情况和系统属性有关，
Figure PCTCN2018106093-appb-000003
变压器共振时，如图1和图2中的2级功率放大器、输入匹配、中间匹配和输出匹配都调谐在同一频点时，增益、频带选择性、带内群延时、增益平缓度、系统效率这些指标是高度耦合的，依据工艺及偏置条件不同，跃迁频率不一样，设计空间也会变得狭窄，需要复杂的折中，往往我们为了效率，去优化增益分配及偏置条件，在带宽上便会受到严重的限制。
申请内容
本申请的主要目的是提出一种功率放大器，旨在确保信号在带宽内增益、实现群延时平坦提高信号质量、减少使用面积、增加可靠性和效率。
为实现上述目的，本申请提出一种功率放大器，包括参差调谐电路和包含两个伪差分对放大器的功率合成电路，其中，所述的参差调谐电路的输出端连接功率合成电路的输入端；
所述的参差调谐电路通过将前级匹配网络及其输入匹配拆成级联的调谐电路，并设置不同级的并联谐振网络的中央频率处在以设定关系错开的不同值上，并驱动后一级的功率合成电路；
所述的功率合成电路通过两个伪差分对放大器输出功率并进行合成，获得最终合成的功率放大信号。
可选地，所述的参差调谐电路包括输入匹配网络、第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的输入匹配网络的输出端连接所述第一放大器的输入端，所述第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
可选地，所述的参差调谐电路包括第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
可选地，所述的设定关系具体为通过预设频率值与协调系数相乘或除获得不同级的并联谐振网络的中央频率，所述的预设频率值是功率放大器工作通带的中心频率，所述的协调系数根据所需系统带宽及其带内平整度获得。
可选地，所述的功率合成电路包括第三放大器、第四放大器和功率合成谐振网络，所述第三放大器与第四放大器并联，所述第三放大器的输出端与所述第四放大器的输出端均连接功率合成谐振网络的输入端。
可选地，所述的第三放大器和所述第四放大器为一个三层级联伪差分对；所述第三放大器和所述第四放大器内部结构相同，均包括第一深N阱N-MOS管、第二深N阱N-MOS管、第三深N阱N-MOS管、第四深N阱N-MOS管、第一N-MOS管、第二N-MOS管、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻、第七电阻和第八电阻，其中，所述的第一深N阱N-MOS管的深N阱连接所述第一电阻的一端，所述第一电阻的另一端连接所述第二电阻的一端并接电源电压，所述第二电阻的另一端连接所述第二深N阱N-MOS管的深N阱；所述的第一深N阱N-MOS管的体端连接所述 第三电阻的一端，所述第三电阻的另一端连接所述第一深N阱N-MOS管的源极并连接所述第三深N阱N-MOS管的漏极；所述的第二深N阱N-MOS管的体端连接所述第四电阻的一端，所述第四电阻的另一端连接所述第二深N阱N-MOS管的源极并连接所述第四深N阱N-MOS管的漏极；所述的第三深N阱N-MOS管的深N阱连接所述第五电阻的一端，所述第五电阻的另一端连接所述第六电阻的一端并接电源电压，所述第六电阻的另一端连接所述第四深N阱N-MOS管的深N阱；所述的第三深N阱N-MOS管的体端连接所述第七电阻的一端，所述第七电阻的另一端连接所述第三深N阱N-MOS管的源极并连接所述第一N-MOS管的漏极；所述的第四深N阱N-MOS管的体端连接所述第八电阻的一端，所述第八电阻的另一端连接所述第四深N阱N-MOS管的源极并连接所述第二N-MOS管的漏极；所述的第一N-MOS管的源极连接所述第二N-MOS管的源极并接地。
可选地，所述的第一深N阱N-MOS管和第二深N阱N-MOS管均为深N阱正常电压门限厚栅氧层N-MOS管。
可选地，所述的第三深N阱N-MOS管和第四深N阱N-MOS管均为深N阱低电压门限薄栅氧层N-MOS管。
可选地，所述的第一N-MOS管和第二N-MOS管均为低电压门限薄栅氧层N-MOS管。
本申请还提出一种电子设备，所述电子设备包括功率放大器，所述功率放大器包括参差调谐电路和包含两个伪差分对放大器的功率合成电路，其中，所述的参差调谐电路的输出端连接功率合成电路的输入端；
所述的参差调谐电路通过将前级匹配网络及其输入匹配拆成级联的调谐电路，并设置不同级的并联谐振网络的中央频率处在以设定关系错开的不同值上，并驱动后一级的功率合成电路；
所述的功率合成电路通过两个伪差分对放大器输出功率并进行合成，获得最终合成的功率放大信号。
可选地，所述的参差调谐电路包括输入匹配网络、第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的输入匹配网络的输出端连接所述第一放大器的输入端，所述第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
可选地，所述的参差调谐电路包括第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
可选地，所述的设定关系具体为通过预设频率值与协调系数相乘或除获得不同级的并联谐振网络的中央频率，所述的预设频率值是功率放大器工作通带的中心频率，所述的协调系数根据所需系统带宽及其带内平整度获得。
可选地，所述的功率合成电路包括第三放大器、第四放大器和功率合成谐振网络，所述第三放大器与第四放大器并联，所述第三放大器的输出端与所述第四放大器的输出端均连接功率合成谐振网络的输入端。
可选地，所述的第三放大器和所述第四放大器为一个三层级联伪差分对；所述第三放大器和所述第四放大器内部结构相同，均包括第一深N阱N-MOS管、第二深N阱N-MOS管、第三深N阱N-MOS管、第四深N阱N-MOS管、第一N-MOS管、第二N-MOS管、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻、第七电阻和第八电阻，其中，所述的第一深N阱N-MOS管的深N阱连接所述第一电阻的一端，所述第一电阻的另一端连接所述第二电阻的一端并接电源电压，所述第二电阻的另一端连接所述第二深N阱N-MOS管的深N阱；所述的第一深N阱N-MOS管的体端连接所述第三电阻的一端，所述第三电阻的另一端连接所述第一深N阱N-MOS管的源极并连接所述第三深N阱N-MOS管的漏极；所述的 第二深N阱N-MOS管的体端连接所述第四电阻的一端，所述第四电阻的另一端连接所述第二深N阱N-MOS管的源极并连接所述第四深N阱N-MOS管的漏极；所述的第三深N阱N-MOS管的深N阱连接所述第五电阻的一端，所述第五电阻的另一端连接所述第六电阻的一端并接电源电压，所述第六电阻的另一端连接所述第四深N阱N-MOS管的深N阱；所述的第三深N阱N-MOS管的体端连接所述第七电阻的一端，所述第七电阻的另一端连接所述第三深N阱N-MOS管的源极并连接所述第一N-MOS管的漏极；所述的第四深N阱N-MOS管的体端连接所述第八电阻的一端，所述第八电阻的另一端连接所述第四深N阱N-MOS管的源极并连接所述第二N-MOS管的漏极；所述的第一N-MOS管的源极连接所述第二N-MOS管的源极并接地。
可选地，所述的第一深N阱N-MOS管和第二深N阱N-MOS管均为深N阱正常电压门限厚栅氧层N-MOS管。
可选地，所述的第三深N阱N-MOS管和第四深N阱N-MOS管均为深N阱低电压门限薄栅氧层N-MOS管。
可选地，所述的第一N-MOS管和第二N-MOS管均为低电压门限薄栅氧层N-MOS管。
本申请技术方案采用先参差调谐再功率合成这种两级功率放大器架构，此外，本申请把前级以及其输入匹配的驱动拆成级联的参差调谐，使其中央频率处在频点1和频点2，再把最后一级调谐在频点3。因为前面一级拆成的参差调谐拓宽了带宽，所以即使最后一级的调谐网络会减低带宽，也不会减弱太多；在先进的工艺节点(比如：65nm或以下)，集成该架构的功率放大器芯片，对比已知架构，用同样数量的变压器(面积一样)，带内信号质量和带过滤，会更好；由于其带内平坦性好，因此，此架构尤其适合载波聚合通讯场合。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面 将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为第一已知放大器构架结构示意图；
图2为第二已知放大器构架结构示意图；
图3为本申请功率放大器的功能模块示意图；
图4为本申请功率放大器第一实施例的含有输入级匹配参差调谐电路结构示意图；
图5为本申请功率放大器第二实施例的不含有输入级匹配参差调谐电路结构示意图；
图6为本申请功率放大器第三实施例的功率合成电路示意图；
图7为本申请功率放大器第四实施例的功率合成电路内部放大器电路示意图；
图8为本申请功率放大器第五实施例的不含有输入级匹配时功率放大器构架示意图；
图9为本申请功率放大器第六实施例的含有输入级匹配时功率放大器构架示意图；
图10为本申请功率放大器的不含输入匹配型参差调谐的频率响应示意图；
图11为本申请功率放大器的含输入匹配型参差调谐的频率响应示意图；
图12为重叠调谐时候的频率响应示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一 部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种功率放大器。
如图3所示，本申请提出的功率放大器包括参差调谐电路100和包含两个伪差分对放大器的功率合成电路200，其中，所述的参差调谐电路100的输出端连接功率合成电路200的输入端；
所述的参差调谐电路100通过将前级匹配网络及其输入匹配拆成级联的调谐电路，并设置不同级的并联谐振网络的中央频率处在以设定关系错开的不同值上，并驱动后一级的功率合成电路200；
所述的功率合成电路200通过两个伪差分对放大器输出功率并进行合成，获得最终合成的功率放大信号。
本申请采用先参差调谐再功率合成这种两级功率放大器架构，对比已知架构，用同样数量的变压器(面积一样)，带内信号质量和带过滤，会更好；由于其带内平坦性好。
本申请所述的参差调谐电路100分为含有输入级匹配和不含有输入级匹配。
参考图4，在本申请一实施例中，所述的参差调谐电路100包括输入匹配网络M 1、第一放大器A 1、第二放大器A 2、第一中间级匹配网络M 2和第二中间级匹配网络M 3，所述的输入匹配网络M 1的输出端连接第一放大器A 1的输入端，第一放大器A 1的输出端连接第一中间级匹配网络M 2的输入端，第一中间级匹配网络M 2的输出端连接第二放大器A 2的输入端，第二放大器A 2的输出端连接第二中间级匹配网络M 3的输入端。
设置第一中间级匹配网络M 2和第二中间级匹配网络M 3的中央频率处在以设定关系错开的不同值上，具体为：第一中间级匹配网络M 2调谐在f 0/alpha，第二中间级匹配网络M 3调谐在f 0×alpha，一般f 0处于功率放大器的中心频率，参数alpha是一个无量纲的设计参数，根据所需设计的系统带宽及其带内平整度去选择；本实施例把前级以及其输入匹配的驱动拆成级联的参差调谐，使其中央频率处在频点1和频点2，再把最后一级调谐在频点3。因为前面一级拆成的参差调谐拓宽了带宽，所以即使最后一级的调谐网络会减低带宽，也不会减弱太多。
参考图5，在本申请一实施例中，所述的参差调谐电路100包括第一放大器A 1、第二放大器A 2、第一中间级匹配网络M 2和第二中间级匹配网络M 3，所述的第一放大器A 1的输出端连接第一中间级匹配网络M 2的输入端，第一中间级匹配网络M 2的输出端连接第二放大器A 2的输入端，第二放大器A 2的输出端连接第二中间级匹配网络M 3的输入端。
设置第一中间级匹配网络M 2和第二中间级匹配网络M 3的中央频率处在以设定关系错开的不同值上，具体为：第一中间级匹配网络M 2调谐在f 0/alpha，第二中间级匹配网络M 3调谐在f 0×alpha；其中：f 0是功率放大器工作通带的中心频率，参数alpha是一个无量纲的设计参数，根据所需设计的系统带宽及其带内平整度去选择；本实施例把前级以及其输入匹配的驱动拆成级联的参差调谐，使其中央频率处 在频点1和频点2，再把最后一级调谐在频点3。因为前面一级拆成的参差调谐拓宽了带宽，所以即使最后一级的调谐网络会减低带宽，也不会减弱太多。
参考图6，在本申请一实施例中，所述的功率合成电路200包括第三放大器A 3、第四放大器A 4和功率合成谐振网络，所述第三放大器A 3与第四放大器A 4并联，第三放大器的输出端与第四放大器的输出端均连接功率合成谐振网络的输入端。本实施将两个放大器并联连接至功率合成谐振网络，节省变压器的使用个数。
本申请所述的第三放大器A 3与第四放大器A 4为一个三层级联伪差分对；参考图7，第三放大器A 3与第四放大器A 4内部结构相同，均包括第一深N阱N-MOS管M 3m、第二深N阱N-MOS管M 3p、第三深N阱N-MOS管M 2m、第四深N阱N-MOS管M 2p、第一N-MOS管M 1m、第二N-MOS管M 1p、第一电阻R 3m2、第二电阻R 3p2、第三电阻R 3m1、第四电阻R 3p2、第五电阻R 2m2、第六电阻R 2p2、第七电阻R 2m1和第八电阻R 2p1；
在一可选实施例中，所述的第一深N阱N-MOS管M 3m和第二深N阱N-MOS管M 3p均为深N阱正常电压门限厚栅氧层N-MOS管，该管是个6端口器件，其深N阱通过一个大电阻(R 3m2,R 3p2)偏置在较高供电电压；其体端通过一个大电阻(R 3m1,R 3p1,10Kohm)分别接到自己的源极。其门级偏置在较高电压，使得p m,p p上的高压摆幅不超过其漏级-门级耐受极限。所述的第三深N阱N-MOS管M 2m和第四深N阱N-MOS管M 2p均为深N阱低电压门限薄栅氧层N-MOS管，深N阱低电压门限薄栅氧层NMOS，其是个6端口器件；其深N阱通过一个大电阻(R 2m2,R 2p2)偏置在较高电压。其体端通过一个大电阻(R 2m1,R 2p1,10Kohm)分别接到自己的源端。所述的第一N-MOS管M 1m、第二N-MOS管M 1p均为低电压门限薄栅氧层N-MOS管，其是个4端口器件；
所述的第一N-MOS管M 1m、第二N-MOS管M 1p、第三深N阱 N-MOS管M 2m和第四深N阱N-MOS管M 2p的门限电压安排是为了降低导通电阻R on，从而降低膝电压V knee；因为R on,V knee和最大电流I max有以下关系:
V knee＝I×R on               (3)
从而提高功率放大器的效率；而最上面的第一深N阱N-MOS管M 3m和第二深N阱N-MOS管M 3p则是为了可靠性设计而存在的，去保护下面较脆弱的两个薄栅氧层的各个端口的压降摆幅都处于耐受范围内。
片上功率合成的方式，比不使用合成方式而使用一个更大转换比率的匹配网络去传输功率的设计来说，也会提高效率；如下式所示:
Figure PCTCN2018106093-appb-000004
其中，η tf为变压器功率传输效率；Q 2 ind为其质量因子；r表示阻抗转换比率。
参考图7，在一可选实施例中，所述的第一深N阱N-MOS管M 3m的深N阱连接第一电阻R 3m2的一端，第一电阻R 3m2的另一端连接第二电阻R 3p2的一端并接V dd，第二电阻R 3p2的另一端连接第二深N阱N-MOS管M 3p的深N阱；所述的第一深N阱N-MOS管M 3m的体端连接第三电阻R 3m1的一端，第三电阻R 3m1的另一端连接第一深N阱N-MOS管M 3m的源极并连接第三深N阱N-MOS管M 2m的漏极；所述的第二深N阱N-MOS管M 3p的体端连接第四电阻R 3p2的一端，第四电阻R 3p2的另一端连接第二深N阱N-MOS管M 3p的源极并连接第四深N阱N-MOS管M 2p的漏极；所述的第三深N阱N-MOS管M 2m的深N阱连接第五电阻R 2m2的一端，第五电阻R 2m2的另一端连接第六电阻R 2p2的一端并接V dd，第六电阻R 2p2的另一端连接第四深N阱N-MOS管M 2p的深N阱；所述的第三深N阱N-MOS管M 2m的 体端连接第七电阻R 2m1的一端，第七电阻R 2m1的另一端连接第三深N阱N-MOS管M 2m的源极并连接第一N-MOS管M 1m的漏极；所述的第四深N阱N-MOS管M 2p的体端连接第八电阻R 2p1的一端，第八电阻R 2p1的另一端连接第四深N阱N-MOS管M 2p的源极并连接第二N-MOS管M 1p的漏极；所述的第一N-MOS管M 2p的源极连接第二N-MOS管M 1p的源极并接V SS。
在一可选实施例中，本申请所有的放大器都是偏置在深AB类下，其管子参数的设置，以及偏置电压的设置，应使得深AB类操作得到实现。其中A1、A2的设计参数一样，设类型是AX；A3、A4的设计参数一样，设类型是AY；AX中，从上到下三个管子的宽度分别是AX.W1、AX.W2、AX.W3；那么AY中，三个管子的宽度，分别AY.W1、AY.W2、AY.W3；则有AX.W1＝a×AY.W1,AX.W2＝a×AY.W2,AX.W3＝a×AY.W3，其中a建议是1/32～1/2之间的一个数。
在一可选实施例中，本申请中的变压器，指CMOS射频集成电路中常见的片上平面螺旋变压器(Planar Spiral Transformer)和叠层式螺旋变压器(Stacked Spiral Transformer)，均可实现。设计应视应用场合及面积限制，选择合适的k(互感系数)，L 1(主线圈自感值)，L 2(次线圈自感值)，R，C，去设计足够的增益，足够的带宽；另外，谐振变压器网络需要设计成满足匹配要求，对于Txfmr 3,Txfmr 4的谐振网络，需要设计成满足输出饱和功率Psat的最优输出功率匹配(Optimal Power Matching)；对于Txfmr 1和Txfmr 2的谐振网络，需要设计成满足参差调谐带宽平坦性要求，且实现功率比a。
本申请参差调谐电路100和功率合成电路200连接的整体电路构 架具体如下：
参考图8和9，图中V dd为供电电压，Vcg1为偏置电压；A 1、A 2、A 3和A 4为放大器，在图9中，C 0和C 2是调谐电容，C 1起到偶次谐波及共模分量抑制的作用，C 3、C 4、C 5、C 6、C 7、C 8和C 9为调谐电容，应对工艺偏差，该调谐电容部分可以被由可编程开关电容阵列实现，并应该被本专利覆盖；在图8中，C 10和C 11是交流耦合电容；Txfmr 0、Txfmr 1、Txfmr 2变压器的主级线圈与次级线圈都有中心抽头，是个6端口器件，其主级线圈中央抽头上应加入RC串联阵列以起到抑制自激及供电电压稳压作用；其次级线圈中央抽头上可选加入电容到地以抑制偶次谐波及共模飘移作用；Txfmr 3、Txfmr 4变压器的次级线圈无中心抽头；R 3、R 4是次级线圈的终断电阻，根据所需设计的系统带宽及其带内平整度去选择；R 1、R 2是偏置电阻，一般阻值>10kOhm的大电阻。
参考图8，当不含有输入级匹配时，对于Txfmr 1和C 3、C 4、R 3构成的谐振网络M 2，和Txfmr 2及C 5、C 6、R 4构成的谐振网络M 3，需要设计成满足带宽平坦性的参差调谐，且使得功率比a得以达到的形式；
参考图9，为含输入匹配型参差调谐架构，Txfmr 3、Txfmr 4及C 7、C 8、C 9构成的功率合成谐振网络，需要设计成满足输出饱和功率Psat的最优输出功率匹配(Optimal Power Matching)；对于Txfmr 0、C 0、C 1、C 2和R 1构成的输入级匹配M 1，对于Txfmr 1和C 3、C 4、R 3构成的谐振网络M 2和Txfmr 2及C 5、C 6、R 4构成的谐振网络M 3，需要设计成满足带宽平坦性的参差调谐，且使得功率比a得以达到的形式。
本实施例在先进的工艺节点，集成该架构的放大器芯片，对比已知架构，用同样数量的变压器(面积一样)，带内信号质量和带过滤，会更好；由于其带内平坦性好，因此，此架构尤其适合载波聚合通讯场合。
参考图10，该图为不含输入匹配型参差调谐的频率响应示意图，参考图11，为含输入匹配型参差调谐的频率响应示意图，图中横轴是频率(Hz)，竖轴是频率响应的模(dB)，8号线是系统输入至输出 的频率响应曲线(图8对应图10，图9对应图11)；9号线是A 1+M 1的频率响应，它调谐的频点处于f 0/alpha，10号线是A 2+M 2的频率效应，调谐的频点f 0×alpha的频率响应，11号线是M 1+A 0频率响应图，它假设了输入匹配被A 0所驱动，设所述A 0为视情况而定加的驱动放大器，并未在电路(图9或者图8)中画出。
参考图11为重叠调谐时候的频率响应示意图，从该图中可知9号线是调谐在中心频率2.4G的放大器单独的频率响应，当这个放大器级联两个的时候，其系统的频率响应如绿线所示，可以看到带宽缩小，且带内增益响应平坦性变差；将图10和图11与图12进行对比可知，图10和图11带内都平整了，带宽增高了，然而带外抑制能力却无牺牲。
本申请还提出一种电子设备，所述电子设备包括所述的功率放大器，该电子设备包含上述功率放大器的所有实施例，因此，也具有与功率放大器的各实施例相同的技术效果，此处不再赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种功率放大器，其中，包括参差调谐电路和包含两个伪差分对放大器的功率合成电路，其中，所述的参差调谐电路的输出端连接功率合成电路的输入端；
    所述的参差调谐电路通过将前级匹配网络及其输入匹配拆成级联的调谐电路，并设置不同级的并联谐振网络的中央频率处在以设定关系错开的不同值上，并驱动后一级的功率合成电路；
    所述的功率合成电路通过两个伪差分对放大器输出功率并进行合成，获得最终合成的功率放大信号。
  2. 如权利要求1所述的功率放大器，其中，所述的参差调谐电路包括输入匹配网络、第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的输入匹配网络的输出端连接所述第一放大器的输入端，所述第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
  3. 如权利要求1所述的功率放大器，其中，所述的参差调谐电路包括第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
  4. 如权利要求1所述的功率放大器，其中，所述的设定关系具体为通过预设频率值与协调系数相乘或除获得不同级的并联谐振网络的中央频率，所述的预设频率值是功率放大器工作通带的中心频率，所述的协调系数根据所需系统带宽及其带内平整度获得。
  5. 如权利要求1所述的功率放大器，其中，所述的功率合成电路包括第三放大器、第四放大器和功率合成谐振网络，所述第三放大器与第四放大器并联，所述第三放大器的输出端与所述第四放大器的输出端均连接功率合成谐振网络的输入端。
  6. 如权利要求5所述的功率放大器，其中，所述的第三放大器和所述第四放大器为一个三层级联伪差分对；所述第三放大器和所述第四放大器内部结构相同，均包括第一深N阱N-MOS管、第二深N阱N-MOS管、第三深N阱N-MOS管、第四深N阱N-MOS管、第一N-MOS管、第二N-MOS管、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻、第七电阻和第八电阻，其中，所述的第一深N阱N-MOS管的深N阱连接所述第一电阻的一端，所述第一电阻的另一端连接所述第二电阻的一端并接电源电压，所述第二电阻的另一端连接所述第二深N阱N-MOS管的深N阱；所述的第一深N阱N-MOS管的体端连接所述第三电阻的一端，所述第三电阻的另一端连接所述第一深N阱N-MOS管的源极并连接所述第三深N阱N-MOS管的漏极；所述的第二深N阱N-MOS管的体端连接所述第四电阻的一端，所述第四电阻的另一端连接所述第二深N阱N-MOS管的源极并连接所述第四深N阱N-MOS管的漏极；所述的第三深N阱N-MOS管的深N阱连接所述第五电阻的一端，所述第五电阻的另一端连接所述第六电阻的一端并接电源电压，所述第六电阻的另一端连接所述第四深N阱N-MOS管的深N阱；所述的第三深N阱N-MOS管的体端连接所述第七电阻的一端，所述第七电阻的另一端连接所述第三深N阱N-MOS管的源极并连接所述第一N-MOS管的漏极；所述的第四深N阱N-MOS管的体端连接所述第八电阻的一端，所述第八电阻的另一端连接所述第四深N阱N-MOS管的源极并连接所述第二N-MOS管的漏极；所述的第一N-MOS管的源极连接所述第二N-MOS管的源极并接地。
  7. 如权利要求6所述的功率放大器，其中，所述的第一深N阱N-MOS管和第二深N阱N-MOS管均为深N阱正常电压门限厚栅氧层N-MOS管。
  8. 如权利要求6所述的功率放大器，其中，所述的第三深N阱N-MOS管和第四深N阱N-MOS管均为深N阱低电压门限薄栅氧层N-MOS管。
  9. 如权利要求6所述的功率放大器，其中，所述的第一N-MOS管和第二N-MOS管均为低电压门限薄栅氧层N-MOS管。
  10. 一种电子设备，其中，所述电子设备包括功率放大器，所述功率放大器包括参差调谐电路和包含两个伪差分对放大器的功率合成电路，其中，所述的参差调谐电路的输出端连接功率合成电路的输入端；
    所述的参差调谐电路通过将前级匹配网络及其输入匹配拆成级联的调谐电路，并设置不同级的并联谐振网络的中央频率处在以设定关系错开的不同值上，并驱动后一级的功率合成电路；
    所述的功率合成电路通过两个伪差分对放大器输出功率并进行合成，获得最终合成的功率放大信号。
  11. 如权利要求10所述的电子设备，其中，所述的参差调谐电路包括输入匹配网络、第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的输入匹配网络的输出端连接所述第一放大器的输入端，所述第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
  12. 如权利要求10所述的电子设备，其中，所述的参差调谐电 路包括第一放大器、第二放大器、第一中间级匹配网络和第二中间级匹配网络，所述的第一放大器的输出端连接所述第一中间级匹配网络的输入端，所述第一中间级匹配网络的输出端连接所述第二放大器的输入端，所述第二放大器的输出端连接所述第二中间级匹配网络的输入端。
  13. 如权利要求10所述的电子设备，其中，所述的设定关系具体为通过预设频率值与协调系数相乘或除获得不同级的并联谐振网络的中央频率，所述的预设频率值是功率放大器工作通带的中心频率，所述的协调系数根据所需系统带宽及其带内平整度获得。
  14. 如权利要求10所述的电子设备，其中，所述的功率合成电路包括第三放大器、第四放大器和功率合成谐振网络，所述第三放大器与第四放大器并联，所述第三放大器的输出端与所述第四放大器的输出端均连接功率合成谐振网络的输入端。
  15. 如权利要求14所述的电子设备，其中，所述的第三放大器和所述第四放大器为一个三层级联伪差分对；所述第三放大器和所述第四放大器内部结构相同，均包括第一深N阱N-MOS管、第二深N阱N-MOS管、第三深N阱N-MOS管、第四深N阱N-MOS管、第一N-MOS管、第二N-MOS管、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻、第七电阻和第八电阻，其中，所述的第一深N阱N-MOS管的深N阱连接所述第一电阻的一端，所述第一电阻的另一端连接所述第二电阻的一端并接电源电压，所述第二电阻的另一端连接所述第二深N阱N-MOS管的深N阱；所述的第一深N阱N-MOS管的体端连接所述第三电阻的一端，所述第三电阻的另一端连接所述第一深N阱N-MOS管的源极并连接所述第三深N阱N-MOS管的漏极；所述的第二深N阱N-MOS管的体端连接所述第四电阻的一端，所述第四电阻的另一端连接所述第二深N阱N-MOS管的源极并连接所述第四深N阱N-MOS管的漏极；所述的 第三深N阱N-MOS管的深N阱连接所述第五电阻的一端，所述第五电阻的另一端连接所述第六电阻的一端并接电源电压，所述第六电阻的另一端连接所述第四深N阱N-MOS管的深N阱；所述的第三深N阱N-MOS管的体端连接所述第七电阻的一端，所述第七电阻的另一端连接所述第三深N阱N-MOS管的源极并连接所述第一N-MOS管的漏极；所述的第四深N阱N-MOS管的体端连接所述第八电阻的一端，所述第八电阻的另一端连接所述第四深N阱N-MOS管的源极并连接所述第二N-MOS管的漏极；所述的第一N-MOS管的源极连接所述第二N-MOS管的源极并接地。
  16. 如权利要求15所述的电子设备，其中，所述的第一深N阱N-MOS管和第二深N阱N-MOS管均为深N阱正常电压门限厚栅氧层N-MOS管。
  17. 如权利要求15所述的电子设备，其中，所述的第三深N阱N-MOS管和第四深N阱N-MOS管均为深N阱低电压门限薄栅氧层N-MOS管。
  18. 如权利要求15所述的电子设备，其中，所述的第一N-MOS管和第二N-MOS管均为低电压门限薄栅氧层N-MOS管。
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