WO2019037792A1 - 一种干扰处理方法、装置和电路 - Google Patents

一种干扰处理方法、装置和电路 Download PDF

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Publication number
WO2019037792A1
WO2019037792A1 PCT/CN2018/102527 CN2018102527W WO2019037792A1 WO 2019037792 A1 WO2019037792 A1 WO 2019037792A1 CN 2018102527 W CN2018102527 W CN 2018102527W WO 2019037792 A1 WO2019037792 A1 WO 2019037792A1
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Prior art keywords
ddr
signal
processing
reference signal
interference
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PCT/CN2018/102527
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English (en)
French (fr)
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杜冰
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西安中兴新软件有限责任公司
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Publication of WO2019037792A1 publication Critical patent/WO2019037792A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
    • H04B1/1036—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters

Definitions

  • the present disclosure relates to, but is not limited to, the field of wireless communication technology.
  • RF transceiver performance has become one of the main performance indicators of users' attention.
  • the radio frequency transceiver performance of a terminal device (such as a smart terminal) is directly related to the user's call or data communication experience.
  • a good antenna receiving sensitivity can ensure that the user can still obtain a good call experience under weak signals.
  • the receiving sensitivity and the conduction sensitivity of the antenna are closely related to the electromagnetic compatibility (Electro Magnetic Compatibility, EMC for short) design of the terminal device.
  • EMC Electro Magnetic Compatibility
  • the interference of high-speed digital signals mainly comes from double-rate synchronous dynamic random access memory (Dual Data Rate, DDR for short).
  • DDR Double Data Rate
  • the current EMC design of the terminal uses the routing stack to avoid and increase the shield. Physical shielding is achieved to solve electromagnetic interference (Electro Magnetic Interference, EMI) and EMC problems.
  • EMI Electro Magnetic Interference
  • the design of the trace stack avoidance is limited by the size of the board, and the smaller the board size, the more difficult the design of the trace stack avoidance.
  • the shield cover in order to increase the physical shielding of the shield cover: on the one hand, it will increase the bill of material (Bill of Material, BOM for short); on the other hand, the shield will have a gap, and the electromagnetic field energy will be diffracted through the slit. It is free space and coupled to the receiving circuit through an antenna, thereby interfering with the receiving sensitivity of the antenna.
  • BOM Bill of Material
  • an embodiment of the present disclosure provides an interference processing method, apparatus, and circuit.
  • an embodiment of the present disclosure provides an interference processing method, including: performing inverse processing on a double rate synchronous dynamic random access memory (DDR) reference signal according to a pre-configured processing parameter to generate a DDR reverse reference signal. And performing cancellation processing on the signal received by the terminal device by using the DDR reverse reference signal to obtain a feedback signal, where the signal received by the terminal device includes an operation signal and a DDR interference signal.
  • DDR double rate synchronous dynamic random access memory
  • an embodiment of the present disclosure further provides an interference processing apparatus, where the interference processing apparatus includes: a processing module configured to perform inverse processing on the DDR reference signal according to the pre-configured processing parameter to generate a DDR reverse reference signal And a cancellation module configured to cancel the signal received by the terminal device by using the DDR reverse reference signal generated by the processing module to obtain a feedback signal, where the signal received by the terminal device includes an operation signal and a DDR interference signal.
  • the interference processing apparatus includes: a processing module configured to perform inverse processing on the DDR reference signal according to the pre-configured processing parameter to generate a DDR reverse reference signal
  • a cancellation module configured to cancel the signal received by the terminal device by using the DDR reverse reference signal generated by the processing module to obtain a feedback signal, where the signal received by the terminal device includes an operation signal and a DDR interference signal.
  • an embodiment of the present disclosure further provides an interference processing circuit including: a DDR chip, a processor, and a coupler, wherein the DDR chip is configured to generate a DDR signal; the processor is configured to Performing a reverse processing on the DDR reference signal according to the pre-configured processing parameters to generate a DDR reverse reference signal, the DDR reference signal being the same as the DDR signal; the coupler being configured as a DDR reverse generated by the processor
  • the reference signal cancels the signal received by the terminal device, obtains a feedback signal, and transmits the feedback signal to the receiving circuit, where the signal received by the terminal device includes a working signal and a (induced) DDR brought by the DDR chip. Interference signal.
  • an embodiment of the present disclosure further provides a computer readable storage medium storing computer executable instructions, and when the processor executes the computer executable instructions, performing the following operations:
  • the configured processing parameter reversely processes the DDR reference signal to generate a DDR reverse reference signal; and, by using the DDR reverse reference signal, cancels a signal received by the terminal device to obtain a feedback signal, and the terminal device receives the The signal includes the working signal and the DDR interference signal.
  • FIG. 1 is a flowchart of an interference processing method according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of another interference processing method according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of still another interference processing method according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an interference processing apparatus according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another interference processing apparatus according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another interference processing apparatus according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an interference processing circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another interference processing circuit according to an embodiment of the present disclosure.
  • the receiving sensitivity and conduction sensitivity of the antenna are closely related to the EMC design of the terminal device. If the high-speed digital circuit brings additional interference signals, the deterioration of the receiving sensitivity is very significant, and in extreme cases, it will have a catastrophic impact on the user's call or data service.
  • the interference for high-speed digital signals mainly comes from the current status of DDR chips.
  • the EMC design of terminal devices uses the method of routing stack avoidance and adding shields to achieve physical shielding to solve EMI and EMC problems.
  • the broadband harmonic interference caused by the DDR chip is difficult to be completely eliminated by the above method, and will bring Additional cost. Therefore, how to eliminate the interference of the DDR chip to the antenna receiving sensitivity is an urgent problem to be solved.
  • the DDR chip in the following embodiments of the present disclosure is a chip disposed in the terminal device, and the terminal device is, for example, a terminal having a communication function, such as a smart phone or a tablet computer, in the following.
  • the terminal device is, for example, a terminal having a communication function, such as a smart phone or a tablet computer, in the following.
  • the following specific embodiments of the present disclosure may be combined with each other, and the same or similar concepts or processes may not be described in some embodiments.
  • FIG. 1 is a flowchart of an interference processing method according to an embodiment of the present disclosure.
  • the interference processing method provided in this embodiment is applicable to the situation of eliminating interference caused by the DDR chip of the terminal device.
  • the method can be performed by an interference processing device implemented by a combination of hardware and software, which can be integrated in a processor of the terminal device for use by the processor.
  • the method of the embodiment of the present disclosure may include the following steps:
  • S110 Perform reverse processing on the DDR reference signal according to the pre-configured processing parameter to generate a DDR reverse reference signal.
  • the interference processing method provided by the embodiment of the present disclosure is a method for processing a (caused) DDR interference signal brought by a DDR chip in a terminal device.
  • the pre-configured processing parameter may be a parameter configured in the terminal device processor, and the processing parameter corresponds to an operation mode for performing reverse processing. For example, if the reverse processing includes clipping processing, the processing parameter may include a limiting parameter. If the reverse processing includes delay processing, the processing parameters may include delay parameters; if the reverse processing includes phase shift processing, the processing parameters may include phase parameters.
  • the DDR reference signal in the embodiment of the present disclosure is the same signal as the DDR signal generated by the DDR chip, that is, the DDR reference signal and the DDR signal have the same amplitude and phase, but the DDR reference signal is inversely processed.
  • the post-generated DDR reverse reference signal is different from the DDR signal.
  • the DDR reference signal in embodiments of the present disclosure may be a digital signal reconstruction of a DDR signal.
  • the pre-configured processing parameters in the embodiments of the present disclosure may be preset by the designer according to experience, or may be initial processing parameters set according to the DDR interference signal brought by the DDR chip, or may be based on the feedback signal ( The adjusted processing parameters will be described below).
  • S120 Perform cancellation processing on the signal received by the terminal device by using the DDR reverse reference signal to obtain a feedback signal, where the signal received by the terminal device includes an operation signal and a DDR interference signal.
  • the signal received through the antenna includes an operation signal and a DDR interference signal
  • the working signal may be a valid signal when the user uses the terminal device to make a call or the terminal device transmits the data service, DDR.
  • the interference signal is an interference signal brought by the DDR chip in the terminal device, and the DDR interference signal is the main source of the interference signal in the high-speed digital circuit, that is, the DDR interference signal may have a catastrophic effect on the receiving sensitivity of the terminal device. Therefore, how to eliminate the DDR interference signal when the terminal device normally communicates is a problem to be solved by the embodiments of the present disclosure.
  • the DDR reverse reference signal generated by the reverse processing cancels the signal received by the terminal device (including the working signal and the DDR interference signal), that is, the DDR interference signal is cancelled.
  • the cancellation processing refers to performing vector superposition processing on the above signals, and the result of the cancellation processing requires that the DDR reverse reference signal can cancel out the DDR.
  • the interference effect of the interference signal on the working signal that is to say, the embodiment of the present disclosure eliminates the influence of the DDR interference signal on the high-speed digital circuit by forming a signal having a cancellation effect with the DDR interference signal brought by the DDR chip.
  • the prior art eliminates the interference caused by the DDR chip: on the one hand, the way of routing snagging avoidance is limited by the size of the circuit board, and it is more and more difficult to realize the design of the routing evasion as the size of the circuit board is reduced. On the other hand, increasing the shielding cover not only increases the cost of the terminal device, but also brings new interference factors; therefore, the prior art methods cannot completely eliminate the interference problem caused by the DDR chip.
  • the interference processing method provided by the embodiment of the present disclosure eliminates the impact of the DDR interference signal caused by the DDR chip on the high-speed digital circuit by forming a signal having a canceling effect with the DDR interference signal, wherein
  • the method for forming the above-mentioned signal with cancellation effect that is, the DDR reverse reference signal is easy to implement, and a DDR reference signal identical to the DDR signal can be constructed first, and the physical variables of the DDR reference signal are processed in a specified manner. Obtained, and then, the above two signals are subjected to vector superposition processing to eliminate the DDR interference signal as much as possible, and the working signal required by the terminal device can be obtained.
  • the interference processing method provided by the embodiment of the present disclosure performs reverse processing on the DDR reference signal by using pre-configured processing parameters to generate a DDR reverse reference signal; and cancels the signal received by the terminal device by using the generated DDR reverse reference signal. And obtaining a feedback signal, wherein the signal received by the terminal device includes an operation signal and a DDR interference signal.
  • the DDR reverse reference signal can cancel the DDR interference signal brought by the DDR chip in the terminal device, thereby obtaining an operation signal for the normal operation of the terminal.
  • the above feedback signal can reflect the extent to which the DDR reverse reference signal cancels the DDR interference signal, thereby determining whether the DDR interference signal is completely cancelled for subsequent processing.
  • the method provided by the embodiment of the present disclosure solves the problem that the interference caused by the DDR chip cannot be completely eliminated in the prior art.
  • Embodiments of the present disclosure reconstruct a DDR interference signal that is injected back into the receiving circuit through a coupler. Through the above method, the problem that the interference caused by the DDR chip cannot be completely eliminated in the prior art is solved.
  • FIG. 2 is a flowchart of another interference processing method according to an embodiment of the present disclosure.
  • the method provided by the embodiment of the present disclosure may further include:
  • the DDR reference signal in step S110 is exactly the same as the DDR signal generated by the DDR chip, and the purpose is to construct a signal identical to the DDR signal, and inversely process the signal, so that The reverse processed DDR reverse reference signal can achieve the effect of canceling the DDR interference signal. Therefore, before the step S110, the embodiment of the present disclosure can construct a DDR reference signal identical thereto according to the known DDR signal, and perform reverse processing on the DDR reference signal as a target object.
  • the DDR reference signal can be a digital signal reconstruction of the DDR signal.
  • the processing parameter pre-configured in the terminal device may include one or more of a clipping parameter, a delay parameter, and a phase parameter.
  • the implementation manner of step S110 may include the following processing manner. One or more of them:
  • a limiter can be used to perform amplitude control on the DDR reference signal.
  • the limiter has several adjustable ports, and different gear positions limit the amplitude of the signal to a preset.
  • the preset range is: +/-10mv
  • the amplitude of the DDR reference signal after the amplitude control is greater than +10mv or the amplitude is less than -10mv is limited to the range of +/-10mv, ie
  • the amplitude of the processed signal does not exceed +/- 10 mv; in another example, depending on the amplitude of the DDR reference signal (ie, the amplitude of the DDR signal) and the amplitude of the DDR interfering signal actually present in the signal received by the terminal device,
  • the limiter scales the amplitude of the DDR reference signal proportionally.
  • the delay processing of the DDR parameter by the delay device may also be adopted.
  • the magnitude of the delay parameter is usually determined by the processing rate of the DDR chip.
  • the processing rate of the DDR chip is megahertz (MHz).
  • the delay parameter is in the microsecond (us) level, and the delay parameter can be divided into 10 gear positions of 0 to 9 us, and each gear position adjusts the delay of the DDR reference signal to a different extent.
  • the phase shift processing method of the DDR reference signal by the phase shifter may be further adopted. For the digital signal, the phase is divided into 0 and 1, 0 represents 0 to 180 degrees, and 1 represents 180 360 degrees, phase control is performed by setting 0 or 1.
  • the embodiment of the present disclosure does not limit the specific manner of performing reverse processing on the DDR reference signal.
  • the foregoing various processing manners are only illustrative, and one or more of the foregoing may be performed, and may also include other reverse directions.
  • the processing manner can be used in the reverse processing manner in the embodiment of the present disclosure as long as it can form a processing manner for canceling the DDR interference signal.
  • the embodiment of the present disclosure does not limit the execution order of the steps S111 to S113.
  • the steps may be sequentially performed in the order of S111 to S113, or may be performed synchronously.
  • the flow shown in FIG. 2 is shown by taking S111 to S113 as an example.
  • FIG. 3 is a flowchart of still another interference processing method according to an embodiment of the present disclosure.
  • the feedback signal obtained by performing the cancellation processing in step S120 can be used to indicate the extent to which the DDR interference signal is cancelled by the DDR reverse reference signal.
  • the DDR interference signal may not be completely cancelled by the DDR reverse reference signal, only a part of which is cancelled.
  • the method provided by the embodiment of the present disclosure may further include:
  • step S125 Determine whether the feedback signal indicates that the DDR interference signal is completely cancelled by the DDR reverse reference signal. If the result of the determination is YES, the flow ends, and if the result of the determination is No, step S130 is performed.
  • step S130 Adjust the current processing parameter according to the feedback signal obtained by the last offset processing (step S120 or step S150 described below).
  • S140 Perform reverse processing on the DDR reference signal according to the adjusted processing parameter.
  • the feedback signal is obtained by canceling the signal received by the terminal device through the reverse processed DDR reverse reference signal, and the DDR reference before the DDR reverse reference signal is reverse processed.
  • the signal is exactly the same as the DDR signal.
  • the purpose of the reverse processing is to offset the DDR interference signal by the DDR reverse reference signal, thereby eliminating the influence of the DDR interference signal on the working signal. Therefore, in the embodiment of the present disclosure, the DDR reverse reference signal can be used to determine the degree of the DDR interference signal by the feedback signal, that is, the feedback signal can reflect the receiving sensitivity index of the terminal device, and the higher the sensitivity index, the degree to which the DDR interference signal is cancelled.
  • the lower the sensitivity index the less the DDR interference signal is cancelled. Therefore, when the feedback signal indicates that there is still a certain degree of DDR interference signal, it indicates that the DDR reverse reference signal does not completely cancel the DDR interference signal.
  • the pre-configured processing parameter can also be adjusted by the feedback signal, thereby Re-processing the DDR reference signal according to the adjusted processing parameters, and performing the cancellation processing on the DDR interference signal again by the retrieved DDR reverse reference signal, thereby continuously adjusting the processing parameters, that is, repeating steps S130-S150 Until the DDR reverse reference signal obtained after processing according to the processing parameters can completely cancel out the DDR interference signal.
  • the embodiment of the present disclosure reversely processes the DDR reference signal by using the processing parameters, and adjusts the processing parameters according to the feedback signal after the cancellation processing to form a closed-loop processing mode, and the DDR reverse reference signal interferes with the DDR by continuously adjusting the processing parameters.
  • the offset of the signal is getting higher and higher until the DDR interference signal can be completely cancelled.
  • the way to adjust the processing parameters according to the feedback signal can be implemented by software. For example, by adjusting multiple times, it can be judged that the DDR interference signal is completely cancelled.
  • the processing parameters of the signal, namely amplitude, delay and phase, and the DDR reference signal are adjusted accordingly, and the target of completely canceling the DDR interference signal is continuously approached during the adjustment process.
  • the feedback signal described above can be instantiated as the receiving sensitivity of the terminal device.
  • the "complete cancellation" mentioned above can be instantiated as the receiving sensitivity of the terminal device reaches a preset threshold.
  • the amplitude and delay factor of the injected interference signal can be adjusted according to the degree to which the receiving sensitivity is lower than the preset threshold, thereby performing closed-loop adjustment.
  • FIG. 4 is a schematic structural diagram of an interference processing apparatus according to an embodiment of the present disclosure.
  • the interference processing device provided in this embodiment is applicable to the situation of eliminating the interference caused by the DDR chip of the terminal device.
  • the interference processing device is implemented by a combination of hardware and software, and the device can be integrated in the processor of the terminal device for The processor calls are used.
  • the interference processing apparatus 10 of this embodiment may include: a processing module 11 and a cancellation module 12.
  • the processing module 11 is configured to inversely process the DDR reference signal according to the pre-configured processing parameters to generate a DDR reverse reference signal.
  • the cancellation module 12 is configured to cancel the signal received by the terminal device by using the DDR reverse reference signal generated by the processing module 11, to obtain a feedback signal, and the signal received by the terminal device includes an operation signal and a DDR interference signal.
  • the DDR reverse reference signal generated by the cancellation module 12 after being processed by the processing module 11 performs cancellation processing on the signal received by the terminal device (including the working signal and the DDR interference signal), that is, the DDR is The interference signal is subjected to cancellation processing. Since the DDR interference signal and the DDR reverse reference signal are directional and have different phases, the cancellation processing refers to performing vector superposition processing on the above signals. The result of the cancellation processing by the cancellation module 12 requires that the DDR reverse reference signal can offset the interference effect of the DDR interference signal on the working signal.
  • the interference processing device provided by the embodiment of the present disclosure is configured to perform the interference processing method provided by the embodiment shown in FIG. 1 of the present disclosure, and has a corresponding functional module, and the implementation principle and the technical effect thereof are similar, and details are not described herein again.
  • FIG. 5 is a schematic structural diagram of another interference processing apparatus according to an embodiment of the present disclosure.
  • the interference processing apparatus 10 provided by the embodiment of the present disclosure may further include:
  • the construction module 13 is configured to construct a DDR reference signal according to the DDR signal generated by the DDR chip before the processing module 11 reverse-processes the DDR reference signal according to the pre-configured processing parameters, and the DDR reference signal is the same as the DDR signal.
  • the building block 13 in the embodiment of the present disclosure can construct a DDR reference signal identical thereto according to the known DDR signal, and perform reverse processing on the DDR reference signal as a target object.
  • the DDR reference signal can be a digital signal reconstruction of the DDR signal.
  • the pre-configured processing parameters in the terminal device may include one or more of a clipping parameter, a delay parameter, and a phase parameter.
  • the processing module 11 may include one of the following units. Item or items:
  • a limiting unit 111 configured to control the amplitude of the DDR reference signal according to the limiting parameter
  • a delay unit 112 configured to control a delay factor of the DDR reference signal according to the delay parameter
  • the phase shifting unit 113 is configured to control the phase of the DDR reference signal according to the phase parameter.
  • the limiting unit 111 may be used to perform amplitude control on the DDR reference signal.
  • the limiting unit 111 has several adjustable ports, and different gear positions limit the amplitude of the signal to Within the preset range, for example, the preset range is: +/-10mv, then the amplitude of the DDR reference signal after the amplitude control is greater than +10mv or the amplitude is less than -10mv is limited to the range of +/-10mv, That is, the amplitude of the signal after clipping processing does not exceed +/- 10 mv; in another example, according to the amplitude of the DDR reference signal (ie, the amplitude of the DDR signal) and the DDR interference signal actually present in the signal received by the terminal device
  • the amplitude, clipping unit 111 scales the amplitude of the DDR reference signal proportionally.
  • the delay unit 112 may also be used to perform delay control on the DDR parameter.
  • the magnitude of the delay parameter is usually determined by the processing rate of the DDR chip.
  • the processing rate of the DDR chip is megahertz (MHz).
  • the delay parameter is in the order of microseconds (us), and the delay parameter can be divided into 10 gear positions of 0 to 9 us, and the degree of adjustment of the delay of the DDR reference signal is different for each gear position;
  • the DDR reference signal performs phase control processing. For digital signals, the phase is divided into 0 and 1, 0 means 0 to 180 degrees, and 1 means 180 to 360 degrees. Phase control is performed by setting 0 or 1.
  • the embodiment of the present disclosure does not limit the specific manner in which the processing module 11 performs reverse processing on the DDR reference signal.
  • the limiting unit 111, the delay unit 112, and the phase shifting unit 113 are only illustrative, and the processing module 11 may Including one or more of them, may also include other functional modules for performing reverse processing, as long as it is a functional module that can form a cancellation for DDR interference signals, which can be used to perform the embodiments in the embodiments of the present disclosure. Reverse processing.
  • the embodiment of the present disclosure does not limit the order in which the limiter unit 111, the delay unit 112, and the phase shifting unit 113 perform processing, which may be performed according to a certain order, or may be performed synchronously.
  • the interference processing apparatus provided by the embodiment of the present disclosure is configured to perform the interference processing method provided by the embodiment shown in FIG. 2 of the present disclosure, and has a corresponding functional module, and the implementation principle and the technical effect are similar, and details are not described herein again.
  • FIG. 6 is a schematic structural diagram of still another interference processing apparatus according to an embodiment of the present disclosure.
  • the feedback signal obtained by the cancellation module 12 after the cancellation processing is used to indicate the extent to which the DDR interference signal is cancelled by the DDR reverse reference signal, that is, after the cancellation module 12 performs an offset process.
  • the DDR interference signal may not be completely offset by the DDR backreference signal, only a fraction of which is offset.
  • the interference processing device 10 provided by the embodiment of the present disclosure may further include:
  • the adjustment module 14 is configured to adjust the processing parameters according to the feedback signal obtained by the cancellation module 12.
  • the processing module 11 may re-process the DDR reference signal according to the adjusted processing parameters of the adjustment module 14; and the cancellation module 12 may be reverse processed by the processing module 11
  • the DDR reverse reference signal cancels the signal received by the terminal device and regains the feedback signal.
  • the DDR reverse reference signal when the feedback signal indicates that there is still a certain degree of DDR interference signal, the DDR reverse reference signal does not completely cancel the DDR interference signal, and may be passed by the adjustment module 14 at this time.
  • the feedback signal adjusts the pre-configured processing parameters, so that the processing module 11 re-processes the DDR reference signal according to the adjusted processing parameter, and the recovered DDR reverse reference signal is obtained by the cancellation module 12.
  • the DDR interference signal is again cancelled, so that the processing parameters are continuously adjusted, that is, the operations of performing reverse processing, canceling processing, and adjusting processing parameters are repeated until the DDR reverse reference signal obtained after processing according to the processing parameters can be completely cancelled out. DDR interference signal.
  • the embodiment of the present disclosure reversely processes the DDR reference signal by using the processing parameters, and adjusts the processing parameters according to the feedback signal after the cancellation processing to form a closed-loop processing mode, and the DDR reverse reference signal interferes with the DDR by continuously adjusting the processing parameters.
  • the offset of the signal is higher and higher until the DDR interference signal can be completely cancelled.
  • the manner in which the adjustment module 14 adjusts the processing parameters according to the feedback signal can be implemented by software. For example, by adjusting multiple times, it can be determined that the DDR can be completely cancelled.
  • the processing parameters of the signal of the interference signal, namely amplitude, delay and phase, etc., and the DDR reference signal are adjusted accordingly, and the target of completely canceling the DDR interference signal is continuously approached during the adjustment process.
  • the adjustment module 14 can store the processed parameters after each adjustment as a parameter for the next reverse processing of the DDR reference signal.
  • the interference processing apparatus provided by the embodiment of the present disclosure is configured to perform the interference processing method provided by the embodiment shown in FIG. 3 of the present disclosure, and has a corresponding function module, and the implementation principle and the technical effect are similar, and details are not described herein again.
  • FIG. 7 is a schematic structural diagram of an interference processing circuit according to an embodiment of the present disclosure.
  • the interference processing circuit may be disposed in the terminal device.
  • the interference processing circuit of this embodiment may include a DDR chip 21, a processor 22, a coupler 23, and a receiving circuit 24.
  • the DDR chip 21 is configured to generate a DDR signal.
  • the processor 22 is configured to inverse process the DDR reference signal according to the pre-configured processing parameters to generate a DDR reverse reference signal that is identical to the DDR signal described above.
  • the interference processing circuit provided by the embodiment of the present disclosure is configured to process a DDR interference signal brought by the DDR chip 21 in the terminal device.
  • the pre-configured processing parameters may be parameters configured in the terminal device processor 22, and the processing parameters are corresponding to the operation mode for performing the reverse processing, which has been described in detail in the foregoing embodiments, and therefore will not be further described herein.
  • the DDR chip 21 is a conventional chip configured in the terminal device, which itself generates a DDR signal, and brings a DDR interference signal in a signal received by the terminal device during use.
  • the DDR reference signal in the embodiment of the present disclosure is the same signal as the DDR signal generated by the DDR chip 21, that is, the DDR reference signal and the DDR signal have the same amplitude and phase, and the DDR reference signal can be implemented by software.
  • the DDR reverse reference signal generated by the processor 22 after the reverse processing of the DDR reference signal is different from the DDR interference signal.
  • the pre-configured processing parameters in the embodiment of the present disclosure may be preset by the designer according to experience. It may also be an initial processing parameter set according to the DDR interference signal brought to the DDR chip 21.
  • the coupler 23 is configured to cancel the signal received by the terminal device by using the DDR reverse reference signal generated by the processor 22, obtain a feedback signal, and transmit the feedback signal to the receiving circuit 24, where the signal received by the terminal device includes an operating signal. And the DDR interference signal brought by the DDR chip 21.
  • the signal received by the coupler 23 through the antenna 25 includes an operation signal and a DDR interference signal.
  • the DDR reverse reference signal generated by the coupler 23 after the reverse processing by the processor 22 cancels the signal received by the terminal device (including the working signal and the DDR interference signal), that is, cancels the DDR interference signal.
  • the result of the cancellation processing by the coupler 23 requires that the DDR reverse reference signal can offset the interference effect of the DDR interference signal on the working signal. That is to say, the embodiment of the present disclosure eliminates the influence of the DDR interference signal brought by the DDR chip 21 on the high-speed digital circuit by forming a signal having a canceling effect with the DDR interference signal.
  • the interference processing circuit provided by the embodiment of the present disclosure is used to perform the interference processing method provided by the embodiment shown in FIG. 1 of the present disclosure, and has a corresponding physical device, and the implementation principle and the technical effect are similar, and details are not described herein again.
  • FIG. 8 is a schematic structural diagram of another interference processing circuit according to an embodiment of the present disclosure.
  • the circuit provided by the embodiment of the present disclosure may further include:
  • the simulator 26 is configured to construct a DDR reference signal based on the DDR signal generated by the DDR chip 21 before the processor 22 reverse-processes the DDR reference signal according to the pre-configured processing parameters, the DDR reference signal being the same as the DDR signal.
  • the DDR reference signal can be constructed by software, and the simulator 26 is, for example, a carrier for constructing a DDR reference signal by software.
  • the object to be reverse processed by the processor 22, that is, the DDR reference signal is exactly the same as the DDR signal generated by the DDR chip 21, in order to construct a signal identical to the DDR signal.
  • the signal is reverse processed, so that the reverse processed DDR reverse reference signal can achieve the effect of canceling the DDR interference signal.
  • the simulator 26 in the embodiment of the present disclosure can construct a DDR reference signal identical thereto according to the known DDR signal, and perform reverse processing on the DDR reference signal as a target object.
  • the DDR reference signal can be a digital signal reconstruction of the DDR signal.
  • the processing parameters pre-configured in the terminal device may include one or more of a clipping parameter, a delay parameter, and a phase parameter.
  • the processor 22 may include one or more of the following: item:
  • a limiter 221 configured to control an amplitude of the DDR reference signal according to the clipping parameter
  • a delay 222 configured to control a delay factor of the DDR reference signal according to the delay parameter
  • a phase shifter 223 is configured to control the phase of the DDR reference signal based on the phase parameter.
  • the interference processing circuit provided by the embodiment of the present disclosure is used to perform the interference processing method provided by the embodiment shown in FIG. 2 of the present disclosure, and has a corresponding physical device, and the implementation principle and the technical effect are similar, and details are not described herein again.
  • the feedback signal obtained by the coupler 23 after the cancellation processing is used to indicate the extent to which the DDR interference signal is cancelled by the DDR reverse reference signal, that is, the canceling is performed at the coupler 23.
  • the DDR interfering signal may not be completely offset by the DDR backreference signal, only a fraction of which is offset.
  • the receiving circuit 24 can be configured to transmit a feedback signal to the processor 22;
  • the processor 22 is further configured to adjust the processing parameters according to the feedback signal, and re-process the DDR reference signal according to the adjusted processing parameters;
  • the coupler 23 can also be configured to cancel the feedback signal by canceling the signal received by the terminal device by the DDR reverse reference signal obtained by the processor 22 to perform the reverse processing.
  • the DDR reverse reference signal when the feedback signal indicates that there is still a certain degree of DDR interference signal, the DDR reverse reference signal does not completely cancel the DDR interference signal.
  • the receiving circuit 24 may be directed to the processor. 22, the feedback signal is sent, and the processor 22 can further adjust the pre-configured processing parameters by using the feedback signal, so that the DDR reference signal is re-processed according to the adjusted processing parameter, and then the coupler 23 passes The retrieved DDR reverse reference signal again cancels the DDR interference signal, so that the processor 22 can continuously adjust the processing parameters, that is, repeatedly perform the reverse processing, the offset processing, and the adjustment processing parameters until the processing is performed according to the processing parameters. The resulting DDR reverse reference signal can completely cancel out the DDR interference signal.
  • the processor 22 in the embodiment of the present disclosure reversely processes the DDR reference signal by using the processing parameters, and adjusts the processing parameters according to the feedback signal after the cancellation processing to form a closed loop processing mode, and the DDR reverse is performed by continuously adjusting the processing parameters.
  • the offset of the reference signal to the DDR interference signal is higher and higher until the DDR interference signal can be completely cancelled.
  • the manner in which the processor 22 adjusts the processing parameters according to the feedback signal can be implemented by software, for example, by multiple adjustments.
  • the processing parameters of the signal used to completely cancel the DDR interference signal, namely amplitude, delay and phase, etc., and the DDR reference signal are adjusted accordingly, and the target of completely canceling the DDR interference signal is continuously approached during the adjustment process.
  • the interference processing circuit provided by the embodiment of the present disclosure is configured to perform the interference processing method provided by the embodiment shown in FIG. 3 of the present disclosure, and has a corresponding physical device, and the implementation principle and the technical effect are similar, and details are not described herein again.
  • the embodiment of the present disclosure further provides a computer readable storage medium storing computer executable instructions, and when the processor executes the computer executable instructions, the following operations are performed:
  • S31 Perform reverse processing on the DDR reference signal according to the pre-configured processing parameter to generate a DDR reverse reference signal.
  • the foregoing parameter may include one or more of a clipping parameter, a delay parameter, and a phase parameter, and when the processor executes the computer executable instruction, performing the implementation of operation S32.
  • a clipping parameter e.g., a clipping parameter, a delay parameter, and a phase parameter
  • the processor executes the computer executable instruction, performing the implementation of operation S32.
  • the feedback signal is used to indicate that the DDR interference signal is offset by the DDR reverse reference signal, and when the processor executes the computer executable instruction, the following operations are further performed:
  • a program to instruct related hardware e.g., a processor
  • a computer readable storage medium such as a read only memory, disk or optical disk. Wait.
  • all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits.
  • each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
  • Embodiments of the present disclosure are not limited to any specific form of combination of hardware and software.

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Abstract

本公开实施例公开了一种干扰处理方法、装置和电路。本公开实施例中的干扰处理方法包括：根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；通过所述DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。

Description

一种干扰处理方法、装置和电路 技术领域
本公开涉及但不限于无线通信技术领域。
背景技术
随着终端设备的发展与广泛应用，射频收发性能成为用户关注的主要性能指标之一。终端设备(例如智能终端)的射频收发性能直接关系到用户的通话或者数据通信体验，良好的天线接收灵敏度可以保证用户在弱信号下依然可以获得好的通话体验。
在终端设备的天线形式确定的情况下，天线的接收灵敏度以及传导灵敏度与终端设备的电磁兼容(Electro Magnetic Compatibility，简称为：EMC)设计密切相关。通常地，高速数字信号的干扰主要来自于双倍速率同步动态随机存储器(Dual Data Rate，简称为：DDR)芯片，针对这一现状，目前终端的EMC设计采用走线叠层避让和增加屏蔽罩实现物理屏蔽的方式来解决电磁干扰(Electro Magnetic Interference，简称为：EMI)和EMC问题。然而，走线叠层避让的设计方式受限于电路板尺寸，电路板尺寸越小，走线叠层避让的设计越困难。另外，针对增加屏蔽罩实现物理屏蔽的方式：一方面，会增加终端设备的物料清单(Bill of Material，简称为：BOM)成本；另一方面，屏蔽罩会有缝隙，电磁场能量会通过缝隙衍射到自由空间并且通过天线耦合到接收电路，从而干扰天线的接收灵敏度。
发明内容
为了至少部分解决上述技术问题，本公开实施例提供了一种干扰处理方法、装置和电路。
根据第一方面，本公开实施例提供一种干扰处理方法，该方法包括：根据预配置的处理参数对双倍速率同步动态随机存储器(DDR)参考信号进行 反向处理，生成DDR反向参考信号；以及，通过所述DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。
根据第二方面，本公开实施例还提供一种干扰处理装置，该干扰处理装置包括：处理模块，其构造为根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；以及，抵消模块，其构造为通过所述处理模块生成的DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。
根据第三方面，本公开实施例还提供一种干扰处理电路，该干扰处理电路包括：DDR芯片、处理器和耦合器，其中，所述DDR芯片构造为产生DDR信号；所述处理器构造为根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号，所述DDR参考信号与所述DDR信号相同；所述耦合器构造为通过所述处理器生成的DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，并将所述反馈信号传输到接收电路，所述终端设备接收的信号包括工作信号和所述DDR芯片带来的(导致的)DDR干扰信号。
根据第四方面，本公开实施例还提供一种计算机可读存储介质，所述计算机可读存储介质存储有计算机可执行指令，处理器执行所述计算机可执行指令时，进行如下操作：根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；以及，通过所述DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的一种干扰处理方法的流程图；
图2为本公开实施例提供的另一种干扰处理方法的流程图；
图3为本公开实施例提供的又一种干扰处理方法的流程图；
图4为本公开实施例提供的一种干扰处理装置的结构示意图；
图5为本公开实施例提供的另一种干扰处理装置的结构示意图；
图6为本公开实施例提供的又一种干扰处理装置的结构示意图；
图7为本公开实施例提供的一种干扰处理电路的结构示意图；
图8为本公开实施例提供的另一种干扰处理电路的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
如在上述背景技术中所说明，天线的接收灵敏度及传导灵敏度与终端设备的EMC设计密切相关。如果高速数字电路带来额外的干扰信号，则对接收灵敏度的恶化非常可观，极端情况下会对用户的通话或者数据业务带来灾难性的影响。
针对高速数字信号的干扰主要来自于DDR芯片的现状，现有技术中终端设备的EMC设计采用走线叠层避让和增加屏蔽罩实现物理屏蔽的方式来解决EMI和EMC问题。但随着终端设备电路板尺寸的减小和物理屏蔽的固有缺陷(屏蔽罩的使用会增加成本)，DDR芯片带来的宽频谐波干扰很难通过上述方式得到彻底的消除，并且会带来额外的成本。因此，如何消除DDR芯片对天线接收灵敏度的干扰，是目前亟需解决的问题。
下面通过具体的实施例对本公开的技术方案进行详细说明，本公开以下各实施例中的DDR芯片为配置于终端设备中的芯片，终端设备例如为智能 手机、平板电脑等具有通信功能的终端。本公开提供的以下几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图1为本公开实施例提供的一种干扰处理方法的流程图。本实施例提供的干扰处理方法适用于消除终端设备的DDR芯片带来的干扰的情况。该方法可以由干扰处理装置执行，该干扰处理装置通过硬件和软件结合的方式来实现，该装置可以集成在终端设备的处理器中，供处理器调用使用。如图1所示，本公开实施例的方法可以包括如下步骤：
S110，根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号。
本公开实施例提供的干扰处理方法，为对终端设备中DDR芯片带来的(导致的)DDR干扰信号进行处理的方法。其中，预配置的处理参数可以为配置于终端设备处理器中的参数，这些处理参数与进行反向处理的操作方式对应，例如，如果反向处理包括限幅处理，处理参数可以包括限幅参数；如果反向处理包括延迟处理，处理参数可以包括延迟参数；如果反向处理包括移相处理，处理参数可以包括相位参数。
需要说明的是，本公开实施例中的DDR参考信号为与DDR芯片所产生的DDR信号相同的信号，即DDR参考信号与DDR信号的幅度和相位完全相同，但对DDR参考信号进行反向处理后生成的DDR反向参考信号与DDR信号不同。本公开实施例中的DDR参考信号可以是DDR信号的数字信号重建。另外，本公开实施例中预配置的处理参数可以是设计人员根据经验预先设定的，也可以是根据对DDR芯片所带来的DDR干扰信号设置的初始处理参数，还可以是根据反馈信号(将在下文中描述)而调整后的处理参数。
S120，通过DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，该终端设备接收的信号包括工作信号和DDR干扰信号。
在本公开实施例中，终端设备在正常工作时，通过天线接收到的信号包括工作信号和DDR干扰信号，工作信号可以为用户使用终端设备进行通话或者终端设备传输数据业务时的有效信号，DDR干扰信号则是由终端设备中的DDR芯片带来的干扰信号，该DDR干扰信号为高速数字电路中干扰信号 的主要来源，即DDR干扰信号可能对终端设备的接收灵敏度造成灾难性的影响。因此，如何消除终端设备正常通信时的DDR干扰信号是本公开实施例所要解决的问题。
在本公开实施例中，通过反向处理后生成的DDR反向参考信号对终端设备接收到的信号(包括工作信号和DDR干扰信号)进行抵消处理，即是对DDR干扰信号进行抵消处理。由于DDR干扰信号和DDR反向参考信号是具有方向性的，且具有不同的相位，该抵消处理是指对上述信号进行矢量叠加处理，抵消处理后的结果要求DDR反向参考信号可以抵消掉DDR干扰信号对工作信号带来的干扰影响。也就是说，本公开实施例通过形成一个与DDR芯片所带来的DDR干扰信号具有抵消效果的信号，来消除该DDR干扰信号对高速数字电路带来的影响。
现有技术消除DDR芯片带来干扰的方式中：一方面，走线叠层避让的方式受限于电路板尺寸，随着电路板尺寸的减小越来越难实现走线叠层避让的设计方式；另一方面，增加屏蔽罩不仅会增加终端设备的成本，还会带来新的干扰因素；因此，即现有技术中的方式均无法彻底消除DDR芯片带来的干扰问题。相比之下，本公开实施例提供的干扰处理方法，通过形成一个与DDR干扰信号具有抵消效果的信号，来消除该DDR芯片所带来的DDR干扰信号对高速数字电路带来的影响，其中，形成上述具有抵消效果的信号，即DDR反向参考信号的方式易于实现，可以先构建出一个与DDR信号完全相同的DDR参考信号，并对该DDR参考信号的物理变量进行指定方式的处理即可得到，随后，对上述两个信号进行矢量叠加处理以尽可能消除掉DDR干扰信号，就可以得到终端设备所需的工作信号。
本公开实施例提供的干扰处理方法，通过预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；并通过生成的DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，其中，该终端设备接收的信号包括工作信号和DDR干扰信号。上述DDR反向参考信号可以对终端设备中DDR芯片所带来的DDR干扰信号进行抵消，从而得到用于终端正常工作时的工作信号。上述反馈信号可以反映应出DDR反向参考信号对DDR干扰信号进行抵消的程度，从而确定出DDR干扰信号是否被完全 抵消掉，以便进行后续处理。本公开实施例提供的方法，解决了现有技术中无法彻底消除DDR芯片带来的干扰的问题。
本公开实施例重建DDR干扰信号，通过耦合器反向注入接收电路。通过上述方法，解决了现有技术中无法彻底消除DDR芯片带来的干扰的问题。
可选地，图2为本公开实施例提供的另一种干扰处理方法的流程图。在上述实施例的基础上，本公开实施例提供的方法在步骤S110之前，还可以包括：
S100，根据DDR芯片产生的DDR信号构建DDR参考信号，该DDR参考信号与DDR信号相同。
本公开上述实施例中已经说明，步骤S110中的DDR参考信号与DDR芯片所产生的DDR信号完全相同，目的在于构建出一个与DDR信号完全相同的信号，并对该信号进行反向处理，使得反向处理后的DDR反向参考信号可以实现与DDR干扰信号相抵消的效果。因此，本公开实施例在步骤S110之前，可以根据已知的DDR信号构建出与其完全相同的DDR参考信号，将该DDR参考信号作为目标对象进行反向处理。该DDR参考信号可以是该DDR信号的数字信号重建。
可选地，在本公开实施例中，终端设备中预配置的处理参数可以包括限幅参数、延迟参数和相位参数中的一项或多项，另外，步骤S110的实现方式可以包括以下处理方式中的一项或多项：
S111，根据限幅参数对DDR参考信号的幅度进行控制；
S112，根据延迟参数对DDR参考信号的延迟因子进行控制；
S113，根据相位参数对DDR参考信号的相位进行控制。
在本公开实施例中，可以采用限幅器对DDR参考信号进行幅度控制的处理方式，在一个实例中，限幅器中具有几档可调节端口，不同档位将信号的幅度限制在预设范围内，例如，预设范围为：+/-10mv，则DDR参考信号经过幅度控制后，幅度大于+10mv或幅度小于-10mv的部分的被限制在+/-10mv的幅度范围内，即限幅处理后信号的幅度不会超过+/-10mv；在另一个实例中，根据DDR参考信号的幅度(即DDR信号的幅度)以及实际存在 于终端设备接收的信号中的DDR干扰信号的幅度，限幅器对DDR参考信号的幅度进行等比例缩小。另外，在本公开实施例中，还可以采用延迟器对DDR参数进行延迟控制的处理方式，延迟参数的数量级通常由DDR芯片的处理速率决定，例如，DDR芯片的处理速率为兆赫兹(MHz)，延迟参数为微秒(us)级，可以将延迟参数划分为0～9us这10个档位，每个档位对DDR参考信号的延迟的调节程度不同。此外，在本公开实施例中，还可以采用移相器对DDR参考信号进行相位控制的处理方式，对于数字信号来说，相位分为0和1，0表示0～180度，1表示180～360度，采用置位0或1的方式进行相位控制。
需要说明的是，本公开实施例不限制对DDR参考信号进行反向处理的具体方式，上述各种处理方式仅是示意性说明，可以执行其中的一项或多项，还可以包括其它反向处理方式，只要是可以形成用于对DDR干扰信号进行抵消的处理方式，都可以用于本公开实施例中的反向处理方式。另外，本公开实施例不限制步骤S111～S113的执行顺序，例如，这些步骤可以是按S111～S113的顺序依次执行的，也可以是同步执行的。图2所示流程以S111～S113为顺序执行为例予以示出。
可选地，图3为本公开实施例提供的又一种干扰处理方法的流程图。在本公开上述各实施例中，步骤S120中进行抵消处理得到的反馈信号可用于指示DDR干扰信号被DDR反向参考信号所抵消的程度。在执行一次步骤S120后，DDR干扰信号可能没有完全被DDR反向参考信号所抵消，只抵消了其中一部分。为了更有效地消除DDR干扰信号对终端设备中工作信号的影响，本公开实施例提供的方法还可以包括：
S125，判断反馈信号是否指示DDR干扰信号完全被DDR反向参考信号抵消。如果判断结果为是，则流程结束，如果判断结果为否，则执行步骤S130。
S130，根据上一次抵消处理(上述步骤S120或下述步骤S150)得到的反馈信号对当前的处理参数进行调整。
S140，根据调整后的处理参数重新对DDR参考信号进行反向处理；
S150，通过重新进行反向处理后得到的DDR反向参考信号对终端设备接收的信号进行抵消处理，重新得到反馈信号。然后，流程返回步骤S125。
在本公开实施例中，如上所述，反馈信号为通过反向处理后的DDR反向参考信号对终端设备接收的信号进行抵消处理得到的，DDR反向参考信号进行反向处理前的DDR参考信号与DDR信号完全相同，进行反向处理的目的是为了后续利用DDR反向参考信号抵消掉DDR干扰信号，从而消除DDR干扰信号对工作信号的影响。因此，本公开实施例中可以通过反馈信号判断DDR反向参考信号抵消DDR干扰信号的程度，即反馈信号可以体现出终端设备的接收灵敏度指标，灵敏度指标越高，说明DDR干扰信号被抵消的程度较优，灵敏度指标越低，说明DDR干扰信号被抵消的程度较差。因此，在反馈信号指示仍然存在一定程度的DDR干扰信号时，说明DDR反向参考信号并没有完全抵消掉DDR干扰信号，此时，还可以通过该反馈信号对预配置的处理参数进行调整，从而根据调整后的处理参数重新对DDR参考信号进行反向处理，以及通过重新得到的DDR反向参考信号再次对DDR干扰信号进行抵消处理，从而不断的调整处理参数，也就是重复执行步骤S130～S150，直到根据处理参数处理后得到的DDR反向参考信号可以完全抵消掉DDR干扰信号。
本公开实施例采用处理参数对DDR参考信号进行反向处理，并根据抵消处理后的反馈信号调整处理参数，形成一个闭环处理方式，通过不断调整的处理参数，使得DDR反向参考信号对DDR干扰信号的抵消程度越来越高，直到可以完全抵消掉DDR干扰信号，其中，根据反馈信号调整处理参数的方式可以采用软件实现，例如，通过多次调整可以判断出用于完全抵消DDR干扰信号的信号的各项处理参数，即幅度、延迟和相位等，并对DDR参考信号进行相应地调整，在调整过程中不断地接近完全抵消DDR干扰信号的目标。
应当理解，上面所说的反馈信号，可以实例化为终端设备的接收灵敏度。上面所说的“完全抵消”，可以实例化为终端设备的接收灵敏度达到预设的阈值。例如，可根据接收灵敏度低于预设阀值的程度来调节注入的干扰信号的幅度和延迟因子，从而进行闭环调节。
图4为本公开实施例提供的一种干扰处理装置的结构示意图。本实施例提供的干扰处理装置适用于消除终端设备的DDR芯片带来的干扰的情况， 该干扰处理装置通过硬件和软件结合的方式来实现，该装置可以集成在终端设备的处理器中，供处理器调用使用。如图4所示，本实施例的干扰处理装置10可以包括：处理模块11和抵消模块12。
其中，处理模块11构造为根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号。
抵消模块12构造为通过处理模块11生成的DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，该终端设备接收的信号包括工作信号和DDR干扰信号。
在本公开实施例中，抵消模块12通过处理模块11进行反向处理后生成的DDR反向参考信号对终端设备接收到的信号(包括工作信号和DDR干扰信号)进行抵消处理，即是对DDR干扰信号进行抵消处理，由于DDR干扰信号和DDR反向参考信号是具有方向性的，且具有不同的相位，该抵消处理是指对上述信号进行矢量叠加处理。抵消模块12进行抵消处理后的结果要求DDR反向参考信号可以抵消掉DDR干扰信号对工作信号带来的干扰影响。
本公开实施例提供的干扰处理装置用于执行本公开图1所示实施例提供的干扰处理方法，具备相应的功能模块，其实现原理和技术效果类似，此处不再赘述。
可选地，图5为本公开实施例提供的另一种干扰处理装置的结构示意图。在上述实施例的基础上，本公开实施例提供的干扰处理装置10还可以包括：
构建模块13，其构造为在处理模块11根据预配置的处理参数对DDR参考信号进行反向处理之前，根据DDR芯片产生的DDR信号构建DDR参考信号，该DDR参考信号与DDR信号相同。
本公开实施例中的构建模块13，可以根据已知的DDR信号构建出与其完全相同的DDR参考信号，将该DDR参考信号作为目标对象进行反向处理。该DDR参考信号可以是DDR信号的数字信号重建。
可选地，在本公开实施例中，终端设备中预配置的处理参数可以包括限幅参数、延迟参数和相位参数中的一项或多项，另外，处理模块11可以包括 以下单元中的一项或多项：
限幅单元111，其构造为根据限幅参数对DDR参考信号的幅度进行控制；
延迟单元112，其构造为根据延迟参数对DDR参考信号的延迟因子进行控制；
移相单元113，其构造为根据相位参数对DDR参考信号的相位进行控制。
在本公开实施例中，可以采用限幅单元111对DDR参考信号进行幅度控制的处理方式，在一个实例中，限幅单元111中具有几档可调节端口，不同档位将信号的幅度限制在预设范围内，例如，预设范围为：+/-10mv，则DDR参考信号经过幅度控制后，幅度大于+10mv或幅度小于-10mv的部分的被限制在+/-10mv的幅度范围内，即限幅处理后信号的幅度不会超过+/-10mv；在另一个实例中，根据DDR参考信号的幅度(即DDR信号的幅度)以及实际存在于终端设备接收的信号中的DDR干扰信号的幅度，限幅单元111对DDR参考信号的幅度进行等比例缩小。另外，在本公开实施例中，还可以采用延迟单元112对DDR参数进行延迟控制的处理方式，延迟参数的数量级通常由DDR芯片的处理速率决定，例如，DDR芯片的处理速率为兆赫兹(MHz)，延迟参数为微秒(us)级，可以将延迟参数划分为0～9us这10个档位，每个档位对DDR参考信号的延迟的调节程度不同；还可以采用移相单元113对DDR参考信号进行相位控制的处理方式，对于数字信号来说，相位分为0和1，0表示0～180度，1表示180～360度，采用置位0或1的方式进行相位控制。
需要说明的是，本公开实施例不限制处理模块11对DDR参考信号进行反向处理的具体方式，上述限幅单元111、延迟单元112和移相单元113仅是示意性说明，处理模块11可以包括其中的一项或多项，还可以包括其它用于进行反向处理的功能模块，只要是可以形成用于对DDR干扰信号进行抵消的功能模块，都可以用于执行本公开实施例中的反向处理。另外，本公开实施例不限制限幅单元111、延迟单元112和移相单元113的执行处理的顺序，它们可以是依据一定的顺序执行，也可以是同步执行。
本公开实施例提供的干扰处理装置用于执行本公开图2所示实施例提供 的干扰处理方法，具备相应的功能模块，其实现原理和技术效果类似，此处不再赘述。
可选地，图6为本公开实施例提供的又一种干扰处理装置的结构示意图。在本公开上述各实施例中，抵消模块12进行抵消处理后得到的反馈信号用于指示DDR干扰信号被DDR反向参考信号所抵消的程度，也就是说，在抵消模块12执行一次抵消处理后，DDR干扰信号可能没有完全被DDR反向参考信号所抵消，只抵消了其中一部分。为了更有效地消除DDR干扰信号对终端设备中工作信号的影响，本公开实施例提供的干扰处理装置10还可以包括：
调整模块14，其构造为根据抵消模块12得到的反馈信号对处理参数进行调整。
此外，在本公开实施例中，处理模块11可根据调整模块14调整后的处理参数重新对所述DDR参考信号进行反向处理；并且抵消模块12可通过由处理模块11进行反向处理后的DDR反向参考信号对终端设备接收的信号进行抵消处理，重新得到反馈信号。
在本公开实施例中，如上所述，在反馈信号指示仍然存在一定程度的DDR干扰信号时，说明DDR反向参考信号并没有完全抵消掉DDR干扰信号，此时，还可以由调整模块14通过该反馈信号对预配置的处理参数进行调整，从而由处理模块11根据过调整后的处理参数重新对所述DDR参考信号进行反向处理，并由抵消模块12通过重新得到的DDR反向参考信号再次对DDR干扰信号进行抵消处理，从而不断的调整处理参数，也就是重复执行反向处理、抵消处理和调整处理参数的操作，直到根据处理参数处理后得到的DDR反向参考信号可以完全抵消掉DDR干扰信号。
本公开实施例采用处理参数对DDR参考信号进行反向处理，并根据抵消处理后的反馈信号调整处理参数，形成一个闭环处理方式，通过不断调整的处理参数，使得DDR反向参考信号对DDR干扰信号的抵消程度越来越高，直到可以完全抵消掉DDR干扰信号，其中，调整模块14根据反馈信号调整处理参数的方式可以采用软件实现，例如，通过多次调整可以判断出用于完全抵消DDR干扰信号的信号的各项处理参数，即幅度、延迟和相位等，并 对DDR参考信号进行相应地调整，在调整过程中不断地接近完全抵消DDR干扰信号的目标。另外，调整模块14可储存每次调整后的处理参数，作为下一次对DDR参考信号进行反向处理的参数。
本公开实施例提供的干扰处理装置用于执行本公开图3所示实施例提供的干扰处理方法，具备相应的功能模块，其实现原理和技术效果类似，此处不再赘述。
图7为本公开实施例提供的一种干扰处理电路的结构示意图。本实施例提供的干扰处理电路适用于消除终端设备的DDR芯片带来的干扰的情况中，该干扰处理电路可以设置于终端设备中。如图7所示，本实施例的干扰处理电路可以包括：DDR芯片21、处理器22、耦合器23和接收电路24。
其中，DDR芯片21构造为产生DDR信号。
处理器22构造为根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号，该DDR参考信号与上述DDR信号相同。
本公开实施例提供的干扰处理电路构造为对终端设备中DDR芯片21带来的DDR干扰信号进行处理。其中，预配置的处理参数可以为配置于终端设备处理器22中的参数，这些处理参数与进行反向处理的操作方式对应，上述实施例中已经详细说明，故在此不再赘述。另外，DDR芯片21为终端设备中配置的常规芯片，其自身产生DDR信号，并且在使用过程中会带来终端设备接收的信号中的DDR干扰信号。
需要说明的是，本公开实施例中的DDR参考信号为与DDR芯片21所产生的DDR信号相同的信号，即DDR参考信号与DDR信号的幅度和相位完全相同，该DDR参考信号可以通过软件方式构建出来，处理器22对DDR参考信号进行反向处理后生成的DDR反向参考信号与DDR干扰信号不同；另外，本公开实施例中预配置的处理参数可以是设计人员根据经验预先设定的，也可以是根据对DDR芯片21所带来的DDR干扰信号设置的初始处理参数。
耦合器23构造为通过处理器22生成的DDR反向参考信号对终端设备 接收的信号进行抵消处理，得到反馈信号，并将该反馈信号传输到接收电路24，该终端设备接收的信号包括工作信号和DDR芯片21带来的DDR干扰信号。
在本公开实施例中，终端设备在正常工作时，耦合器23通过天线25接收到的信号包括工作信号和DDR干扰信号。耦合器23通过处理器22进行反向处理后生成的DDR反向参考信号对终端设备接收到的信号(包括工作信号和DDR干扰信号)进行抵消处理，即是对DDR干扰信号进行抵消处理。耦合器23进行抵消处理后的结果要求DDR反向参考信号可以抵消掉DDR干扰信号对工作信号带来的干扰影响。也就是说，本公开实施例通过形成一个与DDR干扰信号具有抵消效果的信号，来消除该DDR芯片21所带来的DDR干扰信号对高速数字电路带来的影响。
本公开实施例提供的干扰处理电路用于执行本公开图1所示实施例提供的干扰处理方法，具备相应的实体装置，其实现原理和技术效果类似，此处不再赘述。
可选地，图8为本公开实施例提供的另一种干扰处理电路的结构示意图。在上述实施例的基础上，本公开实施例提供的电路还可以包括：
模拟器26，其构造为在处理器22根据预配置的处理参数对DDR参考信号进行反向处理之前，根据DDR芯片21产生的DDR信号构建DDR参考信号，该DDR参考信号与DDR信号相同。
本公开上述实施例中已经说明DDR参考信号可以通过软件方式构建出来，该模拟器26例如是通过软件实现构建DDR参考信号的载体。另外，本公开上述实施例中已经说明，处理器22进行反向处理的对象，即DDR参考信号与DDR芯片21所产生的DDR信号完全相同，目的在于构建出一个与DDR信号完全相同的信号，并对该信号进行反向处理，使得反向处理后的DDR反向参考信号可以实现与DDR干扰信号相抵消的效果。因此，本公开实施例中的模拟器26，可以根据已知的DDR信号构建出与其完全相同的DDR参考信号，将该DDR参考信号作为目标对象进行反向处理。该DDR参考信号可以是DDR信号的数字信号重建。
可选地，在本公开实施例中，终端设备中预配置的处理参数可以包括限 幅参数、延迟参数和相位参数中的一项或多项，另外，处理器22可以包括以下一项或多项：
限幅器221，其构造为根据限幅参数对DDR参考信号的幅度进行控制；
延迟器222，其构造为根据延迟参数对DDR参考信号的延迟因子进行控制；
移相器223，其构造为根据相位参数对DDR参考信号的相位进行控制。
本公开实施例中，限幅器221、延迟器222和移相器223对DDR参考信号进行处理的方式上述实施例中已经详细描述，故在此不再赘述。
本公开实施例提供的干扰处理电路用于执行本公开图2所示实施例提供的干扰处理方法，具备相应的实体装置，其实现原理和技术效果类似，此处不再赘述。
可选地，在本公开实施例中，耦合器23进行抵消处理后得到的反馈信号用于指示DDR干扰信号被DDR反向参考信号所抵消的程度，也就是说，在耦合器23执行一次抵消处理后，DDR干扰信号可能没有完全被DDR反向参考信号所抵消，只抵消了其中一部分。为了更有效地消除DDR干扰信号对终端设备中工作信号的影响，本公开实施例提供的干扰处理电路中：
接收电路24可构造为将反馈信号传输到处理器22；
处理器22还可构造为根据反馈信号对处理参数进行调整，并根据调整后的处理参数重新对所述DDR参考信号进行反向处理；
耦合器23还可构造为通过由处理器22重新进行反向处理后得到的DDR反向参考信号对终端设备接收的信号进行抵消处理，重新得到反馈信号。
在本公开实施例中，如上所述，在反馈信号指示仍然存在一定程度的DDR干扰信号时，说明DDR反向参考信号并没有完全抵消掉DDR干扰信号，此时，接收电路24可以向处理器22发送该反馈信号，处理器22还可以通过该反馈信号对预配置的处理参数进行调整，从而根据过调整后的处理参数重新对所述DDR参考信号进行反向处理，随后，耦合器23通过重新得到的DDR反向参考信号再次对DDR干扰信号进行抵消处理，从而处理器22可以不断的调整处理参数，也就是重复执行反向处理、抵消处理和调整处理 参数的操作，直到根据处理参数处理后得到的DDR反向参考信号可以完全抵消掉DDR干扰信号。
本公开实施例中的处理器22采用处理参数对DDR参考信号进行反向处理，并根据抵消处理后的反馈信号调整处理参数，形成一个闭环处理方式，通过不断调整的处理参数，使得DDR反向参考信号对DDR干扰信号的抵消程度越来越高，直到可以完全抵消掉DDR干扰信号，其中，处理器22根据反馈信号调整处理参数的方式可以采用软件实现，例如，通过多次调整可以判断出用于完全抵消DDR干扰信号的信号的各项处理参数，即幅度、延迟和相位等，并对DDR参考信号进行相应地调整，在调整过程中不断地接近完全抵消DDR干扰信号的目标。
本公开实施例提供的干扰处理电路用于执行本公开图3所示实施例提供的干扰处理方法，具备相应的实体装置，其实现原理和技术效果类似，此处不再赘述。
本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质存储有计算机可执行指令，处理器执行该计算机可执行指令时，进行如下操作：
S31，根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；
S32，通过DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，该终端设备接收的信号包括工作信号和DDR干扰信号。
可选地，在本公开实施例中，该处理器执行该计算机可执行指令时，在执行S31之前，还进行如下操作：
S30，根据DDR芯片产生的DDR信号构建DDR参考信号，该DDR参考信号与DDR信号相同。
可选地，在本公开实施例中，上述理参数可以包括限幅参数、延迟参数和相位参数中的一项或多项，该处理器执行该计算机可执行指令时，执行操作S32的实现方式，可以包括以下处理中的一项或多项：
S321，根据限幅参数对DDR参考信号的幅度进行控制；
S322，根据延迟参数对DDR参考信号的延迟因子进行控制；
S323，根据相位参数对DDR参考信号的相位进行控制。
可选地，在本公开实施例中，上述反馈信号用于指示述DDR干扰信号被DDR反向参考信号所抵消的程度，该处理器执行该计算机可执行指令时，还进行如下操作：
S33，根据反馈信号对处理参数进行调整；
S34，根据调整后的处理参数重新对所述DDR参考信号进行反向处理；
S35，通过反向处理后的DDR反向参考信号对终端设备接收的信号进行抵消处理，重新得到反馈信号，直到该反馈信号指示DDR干扰信号完全被DDR反向参考信号所抵消。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可以通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本公开实施例不限制于任何特定形式的硬件和软件的结合。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (14)

  1. 一种干扰处理方法，包括：
    根据预配置的处理参数对双倍速率同步动态随机存储器DDR参考信号进行反向处理，生成DDR反向参考信号；以及
    通过所述DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。
  2. 根据权利要求1所述的干扰处理方法，其中，在所述根据预配置的处理参数对所述DDR参考信号进行反向处理之前，所述方法还包括：
    根据DDR芯片产生的DDR信号构建所述DDR参考信号，所述DDR参考信号与所述DDR信号相同。
  3. 根据权利要求1所述的干扰处理方法，其中，所述处理参数包括限幅参数、延迟参数和相位参数中的一项或多项，并且所述根据预配置的处理参数对所述DDR参考信号进行反向处理，包括进行以下处理中的一项或多项：
    根据所述限幅参数对所述DDR参考信号的幅度进行控制；
    根据所述延迟参数对所述DDR参考信号的延迟因子进行控制；以及
    根据所述相位参数对所述DDR参考信号的相位进行控制。
  4. 根据权利要求1～3中任一项所述的干扰处理方法，其中，所述反馈信号用于指示所述DDR干扰信号被所述DDR反向参考信号所抵消的程度。
  5. 根据权利要求4所述的干扰处理方法，还包括：在所述反馈信号指示所述DDR干扰信号未完全被所述DDR反向参考信号所抵消的情况下，重复执行以下步骤，直到在以下步骤中重新得到的反馈信号指示所述DDR干扰信号完全被抵消为止：
    根据上一次抵消处理得到的反馈信号对当前的处理参数进行调整；
    根据所述调整后的处理参数重新对所述DDR参考信号进行反向处理；
    通过重新进行反向处理后得到的DDR反向参考信号对所述终端设备接收的信号进行抵消处理，并重新得到反馈信号。
  6. 一种干扰处理装置，包括：
    处理模块，其构造为根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；以及
    抵消模块，其构造为通过所述处理模块生成的DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。
  7. 根据权利要求6所述的干扰处理装置，还包括：
    构建模块，其构造为在所述处理模块根据预配置的处理参数对所述DDR参考信号进行反向处理之前，根据DDR芯片产生的DDR信号构建所述DDR参考信号，所述DDR参考信号与所述DDR信号相同。
  8. 根据权利要求6所述的干扰处理装置，其中，所述处理参数包括限幅参数、延迟参数和相位参数中的一项或多项，所述处理模块包括以下单元中的一项或多项：
    限幅单元，其构造为根据所述限幅参数对所述DDR参考信号的幅度进行控制；
    延迟单元，其构造为根据所述延迟参数对所述DDR参考信号的延迟因子进行控制；以及
    移相单元，其构造为根据所述相位参数对所述DDR参考信号的相位进行控制。
  9. 根据权利要求6～8中任一项所述的干扰处理装置，其中，所述反馈信号用于指示所述DDR干扰信号被所述DDR反向参考信号所抵消的程度。
  10. 根据权利要求9所述的干扰处理装置，还包括：
    调整模块，其构造为根据所述抵消模块得到的反馈信号对所述处理参数进行调整；其中，
    所述处理模块还构造为根据所述调整模块调整后的处理参数重新对所述DDR参考信号进行反向处理；并且
    所述抵消模块还构造为通过由所述处理模块重新进行反向处理后得到的DDR反向参考信号对所述终端设备接收的信号进行抵消处理，并重新得到反馈信号。
  11. 一种干扰处理电路，包括：DDR芯片、处理器和耦合器，其中，
    所述DDR芯片构造为产生DDR信号；
    所述处理器构造为根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号，所述DDR参考信号与所述DDR信号相同；并且
    所述耦合器构造为通过所述处理器生成的DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，并将所述反馈信号传输到接收电路，所述终端设备接收的信号包括工作信号和所述DDR芯片带来的DDR干扰信号。
  12. 根据权利要求11所述的干扰处理电路，所述处理参数包括限幅参数、延迟参数和相位参数中的一项或多项，所述处理器包括以下一项或多项：
    限幅器，其构造为根据所述限幅参数对所述DDR参考信号的幅度进行控制；
    延迟器，其构造为根据所述延迟参数对所述DDR参考信号的延迟因子进行控制；以及
    移相器，其构造为根据所述相位参数对所述DDR参考信号的相位进行控制。
  13. 根据权利要求11或12所述的干扰处理电路，所述反馈信号用于指示所述DDR干扰信号被所述DDR反向参考信号所抵消的程度；
    所述接收电路构造为将所述反馈信号传输到所述处理器；
    所述处理器还构造为根据所述反馈信号对所述处理参数进行调整，并根据所述调整后的处理参数重新对所述DDR参考信号进行反向处理；并且
    所述耦合器还构造为通过由所述处理器重新进行反向处理后得到的DDR反向参考信号对所述终端设备接收的信号进行抵消处理，重新得到反馈信号。
  14. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机可执行指令，处理器执行所述计算机可执行指令时，进行如下操作：
    根据预配置的处理参数对DDR参考信号进行反向处理，生成DDR反向参考信号；以及
    通过所述DDR反向参考信号对终端设备接收的信号进行抵消处理，得到反馈信号，所述终端设备接收的信号包括工作信号和DDR干扰信号。
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