WO2019033647A1 - 闪存的纠错方法、装置、设备以及计算机可读存储介质 - Google Patents

闪存的纠错方法、装置、设备以及计算机可读存储介质 Download PDF

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WO2019033647A1
WO2019033647A1 PCT/CN2017/116256 CN2017116256W WO2019033647A1 WO 2019033647 A1 WO2019033647 A1 WO 2019033647A1 CN 2017116256 W CN2017116256 W CN 2017116256W WO 2019033647 A1 WO2019033647 A1 WO 2019033647A1
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data
hard data
flash memory
adjusted
hard
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PCT/CN2017/116256
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English (en)
French (fr)
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梁冬柳
李志雄
邓恩华
尹慧
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深圳市江波龙电子有限公司
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Publication of WO2019033647A1 publication Critical patent/WO2019033647A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Definitions

  • the present application belongs to the field of electronic communication technologies, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for error correction of a flash memory.
  • Nand flash memory is widely used in portable electronic products such as MP3, smartphones, and tablets.
  • the SSD controller is designed with an error correction module to correct the data read from the flash memory chip and eliminate errors in the data.
  • the mainstream error correction coding uses the BCH code, which is fast in calculation and strong in error correction.
  • BCH error correction algorithm can not provide enough correction for the flash chip Wrong ability.
  • LDPC Low Density Parity Check Code
  • the flash device uses hard decision and soft decision through LDPC error correction, and the flash controller reads hard data composed of logic '0' and logic '1' from the standard interface of the flash chip (Hard Data), usually when the number of error bits of flash data is too high, ECC error correction will be caused by hard data error correction. In this case, soft decision is needed, and the device reads Soft Data to assist LDPC error correction.
  • Hard Data the standard interface of the flash chip
  • the embodiments of the present application provide a method, an apparatus, a device, and a computer readable storage medium for correcting flash memory, so as to solve the problem that the method for obtaining soft data provided by different Nand flash memory manufacturers in the prior art is different and exists. Many restrictions have led to poor LDPC error correction and cannot guarantee the safe and reliable storage of flash data.
  • a first aspect of the present application provides a method for error correction of a flash memory, where the error correction method includes:
  • Reading the initial hard data of the flash memory which is the hard data of the flash memory read under the default window voltage value of the flash memory
  • Reading the hard data of the flash memory where the hard data is hard data of the flash memory that adjusts the window voltage value of the flash memory and is read under the adjusted window voltage value, wherein the window voltage value is adjusted at least 2 times;
  • Error correction is performed on the initial hard data of the flash memory according to the value of the log likelihood ratio LLR.
  • the second aspect of the present application provides an error correction device for a flash memory, where the error correction device includes:
  • An initial data reading unit configured to read initial hard data of the flash memory, where the initial hard data is hard data of the flash memory read under the default window voltage value of the flash memory;
  • Adjusting a data reading unit configured to read the adjusted hard data of the flash memory, wherein the adjusted hard data is a hard data of a flash memory that is adjusted by reading a window voltage value of the flash memory and reading the adjusted window voltage value, wherein The window voltage value is adjusted at least 2 times;
  • a determining unit configured to determine a value of a log likelihood ratio LLR according to the initial hard data and the adjusted hard data
  • an error correction unit configured to perform error correction on the initial hard data of the flash memory according to the value of the log likelihood ratio LLR.
  • a third aspect of the present application provides a terminal device, including: a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein the processor executes the computer program as described above The steps of the error correction method of the flash memory.
  • a fourth aspect of the present application provides a computer readable storage medium storing a computer program that, when executed by a processor, implements the steps of an error correction method of the flash memory as described above.
  • a fifth aspect of the present application provides a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions, the instructions being executable by a processor The steps of the error correction method of the flash memory as described above.
  • the embodiment of the present application has the following beneficial effects: the embodiment of the present application first reads the initial hard data of the flash memory, and the initial hard data is the hard data of the flash memory read under the default window voltage value of the flash memory. And then reading the adjustment hard data of the flash memory, the adjustment hard data is hard data of the flash memory that adjusts the window voltage value of the flash memory and is read under the adjusted window voltage value, wherein the window voltage value Adjusting at least 2 times, determining a value of a log likelihood ratio LLR according to the initial hard data and the adjusted hard data, and finally performing initial hard data of the flash memory according to the value of the log likelihood ratio LLR Error correction, the scheme acquires LLR in the scenario without soft data, which can improve the error correction capability of the low density parity check code LDPC, thereby ensuring the reliability and security of the flash data storage, and prolonging the data storage time.
  • FIG. 1 is a flowchart of an implementation of an error correction method for a flash memory provided by an embodiment of the present application
  • FIG. 2.1 is a flowchart of a method for determining a log likelihood ratio LLR according to an embodiment of the present application
  • FIG. 2.2 is a flowchart of a method for determining binary index data according to an embodiment of the present application
  • FIG. 3.1 is a schematic diagram of a flash memory particle type as a single layer unit SLC according to an embodiment of the present disclosure
  • FIG. 3.2 is a schematic diagram of a flash memory particle type as a double layer unit MLC according to an embodiment of the present application.
  • FIG. 3.3 is a schematic diagram of a flash memory particle type as a three-layer cell TLC according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a scenario of an error correction method for a flash memory according to an embodiment of the present application.
  • FIG. 5 is a structural block diagram of an error correction apparatus for a flash memory according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a terminal device according to an embodiment of the present application.
  • a method, device, device, and computer for correcting the flash memory are provided. Reading the storage medium, the solution reads at least three hard data on the basis of the prior art, combines at least three hard data combinations instead of the hard data and the soft data generated by the instruction inside the flash memory, and processes according to the combined data.
  • the obtained LLR values are error-corrected, thereby improving the error correction capability of the LDPC, thereby ensuring the reliability and security of the flash data storage, and extending the data storage time.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1 :
  • FIG. 1 is a flowchart of a method for error correction of a flash memory provided by an embodiment of the present application, which is described in detail as follows:
  • Step S101 reading initial hard data of the flash memory, where the initial hard data is hard data of the flash memory read under the default window voltage value of the flash memory.
  • the hard data of the flash memory refers to the data stored in the flash memory, and is generally "1" or "0".
  • the default window voltage value refers to a default voltage value of a register corresponding to the read flash page. It should be noted that each Nand flash memory factory has different commands and methods to adjust the window voltage value. The above window voltage value can be adjusted according to the default window voltage value existing in the prior art, or can be set by the user. The application is not limited herein.
  • Step S102 reading adjustment hard data of the flash memory, where the adjustment hard data is hard data of a flash memory that is adjusted by reading a window voltage value of the flash memory and reading the adjusted window voltage value, wherein the window voltage is Adjust the value at least 2 times.
  • the window voltage value of the flash memory refers to a voltage value of a register corresponding to the flash page.
  • the default window voltage value is adjusted according to a preset adjustment rule by sending a related command setting window voltage offset value. Further, with the default window voltage value as the neutral line, the relevant command is sent to set the window voltage offset value to the left of the neutral line or the window voltage offset value to the right of the neutral line, so that the window voltage value is shifted to the left or to the right.
  • the hard data of the flash memory is read once for each window voltage value of the flash memory, and one packet of hard data is read as the adjusted hard data under the adjusted window voltage value. Moreover, in order to improve the accuracy, at least the window voltage value is adjusted twice.
  • the window voltage value adjustment times is a multiple of 2.
  • the reliability of the hard data being "1" or “0” is represented by the soft data generated inside the flash memory. Different flash memories have different definitions. In some flash memories, “0” means reliable, “1” It means that it is unreliable, while in some flash memories, “1” means reliable, “0” means unreliable, and in the embodiment of the present application, the initial hard data and the adjusted hard data are used to obtain LLR data, initial hard data and adjustment hard. A "0” or "1" in the data cannot be directly used to indicate reliability.
  • the hard decision of the LDPC cannot be successfully corrected, the hard data of the flash memory is read.
  • Step S103 determining a value of a log likelihood ratio LLR according to the initial hard data and the adjusted hard data.
  • the step S103 includes:
  • A1 Acquire first adjusted hard data read under the first adjusted window voltage value.
  • A3. Determine the binary index data according to the combined hard data generated by combining the initial hard data, the first adjusted hard data, and the second adjusted hard data.
  • A4 Determine a value of a log likelihood ratio LLR according to the binary index data.
  • the binary index data Bin Index is used to distinguish different data states stored in the flash memory, each state has a different level of reliability.
  • the initial hard data, the first adjusted hard data, and the second adjusted hard data are all binary data
  • the combined hard data generated by the combination is binary data.
  • the binary index data is the decimal data corresponding to the combined hard data.
  • the log likelihood ratio LLR is used to determine the likelihood that the data stored in the flash memory is a logical "1" and the possibility that the data stored in the flash memory is a logical "0".
  • the adjustment window voltage value is not limited to be shifted to the left or to the right, and the window voltage value is not limited to be shifted to the left by the window voltage value.
  • the A3 specifically includes:
  • A31 Combine the initial hard data, the first adjusted hard data, and the data on the same data bit in the second adjusted hard data according to a specified rule to generate combined hard data.
  • A32 Determine binary index data according to the combined hard data.
  • the data in the initial hard data of the read flash memory under the default voltage window value is stored in the first data bit of the combined hard data, and the first adjusted hard data and the second adjusted hard data are sequentially The second data bit and the third data bit of the combined hard data are respectively stored.
  • the first data bit of the combined hard data is a low bit.
  • the A31 specifically includes:
  • A311 The data in the initial hard data is put into the first data bit of the combined hard data, and the data in the first adjusted hard data that is the same as the data bit in the initial hard data is put into the combination.
  • the second data bit of the hard data is used to put the same data in the second hard data as the data bit in the initial hard data into the third data bit of the combined hard data to generate combined hard data.
  • the data of the first data bit in the initial hard data is put into the first data bit of the combined hard data, and the data in the second adjusted hard data that is the same as the data bit in the initial hard data is placed. Entering the second data bit of the combined hard data, putting the same data in the first adjusted hard data as the data bit in the initial hard data into the third data bit of the combined hard data to generate combined hard data .
  • the data of the first data bit in the initial hard data is “1”
  • the data of the first data bit in the first adjusted hard data is “0”
  • the first in the first adjusted hard data is The data of the data bit is "1”.
  • the data in the first adjusted hard data is placed in the second place of the combined hard data, and the data in the second adjusted hard data is put into the combined hard data.
  • the third bit in the case, at this time, the combined hard data is "101", and its corresponding binary index data bit is "5".
  • the combination is performed according to the initial hard data and the adjusted hard data read under each adjusted window voltage value. Generate combined hard data to determine binary index data.
  • Step S104 performing error correction on the initial hard data of the flash memory according to the value of the log likelihood ratio LLR.
  • the log likelihood ratio LLR is used to determine the possibility that the data stored in the flash memory is logical "1" and the data stored in the flash memory is logical "0". For example, when LLR ⁇ 0, it is more likely that the data bit is "1", and LLR>0, indicating that the data bit is "0" is more likely.
  • step S104 includes:
  • the value of the log likelihood ratio LLR is an empirical value, and the value of the log likelihood ratio LLR can be expressed as 0, +3, -3, +6, -6, +12, -12, +15, - 15.
  • the absolute value of the log likelihood ratio LLR is between 0 and 15, and the absolute value of the log likelihood ratio LLR corresponding to the adjacent combined hard data cannot be very close.
  • the flash memory particle type includes: SLC (Single Level Cell), that is, one storage unit stores 1 bit, as shown in FIG. 3.1; (Multiple Level Cell), that is, one storage unit stores 2 bits, as shown in Figure 3.2; 3bit is TLC (Triple Level Cell), that is, one storage unit stores 3 bits, as shown in Figure 3.3.
  • SLC Single Level Cell
  • Multiple Level Cell that is, one storage unit stores 2 bits, as shown in Figure 3.2
  • 3bit is TLC (Triple Level Cell), that is, one storage unit stores 3 bits, as shown in Figure 3.3.
  • the particle type of the flash memory in this example is SLC, that is, one storage unit stores 1 bit.
  • Read the hard data of a pack of flash memory under the default window voltage value that is, the initial hard data of the flash memory, recorded as Hard Data 0, as shown in Figure 4, read Hard Data 0 is "1100"; the default window voltage value is adjusted for the first time.
  • the re-read register command is sent to set the default window voltage value of the neutral line to the left by a certain offset value, and the window voltage value after the adjustment.
  • Read a packet of hard data that is, the first adjustment of hard data, recorded as Hard Data 1, as shown in Figure 4, read Hard Data 1 is “1000”; once again, the default window voltage value is adjusted.
  • the send reread register command sets the default window voltage value of the neutral line to the right by a certain offset value, and under the adjusted window voltage value.
  • Read a packet of hard data that is, the second adjustment of hard data, recorded as Hard Data 2, as shown in Figure 4, read Hard Data 2 is "1110". Among them, "0" and “1" in Hard Data0, Hard Data 1, and Hard Data 2 cannot be directly used to indicate reliability. Will The data on the same data bits in Data0, Hard Data 1, and Hard Data 2 are combined according to the specified rules to generate combined hard data. The order of combination of Hard Data0, Hard Data 1, and Hard Data 2 is not limited. As shown in FIG.
  • each column of data in the figure can be combined into a set of combined hard data, including "111", “101", “001", “000”, etc., and the combined hard data corresponding to the Bin Index is 7" "5 "4" "0", according to the Bin Index, the corresponding LLR values are "-12", “-3", “+3” and "+12", respectively, through multi-packet hard data combination, in the absence of soft data
  • the LLR is obtained in the scenario, and the initial hard data of the flash memory is error-corrected according to the value of the LLR, wherein the LLR ⁇ 0 indicates that the data bit is “1”, and the LLR>0 indicates that the data bit is “0”. "The possibility is even greater.”
  • the initial hard data is the hard data of the flash memory read under the default window voltage value of the flash memory
  • the adjustment hard data is hard data of a flash memory that adjusts a window voltage value of the flash memory and is read under the adjusted window voltage value, wherein the window voltage value is adjusted at least 2 times, for example, when the window voltage
  • the value is adjusted twice, including a set of initial hard data, first adjusted hard data, and second adjusted hard data, the same data in the initial hard data, the first adjusted hard data, and the second adjusted hard data
  • the data on the bits are combined according to a specified rule to generate combined hard data, and then the binary index data is determined according to the combined hard data, thereby determining the value of the log likelihood ratio LLR, and finally according to the log likelihood ratio LLR.
  • the value is used to correct the initial hard data of the flash memory.
  • the solution acquires the LLR in the scenario without soft data, which can improve the error correction capability of the low density parity check code LDPC, thereby ensuring the flash memory. According to a reliable and safe storage, and thus prolong the retention time of the data.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1 :
  • FIG. 5 is a structural block diagram of an error correction device for a flash memory provided by an embodiment of the present application, and the device is applicable to a flash memory storage device. For the convenience of description, only the parts related to the embodiments of the present application are shown.
  • the error correction device of the flash memory includes: an initial data reading unit 21, an adjustment data reading unit 22, a determining unit 23, and an error correction unit 24, wherein:
  • the initial data reading unit 21 is configured to read initial hard data of the flash memory, where the initial hard data is hard data of the flash memory read under the default window voltage value of the flash memory;
  • the adjustment data reading unit 22 is configured to read the adjustment hard data of the flash memory, where the adjustment hard data is hard data of the flash memory that is adjusted by the window voltage value of the flash memory and is read under the adjusted window voltage value. Wherein the window voltage value is adjusted at least twice;
  • a determining unit 23 configured to determine a value of a log likelihood ratio LLR according to the initial hard data and the adjusted hard data
  • the error correction unit 24 is configured to perform error correction on the initial hard data of the flash memory according to the value of the log likelihood ratio LLR.
  • the hard decision of the LDPC cannot be successfully corrected, the hard data of the flash memory is read.
  • the determining unit 23 specifically includes:
  • a first acquiring module configured to acquire first adjusted hard data read under the first adjusted window voltage value
  • a second acquiring module configured to acquire second adjusted hard data read under the second adjusted window voltage value
  • An index data determining module configured to determine binary index data according to the combined hard data generated by combining the initial hard data, the first adjusted hard data, and the second adjusted hard data;
  • a log likelihood ratio determining module is configured to determine a value of a log likelihood ratio LLR based on the binary index data.
  • index data determining module specifically includes:
  • a combined hard data generating submodule configured to combine the initial hard data, the first adjusted hard data, and the data on the same data bit in the second adjusted hard data according to a specified rule to generate combined hard data
  • An index data sub-module for determining binary index data based on combined hard data.
  • the combined hard data generating submodule specifically includes:
  • a first combined hard data generating submodule configured to put data in the initial hard data into a first data bit of the combined hard data, and compare the first adjusted hard data with the data in the initial hard data The same bit of data is placed in the second data bit of the combined hard data, and the data in the second adjusted hard data that is the same as the data bit in the initial hard data is placed in the third data bit of the combined hard data. , generating combined hard data;
  • a second combined hard data generating submodule configured to put data of the first data bit in the initial hard data into a first data bit of the combined hard data, and the second adjusted hard data and the initial Data having the same data bit in the hard data is placed in the second data bit of the combined hard data, and data in the first adjusted hard data that is the same as the data bit in the initial hard data is placed in the combined hard data.
  • the third data bit generates a combined hard data.
  • the error correction unit 24 specifically includes:
  • a first determining module configured to determine, when the value of the log likelihood ratio LLR is greater than zero, that the internal storage data of the flash memory is greater than "0", and the internal storage data of the flash memory is greater than "1" possibility;
  • a second determining module configured to: when the value of the log likelihood ratio LLR is less than zero, determine that the internal storage data of the flash memory is greater than “1”, and the internal storage data of the flash memory is “0” possibility.
  • the initial hard data is hard data of the flash memory read under the default window voltage value of the flash memory, and then reading the adjusted hard data of the flash memory
  • the adjustment hard data is hard data of a flash memory that is adjusted by the window voltage value of the flash memory and read under the adjusted window voltage value, wherein the window voltage value is adjusted at least twice, and then according to the initial hard data. Determining a log likelihood ratio LLR with the adjusted hard data, and finally correcting the initial hard data of the flash memory according to the value of the log likelihood ratio LLR.
  • the solution is in a scenario without soft data. Acquiring the LLR can improve the error correction capability of the low-density parity check code LDPC, thereby ensuring the reliability and security of the flash data storage, thereby prolonging the data retention time.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 6 is a schematic diagram of a terminal device according to an embodiment of the present application.
  • the terminal device 3 of this embodiment includes a processor 30, a memory 31, and a computer program 32 stored in the memory 31 and operable on the processor 30, such as an error correction program of a flash memory. .
  • the processor 30 executes the computer program 32, the steps in the embodiment of the error correction method of each of the above flash memories are implemented, such as steps 101 to 104 shown in FIG.
  • the processor 30 executes the computer program 32, the functions of the modules/units in the above-described respective device embodiments, such as the functions of the units 21 to 24 shown in FIG. 5, are implemented.
  • the computer program 32 can be partitioned into one or more modules/units that are stored in the memory 31 and executed by the processor 30 to complete This application.
  • the one or more modules/units may be a series of computer program instruction segments capable of performing a particular function, the instruction segments being used to describe the execution of the computer program 32 in the terminal device 3.
  • the computer program 32 can be divided into an initial data reading unit, an adjustment data reading unit, a determining unit, and an error correcting unit. The specific functions of each unit are as follows:
  • An initial data reading unit configured to read initial hard data of the flash memory, where the initial hard data is hard data of the flash memory read under the default window voltage value of the flash memory;
  • Adjusting a data reading unit configured to read the adjusted hard data of the flash memory, wherein the adjusted hard data is a hard data of a flash memory that is adjusted by reading a window voltage value of the flash memory and reading the adjusted window voltage value, wherein The window voltage value is adjusted at least 2 times;
  • a determining unit configured to determine a value of a log likelihood ratio LLR according to the initial hard data and the adjusted hard data
  • an error correction unit configured to perform error correction on the initial hard data of the flash memory according to the value of the log likelihood ratio LLR.
  • the terminal device 3 may be a computing device such as a desktop computer, a notebook, a palmtop computer, and a cloud server.
  • the terminal device 3 may include, but is not limited to, a processor 30 and a memory 31. It will be understood by those skilled in the art that FIG. 6 is only an example of the terminal device 3, does not constitute a limitation of the terminal device 3, may include more or less components than those illustrated, or combine some components, or different components.
  • the terminal device may further include an input/output device, a network access device, a bus, and the like.
  • the processor 30 may be a central processing unit (CPU), or may be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 31 may be an internal storage unit of the terminal device 3, such as a hard disk or a memory of the terminal device 3.
  • the memory 31 may also be an external storage device of the terminal device 3, for example, a plug-in hard disk equipped on the terminal device 3, a smart memory card (SMC), and a secure digital (SD). Card, flash card, etc.
  • the memory 31 may also include both an internal storage unit of the terminal device 3 and an external storage device.
  • the memory 31 is used to store the computer program and other programs and data required by the terminal device.
  • the memory 31 can also be used to temporarily store data that has been output or is about to be output.
  • each functional unit and module in the foregoing system may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit, and the integrated unit may be implemented by hardware.
  • Formal implementation can also be implemented in the form of software functional units.
  • the specific names of the respective functional units and modules are only for the purpose of facilitating mutual differentiation, and are not intended to limit the scope of protection of the present application.
  • the disclosed apparatus and method may be implemented in other manners.
  • the system embodiment described above is merely illustrative.
  • the division of the module or unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the processes in the foregoing embodiments, and may also be completed by a computer program to instruct related hardware.
  • the computer program may be stored in a computer readable storage medium. The steps of the various method embodiments described above may be implemented when the program is executed by the processor.
  • the computer program comprises computer program code, which may be in the form of source code, object code form, executable file or some intermediate form.
  • the computer readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a removable hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM). , random access memory (RAM, Random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. It should be noted that the content contained in the computer readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in a jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, computer readable media It does not include electrical carrier signals and telecommunication signals.

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Abstract

用于电子通信技术领域，提供了一种闪存的纠错方法、装置、设备以及计算机可读存储介质，所述纠错方法包括：读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据（S101）；读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次（S102）；根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值（S103）；根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错（S104）。上述方法可以提高LDPC的纠错能力。

Description

闪存的纠错方法、装置、设备以及计算机可读存储介质
相关申请的交叉参考
本申请要求于2017年8月16日提交中国专利局、申请号为201710703447.9、发明名称为“闪存的纠错方法、装置、设备以及计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于电子通信技术领域，尤其涉及一种闪存的纠错方法、装置、设备以及计算机可读存储介质。
 背景技术
Nand闪存广泛地应用于MP3、智能手机、平板电脑等便携式电子产品。为了能够延长闪存芯片的使用寿命，保证用户数据的安全，固态硬盘控制器中设计有纠错模块，对从闪存芯片中读取的数据进行纠错处理，消除数据中的错误。传统上，主流的纠错编码都采用BCH码，这种编码方式计算快速，纠错能力强。然而，随着闪存颗粒的磨损或Data Retention（数据保存）、温度等变化，闪存数据的错误比特数会增加，进而会导致数据ECC（Error Correction Code，纠错码）纠错失败，BCH纠错算法已无法为闪存芯片提供足够的纠错能力。在通讯领域中广泛使用的LDPC（Low Density Parity Check Code，低密度奇偶校验码）凭借其强大的纠错能力开始成为将来闪存纠错发展的新趋势。
闪存设备通过LDPC纠错使用硬判决和软判决之分，闪存控制器从闪存芯片的标准接口中读取到由逻辑‘0’和逻辑‘1’构成的硬数据（Hard Data），通常闪存数据的错误比特数偏高时，通过硬数据纠错会导致ECC纠错失败，此时则需要利用软判决，设备读取软数据（Soft Data）辅助LDPC纠错。但不同Nand 闪存原厂提供的获取软数据的方法都不相同，并且存在诸多限制，这样直接导致LDPC纠错效果不佳，无法保证安全可靠的存储闪存数据的问题。
发明内容
有鉴于此，本申请实施例提供了一种闪存的纠错方法、装置、设备以及计算机可读存储介质，以解决现有技术中不同Nand 闪存原厂提供的获取软数据的方法不相同且存在诸多限制，导致LDPC纠错效果不佳，无法保证安全可靠的存储闪存数据的问题。
本申请第一方面提供了一种闪存的纠错方法，所述纠错方法包括：
读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据；
读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次；
根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值；
根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
本申请第二方面提供了一种闪存的纠错装置，所述纠错装置包括：
初始数据读取单元，用于读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据；
调整数据读取单元，用于读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次；
确定单元，用于根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值；
纠错单元，用于根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
本申请第三方面提供了一种终端设备，包括：存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如上所述闪存的纠错方法的步骤。
本申请第四方面提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现如上所述闪存的纠错方法的步骤。
本申请第五方面提供了一种计算机程序产品，所述计算机程序产品包括存储在计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，所述指令被处理器执行时，可实现如上所述闪存的纠错方法的步骤。
本申请实施例与现有技术相比存在的有益效果是：本申请实施例通过先读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据，然后读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次，再根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值，最后根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错，本方案在没有软数据的场景下获取LLR，可提升低密度奇偶校验码LDPC的纠错能力，从而保证闪存数据存储的可靠与安全，并可延长数据的保存时间。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种闪存的纠错方法的实现流程图；
图2.1是本申请实施例提供的一种确定对数似然比LLR的方法实现流程图；
图2.2是本申请实施例提供的一种确定二进制索引数据的方法实现流程图；
图3.1是本申请实施例提供的闪存颗粒类型为单层单元SLC的示意图；
图3.2是本申请实施例提供的闪存颗粒类型为双层单元MLC的示意图；
图3.3是本申请实施例提供的闪存颗粒类型为三层单元TLC的示意图；
图4是本申请实施例提供的一种闪存的纠错方法的场景示意图；
图5是本申请实施例提供的一种闪存的纠错装置的结构框图；
图6是本申请实施例提供的一种终端设备的示意图。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
现有技术中，本申请实施例为了在部分闪存不支持内部产生软数据时，提高低密度奇偶校验码LDPC的纠错能力，提供了一种闪存的纠错方法、装置、设备以及计算机可读存储介质，该方案在现有技术的基础上，读取至少三次的硬数据，将至少三次的硬数据组合代替硬数据与闪存内部通过指令生成的软数据组合，根据组合后的数据进行处理得到的LLR的值进行纠错，进而可提升LDPC的纠错能力，从而保证闪存数据存储的可靠与安全，并可延长数据的保存时间。为了具体说明上述闪存的纠错方法、装置、设备以及计算机可读存储介质，下面通过具体实施例来进行说明。
实施例一：
图1示出了本申请实施例提供的一种闪存的纠错方法的流程图，详述如下：
步骤S101，读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据。
具体地，在默认的窗口电压值下读取一包硬数据（Hard Data）作为初始硬数据。其中，闪存的硬数据是指闪存内部存储的数据，一般为“1”或“0”。在本申请实施例中，默认的窗口电压值是指读取闪存页对应的寄存器的默认电压值。需说明的是，每个Nand闪存原厂都有不同的命令和方法调整窗口电压值，上述窗口电压值可以根据现有技术中已有的默认的窗口电压值进行调整，也可以由用户自己设定，本申请在此不做限定。
步骤S102，读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次。
其中，所述闪存的窗口电压值是指闪存页对应的寄存器的电压值。具体地，按预设调整规则发送相关命令设置窗口电压偏移值对默认的窗口电压值进行调整。进一步地，以默认的窗口电压值为中线，发送相关命令设置中线左边的窗口电压偏移值或中线右边的窗口电压偏移值，从而使得窗口电压值向左偏移或者向右偏移。在本申请实施例中，每调整一次闪存的窗口电压值则读取一次闪存的硬数据，在调整后的窗口电压值下读取一包硬数据作为调整硬数据。并且，为了提高准确性，至少调整2次窗口电压值，因此，本申请实施例中至少存在一组初始硬数据和两组调整硬数据。可选地，所述窗口电压值调整次数为2的倍数。现有技术中，通过闪存内部产生的软数据来表示硬数据为“1”或“0”的可靠性，不同的闪存有不同的定义，在有些闪存中，“0”表示可靠，“1”表示不可靠，而有些闪存中“1”表示可靠，“0”表示不可靠，而在本申请实施例中的初始硬数据和调整硬数据是用来获取LLR的数据，初始硬数据和调整硬数据中的“0”或“1”不能直接用来表示可靠性。
可选地，在本申请实施例中，当闪存数据的错误比特数高于预设的错误比特数时，若LDPC的硬判决无法纠错成功，读取所述闪存的调整硬数据。
步骤S103，根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值。
进一步地，当所述窗口电压值调整2次时，包括一组初始硬数据和两组调整硬数据，此时，如图2.1所示，在本申请实施例中，所述步骤S103包括：
A1、获取在第一次调整后的窗口电压值下读取的第一调整硬数据。
A2、获取在第二次调整后的窗口电压值下读取的第二调整硬数据。
A3、根据所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据进行组合生成的组合硬数据，确定二进制索引数据。
A4、根据所述二进制索引数据确定对数似然比LLR的值。
其中，二进制索引数据Bin Index用于区分闪存存储的不同的数据状态，每种状态都有不同的可靠性水平。本申请实施例中，所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据都是二进制数据，其组合生成的组合硬数据为二进制数据。二进制索引数据为组合硬数据对应的十进制数据。对数似然比LLR用于判定闪存存储的数据为逻辑“1”的可能性以及闪存存储的数据为逻辑“0”的可能性。
需说明的是，在本申请实施例中，不限定调整窗口电压值向左偏右或者向右偏移，也不限定窗口电压值向左偏移是否与窗口电压值向右偏移对称。
进一步地，如图2.2所示，在本申请实施例中，所述A3具体包括：
A31、将所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据中相同数据位上的数据按指定规则分别进行组合，生成组合硬数据。
A32、根据组合硬数据确定二进制索引数据。
具体地，将默认的电压窗口值下的读取的闪存的初始硬数据中的数据，存入组合硬数据的第一数据位中，依次将所述第一调整硬数据以及第二调整硬数据分别存入组合硬数据的第二数据位和第三数据位。其中，所述组合硬数据的第一数据位为低位。进一步地，在本申请实施例中，所述A31具体包括：
A311、将所述初始硬数据中的数据放入所述组合硬数据的第一数据位，将所述第一调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第二数据位，将所述第二调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第三数据位，生成组合硬数据。
或者，
A312、将所述初始硬数据中第一数据位的数据放入所述组合硬数据的第一数据位，将所述第二调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第二数据位，将所述第一调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第三数据位，生成组合硬数据。
示例性地，所述初始硬数据中第一数据位的数据为“1”，所述第一调整硬数据中第一数据位的数据为“0”，所述第一调整硬数据中第一数据位的数据为“1”，此时，将所述第一调整硬数据中的数据放入组合硬数据的中第二位，将所述第二调整硬数据中的数据放入组合硬数据中的第三位，此时，该组合硬数据为“101”，其对应的二进制索引数据位“5”。
需说明的是，在本申请实施例中，当所述窗口电压值调整不止2次时，则根据所述初始硬数据以及在每一次调整后的窗口电压值下读取的调整硬数据进行组合生成的组合硬数据，确定二进制索引数据。
步骤S104，根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
其中，对数似然比LLR用于判定闪存存储的数据为逻辑“1”的可能性以及闪存存储的数据为逻辑“0”的可能性。例如，当LLR<0 ，表示数据比特为“1”的可能性更大，LLR>0，表示数据比特为“0”的可能性更大。
进一步地，在本申请实施例中，所述步骤S104包括：
B1、当所述对数似然比LLR的值大于零时，判定所述闪存的内部存储数据为“0”的可能性大于所述闪存的内部存储数据为“1”的可能性；
B2、当所述对数似然比LLR的值小于零时，判定所述闪存的内部存储数据为“1”的可能性大于所述闪存的内部存储数据为“0”的可能性。
具体地，对数似然比LLR的值是经验值，对数似然比LLR的值可以表示为0，+3，-3，+6，-6，+12，-12，+15，-15，对数似然比LLR的绝对值越大，表示可能性越高。例如， “15”为非常可靠，“12”为可靠，“6”为有点可靠，“3”为不可靠，“0”为不存在即不可靠。进一步地，对数似然比LLR的绝对值在0~15之间，且相邻的组合硬数据对应的对数似然比LLR的绝对值不能非常靠近。
进一步地，在本申请实施例中，闪存颗粒类型包括：SLC (Single Level Cell，单层单元)，即一个存储单元存储1bit，如图3.1所示；MLC (Multiple Level Cell，双层单元) ，即一个存储单元存储2bit，如图3.2所示；3bit为TLC (Triple Level Cell，三层单元) ，即一个存储单元存储3bit，如图3.3所示。
以一个应用场景为例，如图4所示，该示例中闪存的颗粒类型为SLC ，即一个存储单元存储1bit。在默认的窗口电压值下读取一包闪存的硬数据，即闪存的初始硬数据，记为Hard Data 0，如图4，读取的Hard Data 0为“1100”；第一次对默认的窗口电压值进行调整，发送重读寄存器命令设置中线的默认的窗口电压值向左移动一定的偏移值，并在该次调整后的窗口电压值下读取一包硬数据，即第一调整硬数据，记为Hard Data 1，如图4，读取的Hard Data 1为“1000”；再一次对默认的窗口电压值进行调整，发送重读寄存器命令设置中线的默认的窗口电压值向右移动一定的偏移值，并在该次调整后的窗口电压值下读取一包硬数据，即第二调整硬数据，记为Hard Data 2，如图4，读取的Hard Data 2为“1110”。其中，Hard Data0、Hard Data 1和Hard Data 2中的“0”和“1”不能直接用于表示可靠性。将Hard Data0、Hard Data 1和Hard Data 2中相同数据位上的数据按指定规则分别进行组合，生成组合硬数据。其中，Hard Data0、Hard Data 1和Hard Data 2的组合顺序不限制。如图4所示，图中每一列数据可组合成一组组合硬数据，包括“111”、“101”、“001”、“000”等，组合硬数据分别对应的Bin Index为7”“5”“4”“0”，根据Bin Index确定对应的LLR的值分别为“-12”、“-3”、“+3”和“+12”，通过多包硬数据组合，在没有软数据的场景下获取LLR，根据LLR的值，对闪存的初始硬数据进行纠错，其中，LLR<0 的表示数据比特为“1”的可能性更大，LLR>0的表示数据比特为“0”的可能性更大。
本申请第一实施例中，通过先读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据，然后读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次，例如，当所述窗口电压值调整2次时，包括一组初始硬数据、第一调整硬数据和第二调整硬数据，将所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据中相同数据位上的数据按指定规则分别进行组合，生成组合硬数据，再根据所述组合硬数据确定二进制索引数据，进而确定对数似然比LLR的值，最后根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错，本方案在没有软数据的场景下获取LLR，可提升低密度奇偶校验码LDPC的纠错能力，从而保证闪存数据存储的可靠与安全，进而可延长数据的保存时间。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
实施例二：
对应于上文实施例所述的一种闪存的纠错方法，图5示出了本申请实施例提供的一种闪存的纠错装置的结构框图，该装置可应用于闪存存储设备。为了便于说明，仅示出了与本申请实施例相关的部分。
参照图5，该闪存的纠错装置包括：初始数据读取单元21，调整数据读取单元22，确定单元23，纠错单元24，其中：
初始数据读取单元21，用于读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据；
调整数据读取单元22，用于读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次；
确定单元23，用于根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值；
纠错单元24，用于根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
可选地，在本申请实施例中，当闪存数据的错误比特数高于预设的错误比特数时，若LDPC的硬判决无法纠错成功，读取所述闪存的调整硬数据。
进一步地，所述确定单元23具体包括：
第一获取模块，用于获取在第一次调整后的窗口电压值下读取的第一调整硬数据；
第二获取模块，用于获取在第二次调整后的窗口电压值下读取的第二调整硬数据；
索引数据确定模块，用于根据所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据进行组合生成的组合硬数据，确定二进制索引数据；
对数似然比确定模块，用于根据所述二进制索引数据确定对数似然比LLR的值。
进一步地，所述索引数据确定模块具体包括：
组合硬数据生成子模块，用于将所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据中相同数据位上的数据按指定规则分别进行组合，生成组合硬数据；
索引数据子模块，用于根据组合硬数据确定二进制索引数据。
可选地，所述组合硬数据生成子模块具体包括：
第一组合硬数据生成子模块，用于将所述初始硬数据中的数据放入所述组合硬数据的第一数据位，将所述第一调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第二数据位，将所述第二调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第三数据位，生成组合硬数据；
第二组合硬数据生成子模块，用于将所述初始硬数据中第一数据位的数据放入所述组合硬数据的第一数据位，将所述第二调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第二数据位，将所述第一调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第三数据位，生成组合硬数据。
可选地，所述纠错单元24具体包括：
第一判定模块，用于当所述对数似然比LLR的值大于零时，判定所述闪存的内部存储数据为“0”的可能性大于所述闪存的内部存储数据为“1”的可能性；
第二判定模块，用于当所述对数似然比LLR的值小于零时，判定所述闪存的内部存储数据为“1”的可能性大于所述闪存的内部存储数据为“0”的可能性。
本申请第二实施例中，通过先读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据，然后读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次，再根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值，最后根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错，本方案在没有软数据的场景下获取LLR，可提升低密度奇偶校验码LDPC的纠错能力，从而保证闪存数据存储的可靠与安全，进而可延长数据的保存时间。
实施例三：
图6是本申请一实施例提供的一种终端设备的示意图。如图6所示，该实施例的终端设备3包括：处理器30、存储器31以及存储在所述存储器31中并可在所述处理器30上运行的计算机程序32，例如闪存的纠错程序。所述处理器30执行所述计算机程序32时实现上述各个闪存的纠错方法实施例中的步骤，例如图1所示的步骤101至104。或者，所述处理器30执行所述计算机程序32时实现上述各装置实施例中各模块/单元的功能，例如图5所示单元21至24的功能。
示例性的，所述计算机程序32可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器31中，并由所述处理器30执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序32在所述终端设备3中的执行过程。例如，所述计算机程序32可以被分割成初始数据读取单元、调整数据读取单元、确定单元、纠错单元，各单元具体功能如下：
初始数据读取单元，用于读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据；
调整数据读取单元，用于读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次；
确定单元，用于根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值；
纠错单元，用于根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
所述终端设备3可以是桌上型计算机、笔记本、掌上电脑及云端服务器等计算设备。所述终端设备3可包括，但不仅限于，处理器30、存储器31。本领域技术人员可以理解，图6仅仅是终端设备3的示例，并不构成对终端设备3的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如所述终端设备还可以包括输入输出设备、网络接入设备、总线等。
所称处理器30可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器 (Digital Signal Processor，DSP)、专用集成电路 (Application Specific Integrated Circuit，ASIC)、现成可编程门阵列 (Field-Programmable Gate Array，FPGA) 或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器31可以是所述终端设备3的内部存储单元，例如终端设备3的硬盘或内存。所述存储器31也可以是所述终端设备3的外部存储设备，例如所述终端设备3上配备的插接式硬盘，智能存储卡（Smart Media Card, SMC），安全数字（Secure Digital, SD）卡，闪存卡（Flash Card）等。进一步地，所述存储器31还可以既包括所述终端设备3的内部存储单元也包括外部存储设备。所述存储器31用于存储所述计算机程序以及所述终端设备所需的其他程序和数据。所述存储器31还可以用于暂时地存储已经输出或者将要输出的数据。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的系统实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器（ROM，Read-Only Memory）、随机存取存储器（RAM，Random Access Memory）、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括是电载波信号和电信信号。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (11)

  1. 一种闪存的纠错方法，其特征在于，所述纠错方法包括：
    读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据；
    读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次；
    根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值；
    根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
  2. 如权利要求1所述的纠错方法，其特征在于，当所述窗口电压值调整2次时，所述根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值，具体包括：
    获取在第一次调整后的窗口电压值下读取的第一调整硬数据；
    获取在第二次调整后的窗口电压值下读取的第二调整硬数据；
    根据所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据进行组合生成的组合硬数据，确定二进制索引数据；
    根据所述二进制索引数据确定对数似然比LLR的值。
  3. 如权利要求2所述的纠错方法，其特征在于，所述根据所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据进行组合生成的组合硬数据，确定二进制索引数据，具体包括：
    将所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据中相同数据位上的数据按指定规则分别进行组合，生成组合硬数据；
    根据组合硬数据确定二进制索引数据。
  4. 如权利要求3所述的纠错方法，其特征在于，所述将所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据中相同数据位上的数据按指定规则分别进行组合，生成组合硬数据，包括：
    将所述初始硬数据中的数据放入所述组合硬数据的第一数据位，将所述第一调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第二数据位，将所述第二调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第三数据位，生成组合硬数据；
    或者，将所述初始硬数据中第一数据位的数据放入所述组合硬数据的第一数据位，将所述第二调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第二数据位，将所述第一调整硬数据中与所述初始硬数据中数据位相同的数据放入所述组合硬数据的第三数据位，生成组合硬数据。
  5. 如权利要求1至4任一项所述的纠错方法，其特征在于，所述根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错，具体包括：
    当所述对数似然比LLR的值大于零时，判定所述闪存的内部存储数据为“0”的可能性大于所述闪存的内部存储数据为“1”的可能性；
    当所述对数似然比LLR的值小于零时，判定所述闪存的内部存储数据为“1”的可能性大于所述闪存的内部存储数据为“0”的可能性。
  6. 一种闪存的纠错装置，其特征在于，所述纠错装置包括：
    初始数据读取单元，用于读取闪存的初始硬数据，所述初始硬数据为闪存默认的窗口电压值下读取的闪存的硬数据；
    调整数据读取单元，用于读取所述闪存的调整硬数据，所述调整硬数据为调整所述闪存的窗口电压值并在调整后的窗口电压值下读取的闪存的硬数据，其中，所述窗口电压值调整至少2次；
    确定单元，用于根据所述初始硬数据与所述调整硬数据确定对数似然比LLR的值；
    纠错单元，用于根据所述对数似然比LLR的值，对所述闪存的初始硬数据进行纠错。
  7. 如权利要求6所述的纠错装置，其特征在于，所述确定单元具体包括：
    第一获取模块，用于获取在第一次调整后的窗口电压值下读取的第一调整硬数据；
    第二获取模块，用于获取在第二次调整后的窗口电压值下读取的第二调整硬数据；
    索引数据确定模块，用于根据所述初始硬数据、所述第一调整硬数据以及所述第二调整硬数据进行组合生成的组合硬数据，确定二进制索引数据；
    对数似然比确定模块，用于根据所述二进制索引数据确定对数似然比LLR的值。
  8. 如权利要求6或7任一项所述的纠错装置，其特征在于，所述纠错单元具体包括：
    第一判定模块，用于当所述对数似然比LLR的值大于零时，判定所述闪存的内部存储数据为“0”的可能性大于所述闪存的内部存储数据为“1”的可能性；
    第二判定模块，用于当所述对数似然比LLR的值小于零时，判定所述闪存的内部存储数据为“1”的可能性大于所述闪存的内部存储数据为“0”的可能性。
  9. 一种终端设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求1至5任一项所述闪存的纠错方法的步骤。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1至5任一项所述闪存的纠错方法的步骤。
  11. 一种计算机程序产品，其特征在于，所述计算机程序产品包括存储在计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，所述指令被处理器执行时，可实现如权利要求1至5任一项所述闪存的纠错方法的步骤。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102073563A (zh) * 2011-02-23 2011-05-25 深圳市江波龙电子有限公司 闪存设备、闪存设备中存储块的管理方法及系统
CN102394113A (zh) * 2011-11-14 2012-03-28 清华大学 一种应用于快闪存储器中的动态ldpc纠错码方法
US20150242268A1 (en) * 2014-02-27 2015-08-27 Seagate Technology Llc Periodically updating a log likelihood ratio (llr) table in a flash memory controller
CN105468471A (zh) * 2014-09-12 2016-04-06 光宝科技股份有限公司 固态存储装置及其错误更正方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012181761A (ja) * 2011-03-02 2012-09-20 Toshiba Corp 半導体メモリ装置および復号方法
KR101968746B1 (ko) * 2011-12-30 2019-04-15 삼성전자주식회사 저장 장치로부터 데이터를 읽는 읽기 방법, 에러 정정 장치, 그리고 에러 정정 코드 디코더를 포함하는 저장 시스템
US8990668B2 (en) * 2013-03-14 2015-03-24 Western Digital Technologies, Inc. Decoding data stored in solid-state memory
KR102081415B1 (ko) * 2013-03-15 2020-02-25 삼성전자주식회사 비휘발성 메모리 장치의 llr 최적화 방법 및 비휘발성 메모리 장치의 에러 정정 방법
US9450619B2 (en) * 2013-03-22 2016-09-20 Seagate Technology Llc Dynamic log likelihood ratio quantization for solid state drive controllers
US9189333B2 (en) * 2013-10-17 2015-11-17 Seagate Technology Llc Generating soft decoding information for flash memory error correction using hard decision patterns

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102073563A (zh) * 2011-02-23 2011-05-25 深圳市江波龙电子有限公司 闪存设备、闪存设备中存储块的管理方法及系统
CN102394113A (zh) * 2011-11-14 2012-03-28 清华大学 一种应用于快闪存储器中的动态ldpc纠错码方法
US20150242268A1 (en) * 2014-02-27 2015-08-27 Seagate Technology Llc Periodically updating a log likelihood ratio (llr) table in a flash memory controller
CN105468471A (zh) * 2014-09-12 2016-04-06 光宝科技股份有限公司 固态存储装置及其错误更正方法

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