WO2019033607A1 - 驱动电路及显示装置 - Google Patents

驱动电路及显示装置 Download PDF

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Publication number
WO2019033607A1
WO2019033607A1 PCT/CN2017/112974 CN2017112974W WO2019033607A1 WO 2019033607 A1 WO2019033607 A1 WO 2019033607A1 CN 2017112974 W CN2017112974 W CN 2017112974W WO 2019033607 A1 WO2019033607 A1 WO 2019033607A1
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Prior art keywords
thin film
film transistor
driving circuit
scan driving
state
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PCT/CN2017/112974
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English (en)
French (fr)
Inventor
石龙强
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/749,219 priority Critical patent/US10573241B2/en
Publication of WO2019033607A1 publication Critical patent/WO2019033607A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a driving circuit and a display device.
  • the conventional Organic Light-Emitting Diode (OLED) driving circuit is composed of at least 2T1C, that is, a switching thin film transistor, a driving thin film transistor and a storage capacitor, thereby realizing stable display of the OLED.
  • the driving thin film transistor is subjected to severe voltage stress, which may cause the threshold voltage of the driving thin film transistor to drift, thereby affecting the brightness of the OLED, so that each pixel unit of the display panel is displayed. Inconsistent.
  • the embodiment of the invention provides a driving circuit and a display device, which can ensure the consistency of display of the pixel unit, thereby improving the display effect of the OLED.
  • an embodiment of the present invention provides a driving circuit including a first scan driving circuit, a second scan driving circuit, a selector, and at least one pixel unit; wherein the first scan driving circuit and the second scan driving circuit Separably electrically connected to the selector, and the selector is electrically connected to the at least one pixel unit;
  • the selector is configured to output a first scan driving signal of the first scan driving circuit to the at least one pixel unit in a first time period, to enable the at least one pixel unit to be in a display state; Outputting, by the second time period, a second scan driving signal of the second scan driving circuit to the at least one pixel unit, to enable the at least one pixel unit to be in a compensation state; the first time period and the second time The time period is different.
  • the selector comprises at least one thin film transistor, a trigger signal terminal, a high voltage input terminal and a low voltage input terminal;
  • the selector is configured to receive the trigger signal provided by the trigger signal terminal during the first time period when receiving the high voltage DC signal provided by the high voltage input terminal and the low voltage DC signal provided by the low voltage input terminal, Controlling the at least one thin film transistor to select the first scan driving signal output of the first scan driving circuit to the at least one pixel unit;
  • the selector is further configured to receive the trigger signal input input during a second time period when receiving the high voltage DC signal provided by the high voltage input terminal and the low voltage DC signal provided by the low voltage input terminal And triggering a signal, and controlling the at least one thin film transistor to select a first scan driving signal output of the second scan driving circuit to the at least one pixel unit.
  • the at least one thin film transistor comprises:
  • T1 a first thin film transistor having a gate and a source electrically connected to the high voltage input terminal, and a drain connected to the first node;
  • T2 a second thin film transistor having a gate connected to the trigger signal terminal, a drain connected to the first node, and a source connected to the low voltage input terminal;
  • T3 a third thin film transistor having a gate connected to the first node, a source connected to the first scan driving circuit, and a drain connected to the scan line;
  • the fourth thin film transistor (T4) has a gate connected to the trigger signal terminal, a source connected to the second scan driving circuit, and a drain connected to the scan line.
  • a switching state of the thin film transistor in the at least one thin film transistor is controlled by the trigger signal; and the switching state includes an off state or an on state.
  • the trigger signal in the first period of time, is in a low potential state, the second thin film transistor (T2) and the fourth thin film transistor (T4) are in an off state, and the third thin film transistor ( T3) is in an on state to select the first scan driving circuit to provide a first scan driving signal;
  • the trigger signal is in a high potential state
  • the second thin film transistor (T2) and the fourth thin film transistor (T4) are in an on state
  • the third thin film transistor (T3) In an off state, the second scan driving circuit is selected to provide a second scan driving signal.
  • the first node when the trigger signal is in a low potential state, the first node is at a high potential; and when the trigger signal is in a high potential state, the first node is at a low potential.
  • the third thin film transistor (T3) has a gate connected to the second node, a source connected to the first driving circuit, and a drain connected to the scan line;
  • the at least one thin film transistor further includes:
  • T5 a fifth thin film transistor having a gate connected to the first node, a source connected to the high voltage input terminal, and a drain connected to the second node;
  • the sixth thin film transistor (T6) has a gate connected to the trigger signal terminal, a source connected to the low voltage input terminal, and a drain connected to the second node.
  • the trigger signal in the first period of time, is in a low potential state, and the second thin film transistor (T2), the fourth thin film transistor (T4), and the sixth thin film transistor (T6) are off.
  • the third thin film transistor (T3) and the fifth thin film transistor (T5) are in an on state to select the first scan driving circuit to provide a first scan driving signal;
  • the trigger signal is in a high potential state, and the second thin film transistor (T2), the fourth thin film transistor (T4), and the sixth thin film transistor (T6) are in a conducting state.
  • the third thin film transistor (T3) and the fifth thin film transistor (T5) are in an off state to select the second scan driving circuit to provide a second scan driving signal.
  • the at least one pixel unit comprises:
  • T7 a seventh thin film transistor having a source connected to the data line and a gate connected to the scan line;
  • An eighth thin film transistor (T8) having a gate connected to a drain of the seventh thin film transistor (T7), a source connected to the high voltage DC input terminal, and a drain and an organic light included in the at least one pixel unit a positive electrode connection of the diode; a negative electrode of the organic light emitting diode is grounded;
  • a ninth thin film transistor having a gate connected to the scan line, a source connected to the detection module, and a drain connected to a drain of the eighth thin film transistor (T8);
  • the coupling capacitor has a first end connected to the gate of the eighth thin film transistor (T8) and a second end connected to the drain of the eighth thin film transistor (T8).
  • an embodiment of the present invention provides a display device including at least the driving circuit according to any one of claims 1 to 9.
  • the driving circuit and the display device of the embodiment of the present invention can provide a scan driving signal for the pixel unit according to the compensation or driving requirement of the pixel unit.
  • different scan driving circuits can alternately provide scanning driving signals to the pixel unit through the selector, which ensures the image to some extent.
  • the display quality of the prime unit can be provided.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of waveforms of a scan driving signal according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a driving circuit according to still another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of waveforms of a high voltage direct current signal, a low voltage direct current signal, and a trigger signal according to an embodiment of the present invention
  • FIG. 5 is a schematic circuit diagram of a driving circuit according to another embodiment of the present invention.
  • ground connection or integral connection; can be mechanical connection; can be directly connected or through The intermediate medium is indirectly connected and can be internal to the two components.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • the driving circuit and the display device of the embodiment of the invention can provide a scan driving signal for the pixel unit according to the compensation or driving requirement of the pixel unit.
  • different scan driving circuits can alternately provide scan driving signals to the pixel unit through the selector, which ensures the display quality of the pixel unit to some extent.
  • a driving circuit and a display device according to an embodiment of the present invention will be specifically described below with reference to FIG. 1 to FIG.
  • the driving circuit shown in the figure includes at least: a first scan driving circuit 100, a second scan driving circuit 200, a selector 300, and At least one pixel unit 400.
  • the first scan driving circuit 100 and the second scan driving circuit 200 are electrically connected to the selector 300, respectively, and the selector 300 is electrically connected to the at least one pixel unit 400.
  • the first scan driving circuit 100 and the second scan driving circuit 200 may be fabricated by a Gate Driver On Array (GOA) technology, and may be Used to drive the display of an Organic Light-Emitting Diode (OLED).
  • GOA Gate Driver On Array
  • the first scan driving circuit 100 can provide the first scan driving signal to the at least one pixel unit 400.
  • the second scan driving circuit 200 can provide the second scan driving signal to the at least one pixel unit 400.
  • the first scan driving signal can satisfy the normal driving requirement of the at least one pixel unit 400, and the second scan driving signal can satisfy the compensation requirement of the at least one pixel unit 400.
  • the selector 300 may selectively output a first scan driving signal to the at least one pixel unit 400 for causing the at least one pixel unit 400 to be in a display state during the first period of time. In the second period of time, the selector 300 may selectively output a second scan driving signal to the at least one pixel unit 400 for causing the at least one pixel unit to be in a compensation state.
  • the selector 300 may include at least one thin film transistor, and the selector 300 may realize selection of a scan driving signal of each scan driving circuit by cooperation between respective thin film transistors of the at least one thin film transistor. That is, the first scan driving signal or the second scan driving signal is selected to be output to the at least one pixel unit 400.
  • the first scan drive signal and the second scan drive signal may be different.
  • 01 is the waveform of the first scan signal 100
  • 02 is the waveform of the second scan drive signal.
  • the selector can alternately provide the scan driving signal to the at least one pixel unit, and simultaneously satisfy the waveforms of the two scan driving signals required for normal operation and compensation.
  • the display quality of the pixel unit is guaranteed to some extent.
  • FIG. 3 is a schematic circuit diagram of a driving circuit according to an embodiment of the present invention.
  • the driving circuit shown in FIG. 3 includes at least a first scan driving circuit 100, a second scan driving circuit 200, a selector 300, and at least one pixel unit 400.
  • the first scan driving circuit 100 and the second scan driving circuit 200 are electrically connected to the selector 300, respectively, and the selector 300 is electrically connected to the pixel unit 400.
  • the selector 300 can include at least one thin film transistor, a trigger signal terminal V_Comp, a high voltage input terminal DCH, and a low voltage input terminal VSS. As shown in FIG. 3, the selector 200 may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4.
  • the selector 300 can receive the trigger signal provided by the trigger signal terminal V_Comp.
  • the trigger signal is at a low potential for a first period of time and at a high potential for a second period of time.
  • the selector 300 can control the respective thin film transistors in the selector 300 through the received high voltage DC signal provided by the high voltage input terminal DCH, and the low voltage DC signal provided by the low voltage input terminal VSS and the trigger signal provided by the trigger signal terminal V_Comp. Collaborate to complete the selection process of the scan drive signals provided by the different scan drive circuits.
  • the high voltage DC signal provided by the high voltage input terminal DCH can be always in a high potential state during different time periods, and the low voltage DC signal provided by the low voltage input terminal VSS can always be in a low potential state, and the trigger signal is set according to the setting. Can alternate between high potential and low potential state.
  • the at least one thin film transistor may be controlled to select the first scan driving signal of the first scan driving circuit 100.
  • the trigger signal received by the selector 300 during the first time period is in a low state.
  • the selector 300 receives the trigger signal during the second period of time the at least one thin film transistor may be controlled to select the second scan driving signal of the second scan driving circuit 200.
  • the trigger signal received by the selector 300 during the second time period is in a high potential state.
  • At least one thin film transistor of the selector 300 may include: a first thin film transistor T1, and a gate and a source thereof are electrically connected to the high voltage input terminal DCH, and the drain thereof The pole is connected to the first node S(N); the second thin film transistor T2 has a gate connected to the trigger signal terminal V_Comp, a drain connected to the first node S(N), and a source thereof The low-voltage input terminal VSS is connected; the third thin film transistor T3 has a gate connected to the first node S(N), a source connected to the first scan driving circuit 100, and a drain and a scan line G(N) The fourth thin film transistor T4 has a gate connected to the trigger signal terminal V_Comp, a source connected to the second scan driving circuit 200, and a drain connected to the scan line G(N).
  • the gate of each thin film transistor can control the switching state (off state or on state) of the thin film transistor according to the received signal.
  • the trigger signal is in a low state during the first period of time, the second thin film transistor T2 and the fourth thin film transistor T4 are in an off state, and the third thin film transistor T3 is in an on state.
  • the first scan driving circuit 100 is selected to provide a first scan driving signal; in the second period, the trigger signal is in a high potential state, and the second thin film transistor T2 and the fourth thin film transistor T4 are in an on state,
  • the third thin film transistor T3 is in an off state to select the second scan driving circuit 200 to provide a second scan driving signal.
  • the first thin film transistor T1 when the trigger signal is in a low potential state, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, and the first node S(N) may be at a high potential, so that the third thin film transistor T1 Turn on.
  • the second thin film transistor T1 When the trigger signal is in a high potential state, the second thin film transistor T1 is turned on, so that the low voltage DC signal of the low voltage input terminal VSS is input, so that the first node S(N) is at a low potential, thereby causing the third thin film transistor. T1 is turned off.
  • FIG. 4 includes a waveform diagram of a trigger signal provided by the trigger signal terminal V_Comp, The waveform diagram of the high voltage DC signal provided by the high voltage input terminal DCH and the waveform diagram of the low voltage DC signal provided by the low voltage input terminal VSS.
  • the voltage of the trigger signal provided by the trigger signal terminal V_Comp is -8V
  • the voltage of the high voltage DC signal provided by the high voltage input terminal DCH is 27V
  • the low voltage input terminal VSS provides the low voltage.
  • the voltage of the DC signal is -8V.
  • the 27V high-voltage DC signal, the -8V trigger signal, and the -8V low-voltage DC signal can turn off the second thin film transistor T2 and the fourth thin film transistor T4, and the third thin film transistor T3 is turned on, thereby making selection
  • the device 300 can select the first scan driving circuit 100 to provide a first scan driving signal output to the at least one pixel unit 400. Among them, when arriving at time t2, the potential of the trigger signal will change from a low potential to a high potential.
  • FIG. 4 includes a waveform diagram of a trigger signal provided by the trigger signal terminal V_Comp, a waveform diagram of a high voltage DC signal provided by the high voltage input terminal DCH, and a waveform diagram of a low voltage DC signal provided by the low voltage input terminal VSS.
  • the voltage of the trigger signal provided by the trigger signal terminal V_Comp is -8V
  • the voltage of the high voltage DC signal provided by the high voltage input terminal DCH is 27V
  • the low voltage input terminal VSS provides the low voltage.
  • the voltage of the DC signal is -8V.
  • the 27V high-voltage DC signal and the 27V trigger signal-8V low-voltage DC signal can make the second thin film transistor T2 and the fourth thin film transistor T4 be turned on, and the third thin film transistor T3 is turned off, thereby making the selector
  • the second scan driving circuit 200 can be selected to provide a second scan driving signal output to the at least one pixel unit 400.
  • the at least one pixel unit 400 may include at least a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, a coupling capacitor Cst, and an OLED.
  • the seventh thin film transistor T7 has a source connected to the data line, a gate connected to the scan line G(N), and an eighth thin film transistor T8 whose gate is connected to the drain of the seventh thin film transistor T7.
  • the source is connected to the high voltage DC input terminal VDD, the drain thereof is connected to the anode of the OLED included in the pixel unit; the cathode of the OLED is grounded; and the ninth thin film transistor T9 has a gate connected to the scan line G(N).
  • the source is connected to the detection module Senser, and the drain thereof is connected to the drain of the eighth thin film transistor T8; the first end of the coupling capacitor Cst is connected to the gate of the eighth thin film transistor T8, and the second end thereof The drain of the eight thin film transistor T8 is connected.
  • the data line can be used to provide a data signal for controlling the display of the OLED.
  • the detection module Senser can realize the detection of circuit parameters such as voltage and current.
  • the coupling capacitor Cst can implement the eighth thin film transistor T8 according to the received scan driving signal. Charge and discharge.
  • the at least one pixel unit 400 may receive the first scan driving signal or the second scan driving signal from the selector 300 through the scan line G(N). After receiving the first scan driving signal, the at least one pixel unit 400 can drive the OLED to operate normally through cooperation between the respective thin film transistors included in the at least one pixel unit 400. After receiving the second scan signal, the at least one pixel unit 400 may perform compensation for the OLED through cooperation between the respective thin film transistors included in the at least one pixel unit 400.
  • the first scanning signal of the first scan driving circuit 100 is selected and output to the at least one pixel unit 400 in the first time period by the cooperation between the respective thin film transistors included in the selector 300, thereby The normal operation of the at least one pixel unit 400 is ensured; or the second scan signal of the second scan driving circuit 200 is selected to be output to the at least one pixel unit 400 in the second period of time, thereby realizing compensation for the pixel unit 400.
  • the scan driving signals of the different scan driving circuits are output to the at least one pixel unit 400 through different time periods, thereby ensuring the consistency of the pixel display and improving the display effect.
  • FIG. 5 is a schematic circuit diagram of a driving circuit according to another embodiment of the present invention.
  • the driving circuit shown in FIG. 5 includes at least a first scan driving circuit 100, a second scan driving circuit 200, a selector 300, and at least one pixel unit 400.
  • the first scan driving circuit 100 and the second scan driving circuit 200 are electrically connected to the selector 300, respectively, and the selector 300 is electrically connected to the pixel unit 400.
  • the selector 300 can include at least one thin film transistor. As shown in FIG. 5, the selector 200 may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a trigger signal. Terminal V_Comp, high voltage input terminal DCH, low voltage input terminal VSS.
  • the selector 300 can receive the trigger signal provided by the trigger signal terminal V_Comp.
  • the trigger signal is in a low state for a first period of time and a high state for a second period of time.
  • the selector 300 can control at least one thin film transistor in the selector 300 by receiving the high voltage DC signal provided by the high voltage input terminal DCH, and the low voltage DC signal provided by the low voltage input terminal VSS and the trigger signal provided by the trigger signal terminal V_Comp.
  • the thin film transistors cooperate to complete the selection process of the scan driving signals provided by the different scan driving circuits.
  • the high voltage DC signal may be always in a high potential state for different periods of time, and the low voltage DC signal may be always in a low potential state, and the trigger signal may alternately be in a high potential state and a low potential state according to the setting.
  • the at least one thin film transistor may be controlled to select the first scan driving signal of the first scan driving circuit 100.
  • the trigger signal received by the selector 300 during the first time period is in a low state.
  • the selector 300 receives the trigger signal during the second period of time the at least one thin film transistor may be controlled to select the second scan driving signal of the second scan driving circuit 200.
  • the trigger signal received by the selector 300 during the second time period is in a high potential state.
  • the at least one thin film transistor of the selector 300 may include: a first thin film transistor T1 having a gate and a source electrically connected to the high voltage input terminal DCH, and a drain and a first node thereof S(N) is connected; the second thin film transistor T2 has a gate connected to the trigger signal terminal V_Comp, a drain connected to the first node S(N), and a source connected to the low voltage input terminal VSS; The three thin film transistor T3 has a gate connected to the second node T(N), a source connected to the first scan driving circuit 100, a drain connected to the scan line G(N), and a fourth thin film transistor T4.
  • a gate connected to the trigger signal terminal V_Comp, a source connected to the second scan driving circuit 200, a drain connected to the scan line G(N), and a fifth thin film transistor T5 having a gate and a a node S(N) is connected, a source thereof is connected to the high voltage input terminal DCH, a drain thereof is connected to the second node T(N), a sixth thin film transistor T6, a gate thereof and the trigger signal terminal V_Comp
  • the connection has a source connected to the low voltage input terminal VSS and a drain connected to the second node T(N).
  • the gate of each thin film transistor can control the switching state (off state or on state) of the thin film transistor according to the received signal.
  • the thin film transistors in the selector 300 can be provided with different numbers of thin film transistors according to actual needs and the number of scan driving circuits, thereby selecting the scan driving signals of the scan driving circuits that need to be output. Also, a dimension of time may be added to output a scan drive signal of the corresponding scan driver circuit at different time periods to control display of the at least one pixel unit 400.
  • the trigger signal is in a low state during the first period of time, and the second thin film transistor T2, the fourth thin film transistor T4, and the sixth thin film transistor T6 are in an off state, the third film The transistor T3 and the fifth thin film transistor T5 are in an on state to select the first scan
  • the driving circuit 100 provides a first scan driving signal. Wherein, when the trigger signal is in a low potential state, the first thin film transistor T1 is turned on, and the second thin film transistor T2 is turned off, so that the first node S(N) is at a high potential, thereby making the fifth thin film transistor T5 Can be turned on.
  • the fifth thin film transistor T5 is turned on and the sixth thin film transistor T6 is turned off, the second node T(N) can be at a high potential, so the third thin film transistor T3 can be turned on, thereby achieving the first The selection of the scan drive signal provided by scan drive circuit 100.
  • FIG. 4 includes a waveform diagram of a trigger signal provided by the trigger signal terminal V_Comp, a waveform diagram of a high voltage DC signal provided by the high voltage input terminal DCH, and a waveform diagram of a low voltage DC signal provided by the low voltage input terminal VSS.
  • the voltage of the trigger signal provided by the trigger signal terminal V_Comp is -8V
  • the voltage of the high voltage DC signal provided by the high voltage input terminal DCH is 27V
  • the low voltage input terminal VSS provides the low voltage.
  • the voltage of the DC signal is -8V.
  • the 27V high-voltage DC signal, the -8V trigger signal, and the -8V low-voltage DC signal can turn off the second thin film transistor T2, the sixth thin film transistor T6, and the fourth thin film transistor T4, and the fifth thin film transistor T5, the third thin film transistor T3 is turned on, so that the selector 300 can select the first scan driving circuit 100 to provide a first scan driving signal output to the at least one pixel unit 400.
  • the potential of the trigger signal when arriving at time t2, the potential of the trigger signal will change from a low potential to a high potential.
  • the trigger signal is in a high potential state
  • the second thin film transistor T2, the fourth thin film transistor T4, and the sixth thin film transistor T6 are in an on state
  • the third film The transistor T3 and the fifth thin film transistor T5 are in an off state to select the second scan driving circuit 200 to provide a second scan driving signal.
  • the trigger signal is in a high potential state
  • the second thin film transistor T2 is turned on
  • the fourth thin film transistor T4 is turned on
  • the sixth thin film transistor T6 is turned on.
  • a low voltage DC signal is input, causing the first node S(N) to be at a low potential.
  • the fifth thin film transistor T5 is turned off.
  • the sixth thin film transistor T6 is turned on, the low voltage DC input terminal VSS inputs a low voltage DC signal, so that the second node T(N) is at a low potential, so that the third thin film transistor T3 is turned off.
  • FIG. 4 includes a waveform diagram of a trigger signal provided by the trigger signal terminal V_Comp, a waveform diagram of a high voltage DC signal provided by the high voltage input terminal DCH, and a waveform diagram of a low voltage DC signal provided by the low voltage input terminal VSS.
  • the trigger signal terminal V_Comp provides The voltage of the trigger signal is -8V, the voltage of the high voltage DC signal provided by the high voltage input terminal DCH is 27V, and the voltage of the low voltage DC signal provided by the low voltage input terminal VSS is -8V.
  • the 27V high voltage DC signal and the 27V trigger signal -8V low voltage DC signal can make the second thin film transistor T2, the sixth thin film transistor T6 and the fourth thin film transistor T4 be turned on, the fifth film transistor T5 and the The three thin film transistor T3 is turned off, so that the selector 300 can select the second scan driving circuit 200 to provide a second scan driving signal output to the at least one pixel unit 400.
  • the at least one pixel unit 400 may include at least a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, a coupling capacitor Cst, and an OLED.
  • the seventh thin film transistor T7 has a source connected to the data line, a gate connected to the scan line G(N), and an eighth thin film transistor T8 whose gate is connected to the drain of the seventh thin film transistor T7.
  • the source is connected to the high voltage DC input terminal VDD, the drain thereof is connected to the anode of the OLED included in the pixel unit; the cathode of the OLED is grounded; and the ninth thin film transistor T9 has a gate connected to the scan line G(N).
  • the source is connected to the sensing module Senser, the drain thereof is connected to the drain of the eighth thin film transistor T8, and the coupling capacitor Cst has a first end connected to the gate of the eighth thin film transistor T8, and a second end thereof The drain of the eighth thin film transistor T8 is connected.
  • the data line can be used to provide a data signal for controlling the display of the OLED.
  • the at least one pixel unit 400 may receive the first scan driving signal or the second scan driving signal from the selector 300 through the scan line G(N). After receiving the first scan signal, the at least one pixel unit 400 can drive the OLED to work normally by cooperation between the included thin film transistors. After receiving the second scan signal, the at least one pixel unit 400 may perform compensation for the OLED by cooperation between the respective thin film transistors included.
  • the detection module Senser can be used to detect circuit parameters such as voltage and current.
  • the first scanning signal of the first scan driving circuit 100 is selected and output to the at least one pixel unit 400 in the first time period by the cooperation between the respective thin film transistors included in the selector 300, thereby The normal operation of the at least one pixel unit 400 is ensured; or the second scan signal of the second scan driving circuit 200 is selected to be output to the at least one pixel unit 400 in the second period of time, thereby realizing compensation for the pixel unit 400.
  • Outputting the scan driving signals of different scan driving circuits to the at least one pixel unit 400 through different time periods can ensure the consistency of display of each pixel unit and improve the display effect.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动电路及显示装置，驱动电路包括第一扫描驱动电路(100)、第二扫描驱动电路(200)、选择器(300)以及至少一个像素单元(400)；其中，第一扫描驱动电路(100)以及第二扫描驱动电路(200)分别与选择器(300)电性连接，并且选择器(300)与至少一个像素单元(400)电性连接；选择器(300)，用于在第一时间段将第一扫描驱动电路(100)的第一扫描驱动信号输出至至少一个像素单元(400)，用以使至少一个像素单元(400)处于显示状态；在第二时间段将第二扫描驱动电路(200)的第二扫描驱动信号输出至至少一个像素单元(400)，用以使至少一个像素单元(400)处于补偿状态；第一时间段与第二时间段不同。驱动电路可以保证像素单元(400)显示的一致性，进而提高有机发光二极管(OLED)的显示效果。

Description

驱动电路及显示装置
本申请要求2017年08月15日递交的发明名称为“驱动电路及显示装置”的申请号为201710697988.5的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及电子技术领域，尤其涉及一种驱动电路及一种显示装置。
背景技术
传统的有机发光二极管(Organic Light-Emitting Diode，OLED)驱动电路至少是由2T1C组成的，即由一个开关薄膜晶体管、一个驱动薄膜晶体管以及一个存储电容，从而实现OLED的稳定显示。然而，由于OLED驱动电路长时间工作等原因，该驱动薄膜晶体管受到电压应力严重，会导致该驱动薄膜晶体管的阀值电压发生漂移，从而对OLED的亮度产生影响，致使显示面板的各个像素单元显示不一致。
发明内容
本发明实施例提供了一种驱动电路及显示装置，其可以保证像素单元显示的一致性，进而提高OLED的显示效果。
一方面，本发明实施例提供了一种驱动电路，包括第一扫描驱动电路、第二扫描驱动电路、选择器以及至少一个像素单元；其中，所述第一扫描驱动电路以及第二扫描驱动电路分别与所述选择器电性连接，并且所述选择器与所述至少一个像素单元电性连接；
所述选择器，用于在第一时间段将所述第一扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元，用以使所述至少一个像素单元处于显示状态；在第二时间段将所述第二扫描驱动电路的第二扫描驱动信号输出至所述至少一个像素单元，用以使所述至少一个像素单元处于补偿状态；所述第一时间段与所述第二时间段不同。
其中，所述选择器包括至少一个薄膜晶体管、触发信号端、高压输入端以及低压输入端；
所述选择器用以在接收到由所述高压输入端提供的高压直流信号以及所述低压输入端提供的低压直流信号时，若在第一时间段接收到所述触发信号端提供的触发信号，则控制所述至少一个薄膜晶体管选择所述第一扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元；
所述选择器，还用以在接收到由所述高压输入端提供的高压直流信号以及所述低压输入端提供的低压直流信号时，若在第二时间段接收到所述触发信号端输入的触发信号，则控制所述至少一个薄膜晶体管选择所述第二扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元。
其中，所述至少一个薄膜晶体管包括：
第一薄膜晶体管(T1)，其栅极以及源极均与所述高压输入端电性连接，其漏极与第一结点连接；
第二薄膜晶体管(T2)，其栅极与所述触发信号端连接，其漏极与所述第一结点连接，其源极与所述低压输入端连接；
第三薄膜晶体管(T3)，其栅极与所述第一结点连接，其源极与所述第一扫描驱动电路连接，其漏极与扫描线连接；
第四薄膜晶体管(T4)，其栅极与所述触发信号端相连，其源极与所述第二扫描驱动电路连接，其漏极与所述扫描线连接。
其中，所述至少一个薄膜晶体管中的薄膜晶体管的开关状态是由所述触发信号控制的；所述开关状态包括关断状态或导通状态。
其中，在所述第一时间段，所述触发信号处于低电位状态，所述第二薄膜晶体管(T2)以及所述第四薄膜晶体管(T4)处于关断状态，所述第三薄膜晶体管(T3)处于导通状态，以选取所述第一扫描驱动电路提供第一扫描驱动信号；
在所述第二时间段，所述触发信号处于高电位状态，所述第二薄膜晶体管(T2)以及所述第四薄膜晶体管(T4)处于导通状态，所述第三薄膜晶体管(T3)处于关断状态，以选取所述第二扫描驱动电路提供第二扫描驱动信号。
其中，在所述触发信号处于低电位状态时，所述第一结点处于高电位；在所述触发信号处于高电位状态时，所述第一结点处于低电位。
其中，所述第三薄膜晶体管(T3)，其栅极与第二结点连接，其源极与所述第一驱动电路连接，其漏极与扫描线连接；
所述至少一个薄膜晶体管还包括：
第五薄膜晶体管(T5)，其栅极与第一结点连接，其源极与所述高压输入端连接，其漏极与所述第二结点连接；
第六薄膜晶体管(T6)，其栅极与所述触发信号端连接，其源极与所述低压输入端连接，其漏极与所述第二结点连接。
其中，在所述第一时间段，所述触发信号处于低电位状态，所述第二薄膜晶体管(T2)、所述第四薄膜晶体管(T4)、所述第六薄膜晶体管(T6)处于关断状态，所述第三薄膜晶体管(T3)、所述第五薄膜晶体管(T5)处于导通状态，以选取所述第一扫描驱动电路提供第一扫描驱动信号；
在所述第二时间段，所述触发信号处于高电位状态，所述第二薄膜晶体管(T2)、所述第四薄膜晶体管(T4)、所述第六薄膜晶体管(T6)处于导通状态，所述第三薄膜晶体管(T3)、所述第五薄膜晶体管(T5)处于关断状态，以选取所述第二扫描驱动电路提供第二扫描驱动信号。
其中，所述至少一个像素单元包括：
第七薄膜晶体管(T7)，其源极与数据线连接，其栅极与所述扫描线连接；
第八薄膜晶体管(T8)，其栅极与所述第七薄膜晶体管(T7)的漏极连接，其源极与高压直流输入端连接，其漏极与所述至少一个像素单元包括的有机发光二极管的正极连接；所述有机发光二极管的负极接地；
第九薄膜晶体管(T9)，其栅极与所述扫描线连接，其源极与检测模块连接，其漏极与所述第八薄膜晶体管(T8)的漏极连接；
耦合电容，其第一端与所述第八薄膜晶体管(T8)的栅极相连、其第二端与所述第八薄膜晶体管(T8)的漏极连接。
另一方面，本发明实施例还提供了一种显示装置，至少包括如权利要求1～9任一项所述的驱动电路。
综上所述，本发明实施例的驱动电路及显示装置，可以根据像素单元的补偿或者驱动需求，来为该像素单元提供扫描驱动信号。其中，不同的扫描驱动电路可以通过选择器交替给像素单元提供扫描驱动信号，一定程度上保证了像 素单元的显示品质。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种驱动电路的结构示意图；
图2是本发明实施例提供的扫描驱动信号波形示意图；
图3是本发明再一实施例提供的一种驱动电路的电路示意图；
图4是本发明实施例提供的高压直流信号、低压直流信号以及触发信号的波形示意图；
图5是本发明又一实施例提供的一种驱动电路的电路示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。显然，所描述的实施方式是本发明的一部分实施方式，而不是全部实施方式。基在本发明中的实施方式，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施方式，都应属在本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过 中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现所述工序所预期的作用则也包括在本用语中。另外，本说明书中用“-”表示的数值范围是指将“-”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
本发明实施例的驱动电路及显示装置，可以根据像素单元的补偿或者驱动需求，来为该像素单元提供扫描驱动信号。其中，不同的扫描驱动电路可以通过选择器交替给像素单元提供扫描驱动信号，一定程度上保证了像素单元的显示品质。下面将结合图1到图5对本发明实施例提供的一种驱动电路及显示装置进行具体描述。
请参见图1，图1是本发明实施例提供的一种驱动电路的结构示意图，如图所示的驱动电路至少包括：第一扫描驱动电路100、第二扫描驱动电路200、选择器300以及至少一个像素单元400。该第一扫描驱动电路100以及第二扫描驱动电路200分别与该选择器300电性连接，并且该选择器300与该至少一个像素单元400电性连接。如图1所示，在本发明的一个实施例中，该第一扫描驱动电路100以及第二扫描驱动电路200可以由阵列基板栅极驱动(Gate Driver On Array，GOA)技术制成，并且可以用于驱动有机发光二极管(Organic Light-Emitting Diode，OLED)的显示。
该第一扫描驱动电路100可以为该至少一个像素单元400提供第一扫描驱动信号。该第二扫描驱动电路200可以为该至少一个像素单元400提供第二扫描驱动信号。该第一扫描驱动信号可以满足该至少一个像素单元400正常的驱动需求，该第二扫描驱动信号可以满足该至少一个像素单元400的补偿需求。
在一个实施例，在第一时间段，选择器300可以选择输出第一扫描驱动信号至该至少一个像素单元400，用以使该至少一个像素单元400处于显示状态。在第二时间段，选择器300可以选择输出第二扫描驱动信号至该至少一个像素单元400，用于使该至少一个像素单元处于补偿状态。
在一个实施例中，该选择器300可以包括至少一个薄膜晶体管，该选择器300可以通过该至少一个薄膜晶体管中各个薄膜晶体管之间的协作，实现对各个扫描驱动电路的扫描驱动信号的选择，即选择第一扫描驱动信号或第二扫描驱动信号输出至该至少一个像素单元400。
在一个实施例中，所述第一扫描驱动信号与第二扫描驱动信号可以不同。例如，如图2所示，01为第一扫描信号100的波形，02为第二扫描驱动信号的波形。
本发明实施例，针对OLED外部补偿扫描驱动信号波形的特点，可以通过该选择器交替给该至少一个像素单元提供扫描驱动信号，同时满足正常工作和补偿时所需要的两种扫描驱动信号波形，一定程度上保证了像素单元的显示品质。
请参见图3，图3是本发明实施例提供的一种驱动电路的电路示意图。结合图1所示的驱动电路，图3所示的驱动电路至少包括：第一扫描驱动电路100、第二扫描驱动电路200、选择器300以及至少一个像素单元400。该第一扫描驱动电路100以及第二扫描驱动电路200分别与该选择器300电性连接，并且该选择器300与该像素单元400电性连接。
该选择器300至少可以包括至少一个薄膜晶体管、触发信号端V_Comp、高压输入端DCH以及低压输入端VSS。如图3所示，该选择器200可以包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4。
其中，该选择器300可以接收到触发信号端V_Comp提供的触发信号。该触发信号在第一时间段处于低电位，在第二时间段处于高电位。
该选择器300可以通过接收到的由高压输入端DCH提供的高压直流信号，以及低压输入端VSS提供的低压直流信号以及触发信号端V_Comp提供的触发信号，控制该选择器300中各个薄膜晶体管之间进行协作，以完成对不同扫描驱动电路提供的扫描驱动信号的选择过程。
在一个实施例中，在不同时间段内由高压输入端DCH提供的高压直流信号可以一直处于高电位状态，由低压输入端VSS提供的低压直流信号可以一直处于低电位状态，该触发信号根据设置可以交替高电位状态以及低电位状 态。
在一个实施例中，若选择器300在第一时间段接收到触发信号，则可以控制该至少一个薄膜晶体管选择第一扫描驱动电路100的第一扫描驱动信号。其中，该选择器300在第一时间段接收到的触发信号处于低电位状态。若选择器300在第二时间段接收到触发信号，则可以控制该至少一个薄膜晶体管选择第二扫描驱动电路200的第二扫描驱动信号。其中，该选择器300在第二时间段接收到的触发信号处于高电位状态。
本发明实施例中，如图3所示，该选择器300中的至少一个薄膜晶体管可以包括：第一薄膜晶体管T1，其栅极以及源极均与该高压输入端DCH电性连接，其漏极与第一结点S(N)连接；第二薄膜晶体管T2，其栅极与该该触发信号端V_Comp连接，其漏极与该第一结点S(N)连接，其源极与该低压输入端VSS连接；第三薄膜晶体管T3，其栅极与该第一结点S(N)连接，其源极与该第一扫描驱动电路100连接，其漏极与扫描线G(N)连接；第四薄膜晶体管T4，其栅极与该触发信号端V_Comp相连，其源极与该第二扫描驱动电路200连接，其漏极与该与扫描线G(N)连接。在一个实施例中，各个薄膜晶体管的栅极可以根据接收到的信号，控制该薄膜晶体管的开关状态(关断状态或者导通状态)。
在一个实施例中，在该第一时间段，该触发信号处于低电位状态，该第二薄膜晶体管T2以及该第四薄膜晶体管T4处于关断状态，该第三薄膜晶体管T3处于导通状态，以选取该第一扫描驱动电路100提供第一扫描驱动信号；在该第二时间段，该触发信号处于高电位状态，该第二薄膜晶体管T2以及该第四薄膜晶体管T4处于导通状态，该第三薄膜晶体管T3处于关断状态，以选取该第二扫描驱动电路200提供第二扫描驱动信号。其中，在该触发信号处于低电位状态时，该第一薄膜晶体管T1导通，该第二薄膜晶体管T2关断，该第一结点S(N)可以位于高电位，使得第三薄膜晶体管T1导通。在该触发信号处于高电位状态时，第二薄膜晶体管T1导通，使得低压输入端VSS的低压直流信号输入，从而使得该第一结点S(N)位于低电位，从而导致第三薄膜晶体管T1关断。
例如，参见图4，图4包括触发信号端V_Comp提供的触发信号的波形图、 高压输入端DCH提供的高压直流信号的波形图、低压输入端VSS提供的低压直流信号的波形图。其中，在第一时间段(t1-t2)，该触发信号端V_Comp提供的触发信号的电压为-8V，该高压输入端DCH提供的高压直流信号的电压为27V，低压输入端VSS提供的低压直流信号的电压为-8V。该27V的高压直流信号、-8V的触发信号以及-8V的低压直流信号，可以使得该第二薄膜晶体管T2以及该第四薄膜晶体管T4关断，该第三薄膜晶体管T3导通，从而使得选择器300可以选取该第一扫描驱动电路100提供第一扫描驱动信号输出到该至少一个像素单元400。其中，在t2时刻到达时，触发信号的电位将由低电位变为高电位。
例如，参见图4，图4包括触发信号端V_Comp提供的触发信号的波形图、高压输入端DCH提供的高压直流信号的波形图、低压输入端VSS提供的低压直流信号的波形图。其中，在第二时间段(t2-t3)，该触发信号端V_Comp提供的触发信号的电压为-8V，该高压输入端DCH提供的高压直流信号的电压为27V，低压输入端VSS提供的低压直流信号的电压为-8V。该27V的高压直流信号、27V的触发信号-8V的低压直流信号，可以使得该第二薄膜晶体管T2以及该第四薄膜晶体管T4导通，该第三薄膜晶体管T3关断，从而使得该选择器300可以选取该第二扫描驱动电路200提供第二扫描驱动信号输出到该至少一个像素单元400。
在一个实施例中，该至少一个像素单元400至少可以包括：第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、耦合电容Cst以及OLED。
其中，第七薄膜晶体管T7，其源极与数据线连接，其栅极与该扫描线G(N)连接；第八薄膜晶体管T8，其栅极与该第七薄膜晶体管T7的漏极连接，其源极与高压直流输入端VDD连接，其漏极与该像素单元包括的OLED的正极连接；该OLED的负极接地；第九薄膜晶体管T9，其栅极与该扫描线G(N)连接，其源极与检测模块Senser连接，其漏极与该第八薄膜晶体管T8的漏极连接；耦合电容Cst的第一端与该第八薄膜晶体管T8的栅极相连，其第二端与该第八薄膜晶体管T8的漏极连接。该数据线可以用于提供数据信号以用于控制OLED的显示。该检测模块Senser，可以实现对电压、电流等电路参数的检测。该耦合电容Cst可以根据接收到的扫描驱动信号实现对该第八薄膜晶体管T8 的充放电。
其中，该至少一个像素单元400可以通过扫描线G(N)接收来自选择器300的第一扫描驱动信号或者第二扫描驱动信号。该至少一个像素单元400在接收到该第一扫描驱动信号后，可以通过该至少一个像素单元400包括的各个薄膜晶体管之间的协作来驱动该OLED正常工作。该至少一个像素单元400在接收到所述第二扫描信号后，可以通过该至少一个像素单元400包括的各个薄膜晶体管之间的协作进行对OLED的补偿。
本发明实施例可以通过所述选择器300中包含的各个薄膜晶体管之间的协作，来在第一时间段选择第一扫描驱动电路100的第一扫描信号输出到该至少一个像素单元400，从而保证该至少一个像素单元400的正常工作；或者在第二时间段选择第二扫描驱动电路200的第二扫描信号输出到该至少一个像素单元400，从而实现对该像素单元400的补偿。通过不同时间段选择不同扫描驱动电路的扫描驱动信号输出到该至少一个像素单元400，可以保证像素显示的一致性，提高显示效果。
参见图5，是本发明又一实施例提供的一种驱动电路的电路示意图。结合图3所示的驱动电路，图5所示的驱动电路至少包括：第一扫描驱动电路100、第二扫描驱动电路200、选择器300以及至少一个像素单元400。该第一扫描驱动电路100以及第二扫描驱动电路200分别与该选择器300电性连接，并且该选择器300与该像素单元400电性连接。
该选择器300至少可以包括至少一个薄膜晶体管。如图5所示，该选择器200可以包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、触发信号端V_Comp、高压输入端DCH、低压输入端VSS。
其中，该选择器300可以接收到触发信号端V_Comp提供的触发信号。该触发信号在第一时间段处于低电位状态，在第二时间段处于高电位状态。
该选择器300可以通过接收到的由高压输入端DCH提供的高压直流信号，以及低压输入端VSS提供的低压直流信号以及触发信号端V_Comp提供的触发信号，控制该选择器300中至少一个薄膜晶体管间各个薄膜晶体管之间进行协作，以完成对不同扫描驱动电路提供的扫描驱动信号的选择过程。
在一个实施例中，在不同时间段内该高压直流信号可以一直处于高电位状态，该低压直流信号可以一直处于低电位状态，该触发信号根据设置可以交替处于高电位状态以及低电位状态。
在一个实施例中，若选择器300在第一时间段接收到触发信号，则可以控制该至少一个薄膜晶体管选择第一扫描驱动电路100的第一扫描驱动信号。其中，该选择器300在第一时间段接收到的触发信号处于低电位状态。若选择器300在第二时间段接收到触发信号，则可以控制该至少一个薄膜晶体管选择第二扫描驱动电路200的第二扫描驱动信号。其中，该选择器300在第二时间段接收到的触发信号处于高电位状态。
本发明实施例中，该选择器300中的至少一个薄膜晶体管可以包括：第一薄膜晶体管T1，其栅极以及源极均与该高压输入端DCH电性连接，其漏极与第一结点S(N)连接；第二薄膜晶体管T2，其栅极与该触发信号端V_Comp连接，其漏极与该第一结点S(N)连接，其源极与该低压输入端VSS连接；第三薄膜晶体管T3，其栅极与该第二结点T(N)连接，其源极与该第一扫描驱动电路100连接，其漏极与扫描线G(N)连接；第四薄膜晶体管T4，其栅极与该触发信号端V_Comp相连，其源极与该第二扫描驱动电路200连接，其漏极与该与扫描线G(N)连接；第五薄膜晶体管T5，其栅极与第一结点S(N)连接，其源极与该高压输入端DCH连接，其漏极与该第二结点T(N)连接；第六薄膜晶体管T6，其栅极与该触发信号端V_Comp连接，其源极与该低压输入端VSS连接，其漏极与该第二结点T(N)连接。
在一个实施例中，各个薄膜晶体管的栅极可以根据接收到的信号，控制该薄膜晶体管的开关状态(关断状态或者导通状态)。
在一个实施例中，选择器300中的薄膜晶体管可以根据实际的需求以及扫描驱动电路的数量设置不同数量薄膜晶体管，从而选择需要输出的扫描驱动电路的扫描驱动信号。并且，可以增添时间的维度，从而在不同的时间段上输出相应扫描驱动电路的扫描驱动信号以控制该至少一个像素单元400的显示。
在一个实施例中，在该第一时间段，该触发信号处于低电位状态，该第二薄膜晶体管T2、该第四薄膜晶体管T4、该第六薄膜晶体管T6处于关断状态，该第三薄膜晶体管T3、该第五薄膜晶体管T5处于导通状态，以选取该第一扫 描驱动电路100提供第一扫描驱动信号。其中，在该触发信号处于低电位状态时，该第一薄膜晶体管T1导通，第二薄膜晶体管T2关断，使得该第一结点S(N)位于高电位，从而使得第五薄膜晶体管T5可以导通。并且，由于第五薄膜晶体管T5导通、第六薄膜晶体管T6关断，使得该第二结点T(N)可以位于高电位，因此该第三薄膜晶体管T3可以导通，从而实现对第一扫描驱动电路100提供的扫描驱动信号的选择。
例如，参见图4，图4包括触发信号端V_Comp提供的触发信号的波形图、高压输入端DCH提供的高压直流信号的波形图、低压输入端VSS提供的低压直流信号的波形图。其中，在第一时间段(t1-t2)，该触发信号端V_Comp提供的触发信号的电压为-8V，该高压输入端DCH提供的高压直流信号的电压为27V，低压输入端VSS提供的低压直流信号的电压为-8V。该27V的高压直流信号、-8V的触发信号以及-8V的低压直流信号，可以使得该第二薄膜晶体管T2、该第六薄膜晶体管T6、该第四薄膜晶体管T4关断，该第五薄膜晶体管T5、该第三薄膜晶体管T3导通，从而使得选择器300可以选取该第一扫描驱动电路100提供第一扫描驱动信号输出到该至少一个像素单元400。其中，在t2时刻到达时，触发信号的电位将由低电位变为高电位。
在一个实施例中，在该第二时间段，该触发信号处于高电位状态，该第二薄膜晶体管T2、该第四薄膜晶体管T4、该第六薄膜晶体管T6处于导通状态，该第三薄膜晶体管T3、该第五薄膜晶体管T5处于关断状态，以选取该第二扫描驱动电路200提供第二扫描驱动信号。其中，在该触发信号处于高电位状态时，该第二薄膜晶体管T2导通、该第四薄膜晶体管T4导通、该第六薄膜晶体管T6导通。在第二薄膜晶体管T2导通后会使得低压直流信号输入，导致该第一结点S(N)位于低电位。由于第一结点S(N)位于低电位，使得第五薄膜晶体管T5关断。在该第六薄膜晶体管T6导通后，该低压直流输入端VSS输入低压直流信号，使得该第二结点T(N)为低电位，从而使得该第三薄膜晶体管T3关断。
例如，参见图4，图4包括触发信号端V_Comp提供的触发信号的波形图、高压输入端DCH提供的高压直流信号的波形图、低压输入端VSS提供的低压直流信号的波形图。其中，在第二时间段(t2-t3)，该触发信号端V_Comp提供 的触发信号的电压为-8V，该高压输入端DCH提供的高压直流信号的电压为27V，低压输入端VSS提供的低压直流信号的电压为-8V。该27V的高压直流信号、27V的触发信号-8V的低压直流信号可以使得该第二薄膜晶体管T2、该第六薄膜晶体管T6以及该第四薄膜晶体管T4导通，该第五膜晶体管T5以及第三薄膜晶体管T3关断，从而使得该选择器300可以选取该第二扫描驱动电路200提供第二扫描驱动信号输出到该至少一个像素单元400。
在一个实施例中，该至少一个像素单元400至少可以包括：第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、耦合电容Cst和OLED。
其中，第七薄膜晶体管T7，其源极与数据线连接，其栅极与该扫描线G(N)连接；第八薄膜晶体管T8，其栅极与该第七薄膜晶体管T7的漏极连接，其源极与高压直流输入端VDD连接，其漏极与该像素单元包括的OLED的正极连接；该OLED的负极接地；第九薄膜晶体管T9，其栅极与该扫描线G(N)连接，其源极与检测模块Senser连接，其漏极与该第八薄膜晶体管T8的漏极连接；耦合电容Cst，其第一端与该第八薄膜晶体管T8的栅极相连、其第二端与该第八薄膜晶体管T8的漏极连接。该数据线可以用于提供数据信号以用于控制OLED的显示。
其中，该至少一个像素单元400可以通过扫描线G(N)接收来自所述选择器300的第一扫描驱动信号或者第二扫描驱动信号。该至少一个像素单元400在接收到所述第一扫描信号后，可以通过包括的各个薄膜晶体管之间的协作来驱动OLED正常工作。该至少一个像素单元400在接收到所述第二扫描信号后，可以通过包括的各个薄膜晶体管之间的协作进行对该OLED的补偿。该检测模块Senser可以用于检测电压、电流等电路参数。
本发明实施例可以通过所述选择器300中包含的各个薄膜晶体管之间的协作，来在第一时间段选择第一扫描驱动电路100的第一扫描信号输出到该至少一个像素单元400，从而保证该至少一个像素单元400的正常工作；或者在第二时间段选择第二扫描驱动电路200的第二扫描信号输出到所述至少一个像素单元400，从而实现对该像素单元400的补偿。通过不同时间段选择不同扫描驱动电路的扫描驱动信号输出到该至少一个像素单元400可以保证各像素单元显示的一致性，提高显示效果。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含在本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上对本发明实施例所提供的一种驱动电路及具有所述驱动电路的显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种驱动电路，包括第一扫描驱动电路、第二扫描驱动电路、选择器以及至少一个像素单元；其中，所述第一扫描驱动电路以及第二扫描驱动电路分别与所述选择器电性连接，并且所述选择器与所述至少一个像素单元电性连接；所述选择器，用于在第一时间段将所述第一扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元，用以使所述至少一个像素单元处于显示状态；在第二时间段将所述第二扫描驱动电路的第二扫描驱动信号输出至所述至少一个像素单元，用以使所述至少一个像素单元处于补偿状态；其中，所述第一时间段与所述第二时间段不同。
  2. 根据权利要求1所述的驱动电路，其中，所述选择器包括至少一个薄膜晶体管、触发信号端、高压输入端以及低压输入端；
    所述选择器用以在接收到由所述高压输入端提供的高压直流信号以及所述低压输入端提供的低压直流信号时，若在第一时间段接收到所述触发信号端提供的触发信号，则控制所述至少一个薄膜晶体管选择所述第一扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元；
    所述选择器，还用以在接收到由所述高压输入端提供的高压直流信号以及所述低压输入端提供的低压直流信号时，若在第二时间段接收到所述触发信号端输入的触发信号，则控制所述至少一个薄膜晶体管选择所述第二扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元。
  3. 根据权利要求2所述的驱动电路，其中，所述至少一个薄膜晶体管包括：
    第一薄膜晶体管(T1)，其栅极以及源极均与所述高压输入端电性连接，其漏极与第一结点连接；
    第二薄膜晶体管(T2)，其栅极与所述触发信号端连接，其漏极与所述第一结点连接，其源极与所述低压输入端连接；
    第三薄膜晶体管(T3)，其栅极与所述第一结点连接，其源极与所述第一扫 描驱动电路连接，其漏极与扫描线连接；
    第四薄膜晶体管(T4)，其栅极与所述触发信号端相连，其源极与所述第二扫描驱动电路连接，其漏极与所述扫描线连接。
  4. 根据权利要求3所述的驱动电路，其中，所述至少一个薄膜晶体管中的薄膜晶体管的开关状态是由所述触发信号控制的；所述开关状态包括关断状态或导通状态。
  5. 根据权利要求4所述的驱动电路，其中，
    在所述第一时间段，所述触发信号处于低电位状态，所述第二薄膜晶体管(T2)以及所述第四薄膜晶体管(T4)处于关断状态，所述第三薄膜晶体管(T3)处于导通状态，以选取所述第一扫描驱动电路提供第一扫描驱动信号；
    在所述第二时间段，所述触发信号处于高电位状态，所述第二薄膜晶体管(T2)以及所述第四薄膜晶体管(T4)处于导通状态，所述第三薄膜晶体管(T3)处于关断状态，以选取所述第二扫描驱动电路提供第二扫描驱动信号。
  6. 根据权利要求5所述的驱动电路，其中，在所述触发信号处于低电位状态时，所述第一结点处于高电位；在所述触发信号处于高电位状态时，所述第一结点处于低电位。
  7. 根据权利要求3所述的驱动电路，其中，所述第三薄膜晶体管(T3)的栅极与第二结点连接，其源极与所述第一驱动电路连接，其漏极与扫描线连接；
    所述至少一个薄膜晶体管还包括：
    第五薄膜晶体管(T5)，其栅极与第一结点连接，其源极与所述高压输入端连接，其漏极与所述第二结点连接；
    第六薄膜晶体管(T6)，其栅极与所述触发信号端连接，其源极与所述低压输入端连接，其漏极与所述第二结点连接。
  8. 根据权利要求7所述的驱动电路，其中，
    在所述第一时间段，所述触发信号处于低电位状态，所述第二薄膜晶体管(T2)、所述第四薄膜晶体管(T4)、所述第六薄膜晶体管(T6)处于关断状态，所述第三薄膜晶体管(T3)、所述第五薄膜晶体管(T5)处于导通状态，以选取所述第一扫描驱动电路提供第一扫描驱动信号；
    在所述第二时间段，所述触发信号处于高电位状态，所述第二薄膜晶体管(T2)、所述第四薄膜晶体管(T4)、所述第六薄膜晶体管(T6)处于导通状态，所述第三薄膜晶体管(T3)、所述第五薄膜晶体管(T5)处于关断状态，以选取所述第二扫描驱动电路提供第二扫描驱动信号。
  9. 根据权利要求3所述的驱动电路，其中，所述至少一个像素单元包括：
    第七薄膜晶体管(T7)，其源极与数据线连接，其栅极与所述扫描线连接；
    第八薄膜晶体管(T8)，其栅极与所述第七薄膜晶体管(T7)的漏极连接，其源极与高压直流输入端连接，其漏极与所述至少一个像素单元包括的有机发光二极管的正极连接；所述有机发光二极管的负极接地；
    第九薄膜晶体管(T9)，其栅极与所述扫描线连接，其源极与检测模块连接，其漏极与所述第八薄膜晶体管(T8)的漏极连接；
    耦合电容，其第一端与所述第八薄膜晶体管(T8)的栅极相连、其第二端与所述第八薄膜晶体管(T8)的漏极连接。
  10. 根据权利要求4所述的驱动电路，其中，所述至少一个像素单元包括：
    第七薄膜晶体管(T7)，其源极与数据线连接，其栅极与所述扫描线连接；
    第八薄膜晶体管(T8)，其栅极与所述第七薄膜晶体管(T7)的漏极连接，其源极与高压直流输入端连接，其漏极与所述至少一个像素单元包括的有机发光二极管的正极连接；所述有机发光二极管的负极接地；
    第九薄膜晶体管(T9)，其栅极与所述扫描线连接，其源极与检测模块连接，其漏极与所述第八薄膜晶体管(T8)的漏极连接；
    耦合电容，其第一端与所述第八薄膜晶体管(T8)的栅极相连、其第二端与所述第八薄膜晶体管(T8)的漏极连接。
  11. 一种显示装置，包括驱动电路，其中，所述驱动电路包括第一扫描驱动电路、第二扫描驱动电路、选择器以及至少一个像素单元；其中，所述第一扫描驱动电路以及第二扫描驱动电路分别与所述选择器电性连接，并且所述选择器与所述至少一个像素单元电性连接；所述选择器，用于在第一时间段将所述第一扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元，用以使所述至少一个像素单元处于显示状态；在第二时间段将所述第二扫描驱动电路的第二扫描驱动信号输出至所述至少一个像素单元，用以使所述至少一个像素单元处于补偿状态；其中，所述第一时间段与所述第二时间段不同。
  12. 根据权利要求11所述的显示装置，其中，所述选择器包括至少一个薄膜晶体管、触发信号端、高压输入端以及低压输入端；
    所述选择器用以在接收到由所述高压输入端提供的高压直流信号以及所述低压输入端提供的低压直流信号时，若在第一时间段接收到所述触发信号端提供的触发信号，则控制所述至少一个薄膜晶体管选择所述第一扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元；
    所述选择器，还用以在接收到由所述高压输入端提供的高压直流信号以及所述低压输入端提供的低压直流信号时，若在第二时间段接收到所述触发信号端输入的触发信号，则控制所述至少一个薄膜晶体管选择所述第二扫描驱动电路的第一扫描驱动信号输出至所述至少一个像素单元。
  13. 根据权利要求12所述的显示装置，其中，所述至少一个薄膜晶体管包括：
    第一薄膜晶体管(T1)，其栅极以及源极均与所述高压输入端电性连接，其漏极与第一结点连接；
    第二薄膜晶体管(T2)，其栅极与所述触发信号端连接，其漏极与所述第一结点连接，其源极与所述低压输入端连接；
    第三薄膜晶体管(T3)，其栅极与所述第一结点连接，其源极与所述第一扫描驱动电路连接，其漏极与扫描线连接；
    第四薄膜晶体管(T4)，其栅极与所述触发信号端相连，其源极与所述第二 扫描驱动电路连接，其漏极与所述扫描线连接。
  14. 根据权利要求13所述的显示装置，其中，所述至少一个薄膜晶体管中的薄膜晶体管的开关状态是由所述触发信号控制的；所述开关状态包括关断状态或导通状态。
  15. 根据权利要求14所述的显示装置，其中，
    在所述第一时间段，所述触发信号处于低电位状态，所述第二薄膜晶体管(T2)以及所述第四薄膜晶体管(T4)处于关断状态，所述第三薄膜晶体管(T3)处于导通状态，以选取所述第一扫描驱动电路提供第一扫描驱动信号；
    在所述第二时间段，所述触发信号处于高电位状态，所述第二薄膜晶体管(T2)以及所述第四薄膜晶体管(T4)处于导通状态，所述第三薄膜晶体管(T3)处于关断状态，以选取所述第二扫描驱动电路提供第二扫描驱动信号。
  16. 根据权利要求15所述的显示装置，其中，在所述触发信号处于低电位状态时，所述第一结点处于高电位；在所述触发信号处于高电位状态时，所述第一结点处于低电位。
  17. 根据权利要求13所述的显示装置，其中，所述第三薄膜晶体管(T3)的栅极与第二结点连接，其源极与所述第一驱动电路连接，其漏极与扫描线连接；
    所述至少一个薄膜晶体管还包括：
    第五薄膜晶体管(T5)，其栅极与第一结点连接，其源极与所述高压输入端连接，其漏极与所述第二结点连接；
    第六薄膜晶体管(T6)，其栅极与所述触发信号端连接，其源极与所述低压输入端连接，其漏极与所述第二结点连接。
  18. 根据权利要求17所述的显示装置，其中，
    在所述第一时间段，所述触发信号处于低电位状态，所述第二薄膜晶体管 (T2)、所述第四薄膜晶体管(T4)、所述第六薄膜晶体管(T6)处于关断状态，所述第三薄膜晶体管(T3)、所述第五薄膜晶体管(T5)处于导通状态，以选取所述第一扫描驱动电路提供第一扫描驱动信号；
    在所述第二时间段，所述触发信号处于高电位状态，所述第二薄膜晶体管(T2)、所述第四薄膜晶体管(T4)、所述第六薄膜晶体管(T6)处于导通状态，所述第三薄膜晶体管(T3)、所述第五薄膜晶体管(T5)处于关断状态，以选取所述第二扫描驱动电路提供第二扫描驱动信号。
  19. 根据权利要求13所述的显示装置，其中，所述至少一个像素单元包括：
    第七薄膜晶体管(T7)，其源极与数据线连接，其栅极与所述扫描线连接；
    第八薄膜晶体管(T8)，其栅极与所述第七薄膜晶体管(T7)的漏极连接，其源极与高压直流输入端连接，其漏极与所述至少一个像素单元包括的有机发光二极管的正极连接；所述有机发光二极管的负极接地；
    第九薄膜晶体管(T9)，其栅极与所述扫描线连接，其源极与检测模块连接，其漏极与所述第八薄膜晶体管(T8)的漏极连接；
    耦合电容，其第一端与所述第八薄膜晶体管(T8)的栅极相连、其第二端与所述第八薄膜晶体管(T8)的漏极连接。
  20. 根据权利要求14所述的显示装置，其中，所述至少一个像素单元包括：
    第七薄膜晶体管(T7)，其源极与数据线连接，其栅极与所述扫描线连接；
    第八薄膜晶体管(T8)，其栅极与所述第七薄膜晶体管(T7)的漏极连接，其源极与高压直流输入端连接，其漏极与所述至少一个像素单元包括的有机发光二极管的正极连接；所述有机发光二极管的负极接地；
    第九薄膜晶体管(T9)，其栅极与所述扫描线连接，其源极与检测模块连接，其漏极与所述第八薄膜晶体管(T8)的漏极连接；
    耦合电容，其第一端与所述第八薄膜晶体管(T8)的栅极相连、其第二端与所述第八薄膜晶体管(T8)的漏极连接。
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CN107274832A (zh) * 2017-08-15 2017-10-20 深圳市华星光电半导体显示技术有限公司 驱动电路及显示装置

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