WO2019033558A1 - 一种 oled 像素驱动电路及像素驱动方法 - Google Patents

一种 oled 像素驱动电路及像素驱动方法 Download PDF

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Publication number
WO2019033558A1
WO2019033558A1 PCT/CN2017/107966 CN2017107966W WO2019033558A1 WO 2019033558 A1 WO2019033558 A1 WO 2019033558A1 CN 2017107966 W CN2017107966 W CN 2017107966W WO 2019033558 A1 WO2019033558 A1 WO 2019033558A1
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Prior art keywords
thin film
film transistor
scan signal
source
gate
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PCT/CN2017/107966
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English (en)
French (fr)
Inventor
陈小龙
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/574,027 priority Critical patent/US10192488B1/en
Publication of WO2019033558A1 publication Critical patent/WO2019033558A1/zh
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an OLED pixel driving circuit and a pixel driving method.
  • OLED Organic Light Emitting Display
  • the display device has self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, and nearly 180 °
  • the viewing angle and wide operating temperature range can realize many advantages such as flexible display and large-area full-color display, and become the most promising display device.
  • the traditional OLED pixel driver circuit is usually 2T1C. That is, two thin film transistors plus a capacitor structure convert the voltage into a current.
  • the existing 2T1C structure OLED pixel driving circuit includes a first thin film transistor T10. a second thin film transistor T20, a capacitor C10, and an organic light emitting diode D10.
  • the first thin film transistor T10 is a driving thin film transistor
  • the second thin film transistor T20 To switch the thin film transistor, the capacitor C10 is a storage capacitor.
  • the gate of the second thin film transistor T20 is connected to the scan signal Gate, and the source is connected to the data signal Data.
  • the drain is electrically connected to the gate of the first thin film transistor T10; the source of the first thin film transistor T10 is connected to the positive voltage of the power supply OVDD, and the drain is electrically connected to the organic light emitting diode D10
  • the anode of the organic light emitting diode D10 is connected to the power supply negative voltage OVSS.
  • One end of the capacitor C10 is electrically connected to the gate of the first thin film transistor T10, and the other end is electrically connected to the first thin film transistor.
  • the source of T10. When the 2T1C pixel driving circuit drives the OLED, the current flowing through the organic light emitting diode D10 satisfies:
  • I k ⁇ ( Vgs-Vth ) 2 ;
  • I is the current flowing through the organic light emitting diode D10
  • k is the intrinsic conduction factor of the driving thin film transistor
  • Vgs The voltage difference between the gate and the source of the first thin film transistor T10
  • Vth is the threshold voltage of the first thin film transistor T10, and it can be seen that the organic light emitting diode D10 flows.
  • the current is related to the threshold voltage of the driving thin film transistor.
  • the threshold voltage of the driving thin film transistor in each pixel driving circuit in the panel is different due to factors such as instability of the panel process. Even if an equal data voltage is applied to the driving thin film transistors in the respective pixel driving circuits, the current flowing into the organic light emitting diodes is made inconsistent, thereby affecting the uniformity of the display image quality.
  • the material of the thin film transistor may be aged and mutated, causing the threshold voltage of the driving thin film transistor to drift, and the aging degree of the thin film transistor material is different, and the threshold voltage drift of each driving thin film transistor The amount is also different, so that the panel display unevenness occurs, and the turn-on voltage of the driving thin film transistor rises, and the current flowing into the organic light emitting diode decreases, causing problems such as lower panel luminance and lower luminous efficiency.
  • the object of the present invention is to provide an OLED
  • the pixel driving circuit and the pixel driving method can improve the uniformity of the panel display, the brightness of the panel, and the luminous efficiency.
  • an OLED pixel driving circuit which includes:
  • a first thin film transistor a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a capacitor, and an organic light emitting diode;
  • a gate of the fifth thin film transistor is connected to a fourth scan signal, a source of the fifth thin film transistor is connected to a positive voltage of a power source, and a drain of the fifth thin film transistor is respectively drained with a drain of the third thin film transistor a pole and a source of the first thin film transistor are connected;
  • a gate of the third thin film transistor is connected to a second scan signal, and a source of the third thin film transistor and a source of the fourth thin film transistor are connected to a data voltage or an initialization voltage; the fourth thin film transistor The gate is connected to the third scan signal;
  • a gate of the first thin film transistor is respectively connected to a source of the second thin film transistor and one end of the capacitor, and the other end of the capacitor is grounded;
  • a gate of the second thin film transistor is connected to the first scan signal, and a drain of the second thin film transistor is respectively connected to a drain of the first thin film transistor, a drain of the fourth thin film transistor, and the a drain connection of six thin film transistors;
  • a gate of the sixth thin film transistor is connected to a fourth scan signal, a source of the sixth thin film transistor is connected to an anode of the organic light emitting diode, and a cathode of the organic light emitting diode is connected to a negative voltage of a power supply;
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are both P The thin film transistor; the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are each generated by an external timing controller.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all low temperature polysilicon thin film transistors and oxides One of a semiconductor thin film transistor and an amorphous silicon thin film transistor.
  • the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are combined to sequentially correspond to an initialization phase, a threshold voltage storage phase, and an illumination display phase;
  • the first scan signal and the third scan signal are both low, and the second scan signal and the fourth scan signal are high;
  • the first scan signal and the second scan signal are both low, and the third scan signal and the fourth three signals are both high;
  • the first scan signal, the second scan signal, and the third scan signal are all at a high potential, and the fourth scan signal is at a low potential.
  • the source of the third thin film transistor and the source of the fourth thin film transistor are both connected to the initialization voltage;
  • the source of the third thin film transistor and the source of the fourth thin film transistor are both connected to the data voltage during a threshold voltage storage phase and the light emission display phase.
  • the first thin film transistor is a driving thin film transistor
  • the sixth thin film transistor is a switching thin film transistor
  • an OLED pixel driving circuit which includes:
  • a first thin film transistor a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a capacitor, and an organic light emitting diode;
  • a gate of the fifth thin film transistor is connected to a fourth scan signal, a source of the fifth thin film transistor is connected to a positive voltage of a power source, and a drain of the fifth thin film transistor is respectively drained with a drain of the third thin film transistor a pole and a source of the first thin film transistor are connected;
  • a gate of the third thin film transistor is connected to a second scan signal, and a source of the third thin film transistor and a source of the fourth thin film transistor are connected to a data voltage or an initialization voltage; the fourth thin film transistor The gate is connected to the third scan signal;
  • a gate of the first thin film transistor is respectively connected to a source of the second thin film transistor and one end of the capacitor, and the other end of the capacitor is grounded;
  • a gate of the second thin film transistor is connected to the first scan signal, and a drain of the second thin film transistor is respectively connected to a drain of the first thin film transistor, a drain of the fourth thin film transistor, and the a drain connection of six thin film transistors;
  • a gate of the sixth thin film transistor is connected to a fourth scan signal, a source of the sixth thin film transistor is connected to an anode of the organic light emitting diode, and a cathode of the organic light emitting diode is connected to a negative voltage of a power source.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all low temperature polysilicon thin film transistors and oxides One of a semiconductor thin film transistor and an amorphous silicon thin film transistor.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all P-type thin film transistors.
  • the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are combined to sequentially correspond to an initialization phase, a threshold voltage storage phase, and an illumination display phase;
  • the first scan signal and the third scan signal are both low, and the second scan signal and the fourth scan signal are high;
  • the first scan signal and the second scan signal are both low, and the third scan signal and the fourth three signals are both high;
  • the first scan signal, the second scan signal, and the third scan signal are all at a high potential, and the fourth scan signal is at a low potential.
  • the source of the third thin film transistor and the source of the fourth thin film transistor are both connected to the initialization voltage;
  • the source of the third thin film transistor and the source of the fourth thin film transistor are both connected to the data voltage during a threshold voltage storage phase and the light emission display phase.
  • the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are each generated by an external timing controller.
  • the first thin film transistor is a driving thin film transistor
  • the sixth thin film transistor is a switching thin film transistor
  • the invention also provides an OLED pixel driving method, comprising the following steps:
  • the OLED pixel driving circuit includes:
  • a first thin film transistor a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a capacitor, and an organic light emitting diode;
  • a gate of the fifth thin film transistor is connected to a fourth scan signal, a source of the fifth thin film transistor is connected to a positive voltage of a power source, and a drain of the fifth thin film transistor is respectively drained with a drain of the third thin film transistor a pole and a source of the first thin film transistor are connected;
  • a gate of the third thin film transistor is connected to a second scan signal, and a source of the third thin film transistor and a source of the fourth thin film transistor are connected to a data voltage or an initialization voltage; the fourth thin film transistor The gate is connected to the third scan signal;
  • a gate of the first thin film transistor is respectively connected to a source of the second thin film transistor and one end of the capacitor, and the other end of the capacitor is grounded;
  • a gate of the second thin film transistor is connected to the first scan signal, and a drain of the second thin film transistor is respectively connected to a drain of the first thin film transistor, a drain of the fourth thin film transistor, and the a drain connection of six thin film transistors;
  • a gate of the sixth thin film transistor is connected to a fourth scan signal, a source of the sixth thin film transistor is connected to an anode of the organic light emitting diode, and a cathode of the organic light emitting diode is connected to a negative voltage of a power supply;
  • the first scan signal provides a low potential, the second thin film transistor is turned on; the third scan signal provides a low potential, the fourth thin film transistor is turned on; and the second scan signal provides a high a potential, the third thin film transistor is turned off; the fourth scan signal provides a high potential, the fifth and sixth thin film transistors are turned off; a voltage of a gate of the first thin film transistor is equal to the initial voltage;
  • the first scan signal provides a low potential, the second thin film transistor is turned on; the second scan signal provides a low potential, the third thin film transistor is turned on; and the third scan signal provides a high Potential, the fourth thin film transistor is turned off; the fourth scan signal provides a high potential, the fifth and sixth thin film transistors are turned off; a voltage of a source of the first thin film transistor is equal to the data voltage, The voltage of the gate of the first thin film transistor changes to Vdata-Vth, wherein Vdata is a data voltage, and Vth is a threshold voltage of the first thin film transistor;
  • the first scan signal provides a high potential, the second thin film transistor is turned off; the second scan signal provides a high potential, the third thin film transistor is turned off; and the third scan signal is provided High potential, the fourth thin film transistor is turned off; the fourth scan signal provides a low potential, the fifth and sixth thin film transistors are turned on; the organic light emitting diode emits light, and a current flowing through the organic light emitting diode
  • the threshold voltage of the first thin film transistor is independent.
  • the voltage of the source of the first thin film transistor is changed to a positive voltage of the power source, and the voltage of the gate of the first thin film transistor is kept unchanged so as to flow through the
  • the current of the organic light emitting diode is independent of the threshold voltage of the first thin film transistor.
  • the source of the third thin film transistor and the source of the fourth thin film transistor are both connected to the initialization voltage;
  • the source of the third thin film transistor and the source of the fourth thin film transistor are both connected to the data voltage during the threshold voltage storage phase and the light emission display phase.
  • the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are each generated by an external timing controller.
  • the first thin film transistor is a driving thin film transistor
  • the sixth thin film transistor is a switching thin film transistor
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all low temperature polysilicon One of a thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are both P Thin film transistor.
  • the OLED pixel driving circuit and the pixel driving method of the present invention By improving the existing pixel driving circuit, the influence of the threshold voltage of the driving thin film transistor on the organic light emitting diode is eliminated, the display uniformity of the panel is improved, and the panel is avoided with the OLED.
  • the aging of the device causes problems such as reduced brightness and reduced luminous efficiency.
  • Figure 1 is a circuit diagram of a conventional 2T1C pixel driving circuit for an OLED
  • FIG. 2 is a circuit diagram of an existing 8T1C pixel driving circuit for an OLED
  • Figure 3 is a circuit diagram of a conventional 7T1C pixel driving circuit for an OLED
  • FIG. 4 is a circuit diagram of an OLED pixel driving circuit of the present invention.
  • FIG. 5 is a timing diagram of an OLED pixel driving circuit of the present invention.
  • step 2 of the OLED pixel driving method of the present invention is a schematic diagram of step 2 of the OLED pixel driving method of the present invention.
  • step 3 of the OLED pixel driving method of the present invention is a schematic diagram of step 3 of the OLED pixel driving method of the present invention.
  • FIG. 8 is a schematic diagram of step 4 of the OLED pixel driving method of the present invention.
  • the OLED is generally used in the prior art.
  • the pixel driving circuit is improved to increase the thin film transistor and the corresponding control signal to compensate the threshold voltage of the driving thin film transistor, so that the current flowing through the organic light emitting diode is independent of the threshold voltage of the driving thin film transistor.
  • an existing OLED pixel driver circuit uses 8T1C.
  • the structure that is, the structure of eight thin film transistors plus one capacitor, including the first thin film transistor T31, the second thin film transistor T32, the third thin film transistor T33, and the fourth thin film transistor T34 , fifth thin film transistor T35 , sixth thin film transistor T36 , seventh thin film transistor T37 , eighth thin film transistor T38 , capacitor C30 and organic light emitting diode D30
  • the specific connection mode of each component is: the gate of the first thin film transistor T31 is connected to the scan signal S2, the source is connected to the reference voltage Vref, the drain is electrically connected to one end of the capacitor C30, and the seventh thin film transistor is connected.
  • the source of the T37, the other end of the capacitor C30 is connected to the source of the third thin film transistor T33 and the gate of the fifth thin film transistor T35, and the drain of the third thin film transistor T33 is connected to the fourth thin film transistor.
  • the source of T34 and the drain of the second thin film transistor T32, and the gates of the third thin film transistor T33 and the fourth thin film transistor T34 are all connected to the scan signal S2.
  • Second thin film transistor T32 The gate is connected to the scan signal S1, and the source of the second thin film transistor T32 is connected to the initial voltage Vini.
  • the drain of the fourth thin film transistor T34 is connected to the drain of the fifth thin film transistor T35 and the organic light emitting diode D30
  • the anode, the cathode of the organic light emitting diode D30 is connected to the negative voltage of the power supply VSS, and the source of the fifth thin film transistor T35 is connected to the drain of the eighth thin film transistor T38 and the seventh thin film transistor T37.
  • the drain of the seventh thin film transistor T37 is connected to the drain of the sixth thin film transistor T36, and the source of the sixth thin film transistor T36 is connected to the power supply positive voltage VDD, and the sixth thin film transistor T36
  • the gate of the gate and the seventh thin film transistor T37 are both connected to the scan signal S3
  • the gate of the eighth thin film transistor T38 is connected to the scan signal S2
  • the source of the eighth thin film transistor T38 is connected to the data voltage. Vdata.
  • the above 8T1C architecture can eliminate the Vth driving the TFT, the TFT used.
  • the large number of panels reduces the aperture ratio of the panel, thereby reducing the display brightness, and more TFTs also cause parasitic capacitance problems.
  • the architecture requires two additional power supplies, Vref and Vini. , resulting in a more complicated hardware structure.
  • FIG. 3 another existing OLED pixel driver circuit uses 7T1C.
  • the structure that is, the structure of seven thin film transistors plus one capacitor, including the first thin film transistor T21, the second thin film transistor T22, the third thin film transistor T23, and the fourth thin film transistor T24
  • the fifth thin film transistor T25, the sixth thin film transistor T26, the seventh thin film transistor T27, the capacitor C20 and the organic light emitting diode D20, the specific components are connected by: capacitor C20 One end is connected to the positive voltage ELVDD, the other end of the capacitor C20 is connected to the second node b, the gate of the seventh thin film transistor T27 is connected to the illuminating signal En, and the source is connected to the positive voltage of the power supply.
  • the drain is connected to the first node a
  • the gate of the first thin film transistor T21 is connected to the second node b
  • the source is connected to the first node a
  • the drain is connected to the third node c
  • the third thin film transistor T23 The gate is connected to the first scan signal Sn
  • the source is connected to the second node b
  • the drain is connected to the third node c
  • the gate of the fourth thin film transistor T24 is connected to the illumination signal En
  • the source is connected to the third node c
  • the drain is connected to the fourth node d
  • the anode of the organic light emitting diode D20 is connected to the fourth node d
  • the cathode of the organic light emitting diode D20 is connected to the negative voltage of the power supply ELVSS
  • the fifth thin film transistor T25 The gate is connected to the second scan signal Sn-1, the drain is connected to the second node b, the source is connected to the power supply negative voltage ELVSS,
  • the above 7T1C compensation architecture can eliminate the Vth of the driving TFT, but the TFT used.
  • the larger number of the panel causes the panel's aperture ratio to decrease, which reduces the display brightness, and a larger number of TFTs cause other parasitic capacitance problems.
  • FIG. 4 is a circuit diagram of an OLED pixel driving circuit of the present invention.
  • the OLED pixel driving circuit of the present invention includes a first thin film transistor T1 and a second thin film transistor T2.
  • the first thin film transistor T1 is a driving thin film transistor
  • the sixth thin film transistor T6 is a switching thin film transistor.
  • the gate of the fifth thin film transistor T5 is connected to the fourth scan signal S4.
  • the source of the fifth thin film transistor T5 is connected to the power supply positive voltage OVDD, and the drain of the fifth thin film transistor T5 is respectively connected to the drain of the third thin film transistor T3 and the first thin film transistor.
  • the source of T1 is connected.
  • the gate of the third thin film transistor T3 is connected to the second scan signal S2, and the third thin film transistor T3
  • the source and the source of the fourth thin film transistor T4 are both connected to the data voltage Vdata or the initialization voltage Vini;
  • the gate of the fourth thin film transistor T4 is connected to the third scan signal S3 .
  • the source of the third thin film transistor T3 and the source of the fourth thin film transistor T4 are both connected to the initialization voltage;
  • the source is connected to the data voltage.
  • the gate of the second thin film transistor T2 is connected to the first scan signal S1, and the second thin film transistor T2
  • the drain is connected to the drain of the first thin film transistor T1, the drain of the fourth thin film transistor T4, and the drain of the sixth thin film transistor T6.
  • the gate of the sixth thin film transistor T6 is connected to the fourth scan signal S4, and the sixth thin film transistor T6
  • the source is connected to the anode of the organic light emitting diode D1, and the cathode of the organic light emitting diode D1 is connected to a power supply negative voltage OVSS.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are each one of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
  • the first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 Both are generated by an external timing controller.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are both P-type thin film transistors.
  • the first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 The phase combination corresponds to an initialization phase, a threshold voltage storage phase, and an illumination display phase.
  • the present invention also provides an OLED pixel driving method, comprising the following steps:
  • the first scan signal S1 is during the initialization phase, i.e., during the t0-t1 period.
  • the third scan signal S3 are both at a low potential, and the second scan signal S2 and the fourth scan signal S4 are at a high potential.
  • the first scan signal S1 provides a low potential, the second thin film transistor T2 is turned on; the third scan signal S3 Providing a low potential, the fourth thin film transistor T4 is turned on; the second scan signal S2 provides a high potential, the third thin film transistor T3 is turned off; the fourth scan signal S4 The high potential is supplied, and the fifth and sixth thin film transistors T5, T6 are turned off.
  • the Vini passes through the T2 and T4.
  • the first scan signal S1 is in the threshold voltage storage phase, i.e., the period t1-t2 And the second scan signal S2 is both low, and the third scan signal S3 and the fourth three signal S4 are both high.
  • the first scan signal S1 provides a low potential, the second thin film transistor T2 is turned on; the second scan signal S2 Providing a low potential, the third thin film transistor T3 is turned on; the third scan signal S3 provides a high potential, the fourth thin film transistor T4 is turned off; the fourth scan signal S4 The high potential is supplied, and the fifth and sixth thin film transistors T5, T6 are turned off.
  • the third thin film transistor T3 Since the third thin film transistor T3 is turned on, Vdata pairs the source of the first thin film transistor T1 through T3 ( The charging is performed such that the voltage Vs of the source of the first thin film transistor T1 is equal to the data voltage Vdata. Since the second thin film transistor T2 is turned on, the fourth and sixth thin film crystals T4, T6 is turned off, g point potential is charged by T2, T1, T3 until the pinch between s point and g point is the threshold voltage of driving thin film transistor (T1) Vth Time is up.
  • Vs-Vg Vth
  • Vg Vdata-Vth.
  • Vdata-Vth the threshold voltage of the first thin film transistor T1.
  • the first scan signal S1 is in the illumination display phase, i.e., during the t2-t3 period.
  • the second scan signal S2 and the third scan signal S3 are both at a high potential, and the fourth scan signal S4 is at a low potential.
  • the first scan signal S1 provides a high potential, the second thin film transistor T2 is turned off; the second scan signal S2 Providing a high potential, the third thin film transistor T3 is turned off; the third scan signal S3 provides a high potential, the fourth thin film transistor T4 is turned off; the fourth scan signal S4 The low potential is supplied, and the fifth and sixth thin film transistors T5, T6 are turned on. Since the fifth and sixth thin film transistors T5 and T6 are turned on, the organic light emitting diode D1 The light is emitted, and the current flowing through the organic light emitting diode D1 is independent of the threshold voltage of the first thin film transistor T1.
  • the g point potential is also the voltage of the gate of the first thin film transistor T1.
  • Vg remains the same, that is, the voltage at the threshold voltage storage stage, Vg is as follows:
  • Vg Vdata -Vth ;
  • the third thin film transistor T3 Since the third thin film transistor T3 is turned off, the fifth thin film transistor T5 is turned on, and OVDD is passed through T5.
  • the source of the first thin film transistor T1 is charged so that the s point potential Vs becomes as follows:
  • Vs OVDD
  • the pinch voltage Vsg between the s point and the g point becomes the following:
  • the current flowing through the organic light emitting diode D1 and the threshold voltage Vth of the driving thin film transistor (T1) can be seen. Irrelevant, the influence of the threshold voltage Vth on the organic light emitting diode is eliminated, thereby improving the uniformity and luminous efficiency of the panel display.
  • the pixel driving circuit and the pixel driving method improve the existing pixel driving circuit, thereby eliminating the influence of the threshold voltage of the driving thin film transistor on the organic light emitting diode, improving the uniformity of the panel display, and avoiding the panel accompanying Problems such as reduced brightness and reduced luminous efficiency of aging of OLED devices.

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Abstract

一种OLED像素驱动电路及像素驱动方法，驱动电路包括：第三薄膜晶体管(T3)的栅极接入第二扫描信号(S2)，第三薄膜晶体管(T3)的源极和第四薄膜晶体管(T4)的源极都接入数据电压(Vdata)或者初始化电压(Vini)；第四薄膜晶体管(T4)的栅极接入第三扫描信号(S3)；第一薄膜晶体管(T1)的栅极分别与第二薄膜晶体管(T2)的源极以及电容(C)的一端连接，电容(C)的另一端接地。

Description

一种 OLED 像素驱动电路及像素驱动方法 技术领域
本发明涉及显示技术领域，特别是涉及一种 OLED 像素驱动电路及像素驱动方法。
背景技术
有机发光二极管（ Organic Light Emitting Display ， OLED ）显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近 180 °视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，成为最有发展潜力的显示装置。
传统的 OLED 像素驱动电路通常为 2T1C ，即两个薄膜晶体管加一个电容的结构，将电压变换为电流。
如图 1 所示，现有的 2T1C 结构的 OLED 像素驱动电路，包括第一薄膜晶体管 T10 、第二薄膜晶体管 T20 、电容 C10 及有机发光二极管 D10 ，所述第一薄膜晶体管 T10 为驱动薄膜晶体管，所述第二薄膜晶体管 T20 为开关薄膜晶体管，所述电容 C10 为存储电容。具体地，所述第二薄膜晶体管 T20 的栅极接入扫描信号 Gate ，源极接入数据信号 Data ，漏极电性连接第一薄膜晶体管 T10 的栅极；所述第一薄膜晶体管 T10 的源极接入电源正电压 OVDD ，漏极电性连接有机发光二极管 D10 的阳极；有机发光二极管 D10 的阴极接入电源负电压 OVSS 。电容 C10 的一端电性连接第一薄膜晶体管 T10 的栅极，另一端电性连接第一薄膜晶体管 T10 的源极。该 2T1C 像素驱动电路在对 OLED 进行驱动时，流过有机发光二极管 D10 的电流满足：
I=k ×（ Vgs-Vth ） 2 ；
其中， I 为流过有机发光二极管 D10 的电流， k 为驱动薄膜晶体管的本征导电因子， Vgs 为第一薄膜晶体管 T10 栅极和源极间的电压差， Vth 为第一薄膜晶体管 T10 的阈值电压，可见流过有机发光二极管 D10 的电流与驱动薄膜晶体管的阈值电压相关。
由于面板制程的不稳定性等因素，使得面板内每个像素驱动电路内的驱动薄膜晶体管的阈值电压产生差别。即使将相等的数据电压施加到各个像素驱动电路内的驱动薄膜晶体管，也会使得流入有机发光二极管的电流不一致，从而影响显示图像质量的均一性。且随着驱动薄膜晶体管的驱动时间的变长，薄膜晶体管的材料会出现老化、变异，导致驱动薄膜晶体管的阈值电压产生漂移，且薄膜晶体管材料的老化程度不同，各驱动薄膜晶体管的阈值电压漂移量也不同，从而出现面板显示不均的现象，同时会使驱动薄膜晶体管的开启电压上升，流入有机发光二极管的电流降低，导致面板亮度降低、发光效率下降等问题。
因此，有必要提供一种 OLED 像素驱动电路及像素驱动方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种 OLED 像素驱动电路及像素驱动方法，能够提高面板显示的均一性、面板的亮度以及发光效率。
技术解决方案
为解决上述技术问题，本发明提供一种 OLED 像素驱动电路，其包括：
第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、电容以及有机发光二极管；
所述第五薄膜晶体管的栅极接入第四扫描信号，所述第五薄膜晶体管的源极接入电源正电压，所述第五薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第一薄膜晶体管的源极连接；
所述第三薄膜晶体管的栅极接入第二扫描信号，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入数据电压或者初始化电压；所述第四薄膜晶体管的栅极接入第三扫描信号；
所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述电容的一端连接，所述电容的另一端接地；
所述第二薄膜晶体管的栅极接入第一扫描信号，所述第二薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极、所述第四薄膜晶体管的漏极以及所述第六薄膜晶体管的漏极连接；
所述第六薄膜晶体管的栅极接入第四扫描信号，所述第六薄膜晶体管的源极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极接入电源负电压；
所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为 P 型薄膜晶体管；所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号均通过外部时序控制器产生。
在本发明的 OLED 像素驱动电路中， 所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
在本发明的 OLED 像素驱动电路中， 所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号相组合，先后对应于初始化阶段、阈值电压存储阶段以及发光显示阶段；
在所述初始化阶段，所述第一扫描信号和所述第三扫描信号都为低电位，所述第二扫描信号和所述第四扫描信号为高电位；
在所述阈值电压存储阶段，所述第一扫描信号和所述第二扫描信号都为低电位，所述第三扫描信号和所述第四三信号都为高电位；
在所述发光显示阶段，所述第一扫描信号、所述第二扫描信号以及所述第三扫描信号都为高电位，所述第四扫描信号为低电位。
在本发明的 OLED 像素驱动电路中， 在所述初始化阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述初始化电压；
在阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述数据电压。
在本发明的 OLED 像素驱动电路中， 所述第一薄膜晶体管为驱动薄膜晶体管，所述第六薄膜晶体管为开关薄膜晶体管。
为解决上述技术问题，本发明提供一种 OLED 像素驱动电路，其包括：
第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、电容以及有机发光二极管；
所述第五薄膜晶体管的栅极接入第四扫描信号，所述第五薄膜晶体管的源极接入电源正电压，所述第五薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第一薄膜晶体管的源极连接；
所述第三薄膜晶体管的栅极接入第二扫描信号，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入数据电压或者初始化电压；所述第四薄膜晶体管的栅极接入第三扫描信号；
所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述电容的一端连接，所述电容的另一端接地；
所述第二薄膜晶体管的栅极接入第一扫描信号，所述第二薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极、所述第四薄膜晶体管的漏极以及所述第六薄膜晶体管的漏极连接；
所述第六薄膜晶体管的栅极接入第四扫描信号，所述第六薄膜晶体管的源极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极接入电源负电压。
在本发明的 OLED 像素驱动电路中， 所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
在本发明的 OLED 像素驱动电路中， 所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为 P 型薄膜晶体管。
在本发明的 OLED 像素驱动电路中， 所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号相组合，先后对应于初始化阶段、阈值电压存储阶段以及发光显示阶段；
在所述初始化阶段，所述第一扫描信号和所述第三扫描信号都为低电位，所述第二扫描信号和所述第四扫描信号为高电位；
在所述阈值电压存储阶段，所述第一扫描信号和所述第二扫描信号都为低电位，所述第三扫描信号和所述第四三信号都为高电位；
在所述发光显示阶段，所述第一扫描信号、所述第二扫描信号以及所述第三扫描信号都为高电位，所述第四扫描信号为低电位。
在本发明的 OLED 像素驱动电路中， 在所述初始化阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述初始化电压；
在阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述数据电压。
在本发明的 OLED 像素驱动电路中， 所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号均通过外部时序控制器产生。
在本发明的 OLED 像素驱动电路中， 所述第一薄膜晶体管为驱动薄膜晶体管，所述第六薄膜晶体管为开关薄膜晶体管。
本发明还提供一种 OLED 像素驱动方法，其包括如下步骤：
提供 OLED 像素驱动电路；
进入初始化阶段；
进入阈值电压存储阶段；以及
进入发光显示阶段；
其中所述 OLED 像素驱动电路包括：
第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、电容以及有机发光二极管；
所述第五薄膜晶体管的栅极接入第四扫描信号，所述第五薄膜晶体管的源极接入电源正电压，所述第五薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第一薄膜晶体管的源极连接；
所述第三薄膜晶体管的栅极接入第二扫描信号，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入数据电压或者初始化电压；所述第四薄膜晶体管的栅极接入第三扫描信号；
所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述电容的一端连接，所述电容的另一端接地；
所述第二薄膜晶体管的栅极接入第一扫描信号，所述第二薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极、所述第四薄膜晶体管的漏极以及所述第六薄膜晶体管的漏极连接；
所述第六薄膜晶体管的栅极接入第四扫描信号，所述第六薄膜晶体管的源极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极接入电源负电压；
在所述初始化阶段，所述第一扫描信号提供低电位，所述第二薄膜晶体管打开；所述第三扫描信号提供低电位，所述第四薄膜晶体管打开；所述第二扫描信号提供高电位，所述第三薄膜晶体管关闭；所述第四扫描信号提供高电位，所述第五、第六薄膜晶体管关闭；所述第一薄膜晶体管的栅极的电压等于所述初始电压；
在阈值电压存储阶段，所述第一扫描信号提供低电位，所述第二薄膜晶体管打开；所述第二扫描信号提供低电位，所述第三薄膜晶体管打开；所述第三扫描信号提供高电位，所述第四薄膜晶体管关闭；所述第四扫描信号提供高电位，所述第五、第六薄膜晶体管关闭；所述第一薄膜晶体管的源极的电压等于所述数据电压，所述第一薄膜晶体管的栅极的电压变化至 Vdata-Vth ，其中 Vdata 为数据电压， Vth 为所述第一薄膜晶体管的阈值电压；
在所述发光显示阶段，所述第一扫描信号提供高电位，所述第二薄膜晶体管关闭；所述第二扫描信号提供高电位，所述第三薄膜晶体管关闭；所述第三扫描信号提供高电位，所述第四薄膜晶体管关闭；所述第四扫描信号提供低电位，所述第五、第六薄膜晶体管打开；所述有机发光二极管发光，且流经所述有机发光二极管的电流与所述第一薄膜晶体管的阈值电压无关。
在本发明的 OLED 像素驱动方法中，在所述发光显示阶段，所述第一薄膜晶体管的源极的电压变化至电源正电压，所述第一薄膜晶体管的栅极的电压保持不变，以使流经所述有机发光二极管的电流与所述第一薄膜晶体管的阈值电压无关。
在本发明的 OLED 像素驱动方法中，在所述初始化阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述初始化电压；
在所述阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述数据电压。
在本发明的 OLED 像素驱动方法中，所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号均通过外部时序控制器产生。
在本发明的 OLED 像素驱动方法中，所述第一薄膜晶体管为驱动薄膜晶体管，所述第六薄膜晶体管为开关薄膜晶体管。
在本发明的 OLED 像素驱动方法中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
在本发明的 OLED 像素驱动方法中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为 P 型薄膜晶体管。
 有益效果
本发明的 OLED 像素驱动电路及像素驱动方法， 通过对现有的像素驱动电路进行改进，从而消除了驱动薄膜晶体管的阈值电压对有机发光二极管的影响，提高了面板显示均匀性，此外还避免了面板随 OLED 器件的老化而出现的亮度降低、发光效率下降等问题。
附图说明
图 1 为现有用于 OLED 的 2T1C 像素驱动电路的电路图；
图 2 为现有用于 OLED 的 8T1C 像素驱动电路的电路图；
图 3 为现有用于 OLED 的 7T1C 像素驱动电路的电路图；
图 4 为本发明的 OLED 像素驱动电路的电路图；
图 5 为本发明的 OLED 像素驱动电路的时序图；
图 6 为本发明的 OLED 像素驱动方法的步骤 2 的示意图；
图 7 为本发明的 OLED 像素驱动方法的步骤 3 的示意图；
图 8 为本发明的 OLED 像素驱动方法的步骤 4 的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
针对驱动薄膜晶体管阈值电压漂移的问题，现有技术中一般会对 OLED 像素驱动电路进行改进，增加薄膜晶体管及相应的控制信号，以对驱动薄膜晶体管的阈值电压进行补偿，使有机发光二极管在发光时，流过其的电流与驱动薄膜晶体管的阈值电压无关。
如图 2 所示，现有的一种 OLED 像素驱动电路采用 8T1C 的结构，也即八个薄膜晶体管加一个电容的结构，包括第一薄膜晶体管 T31 、第二薄膜晶体管 T32 、第三薄膜晶体管 T33 、第四薄膜晶体管 T34 、第五薄膜晶体管 T35 、第六薄膜晶体管 T36 、第七薄膜晶体管 T37 、第八薄膜晶体管 T38 、电容 C30 及有机发光二极管 D30 ，具体各元件的连接方式为：第一薄膜晶体管 T31 的栅极接入扫描信号 S2 ，源极接入参考电压 Vref ，漏极电性连接电容 C30 的一端以及第七薄膜晶体管 T37 的源极，电容 C30 的另一端与第三薄膜晶体管 T33 的源极以及第五薄膜晶体管 T35 的栅极连接，第三薄膜晶体管 T33 的漏极连接第四薄膜晶体管 T34 的源极以及第二薄膜晶体管 T32 的漏极，第三薄膜晶体管 T33 和第四薄膜晶体管 T34 的栅极都接入扫描信号 S2 。第二薄膜晶体管 T32 的栅极接入扫描信号 S1 ，第二薄膜晶体管 T32 的源极接入初始电压 Vini 。
第四薄膜晶体管 T34 的漏极连接第五薄膜晶体管 T35 的漏极和有机发光二极管 D30 的阳极，有机发光二极管 D30 的阴极接入电源负电压 VSS ，第五薄膜晶体管 T35 的源极连接第八薄膜晶体管 T38 的漏极以及第七薄膜晶体管 T37 的漏极，第七薄膜晶体管 T37 的源极与第六薄膜晶体管 T36 的漏极连接，第六薄膜晶体管 T36 的源极接入电源正电压 VDD ，第六薄膜晶体管 T36 的栅极和第七薄膜晶体管 T37 的栅极都接入扫描信号 S3 ，第八薄膜晶体管 T38 的栅极接入扫描信号 S2 ，第八薄膜晶体管 T38 的源极接入数据电压 Vdata 。
上述 8T1C 的架构虽然可以消除驱动 TFT 的 Vth ，但所用 TFT 的数量较多，会降低面板的开口率，从而降低显示亮度，且较多的 TFT 也会产生寄生电容等问题。另一方面，该架构需要两个额外电源 Vref 和 Vini ，导致硬件结构较复杂。
如图 3 所示，现有的另一种 OLED 像素驱动电路采用 7T1C 的结构，也即七个薄膜晶体管加一个电容的结构，包括第一薄膜晶体管 T21 、第二薄膜晶体管 T22 、第三薄膜晶体管 T23 、第四薄膜晶体管 T24 、第五薄膜晶体管 T25 、第六薄膜晶体管 T26 、第七薄膜晶体管 T27 、电容 C20 及有机发光二极管 D20 ，具体各元件的连接方式为：电容 C20 的一端接入电源正电压 ELVDD ， 电容 C20 的另一端连接第二节点 b ，第七薄膜晶体管 T27 的栅极接入发光信号 En ，源极接入电源正电压 ELVDD ，漏极连接第一节点 a ，第一薄膜晶体管 T21 的栅极接入第二节点 b ，源极连接第一节点 a ，漏极连接第三节点 c ，第三薄膜晶体管 T23 的栅极接入第一扫描信号 Sn ，源极连接第二节点 b ，漏极连接第三节点 c ，第四薄膜晶体管 T24 的栅极接入发光信号 En ，源极连接第三节点 c ，漏极连接第四节点 d ，有机发光二极管 D20 的阳极连接第四节点 d ，有机发光二极管 D20 的阴极接入电源负电压 ELVSS ，第五薄膜晶体管 T25 的栅极接入第二扫描信号 Sn-1 ，漏极连接第二节点 b ，源极连接电源负电压 ELVSS ，第六薄膜晶体管 T26 的栅极接入第二扫描信号 Sn-1 ，漏极连接第四节点 d ，源极连接电源负电压 ELVSS ，第二薄膜晶体管 T22 的栅极接入第一扫描信号 Sn ，源极接入输入数据信号 Dm ，漏极连接第一节点 a 。
上述 7T1C 的补偿架构虽然可以消除驱动 TFT 的 Vth ，但所用 TFT 的数量较多，会导致面板的开口率下降，从而降低了显示亮度，且较多数量的 TFT 会产生其他寄生电容等问题。
请参照图 4 ，图 4 为本发明的 OLED 像素驱动电路的电路图。
如图 4 所示，本发明的 OLED 像素驱动电路包括 第一薄膜晶体管 T1 、第二薄膜晶体管 T2 、第三薄膜晶体管 T3 、第四薄膜晶体管 T4 、第五薄膜晶体管 T5 、第六薄膜晶体管 T6 、电容 C 以及有机发光二极管 D1 。其中所述第一薄膜晶体管 T1 为驱动薄膜晶体管，所述第六薄膜晶体管 T6 为开关薄膜晶体管。
具体各元件的连接方式如下：所述第五薄膜晶体管 T5 的栅极接入第四扫描信号 S4 ，所述第五薄膜晶体管 T5 的源极接入电源正电压 OVDD ，所述第五薄膜晶体管 T5 的漏极分别与所述第三薄膜晶体管 T3 的漏极以及所述第一薄膜晶体管 T1 的源极连接。
所述第三薄膜晶体管 T3 的栅极接入第二扫描信号 S2 ，所述第三薄膜晶体管 T3 的源极和所述第四薄膜晶体管 T4 的源极都接入数据电压 Vdata 或者初始化电压 Vini ；所述第四薄膜晶体管 T4 的栅极接入第三扫描信号 S3 。其中在所述初始化阶段，所述第三薄膜晶体管 T3 的源极和所述第四薄膜晶体管 T4 的源极都接入所述初始化电压；
在所述阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管 T3 的源极和所述第四薄膜晶体管 T4 的源极都接入所述数据电压。
所述第一薄膜晶体管 T1 的栅极分别与所述第二薄膜晶体管 T2 的源极以及所述电容 C 的一端连接，所述电容 C 的另一端接地。
所述第二薄膜晶体管 T2 的栅极接入第一扫描信号 S1 ，所述第二薄膜晶体管 T2 的漏极与所述第一薄膜晶体管 T1 的漏极、所述第四薄膜晶体管 T4 的漏极以及所述第六薄膜晶体管 T6 的漏极连接。
所述第六薄膜晶体管 T6 的栅极接入第四扫描信号 S4 ，所述第六薄膜晶体管 T6 的源极与所述有机发光二极管 D1 的阳极连接，所述有机发光二极管 D1 的阴极接入电源负电压 OVSS 。
所述第一薄膜晶体管 T1 、第二薄膜晶体管 T2 、第三薄膜晶体管 T3 、第四薄膜晶体管 T4 、第五薄膜晶体管 T5 以及第六薄膜晶体管 T6 均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
所述第一扫描信号 S1 、第二扫描信号 S2 、第三扫描信号 S3 以及第四扫描信号 S4 均通过外部时序控制器产生。
所述第一薄膜晶体管 T1 、第二薄膜晶体管 T2 、第三薄膜晶体管 T3 、第四薄膜晶体管 T4 、第五薄膜晶体管 T5 以及第六薄膜晶体管 T6 均为 P 型薄膜晶体管。
所述第一扫描信号 S1 、第二扫描信号 S2 、第三扫描信号 S3 以及第四扫描信号 S4 相组合，先后对应于一初始化阶段、一阈值电压存储阶段、及一发光显示阶段。
基于上述 OLED 像素驱动电路，本发明还提供一种 OLED 像素驱动方法，包括如下步骤：
S101 、提供一 OLED 像素驱动电路。
具体请参阅图 4 和上文，在此不再赘述。
S102 、进入初始化阶段。
结合图 5 和 6 ，在所述初始化阶段也即 t0-t1 时段，所述第一扫描信号 S1 和所述第三扫描信号 S3 都为低电位，所述第二扫描信号 S2 和所述第四扫描信号 S4 为高电位。
所述第一扫描信号 S1 提供低电位，所述第二薄膜晶体管 T2 打开；所述第三扫描信号 S3 提供低电位，所述第四薄膜晶体管 T4 打开；所述第二扫描信号 S2 提供高电位，所述第三薄膜晶体管 T3 关闭；所述第四扫描信号 S4 提供高电位，所述第五、第六薄膜晶体管 T5 、 T6 关闭。
由于所述第二、第四薄膜晶体管 T2 、 T4 打开， Vini 通过 T2 、 T4 对所述第一薄膜晶体管 T1 的栅极（ g 点）进行充电，使得所述第一薄膜晶体管 T1 的栅极的电压 Vg 等于初始电压 Vini ，数据线输出的初始电压 Vini 满足下式：
Vini<Vdata-Vth ；
由于第六薄膜晶体管 T6 关闭，因此有机发光二极管 D1 不发光，此阶段完成对 g 点电位的初始化。
S103 、进入阈值电压存储阶段。
结合图 5 和 7 ，在该阈值电压存储阶段也即 t1-t2 时段，所述第一扫描信号 S1 和所述第二扫描信号 S2 都为低电位，所述第三扫描信号 S3 和所述第四三信号 S4 都为高电位。
所述第一扫描信号 S1 提供低电位，所述第二薄膜晶体管 T2 打开；所述第二扫描信号 S2 提供低电位，所述第三薄膜晶体管 T3 打开；所述第三扫描信号 S3 提供高电位，所述第四薄膜晶体管 T4 关闭；所述第四扫描信号 S4 提供高电位，所述第五、第六薄膜晶体管 T5 、 T6 关闭。
由于所述第三薄膜晶体管 T3 打开， Vdata 通过 T3 对所述第一薄膜晶体管 T1 的源极（ s 点）进行充电，使得所述第一薄膜晶体管 T1 的源极的电压 Vs 等于数据电压 Vdata 。由于第二薄膜晶体管 T2 开启，第四、六薄膜晶体 T4 、 T6 关闭， g 点电位通过 T2 、 T1 、 T3 进行充电，直到 s 点与 g 点的之间的夹压为驱动薄膜晶体管 (T1) 的阈值电压 Vth 时截止。
由于 Vs 与 Vg 之间满足下式：
Vs-Vg=Vth ；
其中 Vs=Vdata ；
结合上式，则有 Vg 为：
Vg=Vdata-Vth 。
也即所述第一薄膜晶体管 T1 的栅极的电压变化至 Vdata-Vth ，其中 Vdata 为数据电压， Vth 为所述第一薄膜晶体管 T1 的阈值电压。
由于第六薄膜晶体管 T6 关闭，因此有机发光二极管 D1 不发光。此阶段完成对 g 点电位的存储。
S104 、进入发光显示阶段。
结合图 5 和 8 ，在发光显示阶段也即 t2-t3 时段，所述第一扫描信号 S1 、所述第二扫描信号 S2 以及所述第三扫描信号 S3 都为高电位，所述第四扫描信号 S4 为低电位。
所述第一扫描信号 S1 提供高电位，所述第二薄膜晶体管 T2 关闭；所述第二扫描信号 S2 提供高电位，所述第三薄膜晶体管 T3 关闭；所述第三扫描信号 S3 提供高电位，所述第四薄膜晶体管 T4 关闭；所述第四扫描信号 S4 提供低电位，所述第五、第六薄膜晶体管 T5 、 T6 打开。由于第五、六薄膜晶体管 T5 、 T6 打开，所述有机发光二极管 D1 发光，且流经所述有机发光二极管 D1 的电流与所述第一薄膜晶体管 T1 的阈值电压无关。
具体地，由于第二薄膜晶体管 T2 关闭， g 点电位也即所述第一薄膜晶体管 T1 的栅极的电压 Vg 保持不变，也即与阈值电压存储阶段时的电压一致， Vg 如下：
Vg=Vdata -Vth ；
由于第三薄膜晶体管 T3 关闭，第五薄膜晶体管 T5 打开， OVDD 通过 T5 对第一薄膜晶体管 T1 的源极进行充电，使得 s 点电位 Vs 变为如下：
Vs=OVDD ；
s 点与 g 点之间的夹压 Vsg ，此时变为如下：
Vsg=Vs-Vg=OVDD-(Vdata-Vth)=OVDD-Vdata+Vth ；
由于，流过有机发光二极管 D1 的电流满足：
Ｉ =k(Vsg-Vth)2
结合上面的公式，得到最终流过有机发光二极管 D1 的电流 为：
I=k(OVDD-Vdata)2
由此可见，流过有机发光二极管 D1 的电流与驱动薄膜晶体管 (T1) 的阈值电压 Vth 无关，消除了阈值电压 Vth 对有机发光二极管的影响，从而提高了面板显示的均匀性和发光效率。
本发明的 OLED 像素驱动电路及像素驱动方法，通过对现有的像素驱动电路进行改进，从而消除了驱动薄膜晶体管的阈值电压对有机发光二极管的影响，提高了面板显示均匀性，此外还避免了面板随 OLED 器件的老化而出现的亮度降低、发光效率下降等问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种 OLED 像素驱动电路，其包括：
    第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、电容以及有机发光二极管；
    所述第五薄膜晶体管的栅极接入第四扫描信号，所述第五薄膜晶体管的源极接入电源正电压，所述第五薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第一薄膜晶体管的源极连接；
    所述第三薄膜晶体管的栅极接入第二扫描信号，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入数据电压或者初始化电压；所述第四薄膜晶体管的栅极接入第三扫描信号；
    所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述电容的一端连接，所述电容的另一端接地；
    所述第二薄膜晶体管的栅极接入第一扫描信号，所述第二薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极、所述第四薄膜晶体管的漏极以及所述第六薄膜晶体管的漏极连接；
    所述第六薄膜晶体管的栅极接入第四扫描信号，所述第六薄膜晶体管的源极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极接入电源负电压；
    所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为 P 型薄膜晶体管；所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号均通过外部时序控制器产生。
  2. 如权利要求 1 所述的 OLED 像素驱动电路，其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
  3. 如权利要求 1 所述的 OLED 像素驱动电路，其中所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号相组合，先后对应于初始化阶段、阈值电压存储阶段以及发光显示阶段；
    在所述初始化阶段，所述第一扫描信号和所述第三扫描信号都为低电位，所述第二扫描信号和所述第四扫描信号为高电位；
    在所述阈值电压存储阶段，所述第一扫描信号和所述第二扫描信号都为低电位，所述第三扫描信号和所述第四三信号都为高电位；
    在所述发光显示阶段，所述第一扫描信号、所述第二扫描信号以及所述第三扫描信号都为高电位，所述第四扫描信号为低电位。
  4. 如权利要求 3 所述的 OLED 像素驱动电路，其中在所述初始化阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述初始化电压；
    在阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述数据电压。
  5. 如权利要求 1 所述的 OLED 像素驱动电路，其中所述第一薄膜晶体管为驱动薄膜晶体管，所述第六薄膜晶体管为开关薄膜晶体管。
  6. 一种 OLED 像素驱动电路，其包括：
    第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、电容以及有机发光二极管；
    所述第五薄膜晶体管的栅极接入第四扫描信号，所述第五薄膜晶体管的源极接入电源正电压，所述第五薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第一薄膜晶体管的源极连接；
    所述第三薄膜晶体管的栅极接入第二扫描信号，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入数据电压或者初始化电压；所述第四薄膜晶体管的栅极接入第三扫描信号；
    所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述电容的一端连接，所述电容的另一端接地；
    所述第二薄膜晶体管的栅极接入第一扫描信号，所述第二薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极、所述第四薄膜晶体管的漏极以及所述第六薄膜晶体管的漏极连接；
    所述第六薄膜晶体管的栅极接入第四扫描信号，所述第六薄膜晶体管的源极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极接入电源负电压。
  7. 如权利要求 6 所述的 OLED 像素驱动电路，其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
  8. 如权利要求 6 所述的 OLED 像素驱动电路，其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为 P 型薄膜晶体管。
  9. 如权利要求 8 所述的 OLED 像素驱动电路，其中所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号相组合，先后对应于初始化阶段、阈值电压存储阶段以及发光显示阶段；
    在所述初始化阶段，所述第一扫描信号和所述第三扫描信号都为低电位，所述第二扫描信号和所述第四扫描信号为高电位；
    在所述阈值电压存储阶段，所述第一扫描信号和所述第二扫描信号都为低电位，所述第三扫描信号和所述第四三信号都为高电位；
    在所述发光显示阶段，所述第一扫描信号、所述第二扫描信号以及所述第三扫描信号都为高电位，所述第四扫描信号为低电位。
  10. 如权利要求 9 所述的 OLED 像素驱动电路，其中在所述初始化阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述初始化电压；
    在阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述数据电压。
  11. 如权利要求 6 所述的 OLED 像素驱动电路，其中所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号均通过外部时序控制器产生。
  12. 如权利要求 6 所述的 OLED 像素驱动电路，其中所述第一薄膜晶体管为驱动薄膜晶体管，所述第六薄膜晶体管为开关薄膜晶体管。
  13. 一种 OLED 像素驱动方法，其包括如下步骤：
    提供 OLED 像素驱动电路；
    进入初始化阶段；
    进入阈值电压存储阶段；以及
    进入发光显示阶段；
    其中所述 OLED 像素驱动电路包括：
    第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、电容以及有机发光二极管；
    所述第五薄膜晶体管的栅极接入第四扫描信号，所述第五薄膜晶体管的源极接入电源正电压，所述第五薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第一薄膜晶体管的源极连接；
    所述第三薄膜晶体管的栅极接入第二扫描信号，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入数据电压或者初始化电压；所述第四薄膜晶体管的栅极接入第三扫描信号；
    所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述电容的一端连接，所述电容的另一端接地；
    所述第二薄膜晶体管的栅极接入第一扫描信号，所述第二薄膜晶体管的漏极分别与所述第一薄膜晶体管的漏极、所述第四薄膜晶体管的漏极以及所述第六薄膜晶体管的漏极连接；
    所述第六薄膜晶体管的栅极接入第四扫描信号，所述第六薄膜晶体管的源极与所述有机发光二极管的阳极连接，所述有机发光二极管的阴极接入电源负电压；
    在所述初始化阶段，所述第一扫描信号提供低电位，所述第二薄膜晶体管打开；所述第三扫描信号提供低电位，所述第四薄膜晶体管打开；所述第二扫描信号提供高电位，所述第三薄膜晶体管关闭；所述第四扫描信号提供高电位，所述第五、第六薄膜晶体管关闭；所述第一薄膜晶体管的栅极的电压等于所述初始电压；
    在阈值电压存储阶段，所述第一扫描信号提供低电位，所述第二薄膜晶体管打开；所述第二扫描信号提供低电位，所述第三薄膜晶体管打开；所述第三扫描信号提供高电位，所述第四薄膜晶体管关闭；所述第四扫描信号提供高电位，所述第五、第六薄膜晶体管关闭；所述第一薄膜晶体管的源极的电压等于所述数据电压，所述第一薄膜晶体管的栅极的电压变化至 Vdata-Vth ，其中 Vdata 为数据电压， Vth 为所述第一薄膜晶体管的阈值电压；
    在所述发光显示阶段，所述第一扫描信号提供高电位，所述第二薄膜晶体管关闭；所述第二扫描信号提供高电位，所述第三薄膜晶体管关闭；所述第三扫描信号提供高电位，所述第四薄膜晶体管关闭；所述第四扫描信号提供低电位，所述第五、第六薄膜晶体管打开；所述有机发光二极管发光，且流经所述有机发光二极管的电流与所述第一薄膜晶体管的阈值电压无关。
  14. 如权利要求 13 所述的 OLED 像素驱动方法，其中在所述发光显示阶段，所述第一薄膜晶体管的源极的电压变化至电源正电压，所述第一薄膜晶体管的栅极的电压保持不变，以使流经所述有机发光二极管的电流与所述第一薄膜晶体管的阈值电压无关。
  15. 如权利要求 13 所述的 OLED 像素驱动方法，其中 在所述初始化阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述初始化电压；
    在所述阈值电压存储阶段和所述发光显示阶段，所述第三薄膜晶体管的源极和所述第四薄膜晶体管的源极都接入所述数据电压。
  16. 如权利要求 13 所述的 OLED 像素驱动方法，其中所述第一扫描信号、所述第二扫描信号、所述第三扫描信号以及所述第四扫描信号均通过外部时序控制器产生。
  17. 如权利要求 13 所述的 OLED 像素驱动方法，其中所述第一薄膜晶体管为驱动薄膜晶体管，所述第六薄膜晶体管为开关薄膜晶体管。
  18. 如权利要求 13 所述的 OLED 像素驱动方法，其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管以及非晶硅薄膜晶体管中的一种。
  19. 如权利要求 13 所述的 OLED 像素驱动方法，其中所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为 P 型薄膜晶体管。
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