WO2019026394A1 - Transistor production method and transistor - Google Patents

Transistor production method and transistor Download PDF

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Publication number
WO2019026394A1
WO2019026394A1 PCT/JP2018/019626 JP2018019626W WO2019026394A1 WO 2019026394 A1 WO2019026394 A1 WO 2019026394A1 JP 2018019626 W JP2018019626 W JP 2018019626W WO 2019026394 A1 WO2019026394 A1 WO 2019026394A1
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transistor
semiconductor layer
film
substrate
manufacturing
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PCT/JP2018/019626
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French (fr)
Japanese (ja)
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誠 中積
康孝 西
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株式会社ニコン
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to a method of manufacturing a transistor, and a transistor.
  • the present invention claims priority to Japanese Patent Application No. 2017-148749 filed on Aug. 1, 2017, and the contents described in the application for designated countries permitted to be incorporated by reference to the literature are: Incorporated herein by reference.
  • amorphous oxides such as oxides containing In, Ga and Zn (IGZO; In-Ga-Zn-O) are used (Patent Reference 1). Such semiconductor devices are required to further improve their semiconductor characteristics.
  • a first aspect according to the present invention is a method of manufacturing a transistor including a substrate, a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, and a target including a raw material constituting the semiconductor layer. It is a manufacturing method of a transistor including the semiconductor layer formation process of forming a semiconductor layer by irradiating and carrying out helicon plasma and forming a semiconductor layer.
  • a second aspect according to the present invention is a transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, wherein the substrate contains a resin material, and the film density of the semiconductor layer is 6.1 or less. Is a transistor.
  • FIG. 7 is a view showing the measurement results of the ⁇ -PCD method of Example 1.
  • FIG. 7 is a view showing the measurement results of the ⁇ -PCD method of Example 2.
  • FIG. 7 is a view showing the measurement results of the ⁇ -PCD method of Comparative Example 1. It is the figure which plotted the relationship between the film-forming pressure and DC bias voltage in the film-forming process about the case where a helical antenna is used, and the case where a helical antenna is not used.
  • FIG. 6 is a graph showing measurement results of transfer characteristics of the transistors of Example 1 and Comparative Example 1;
  • FIG. 1 is a cross-sectional view showing an example of a transistor obtained by the method of manufacturing a transistor according to the present embodiment.
  • the method of manufacturing the transistor according to the present embodiment is a method of manufacturing the transistor 1 including the substrate 10, the insulating layer 11, the gate electrode 12, the source electrode 14, the drain electrode 16, and the semiconductor layer 18. It is a manufacturing method including the semiconductor layer formation process of forming a semiconductor layer by irradiating and helicon plasma with respect to the target containing the raw material which comprises a semiconductor layer, and sputtering. First, the structure of the transistor is described.
  • the substrate 10 As a material of the substrate 10, known substrate materials such as glass and resin material can be used, and for example, silicon dioxide (SiO 2 ), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES) And polyether imide, polyether ether ketone, polyphenylene sulfide, polyarylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP) and the like. Further, the substrate 10 may be composed of a plurality of layers such as two layers or three layers, and an inorganic material and an organic material may be used in combination.
  • the insulating layer 11 is provided to cover the gate electrode 12.
  • the insulating layer 11 may be formed using either an inorganic material or an organic material as long as it can electrically insulate the gate electrode 12 from the source electrode 14 and the drain electrode 16.
  • SiO 2 , SiON, SiN x , Al 2 O 3 , MgO, MgF 2 or the like may be used as the inorganic material
  • PMMA polymethyl methacrylate resin
  • epoxy-based photocurable resin may be used as the organic material.
  • para-xylylene polymers, polyimides and the like may be used.
  • the insulating layer 11 may be composed of a plurality of layers such as two layers or three layers, and an inorganic material and an organic material may be used in combination.
  • the insulating layer 11 may be formed in a desired pattern shape.
  • the insulating layer 11 having a desired pattern shape may be obtained by irradiating a pattern light using a photocurable resin as a material of the insulating layer 11, or after forming the insulating layer on one surface, a photolithography process is used.
  • the desired pattern shape may be used.
  • the insulating layer 11 may be obtained by depositing a material through a metal mask having an opening corresponding to a desired pattern.
  • the material of the gate electrode 12 examples include Cu, Ti, Al, Au, Ag, Mo, Pt, ITO (indium tin oxide), IZO (indium zinc oxide), carbon nanotubes, fullerene, and the like.
  • the gate electrode 12 is formed using a known method, and may have a desired pattern shape.
  • the catalyst for electroless plating may be disposed in a desired pattern shape and may be formed by performing electroless plating, or after a metal layer is formed on one surface, the desired pattern shape may be formed using a photolithography process. Good.
  • the gate electrode 12 may be obtained by depositing a gate electrode material through a metal mask having an opening corresponding to a desired pattern.
  • the same material as the material of the gate electrode 12 can be used.
  • the materials of the source electrode 14 and the drain electrode 16 may be the same or different.
  • the source electrode 14 and the drain electrode 16 are formed by using a known method, and may be similar to the method of forming the gate electrode 12.
  • Examples of the material of the semiconductor layer 18 include inorganic semiconductors of zinc oxide (ZnO), oxides containing In, Ga, and Zn (InGaZnO 4 ; IGZO, etc.).
  • ZnO zinc oxide
  • InGaZnO 4 IGZO
  • IGZO InGaZnO 4 is preferable from the viewpoint of having high electric mobility and on / off ratio and being excellent in environmental resistance.
  • single simultaneous sputtering may be employed, which targets one type of material, or cosputtering, which targets multiple types of materials.
  • a sintered oxide of InGaZnO 4 may be used as a target (single simultaneous sputtering).
  • the composition ratio may be controlled to be an IGZO film having a desired composition by simultaneously using three or more of In 2 O 3 , Ga 2 O 3 , and ZnO at the same time (multiple co-sputtering) , Cosputter).
  • the semiconductor layer 18 is formed by irradiating a predetermined target with helicon plasma and sputtering.
  • an antenna helical antenna
  • the rotational return of the peripheral portion of the plasma can be large, and the rotational return of the central portion can be reduced.
  • film formation conditions such as temperature and pressure can be relaxed.
  • a transistor such as a thin film transistor (TFT) can be suitably manufactured.
  • FIG. 2 is a simplified configuration diagram showing an example of a film forming apparatus used for the manufacturing method according to the present embodiment.
  • the film forming apparatus 2 is a film forming apparatus that irradiates helicon plasma, includes a backing plate 22 and a stage 24 on an application table 20, and a helical antenna 26 is provided above the backing plate 22 and the stage 24.
  • the material M of the semiconductor layer 18 is placed on the stage 24 and plasma irradiation is performed on the material M.
  • the material M can be deposited on the surface of the substrate 3 disposed above the helical antenna 26 (see deposition direction F1), and the semiconductor layer 18 can be formed.
  • the step of irradiating and sputtering the helicon plasma can be performed in an atmosphere of an inert gas (argon, helium, neon, krypton, xenon, etc.) or a reactive gas (nitrogen gas, oxygen gas, etc.).
  • an inert gas argon, helium, neon, krypton, xenon, etc.
  • a reactive gas nitrogen gas, oxygen gas, etc.
  • plasma irradiation can be performed, for example, by disposing the film forming apparatus 2 in a chamber and setting it as a mixed gas atmosphere of an inert gas and a reactive gas.
  • a high density, low defects, high density semiconductor layer 18 can be formed by sputtering by irradiation with a helicon plasma. Then, the transistor obtained by the manufacturing method according to the present embodiment can exhibit high mobility and high stability transistor characteristics.
  • an oxide semiconductor such as IGZO has high mobility while having an amorphous structure. Therefore, the transistor having the semiconductor layer 18 is expected to be mounted on a display of a smartphone, a tablet, or the like as having excellent transistor characteristics.
  • high temperature exceeding 200 ° C. is required, and high carrier mobility and stability can not be obtained unless the semiconductor layer can be heated to cause slight crystallization. . From this point of view, post-annealing needs to be performed as a post-process after film formation.
  • the substrate 10 in order to provide the transistor with high flexibility, it has been attempted to use a resin material (sometimes called a resin film or a resin sheet) such as PET or PEN as the substrate 10.
  • a resin material sometimes called a resin film or a resin sheet
  • PET or PEN a resin material
  • the film formation temperature of the semiconductor layer 18 is a high temperature exceeding 200 ° C., the temperature exceeds the softening point of the normal resin material, so there is a problem that the substrate 10 can not withstand the heat.
  • the sputtering is performed by irradiating the helicon plasma, so that the substrate 10 including the resin material layer has high mobility and high stability without raising the film forming temperature to a high temperature.
  • the semiconductor layer 18 can be formed.
  • As a suitable film-forming temperature it can be below the softening point of the board
  • the softening point referred to here is a temperature at which the resin softens and starts deformation, and can be measured by a test method according to JIS K7207 (method A).
  • the fact that film formation is possible at a low temperature below the softening point means that the semiconductor layer 18 such as a-IGZO can be formed on the substrate 10 including the resin material layer. It can be said. If the substrate 10 is a film substrate having a high degree of flexibility, the transistor itself can also be provided with a high degree of flexibility.
  • the substrate 10 is a film substrate, it is possible to adopt a roll-to-roll method or a roll-to-sheet method in which a film is continuously formed as a roll. In addition, high efficiency, simplification, and yield improvement of the manufacturing process can be expected.
  • the specific film forming temperature is preferably 200 ° C. or less, more preferably 150 ° C. or less, and still more preferably 120 ° C. or less.
  • the film forming temperature can be made equal to or lower than the softening point of a wide variety of resins, so a wide range of resins can be adopted as the material of the substrate 10.
  • the manufacturing method of the present embodiment it is possible to adopt an aspect in which the post-annealing step as post-processing is not performed (that is, the heating step is not performed after the semiconductor layer forming step).
  • plasma can be locally confined by using a helical plasma ring.
  • stable plasma can be generated even at low pressure, and film formation at low pressure becomes possible.
  • the specific film forming pressure is preferably 0.1 Pa or less, more preferably 0.07 Pa or less.
  • the lower limit of the film forming pressure is not necessarily defined, but can be 0.05 Pa or more.
  • the semiconductor layer 18 can have a high film density.
  • the film density of the semiconductor layer 18 is preferably 6.1 or more, more preferably 6.2 or more, and still more preferably 6.3 or more.
  • high electron mobility can be expected because the s orbital contributing to conduction has a strong bond.
  • the stability is also improved, which is suitable as a transistor.
  • the roll-to-roll system refers to a film forming method in which a roll-shaped film substrate (sometimes called a sheet substrate) is unwound and continuously formed into a film, and then wound into a roll again.
  • the roll-to-sheet method refers to a film forming method in which a roll-shaped film substrate is unrolled to continuously form a film, and the film is cut to form a sheet.
  • FIG. 3 is a schematic view showing an example of the manufacturing method according to the present embodiment.
  • the manufacturing apparatus 4 is a roll-to-roll type manufacturing apparatus.
  • the substrate 3 is a resin film containing a resin material.
  • the substrate 3 is fed from the unwinding roll 40 in the direction of the arrow F 2, and is conveyed to the drum 44 through the guide roll 42.
  • the step of irradiating the helicon plasma by the above-described film forming apparatus 2 and performing sputtering is performed to form a film.
  • the sheet is conveyed to the take-up roll 48 through the guide roll 46 and taken up in a roll.
  • the drum 44 not only the semiconductor formation process described above, but also a pretreatment process such as cleaning of a substrate by ion irradiation, UV irradiation, or microwave irradiation, or impurities by heating a thin film after film formation.
  • Post-processing steps such as annealing for removal and film density improvement can be further performed.
  • the roll-to-roll deposition can be expected to have effects such as high throughput, high quality, and low cost of the process as a method for mass production of flexible devices including displays and the like.
  • the transistor obtained according to this embodiment can be used as a thin film transistor or the like for components of various electronic devices.
  • it can be suitably used as a component of a flexible device such as a display of various electronic products.
  • a multi-cathode sputtering apparatus film forming apparatus 2 including the helical antenna 26 shown in FIG. 2 was used.
  • a direct current magnetic field was generated by a direct current magnetic field generating coil, and a high frequency electric field (RF: 13.56 MHz) was applied to the helical antenna 26.
  • RF radio frequency
  • the helicon wave is excited to generate plasma, and the target is sputtered to form an oxide thin film (semiconductor layer 1a) having a thickness of 85 nm on the substrate.
  • Sputtering was performed under the following conditions. In addition, after the film formation, the annealing treatment was not performed, and an as-deposited sample was used.
  • Transistor 1b A substrate having a gate insulating layer (SiO 2 film, 200 nm) formed by thermal oxidation on a conductive Si substrate with a thickness of 0.5 mm was prepared, and an opening of 1 mm ⁇ 1 mm was Sputter deposition was performed on the substrate in the same manner as the semiconductor layer 1 a through a metal mask. Thus, an oxide thin film ( ⁇ -IGZO film) having a thickness of 1 nm ⁇ 1 mm and a thickness of 100 nm was formed on the substrate.
  • ⁇ -IGZO film oxide thin film having a thickness of 1 nm ⁇ 1 mm and a thickness of 100 nm was formed on the substrate.
  • the conductive Si substrate corresponds to a gate electrode
  • two Cu electrodes correspond to a source electrode and a drain electrode, respectively.
  • a bottom gate type transistor 1b in which the channel length between the source and drain electrodes is 100 ⁇ m and the channel width is 500 ⁇ m is obtained. According to the manufacturing method of the first embodiment, it is possible to obtain the transistor 1 b which is practicable as a device.
  • Example 2 The semiconductor layer 2a and the transistor 2b were fabricated according to the method of Example 1, except that the substrate temperature for sputter deposition was changed from room temperature to 190 ° C. According to the manufacturing method of the second embodiment, it is possible to obtain the transistor 2 b which is practicable as a device.
  • Comparative Example 1 According to the manufacturing method of Example 1, except that the helical antenna is not used in the multi-cathode sputtering apparatus, and the film forming pressure is changed from 0.07 Pa to 0.22 Pa, the semiconductor layer 3 a and the transistor 3 b was produced.
  • ⁇ -PCD ⁇ Physical evaluation>
  • ⁇ -PCD microwave photoconductivity decay method
  • the levels were evaluated.
  • the film quality was regarded as the transistor characteristics, and the electric characteristics of the transistor were evaluated in the single-layer film state, without electrodes, without contact.
  • the apparatus used was LTA-1610 SP manufactured by Kobelco Research Institute, and measurement was performed at room temperature using a 349 nm laser and a 26 GHz differential ⁇ -PCD detection system.
  • the measurement results of the ⁇ -PCD method of Example 1 are shown in FIG. 4, the measurement results of the ⁇ -PCD method of Example 2 in FIG. 5, and the measurement results of the ⁇ -PCD method of Comparative Example 1 in FIG. .
  • XRR X-ray reflectivity method
  • the apparatus used was Smarlab manufactured by Rigaku Corporation, and the incident X-ray wavelength was 0.15418 nm (Cu K line), and the output was 45 kV and 200 mA.
  • the measurement range (angle formed with the sample surface) was 0.0 to 1.5 °, and the measurement was performed in the measurement step of 0.001 °.
  • Example 1 The film density of Example 1 (semiconductor layer 1a) was 6.12 g / cm 3 , and the surface roughness was 0.58 nm.
  • the film density of Example 2 (semiconductor layer 2a) was 6.30 g / cm 3 , and the surface roughness was 0.626 nm.
  • the film density of Comparative Example 1 (semiconductor layer 3a) was 6.01 g / cm 3 , and the surface roughness was 0.962 nm. Therefore, the semiconductor layers of Examples 1 and 2 have a low film forming temperature, and have a high film density and a smooth surface despite the as-deposited annealing process after the film formation. Was confirmed.
  • FIG. 7 is a diagram in which the relationship between the film forming pressure and the DC bias voltage in the film forming process is plotted for the case where the helical antenna is used and the case where the helical antenna is not used.
  • the transmission power to the target was 100 W
  • the transmission power to the helical antenna was 100 W
  • the film forming pressure was changed, and the DC bias voltage at that time was measured.
  • the transmission power to the target was set to 100 W as in Comparative Example 1, the film forming pressure was changed, and the DC bias voltage at that time was measured.
  • FIG. 8 is a diagram showing the measurement results of the transfer characteristics of the transistors of Example 1 (w Helicon) and Comparative Example 1 (w / o Helicon).
  • the horizontal axis represents gate bias, and the vertical axis represents drain current.
  • the carrier mobility of Example 1 was 5.5 cm 2 / V ⁇ s, and the On / Off ratio was 10 7 . That is, it was confirmed that Example 1 had excellent transfer characteristics even though the film formation temperature was room temperature.
  • the carrier mobility of Comparative Example 1 was 0.1cm 2 / V ⁇ s, On / Off ratio was 10 4. That is, Comparative Example 1 was confirmed to have a very low carrier mobility.

Abstract

The invention is a production method for a transistor 1 that comprises a substrate 10, a gate electrode 12, a source electrode 14, a drain electrode 16, and a semiconductor layer 18, and includes a semiconductor layer forming step of irradiating and sputtering helicon plasma onto a raw material that is to constitute the semiconductor layer 18, thereby causing the semiconductor layer 18 to be formed.

Description

トランジスタの製造方法、及びトランジスタMethod of manufacturing transistor, and transistor
　本発明は、トランジスタの製造方法、及びトランジスタに関する。本発明は2017年8月1日に出願された日本国特許の出願番号2017-148749の優先権を主張し、文献の参照による織り込みが認められる指定国については、その出願に記載された内容は参照により本出願に織り込まれる。 The present invention relates to a method of manufacturing a transistor, and a transistor. The present invention claims priority to Japanese Patent Application No. 2017-148749 filed on Aug. 1, 2017, and the contents described in the application for designated countries permitted to be incorporated by reference to the literature are: Incorporated herein by reference.
　薄膜トランジスタ（ＴＦＴ）等の半導体装置に用いられる半導体材料としては、例えば、Ｉｎ、Ｇａ及びＺｎを含む酸化物（ＩＧＺＯ；Ｉｎ－Ｇａ－Ｚｎ－Ｏ）等のアモルファス酸化物が用いられている（特許文献１参照）。かかる半導体装置については、半導体特性の更なる向上が求められている。 As a semiconductor material used for semiconductor devices such as thin film transistors (TFTs), for example, amorphous oxides such as oxides containing In, Ga and Zn (IGZO; In-Ga-Zn-O) are used (Patent Reference 1). Such semiconductor devices are required to further improve their semiconductor characteristics.
特開２０１３－０５１４２１号公報JP, 2013-051421, A
　本発明に係る第一の態様は、基板と、ゲート電極と、ソース電極と、ドレイン電極と、半導体層とを含むトランジスタの製造方法であって、半導体層を構成する原料を含むターゲットに対して、ヘリコンプラズマを照射してスパッタすることによって、半導体層を形成する半導体層形成工程を含む、トランジスタの製造方法である。 A first aspect according to the present invention is a method of manufacturing a transistor including a substrate, a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, and a target including a raw material constituting the semiconductor layer. It is a manufacturing method of a transistor including the semiconductor layer formation process of forming a semiconductor layer by irradiating and carrying out helicon plasma and forming a semiconductor layer.
　本発明に係る第二の態様は、ゲート電極と、ソース電極と、ドレイン電極と、半導体層とを含むトランジスタであって、基板は、樹脂材料を含み、半導体層の膜密度が６．１以下である、トランジスタである。 A second aspect according to the present invention is a transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, wherein the substrate contains a resin material, and the film density of the semiconductor layer is 6.1 or less. Is a transistor.
本実施形態に係る製造方法により得られるトランジスタの一例を示す断面図である。It is sectional drawing which shows an example of the transistor obtained by the manufacturing method which concerns on this embodiment. 本実施形態に係る製造方法に用いられる成膜装置の一例を示す簡略構成図である。It is a simplified block diagram which shows an example of the film-forming apparatus used for the manufacturing method which concerns on this embodiment. 本実施形態に係る製造方法の一例を示す概略図である。It is the schematic which shows an example of the manufacturing method which concerns on this embodiment. 実施例１のμ－ＰＣＤ法の測定結果を示す図である。FIG. 7 is a view showing the measurement results of the μ-PCD method of Example 1. 実施例２のμ－ＰＣＤ法の測定結果を示す図である。FIG. 7 is a view showing the measurement results of the μ-PCD method of Example 2. 比較例１のμ－ＰＣＤ法の測定結果を示す図である。FIG. 7 is a view showing the measurement results of the μ-PCD method of Comparative Example 1. ヘリカルルアンテナを使用した場合と、ヘリカルアンテナを使用しない場合とについて、成膜プロセスにおける成膜圧力と直流バイアス電圧の関係をプロットした図である。It is the figure which plotted the relationship between the film-forming pressure and DC bias voltage in the film-forming process about the case where a helical antenna is used, and the case where a helical antenna is not used. 実施例１と比較例１のトランジスタの伝達特性の測定結果を示す図である。FIG. 6 is a graph showing measurement results of transfer characteristics of the transistors of Example 1 and Comparative Example 1;
　以下、本発明を実施するための形態（以下、単に「本実施形態」という。）について詳細に説明する。以下の本実施形態は、本発明を説明するための例示であり、本発明を以下の内容に限定する趣旨ではない。なお、図面中、上下左右等の位置関係は、特に断らない限り、図面に示す位置関係に基づくものとする。更に、図面の寸法比率は図示の比率に限られるものではない。 Hereinafter, modes for carrying out the present invention (hereinafter, simply referred to as "the present embodiment") will be described in detail. The following present embodiment is an example for describing the present invention, and is not intended to limit the present invention to the following contents. In the drawings, positional relationships such as upper, lower, left, and right are based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratio in the drawings is not limited to the illustrated ratio.
　図１は、本実施形態に係るトランジスタの製造方法により得られるトランジスタの一例を示す断面図である。本実施形態に係るトランジスタの製造方法は、基板１０と、絶縁層１１と、ゲート電極１２と、ソース電極１４と、ドレイン電極１６と、半導体層１８とを含むトランジスタ１の製造方法であって、半導体層を構成する原料を含むターゲットに対して、ヘリコンプラズマを照射してスパッタすることによって、半導体層を形成する半導体層形成工程を含む製造方法である。まず、トランジスタの構成について説明する。 FIG. 1 is a cross-sectional view showing an example of a transistor obtained by the method of manufacturing a transistor according to the present embodiment. The method of manufacturing the transistor according to the present embodiment is a method of manufacturing the transistor 1 including the substrate 10, the insulating layer 11, the gate electrode 12, the source electrode 14, the drain electrode 16, and the semiconductor layer 18. It is a manufacturing method including the semiconductor layer formation process of forming a semiconductor layer by irradiating and helicon plasma with respect to the target containing the raw material which comprises a semiconductor layer, and sputtering. First, the structure of the transistor is described.
　基板１０の材料としては、ガラスや樹脂材料等の公知の基板材料を用いることができ、例えば、二酸化ケイ素（ＳｉＯ２）、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリエーテルスルホン（ＰＥＳ）、ポリエーテルイミド、ポリエーテルエーテルケトン、ポリフェニレンスルフィド、ポリアリレート、ポリイミド、ポリカーボネート（ＰＣ）、セルローストリアセテート（ＴＡＣ）、セルロースアセテートプロピオネート（ＣＡＰ）等が挙げられる。また、基板１０は、２層や３層といった複数層から構成されるものであってもよく、無機材料と有機材料が組み合わせて使用されてもよい。 As a material of the substrate 10, known substrate materials such as glass and resin material can be used, and for example, silicon dioxide (SiO 2 ), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES) And polyether imide, polyether ether ketone, polyphenylene sulfide, polyarylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP) and the like. Further, the substrate 10 may be composed of a plurality of layers such as two layers or three layers, and an inorganic material and an organic material may be used in combination.
　絶縁層１１は、ゲート電極１２を覆って設けられる。絶縁層１１は、ゲート電極１２と、ソース電極１４及びドレイン電極１６とを電気的に絶縁することが可能であれば、無機材料と有機材料のいずれを用いて形成してもよい。例えば、無機材料としては、ＳｉＯ２、ＳｉＯＮ、ＳｉＮｘ、Ａｌ２Ｏ３、ＭｇＯ、ＭｇＦ２等を用いてよく、有機材料としては、ＰＭＭＡ（ポリメタクリル酸メチル樹脂）、エポキシ系光硬化型樹脂、パラキシリレン系ポリマー、ポリイミド等を用いてもよい。 The insulating layer 11 is provided to cover the gate electrode 12. The insulating layer 11 may be formed using either an inorganic material or an organic material as long as it can electrically insulate the gate electrode 12 from the source electrode 14 and the drain electrode 16. For example, SiO 2 , SiON, SiN x , Al 2 O 3 , MgO, MgF 2 or the like may be used as the inorganic material, and PMMA (polymethyl methacrylate resin), epoxy-based photocurable resin may be used as the organic material. And para-xylylene polymers, polyimides and the like may be used.
　絶縁層１１は、２層や３層といった複数層から構成されるものであってもよく、無機材料と有機材料が組み合わせて使用されてもよい。また、絶縁層１１は、所望のパターン形状に形成されてもよい。例えば、絶縁層１１の材料として光硬化型樹脂を用いてパターン光を照射することで所望のパターン形状の絶縁層１１を得てもよいし、絶縁層を一面に形成した後、フォトリソ工程を用いて所望のパターン形状としてもよい。例えば、所望のパターンに対応した開口部を有するメタルマスクを介して材料を成膜することで絶縁層１１を得てもよい。 The insulating layer 11 may be composed of a plurality of layers such as two layers or three layers, and an inorganic material and an organic material may be used in combination. In addition, the insulating layer 11 may be formed in a desired pattern shape. For example, the insulating layer 11 having a desired pattern shape may be obtained by irradiating a pattern light using a photocurable resin as a material of the insulating layer 11, or after forming the insulating layer on one surface, a photolithography process is used. The desired pattern shape may be used. For example, the insulating layer 11 may be obtained by depositing a material through a metal mask having an opening corresponding to a desired pattern.
　ゲート電極１２の材料としては、例えば、Ｃｕ、Ｔｉ、Ａｌ、Ａｕ、Ａｇ、Ｍｏ、Ｐｔ、ＩＴＯ（インジウム錫酸化物）、ＩＺＯ（インジウム亜鉛酸化物）、カーボンナノチューブ、フラーレン等が挙げられる。ゲート電極１２は、公知の方法を用いて形成され、所望のパターン形状を有していてもよい。例えば、無電解めっき用触媒を所望のパターン形状に配置し、無電解めっきを行うことにより形成してもよいし、金属層を一面に形成した後、フォトリソ工程を用いて所望のパターン形状としてもよい。また、所望のパターンに対応した開口部を有するメタルマスクを介してゲート電極材料を成膜することでゲート電極１２を得てもよい。 Examples of the material of the gate electrode 12 include Cu, Ti, Al, Au, Ag, Mo, Pt, ITO (indium tin oxide), IZO (indium zinc oxide), carbon nanotubes, fullerene, and the like. The gate electrode 12 is formed using a known method, and may have a desired pattern shape. For example, the catalyst for electroless plating may be disposed in a desired pattern shape and may be formed by performing electroless plating, or after a metal layer is formed on one surface, the desired pattern shape may be formed using a photolithography process. Good. Alternatively, the gate electrode 12 may be obtained by depositing a gate electrode material through a metal mask having an opening corresponding to a desired pattern.
　ソース電極１４とドレイン電極１６の材料としては、ゲート電極１２の材料と同様のものを使用できる。ソース電極１４とドレイン電極１６の材料は同じであってもよいし、異なっていてもよい。また、ソース電極１４とドレイン電極１６は、公知の方法を用いて形成され、ゲート電極１２の形成方法と同様であってよい。 As a material of the source electrode 14 and the drain electrode 16, the same material as the material of the gate electrode 12 can be used. The materials of the source electrode 14 and the drain electrode 16 may be the same or different. Further, the source electrode 14 and the drain electrode 16 are formed by using a known method, and may be similar to the method of forming the gate electrode 12.
　半導体層１８の材料については、酸化亜鉛（ＺｎＯ）、Ｉｎ、Ｇａ及びＺｎを含む酸化物（ＩｎＧａＺｎＯ４；ＩＧＺＯ等）の無機半導体が挙げられる。特に、高い電気移動度とｏｎ／ｏｆｆ比を有し、環境耐性に優れる観点から、ＩｎＧａＺｎＯ４（ＩＧＺＯ）であることが好ましい。 Examples of the material of the semiconductor layer 18 include inorganic semiconductors of zinc oxide (ZnO), oxides containing In, Ga, and Zn (InGaZnO 4 ; IGZO, etc.). In particular, InGaZnO 4 (IGZO) is preferable from the viewpoint of having high electric mobility and on / off ratio and being excellent in environmental resistance.
　スパッタリングには、１種の材料をターゲットとする一元同時スパッタを採用してもよいし、複数種の材料をターゲットとするコスパッタを採用してもよい。例えば、ＩＧＺＯ薄膜を基板上に形成する場合、ＩｎＧａＺｎＯ４である酸化物焼結体をターゲットとしてもよい（一元同時スパッタ）。あるいは、Ｉｎ２Ｏ３、Ｇａ２Ｏ３、及びＺｎＯの３種を多元同時に使用することで、組成比を傾斜させて所望の組成を持つＩＧＺＯ膜となるよう制御してもよい（多元同時スパッタ、コスパッタ）。 For sputtering, single simultaneous sputtering may be employed, which targets one type of material, or cosputtering, which targets multiple types of materials. For example, when an IGZO thin film is formed on a substrate, a sintered oxide of InGaZnO 4 may be used as a target (single simultaneous sputtering). Alternatively, the composition ratio may be controlled to be an IGZO film having a desired composition by simultaneously using three or more of In 2 O 3 , Ga 2 O 3 , and ZnO at the same time (multiple co-sputtering) , Cosputter).
　本実施形態に係る製造方法では、ヘリコンプラズマを所定のターゲットに照射してスパッタすることによって、半導体層１８を形成する。具体的には、スパッタターゲットの直上に存在するプラズマを囲むようにアンテナ（ヘリカルアンテナ）を立て、そこに高周波（１３．５６ＭＨｚ）を印加する方法を用いてターゲットをスパッタする。ヘリカル型のプラズマリングを用いることで、プラズマ周辺部の回転返還が大きく、中心部の回転返還を小さくすることができる。その結果、プラズマを局所的に閉じ込めることができる。これにより、温度や圧力等の成膜条件を緩和することが可能となる。さらには、アニールしなくてもアニール処理を施したものと同程度に優れた物性を得ることが可能となる。本実施形態に係る製造方法によれば、薄膜トランジスタ（ＴＦＴ）等のトランジスタを好適に製造することができる。 In the manufacturing method according to the present embodiment, the semiconductor layer 18 is formed by irradiating a predetermined target with helicon plasma and sputtering. Specifically, an antenna (helical antenna) is set so as to surround the plasma present immediately above the sputter target, and the target is sputtered using a method of applying a high frequency (13.56 MHz) thereto. By using the helical plasma ring, the rotational return of the peripheral portion of the plasma can be large, and the rotational return of the central portion can be reduced. As a result, the plasma can be confined locally. Thus, film formation conditions such as temperature and pressure can be relaxed. Furthermore, even without annealing, it is possible to obtain physical properties as excellent as those subjected to annealing. According to the manufacturing method of the present embodiment, a transistor such as a thin film transistor (TFT) can be suitably manufactured.
　図２は、本実施形態に係る製造方法に用いられる成膜装置の一例を示す簡略構成図である。成膜装置２は、ヘリコンプラズマを照射する成膜装置であり、印加台２０上にバッキングプレート２２とステージ２４とを備えており、その上方にヘリカルアンテナ２６が設けられている。半導体層１８の材料Ｍは、ステージ２４上に設置され、材料Ｍに対してプラズマ照射が行われる。これによって、ヘリカルアンテナ２６の上方に設置されている基板３の表面上に、材料Ｍが蒸着し（蒸着方向Ｆ１参考）、半導体層１８を成膜することができる。 FIG. 2 is a simplified configuration diagram showing an example of a film forming apparatus used for the manufacturing method according to the present embodiment. The film forming apparatus 2 is a film forming apparatus that irradiates helicon plasma, includes a backing plate 22 and a stage 24 on an application table 20, and a helical antenna 26 is provided above the backing plate 22 and the stage 24. The material M of the semiconductor layer 18 is placed on the stage 24 and plasma irradiation is performed on the material M. Thus, the material M can be deposited on the surface of the substrate 3 disposed above the helical antenna 26 (see deposition direction F1), and the semiconductor layer 18 can be formed.
　ヘリコンプラズマを照射してスパッタする工程では、不活性ガス（アルゴン、ヘリウム、ネオン、クリプトン、キセノン等）や反応性ガス（窒素ガス、酸素ガス等）の雰囲気下で行うことができる。図示はしないが、例えば、チャンバー内に成膜装置２を配置し、不活性ガスと反応性ガスの混合ガス雰囲気とすることにより、プラズマ照射を行うことができる。 The step of irradiating and sputtering the helicon plasma can be performed in an atmosphere of an inert gas (argon, helium, neon, krypton, xenon, etc.) or a reactive gas (nitrogen gas, oxygen gas, etc.). Although not shown, plasma irradiation can be performed, for example, by disposing the film forming apparatus 2 in a chamber and setting it as a mixed gas atmosphere of an inert gas and a reactive gas.
　ヘリコンプラズマを照射してスパッタすることで、高密度、低欠陥、高密度な半導体層１８を成膜できる。そして、本実施形態に係る製造方法により得られるトランジスタは、高移動度かつ高安定性なトランジスタ特性を発揮できる。 A high density, low defects, high density semiconductor layer 18 can be formed by sputtering by irradiation with a helicon plasma. Then, the transistor obtained by the manufacturing method according to the present embodiment can exhibit high mobility and high stability transistor characteristics.
　トランジスタの半導体層１８について、ＩＧＺＯ等の酸化物半導体はアモルファス構造でありながら高い移動度を有する。そのため、かかる半導体層１８を有するトランジスタは、優れたトランジスタ特性を有するものとして、スマートフォンやタブレットのディスプレイ等への搭載が期待される。しかしながら、従来の製造工程では、２００℃を超える高温とする必要があり、半導体層を加熱してわずかな結晶化を起こさせることができなければ、高いキャリア移動度と安定性が得られなかった。かかる観点から、成膜後の後処理として、ポストアニーリングを行う必要がある。 In the semiconductor layer 18 of the transistor, an oxide semiconductor such as IGZO has high mobility while having an amorphous structure. Therefore, the transistor having the semiconductor layer 18 is expected to be mounted on a display of a smartphone, a tablet, or the like as having excellent transistor characteristics. However, in the conventional manufacturing process, high temperature exceeding 200 ° C. is required, and high carrier mobility and stability can not be obtained unless the semiconductor layer can be heated to cause slight crystallization. . From this point of view, post-annealing needs to be performed as a post-process after film formation.
　その一方で、トランジスタに高いフレキシビリティを付与するために、基板１０としてＰＥＴ、ＰＥＮ等といった樹脂材料（樹脂フィルム、樹脂シートと呼ばれることもある。）を用いることが試みられている。しかしながら、半導体層１８の成膜温度が２００℃を超える高温であれば、通常の樹脂材料の軟化点を超えるため、基板１０が熱に耐えられないという問題がある。 On the other hand, in order to provide the transistor with high flexibility, it has been attempted to use a resin material (sometimes called a resin film or a resin sheet) such as PET or PEN as the substrate 10. However, if the film formation temperature of the semiconductor layer 18 is a high temperature exceeding 200 ° C., the temperature exceeds the softening point of the normal resin material, so there is a problem that the substrate 10 can not withstand the heat.
　この点、本実施形態に係る製造方法によれば、ヘリコンプラズマを照射してスパッタリングを行うことで、成膜温度を高温にすることなく、樹脂材料層を含む基板１０に高移動度かつ高安定な半導体層１８を形成することができる。好適な成膜温度としては、樹脂材料層を含む基板の軟化点以下とするができる。ここでいう軟化点とは、樹脂が軟化して、変形を起こし始める温度をいい、ＪＩＳ　Ｋ７２０７（Ａ法）に準じた試験方法により測定することができる。 In this respect, according to the manufacturing method of the present embodiment, the sputtering is performed by irradiating the helicon plasma, so that the substrate 10 including the resin material layer has high mobility and high stability without raising the film forming temperature to a high temperature. The semiconductor layer 18 can be formed. As a suitable film-forming temperature, it can be below the softening point of the board | substrate containing a resin material layer. The softening point referred to here is a temperature at which the resin softens and starts deformation, and can be measured by a test method according to JIS K7207 (method A).
　本実施形態に係る製造方法によれば軟化点以下という低温で成膜可能であるということは、樹脂材料層を含む基板１０に対して、ａ－ＩＧＺＯ等の半導体層１８が成膜可能であるといえる。基板１０が高いフレキシビリティを有するフィルム基板であれば、トランジスタ自身も高いフレキシビリティを付与できる。 According to the manufacturing method of the present embodiment, the fact that film formation is possible at a low temperature below the softening point means that the semiconductor layer 18 such as a-IGZO can be formed on the substrate 10 including the resin material layer. It can be said. If the substrate 10 is a film substrate having a high degree of flexibility, the transistor itself can also be provided with a high degree of flexibility.
　また、基板１０がフィルム基板であれば、ロール状として連続的に成膜するロール・ツー・ロール（Roll to Roll）方式や、ロール・ツー・シート（Roll to Sheet）方式を採用することができ、製造工程の高効率化、簡略化及び歩留まり向上等が期待できる。 In addition, if the substrate 10 is a film substrate, it is possible to adopt a roll-to-roll method or a roll-to-sheet method in which a film is continuously formed as a roll. In addition, high efficiency, simplification, and yield improvement of the manufacturing process can be expected.
　上述した樹脂の軟化点との関係から、具体的な成膜温度としては、好ましくは２００℃以下であり、より好ましくは１５０℃以下であり、さらに好ましくは１２０℃以下である。これにより、成膜温度を幅広い種類の樹脂の軟化点以下とすることができるため、幅広い樹脂を基板１０の材料として採用することができる。 From the relationship with the softening point of the resin described above, the specific film forming temperature is preferably 200 ° C. or less, more preferably 150 ° C. or less, and still more preferably 120 ° C. or less. Thus, the film forming temperature can be made equal to or lower than the softening point of a wide variety of resins, so a wide range of resins can be adopted as the material of the substrate 10.
　従来、実用レベルの要求特性を満たすトランジスタを得るためには、成膜後に高温でアニーリングする必要があった。例えば、ＩＧＺＯ膜等の場合では、膜質改善の目的で大気中や水蒸気雰囲気下で熱処理を行う必要があった。この点、本実施形態に係る製造方法では、成膜温度が低温であっても、良好なトランジスタ特性を有するトランジスタを効率よく製造することができる。よって、本実施形態に係る製造方法では、後処理としてのポストアニーリング工程を行わない（すなわち、半導体層形成工程後に加熱工程を有しない）という態様をとることもできる。 Heretofore, in order to obtain a transistor that meets the required characteristics at a practical level, it has been necessary to anneal at a high temperature after film formation. For example, in the case of an IGZO film or the like, the heat treatment needs to be performed in the air or in a water vapor atmosphere for the purpose of film quality improvement. In this respect, according to the manufacturing method of the present embodiment, even if the film forming temperature is low, a transistor having good transistor characteristics can be manufactured efficiently. Therefore, in the manufacturing method according to the present embodiment, it is possible to adopt an aspect in which the post-annealing step as post-processing is not performed (that is, the heating step is not performed after the semiconductor layer forming step).
　また、本実施形態に係る製造方法では、ヘリカル型のプラズマリングを用いることで、プラズマを局所的に閉じ込めることができる。これにより、低圧でも安定したプラズマを発生させることができ、低圧での成膜が可能となる。低圧での成膜が可能であることで、プラズマ照射の際に成膜金属以外の不純物混入を抑制することができる。具体的な成膜圧力としては、好ましくは０．１Ｐａ以下であり、より好ましくは０．０７Ｐａ以下である。一方、成膜圧力の下限は、必ずしも規定する必要はないが、０．０５Ｐａ以上とすることができる。 In addition, in the manufacturing method according to the present embodiment, plasma can be locally confined by using a helical plasma ring. Thereby, stable plasma can be generated even at low pressure, and film formation at low pressure becomes possible. By being able to form a film at low pressure, it is possible to suppress the mixing of impurities other than the film forming metal at the time of plasma irradiation. The specific film forming pressure is preferably 0.1 Pa or less, more preferably 0.07 Pa or less. On the other hand, the lower limit of the film forming pressure is not necessarily defined, but can be 0.05 Pa or more.
　さらに、本実施形態に係る製造方法では、膜密度が高い半導体層１８とすることができる。具体的には、半導体層１８の膜密度は、好ましくは６．１以上であり、より好ましくは６．２以上であり、更に好ましくは６．３以上である。膜密度が高い半導体層は、伝導に寄与するｓ軌道が強固な結合を持つことにより、高い電子移動度が期待できる。また、格子欠陥などに由来する欠陥準位を補償することも期待できることから安定性も向上するため、トランジスタとして好適である。 Furthermore, in the manufacturing method according to the present embodiment, the semiconductor layer 18 can have a high film density. Specifically, the film density of the semiconductor layer 18 is preferably 6.1 or more, more preferably 6.2 or more, and still more preferably 6.3 or more. In a semiconductor layer having a high film density, high electron mobility can be expected because the s orbital contributing to conduction has a strong bond. In addition, since it is also expected to compensate for a defect level derived from a lattice defect or the like, the stability is also improved, which is suitable as a transistor.
　上述したように、本実施形態に係る製造方法では、樹脂材料を含む基板１０を用いる態様においてロール・ツー・ロール方式やロール・ツー・シート方式といった連続製造を行うことが可能である。ロール・ツー・ロール方式とは、ロール状のフィルム基板（シート基板と呼ばれることもある。）を巻き出して連続的に成膜し、再びロール状に巻き取る方式の成膜方法をいう。ロール・ツー・シート方式は、ロール状のフィルム基板を巻き出して連続的に成膜し、これをカッティングしてシートとする方式の成膜方法をいう。 As described above, in the manufacturing method according to the present embodiment, it is possible to perform continuous manufacturing such as a roll-to-roll method or a roll-to-sheet method in a mode using the substrate 10 containing a resin material. The roll-to-roll system refers to a film forming method in which a roll-shaped film substrate (sometimes called a sheet substrate) is unwound and continuously formed into a film, and then wound into a roll again. The roll-to-sheet method refers to a film forming method in which a roll-shaped film substrate is unrolled to continuously form a film, and the film is cut to form a sheet.
　図３は、本実施形態に係る製造方法の一例を示す概略図である。製造装置４は、ロール・ツー・ロール方式の製造装置である。基板３は、樹脂材料を含む樹脂フィルムである。基板３は、巻き出しロール４０から矢印Ｆ２方向に送り出され、ガイドロール４２を介して、ドラム４４まで搬送される。ドラム４４では、成膜処理領域Ａにおいて、上述した成膜装置２によってヘリコンプラズマを照射してスパッタリングする工程が行われ、成膜される。そして、ガイドロール４６を介して、巻き取りロール４８まで搬送され、ロール状に巻き取られる。 FIG. 3 is a schematic view showing an example of the manufacturing method according to the present embodiment. The manufacturing apparatus 4 is a roll-to-roll type manufacturing apparatus. The substrate 3 is a resin film containing a resin material. The substrate 3 is fed from the unwinding roll 40 in the direction of the arrow F 2, and is conveyed to the drum 44 through the guide roll 42. In the drum 44, in the film forming process area A, the step of irradiating the helicon plasma by the above-described film forming apparatus 2 and performing sputtering is performed to form a film. Then, the sheet is conveyed to the take-up roll 48 through the guide roll 46 and taken up in a roll.
　また、図示はしないが、ドラム４４では、上述した半導体形成工程だけでなく、イオン照射やＵＶ照射、マイクロ波照射による基板のクリーニングといった前処理工程や、成膜後の薄膜を加熱することによる不純物除去、膜密度向上のためのアニール処理といった後処理工程をさらに行うことができる。 Although not shown, in the drum 44, not only the semiconductor formation process described above, but also a pretreatment process such as cleaning of a substrate by ion irradiation, UV irradiation, or microwave irradiation, or impurities by heating a thin film after film formation. Post-processing steps such as annealing for removal and film density improvement can be further performed.
　ロール・ツー・ロール方式による成膜は、ディスプレイ等をはじめとするフレキシブルデバイスの大量生産の手法として、プロセスの高スループット化、高品質化、低コスト化等の効果が期待できる。 The roll-to-roll deposition can be expected to have effects such as high throughput, high quality, and low cost of the process as a method for mass production of flexible devices including displays and the like.
　本実施形態により得られるトランジスタは、薄膜トランジスタ等として、種々の電子機器の部品に用いることができる。とりわけ、各種電子製品のディスプレイ等をはじめとするフレキシブルデバイスの部品として好適に用いることができる。 The transistor obtained according to this embodiment can be used as a thin film transistor or the like for components of various electronic devices. In particular, it can be suitably used as a component of a flexible device such as a display of various electronic products.
　以下の実施例及び比較例により本発明を更に詳しく説明するが、本発明は以下の実施例に限定されるものではない。 The present invention will be described in more detail by the following examples and comparative examples, but the present invention is not limited to the following examples.
　以下の方法に準拠して各実施例及び各比較例のサンプルを作製し、それらの物性を評価した。 The sample of each Example and each comparative example was produced based on the following method, and those physical properties were evaluated.
＜実施例１＞
（１）半導体層１ａの作製
　基板として、石英ガラス基板（信越石英社製、厚さ０．５ｍｍ）を用いた。スパッタリングターゲットとして、インジウム（Ｉｎ）、ガリウム（Ｇａ）、亜鉛（Ｚｎ）及び酸素（Ｏ）を構成元素とする酸化物焼結体（原子比、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１）を用いた。そして、図２に示すヘリカルアンテナ２６を備えたマルチカソードスパッタ装置（成膜装置２）を用いた。マルチカソードスパッタ装置において、直流磁界発生用コイルで直流磁界を発生させ、ヘリカルアンテナ２６に高周波電界（ＲＦ：１３．５６ＭＨｚ）を印加した。これにより、ヘリコン波を励起させてプラズマを発生させ、ターゲットをスパッタリングすることで、基板上に厚さ８５ｎｍの酸化物薄膜（半導体層１ａ）を形成させた。なお、スパッタリングは以下の条件で行った。また、成膜後はアニール処理を行わず、ａｓ－ｄｅｐｏｓｉｔｅｄ試料とした。 Example 1
(1) Production of Semiconductor Layer 1a As a substrate, a quartz glass substrate (manufactured by Shin-Etsu Quartz Co., Ltd., thickness 0.5 mm) was used. As a sputtering target, an oxide sintered body (atomic ratio, In: Ga: Zn = 1: 1: 1) containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) as constituent elements Using. Then, a multi-cathode sputtering apparatus (film forming apparatus 2) including the helical antenna 26 shown in FIG. 2 was used. In the multi-cathode sputtering apparatus, a direct current magnetic field was generated by a direct current magnetic field generating coil, and a high frequency electric field (RF: 13.56 MHz) was applied to the helical antenna 26. Thereby, the helicon wave is excited to generate plasma, and the target is sputtered to form an oxide thin film (semiconductor layer 1a) having a thickness of 85 nm on the substrate. Sputtering was performed under the following conditions. In addition, after the film formation, the annealing treatment was not performed, and an as-deposited sample was used.
・スパッタリング条件
　電源：ＤＣ
　スパッタターゲット伝送電力：１００Ｗ
　ヘリカルアンテナ伝送電力：１００Ｗ
　基板とターゲットの距離：１７９ｍｍ
　ターゲットサイズ（円盤状）：直径５０ｍｍ、厚さ３ｍｍ
　プロセスガス：アルゴン
　反応性ガス：酸素（流量３ｓｃｃｍ）
　基板温度：室温
　成膜圧力：０．０７Ｐａ
　成膜時間：４０分 Sputtering conditions Power supply: DC
Sputtering target Transmission power: 100 W
Helical antenna transmission power: 100 W
Distance between substrate and target: 179 mm
Target size (disk-like): diameter 50 mm, thickness 3 mm
Process gas: Argon Reactive gas: Oxygen (flow rate 3 sccm)
Substrate temperature: Room temperature Deposition pressure: 0.07 Pa
Deposition time: 40 minutes
（２）トランジスタ１ｂの作製
　厚さ０．５ｍｍの導電性Ｓｉ基板上にゲート絶縁層（ＳｉＯ２膜、２００ｎｍ）が熱酸化により形成された基板を用意した、そして、１ｍｍ×１ｍｍの開口部を有するメタルマスクを介し、当該基板上に半導体層１ａと同様の手法でスパッタ成膜を行った。これにより、基板上に１ｍｍ×１ｍｍで厚さ１００ｎｍの酸化物薄膜（α－ＩＧＺＯ膜）を成膜した。次いで、１ｍｍ×１ｍｍの開口部を有するメタルマスクを介してＣｕを蒸着し、１ｍｍ×１ｍｍで厚さ２００ｎｍのＣｕ電極を２つ成膜した。なお、導電性Ｓｉ基板がゲート電極に相当し、２つのＣｕ電極がそれぞれソース電極、ドレイン電極に相当する。そして、ソース・ドレイン電極間のチャネル長が１００μｍであり、チャネル幅が５００μｍであるボトムゲート型のトランジスタ１ｂを得た。実施例１の製造方法によれば、デバイスとして実用可能な程度のトランジスタ１ｂを得ることができた。 (2) Preparation of Transistor 1b A substrate having a gate insulating layer (SiO 2 film, 200 nm) formed by thermal oxidation on a conductive Si substrate with a thickness of 0.5 mm was prepared, and an opening of 1 mm × 1 mm was Sputter deposition was performed on the substrate in the same manner as the semiconductor layer 1 a through a metal mask. Thus, an oxide thin film (α-IGZO film) having a thickness of 1 nm × 1 mm and a thickness of 100 nm was formed on the substrate. Subsequently, Cu was vapor-deposited through the metal mask which has a 1 mm x 1 mm opening part, and two Cu electrodes 200 nm thick were formed into a film by 1 mm x 1 mm. Note that the conductive Si substrate corresponds to a gate electrode, and two Cu electrodes correspond to a source electrode and a drain electrode, respectively. Then, a bottom gate type transistor 1b in which the channel length between the source and drain electrodes is 100 μm and the channel width is 500 μm is obtained. According to the manufacturing method of the first embodiment, it is possible to obtain the transistor 1 b which is practicable as a device.
＜実施例２＞
　スパッタ成膜の基板温度を室温から１９０℃に変更した点以外は、実施例１の手法に準拠して、半導体層２ａ及びトランジスタ２ｂを作製した。実施例２の製造方法によれば、デバイスとして実用可能な程度のトランジスタ２ｂを得ることができた。 Example 2
The semiconductor layer 2a and the transistor 2b were fabricated according to the method of Example 1, except that the substrate temperature for sputter deposition was changed from room temperature to 190 ° C. According to the manufacturing method of the second embodiment, it is possible to obtain the transistor 2 b which is practicable as a device.
＜比較例１＞
　マルチカソードスパッタ装置においてヘリカルアンテナを使用しなかった点、及び成膜圧力を０．０７Ｐａから０．２２Ｐａに変更した点以外は、実施例１の製造方法に準拠して、半導体層３ａ及びトランジスタ３ｂを作製した。 Comparative Example 1
According to the manufacturing method of Example 1, except that the helical antenna is not used in the multi-cathode sputtering apparatus, and the film forming pressure is changed from 0.07 Pa to 0.22 Pa, the semiconductor layer 3 a and the transistor 3 b Was produced.
＜物性評価＞
（μ－ＰＣＤ）
　各実施例及び比較例で得られた半導体層について、マイクロ波光導電減衰法（μ－ＰＣＤ；Microwave Photo Conductivity Decay）を利用し、膜内のキャリア移動度とバンドギャップ内の酸素欠陥に由来する欠陥準位を評価した。これにより、膜質をトランジスタ特性ととらえ、単層膜状態、電極付けなし、非接触で、トランジスタの電気的特性を評価した。 <Physical evaluation>
(Μ-PCD)
For the semiconductor layer obtained in each of the examples and the comparative example, defects derived from carrier mobility in the film and oxygen defects in the band gap are used by using the microwave photoconductivity decay method (μ-PCD; Microwave Photo Conductivity Decay). The levels were evaluated. Thus, the film quality was regarded as the transistor characteristics, and the electric characteristics of the transistor were evaluated in the single-layer film state, without electrodes, without contact.
　使用した装置は、コベルコ科研社製のＬＴＡ－１６１０ＳＰであり、３４９ｎｍのレーザと、２６ＧＨｚの差動μ－ＰＣＤ検出系を用い、室温にて測定を行った。図４に実施例１のμ－ＰＣＤ法の測定結果を、図５に実施例２のμ－ＰＣＤ法の測定結果を、図６に比較例１のμ－ＰＣＤ法の測定結果を、それぞれ示す。 The apparatus used was LTA-1610 SP manufactured by Kobelco Research Institute, and measurement was performed at room temperature using a 349 nm laser and a 26 GHz differential μ-PCD detection system. The measurement results of the μ-PCD method of Example 1 are shown in FIG. 4, the measurement results of the μ-PCD method of Example 2 in FIG. 5, and the measurement results of the μ-PCD method of Comparative Example 1 in FIG. .
　シグナルピークの評価について説明する。シグナルのピーク値が高ければ、キャリア移動度が高いといえる。この点、実施例１，２は、比較例１に比して、シグナルピーク値が高い。よって、実施例１，２は、高いキャリア移動度を有するといえる。 The evaluation of signal peaks is described. If the peak value of the signal is high, it can be said that the carrier mobility is high. In this respect, Examples 1 and 2 have higher signal peak values than Comparative Example 1. Therefore, it can be said that Examples 1 and 2 have high carrier mobility.
　レーザ光照射オフからの減衰挙動の評価について説明する。まず、シグナルのピークトップからの早い減衰は、膜中の深い欠陥準位に起因しており、この欠陥準位はキャリア移動度の高さを示している。そして、これに続いて起こる遅い減衰は、膜中の浅い欠陥準位に起因し、この準位は薄膜トランジスタとした際のヒステリシスの存在や閾値電圧シフトが大きいことを示している。この点、比較例１では、遅い減衰が強く存在していることから、浅い欠陥準位が強く、薄膜トランジスタとした際のデバイス安定性に欠けるといえる。その一方で、実施例１，２は、比較例１のような強い減衰はみられなかった。よって、実施例１，２は、薄膜トランジスタとした際の照射光強度依存性が少なく、高いデバイス安定性を有するといえる。 The evaluation of the attenuation behavior from the laser light irradiation off will be described. First, the fast decay from the peak top of the signal is due to the deep defect level in the film, and this defect level indicates the high carrier mobility. The slow decay that occurs subsequently is attributed to the shallow defect level in the film, and this level indicates that the presence of hysteresis and the threshold voltage shift in the thin film transistor are large. In this respect, in Comparative Example 1, since the slow decay is strongly present, it can be said that the shallow defect level is strong and the device stability in the thin film transistor is lacking. On the other hand, Examples 1 and 2 did not show strong attenuation like Comparative Example 1. Therefore, it can be said that Examples 1 and 2 have little dependency on irradiation light intensity when forming a thin film transistor, and have high device stability.
（ＸＲＲ）
　各実施例及び比較例で得られた半導体層について、Ｘ線反射率法（ＸＲＲ；X-Ray Reflectivity）を利用して膜密度と表面荒さを評価した。薄膜の膜密度が高いほど、トランジスタのキャリア移動度が高く、薄膜の表面が平滑であるほど、欠陥準位由来の不安定さが抑制され、安定性に優れるといえる。 (XRR)
The film density and surface roughness of the semiconductor layers obtained in each of the examples and comparative examples were evaluated using X-ray reflectivity method (XRR; X-Ray Reflectivity). As the film density of the thin film is higher, the carrier mobility of the transistor is higher, and as the surface of the thin film is smoother, instability due to defect levels is suppressed, and it can be said that the stability is excellent.
　使用した装置は、リガク社製のＳｍａｒｌａｂであり、入射Ｘ線波長を０．１５４１８ｎｍ（ＣｕＫ線）とし、出力４５ｋＶ、２００ｍＡとした。また、測定範囲（試料表面とのなす角）は０．０～１．５°とし、０．００１°の測定ステップで測定した。 The apparatus used was Smarlab manufactured by Rigaku Corporation, and the incident X-ray wavelength was 0.15418 nm (Cu K line), and the output was 45 kV and 200 mA. In addition, the measurement range (angle formed with the sample surface) was 0.0 to 1.5 °, and the measurement was performed in the measurement step of 0.001 °.
　実施例１（半導体層１ａ）の膜密度は６．１２ｇ／ｃｍ３であり、表面荒さは０．５８ｎｍであった。実施例２（半導体層２ａ）の膜密度は６．３０ｇ／ｃｍ３であり、表面荒さは０．６２６ｎｍであった。比較例１（半導体層３ａ）の膜密度は６．０１ｇ／ｃｍ３であり、表面荒さは０．９６２ｎｍであった。よって、実施例１，２の半導体層は、低い成膜温度であり、成膜後のアニール処理を行わなかった（ａｓ－ｄｅｐｏｓｉｔｅｄ）にもかかわらず、高い膜密度であり、かつ、平滑な表面であることが確認された。 The film density of Example 1 (semiconductor layer 1a) was 6.12 g / cm 3 , and the surface roughness was 0.58 nm. The film density of Example 2 (semiconductor layer 2a) was 6.30 g / cm 3 , and the surface roughness was 0.626 nm. The film density of Comparative Example 1 (semiconductor layer 3a) was 6.01 g / cm 3 , and the surface roughness was 0.962 nm. Therefore, the semiconductor layers of Examples 1 and 2 have a low film forming temperature, and have a high film density and a smooth surface despite the as-deposited annealing process after the film formation. Was confirmed.
（ＳＴＥＭ）
　各実施例及び比較例で得られた半導体層の断面を、走査透過電子顕微鏡（ＳＴＥＭ；Scanning Transmission Electron Microscope）によって撮像し、膜の微小領域での結晶状態を確認した。使用した装置は、日本電子社製のＪＥＭ－ＡＲＭ２００Ｆであり、加速電圧２００ｋＶとし、１００万倍の倍率で測定した。その結果、実施例１，２では、リング状の回折像が確認された。しかし、比較例１では、リング状の回折像は確認されず、アモルファスであることが確認された。 (STEM)
The cross section of the semiconductor layer obtained in each Example and Comparative Example was imaged by a scanning transmission electron microscope (STEM) to confirm the crystalline state in a minute region of the film. The apparatus used was JEM-ARM200F manufactured by JEOL Ltd., and the acceleration voltage was 200 kV, and measurement was performed at a magnification of 1,000,000. As a result, in Examples 1 and 2, a ring-shaped diffraction image was confirmed. However, in Comparative Example 1, the ring-shaped diffraction image was not confirmed, and it was confirmed that it was amorphous.
（成膜圧力と直流バイアス電圧の関係）
　ここで、参考として、成膜圧力と直流バイアス（Ｖｄｃ）の関係を、図７を用いて説明する。図７は、ヘリカルルアンテナを使用した場合と、ヘリカルアンテナを使用しない場合とについて、成膜プロセスにおける成膜圧力と直流バイアス電圧の関係をプロットした図である。 (Relationship between deposition pressure and DC bias voltage)
Here, as a reference, the relationship between the film forming pressure and the DC bias (Vdc) will be described with reference to FIG. FIG. 7 is a diagram in which the relationship between the film forming pressure and the DC bias voltage in the film forming process is plotted for the case where the helical antenna is used and the case where the helical antenna is not used.
　ヘリカルアンテナを使用した場合は、実施例１と同様にターゲットへの伝送電力を１００Ｗ、ヘリカルアンテナへの伝送電力を１００Ｗとし、成膜圧力を変化させてそのときの直流バイアス電圧を測定した。ヘリカルアンテナを使用しない場合は、比較例１と同様にターゲットへの伝送電力を１００Ｗとし、成膜圧力を変化させてそのときの直流バイアス電圧を測定した。 When a helical antenna was used, the transmission power to the target was 100 W, the transmission power to the helical antenna was 100 W, the film forming pressure was changed, and the DC bias voltage at that time was measured. When a helical antenna was not used, the transmission power to the target was set to 100 W as in Comparative Example 1, the film forming pressure was changed, and the DC bias voltage at that time was measured.
　その結果、いずれも成膜圧力が低くなるとＶｄｃ値は増加する傾向にあるが、ヘリカルアンテナを使用しない場合には０．１Ｐａ以下では放電しないことが確認された。一方、ヘリカルアンテナを使用した場合には０．１Ｐａ以下であっても放電することが確認された。したがって、ヘリカルアンテナを用いる本実施例の製造プロセスによれば、直流バイアス電圧が低いことからイオン電流が向上することが分かる。また、低い成膜圧力でも放電可能であることから、より長い平均自由行程で成膜することが可能となり、膜質の向上や不純物拡散の抑制が期待できる。 As a result, it was confirmed that the Vdc value tends to increase when the film forming pressure is lowered in all cases, but the discharge does not occur at 0.1 Pa or less when the helical antenna is not used. On the other hand, when the helical antenna was used, it was confirmed that the discharge occurred even at 0.1 Pa or less. Therefore, according to the manufacturing process of the present embodiment using a helical antenna, it is understood that the ion current is improved because the DC bias voltage is low. In addition, since discharge can be performed even at a low deposition pressure, deposition can be performed with a longer mean free path, and improvement in film quality and suppression of impurity diffusion can be expected.
（電導特性）
　実施例１のトランジスタ１ｂと比較例１のトランジスタ３ｂについて、半導体パラメータアナライザ（Ｋｅｉｔｈｌｅｙ社製、４２００－ｓｃｓ）を用いてこれらのトランジスタの伝達特性を評価した。このとき、ソース電極－ドレイン電極間の電圧を１０Ｖとし、ゲート電極－ソース電極間に－５０～＋５０Ｖで１Ｖ間隔にて掃引した際のソース電極－ドレイン電極間の電流値を測定した。 (Conductivity)
The transfer characteristics of the transistor 1b of Example 1 and the transistor 3b of Comparative Example 1 were evaluated using a semiconductor parameter analyzer (4200-scs, manufactured by Keithley). At this time, the voltage between the source electrode and the drain electrode was 10 V, and the current value between the source electrode and the drain electrode was measured when sweeping was performed at an interval of 1 V from -50 to +50 V between the gate electrode and the source electrode.
　図８は、実施例１（w Helicon）と比較例１（w/o Helicon）のトランジスタの伝達特性の測定結果を示す図である。横軸はゲートバイアス、縦軸はドレイン電流を示す。実施例１のキャリア移動度は５．５ｃｍ２／Ｖ・ｓであり、Ｏｎ／Ｏｆｆ比は１０７であった。すなわち、実施例１は、成膜温度が室温であったにもかかわらず、優れた伝達特性を有することが確認された。それに対して、比較例１のキャリア移動度は０．１ｃｍ２／Ｖ・ｓであり、Ｏｎ／Ｏｆｆ比は１０４であった。すなわち、比較例１は、キャリア移動度が非常に低いことが確認された。 FIG. 8 is a diagram showing the measurement results of the transfer characteristics of the transistors of Example 1 (w Helicon) and Comparative Example 1 (w / o Helicon). The horizontal axis represents gate bias, and the vertical axis represents drain current. The carrier mobility of Example 1 was 5.5 cm 2 / V · s, and the On / Off ratio was 10 7 . That is, it was confirmed that Example 1 had excellent transfer characteristics even though the film formation temperature was room temperature. In contrast, the carrier mobility of Comparative Example 1 was 0.1cm 2 / V · s, On / Off ratio was 10 4. That is, Comparative Example 1 was confirmed to have a very low carrier mobility.
　以上より、実施例１，２において得られた薄膜及びトランジスタは、トランジスタとしての種々の電気的特性に優れていることが確認された。 As mentioned above, it was confirmed that the thin film and transistor obtained in Examples 1 and 2 are excellent in various electric characteristics as a transistor.
１…トランジスタ、２…成膜装置、３，１０…基板、４…製造装置、１１…絶縁層、１２…ゲート電極、１４…ソース電極、１６…ドレイン電極、１８…半導体層、２０…印加台、２２…バッキングプレート、２４…ステージ、２６…ヘリカルアンテナ、４０…巻き出しロール、４２，４６…ガイドロール、４４…ドラム、４８…巻き取りロール、Ａ…成膜処理領域、Ｍ…材料、Ｆ１…蒸着方向、Ｆ２，Ｆ３…搬送方向 DESCRIPTION OF SYMBOLS 1... Transistor 2 film forming device 3 10 substrate 4 manufacturing device 11 insulating layer 12 gate electrode 14 source electrode 16 drain electrode 18 semiconductor layer 20 application stage , 22: Backing plate, 24: Stage, 26: Helical antenna, 40: Unrolling roll, 42, 46: Guide roll, 44: Drum, 48: Take-up roll, A: Film formation processing area, M: Material, F1 ... deposition direction, F2, F3 ... transport direction

Claims (11)

  1. 　基板と、ゲート電極と、ソース電極と、ドレイン電極と、半導体層とを含むトランジスタの製造方法であって、
    　前記半導体層を構成する原料を含むターゲットに対して、ヘリコンプラズマを照射してスパッタすることによって、前記半導体層を形成する半導体層形成工程を含むことを特徴とする、トランジスタの製造方法。     A method of manufacturing a transistor, comprising: a substrate, a gate electrode, a source electrode, a drain electrode, and a semiconductor layer,
    A method for manufacturing a transistor, comprising: a semiconductor layer forming step of forming the semiconductor layer by irradiating the helicon plasma and sputtering the target containing the raw material constituting the semiconductor layer.
  2. 　前記基板は、樹脂材料を含むことを特徴とする、請求項１に記載のトランジスタの製造方法。 The method of claim 1, wherein the substrate comprises a resin material.
  3. 　前記半導体層形成工程における成膜温度は、前記基板の軟化点以下であることを特徴とする、請求項２に記載のトランジスタの製造方法。 The method for manufacturing a transistor according to claim 2, wherein a film forming temperature in the semiconductor layer forming step is equal to or lower than a softening point of the substrate.
  4. 　前記成膜温度は、２００℃以下であることを特徴とする、請求項３に記載のトランジスタの製造方法。 The method for manufacturing a transistor according to claim 3, wherein the film formation temperature is 200 ° C. or less.
  5. 　前記成膜温度は、１５０℃以下であることを特徴とする、請求項３に記載のトランジスタの製造方法。 The method for manufacturing a transistor according to claim 3, wherein the film formation temperature is 150 ° C. or less.
  6. 　前記半導体層形成工程における成膜圧力が、０．１Ｐａ以下であることを特徴とする、請求項１～５のいずれか一項に記載のトランジスタの製造方法。 The method for manufacturing a transistor according to any one of claims 1 to 5, wherein a film forming pressure in the semiconductor layer forming step is 0.1 Pa or less.
  7. 　前記半導体層は、Ｉｎ、Ｇａ及びＺｎを含む酸化物であることを特徴とする、請求項１～６のいずれか一項に記載のトランジスタの製造方法。 The method for manufacturing a transistor according to any one of claims 1 to 6, wherein the semiconductor layer is an oxide containing In, Ga and Zn.
  8. 　基板と、ゲート電極と、ソース電極と、ドレイン電極と、半導体層とを含むトランジスタであって、
    　前記基板は、樹脂材料を含み、
    　前記半導体層の膜密度が６．１以上であることを特徴とする、トランジスタ。     A transistor comprising: a substrate, a gate electrode, a source electrode, a drain electrode, and a semiconductor layer,
    The substrate includes a resin material,
    The film density of the said semiconductor layer is 6.1 or more, The transistor characterized by the above-mentioned.
  9. 　前記基板の軟化点が、２００℃以下であることを特徴とする、請求項８に記載のトランジスタ。 The transistor according to claim 8, wherein the softening point of the substrate is 200 ° C. or less.
  10. 　前記基板の軟化点が、１５０℃以下であることを特徴とする、請求項８に記載のトランジスタ。 The transistor according to claim 8, wherein the softening point of the substrate is 150 ° C. or less.
  11. 　前記半導体層は、Ｉｎ、Ｇａ及びＺｎを含む酸化物であることを特徴とする、請求項８～１０のいずれか一項に記載のトランジスタ。 The transistor according to any one of claims 8 to 10, wherein the semiconductor layer is an oxide containing In, Ga and Zn.
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JP2012124446A (en) * 2010-04-07 2012-06-28 Kobe Steel Ltd Oxide for semiconductor layer of thin film transistor and sputtering target, and thin film transistor
JP2013004849A (en) * 2011-06-20 2013-01-07 Dainippon Printing Co Ltd Thin film transistor manufacturing method and roll thin film transistor
JP2015029038A (en) * 2013-05-28 2015-02-12 旭硝子株式会社 Semiconductor device and method of manufacturing the same
WO2015029264A1 (en) * 2013-08-29 2015-03-05 株式会社 アルバック Reactive sputtering device
WO2017094547A1 (en) * 2015-11-30 2017-06-08 国立大学法人東京工業大学 Method for manufacturing photoelectric conversion element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124446A (en) * 2010-04-07 2012-06-28 Kobe Steel Ltd Oxide for semiconductor layer of thin film transistor and sputtering target, and thin film transistor
JP2013004849A (en) * 2011-06-20 2013-01-07 Dainippon Printing Co Ltd Thin film transistor manufacturing method and roll thin film transistor
JP2015029038A (en) * 2013-05-28 2015-02-12 旭硝子株式会社 Semiconductor device and method of manufacturing the same
WO2015029264A1 (en) * 2013-08-29 2015-03-05 株式会社 アルバック Reactive sputtering device
WO2017094547A1 (en) * 2015-11-30 2017-06-08 国立大学法人東京工業大学 Method for manufacturing photoelectric conversion element

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