KR20200145912A - Multi-layer channel IZO oxide thin-film transistor fabricated by solution-processed based on solution process using RF power-based plasma treatment, and fabrication method thereof - Google Patents

Multi-layer channel IZO oxide thin-film transistor fabricated by solution-processed based on solution process using RF power-based plasma treatment, and fabrication method thereof Download PDF

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KR20200145912A
KR20200145912A KR1020190073380A KR20190073380A KR20200145912A KR 20200145912 A KR20200145912 A KR 20200145912A KR 1020190073380 A KR1020190073380 A KR 1020190073380A KR 20190073380 A KR20190073380 A KR 20190073380A KR 20200145912 A KR20200145912 A KR 20200145912A
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izo
thin film
plasma treatment
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oxygen plasma
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김성진
김한상
이재윤
선비
구홍보
손호주
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충북대학교 산학협력단
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Abstract

The present invention relates to a method of manufacturing IZO oxide thin film transistor using RF power-based plasma treatment. The method includes the following steps of: forming an insulation film on a substrate including a gate electrode; forming an active layer on the insulation film; conducting an oxygen plasma treatment process on the active layer; and forming source and drain electrodes on the active layer. In the step of forming the active layer, an oxide thin film is formed such that at least two layers of indium-zinc oxide (IZO) thin films are consecutively stacked, and, in the step of conducting the oxygen plasma treatment process, oxygen plasma is generated through an RF generator and a matching box, and the oxygen plasma treatment process is conducted in a way of applying RF power. According to the present invention, since a solution process-type multichannel IZO thin film transistor device is manufactured through oxygen plasma processing, an electric performance property can be improved.

Description

RF 파워 기반의 플라즈마 처리를 이용한 용액공정형 다채널 IZO 산화물 박막 트랜지스터 및 그 제조 방법 {Multi-layer channel IZO oxide thin-film transistor fabricated by solution-processed based on solution process using RF power-based plasma treatment, and fabrication method thereof}Solution-processed multi-channel IZO oxide thin-film transistor fabricated by solution-processed based on solution process using RF power-based plasma treatment, and fabrication method thereof}

본 발명은 IZO 산화물 트랜지스터에 관한 것으로서, 더욱 상세하게는 산화물 트랜지스터(oxide transistor), 디스플레이 백플레인 소자(display backplane device), 유연한 전자소자(flexible device), 투명 전자소자(transparent device), 용액 공정을 이용한 다층 채널 구조 IZO 박막 제작(fabrication of multi-layer channel structure IZO thin films using solution process), 산소 플라즈마 처리(oxygen plasma treatment)를 이용한 트랜지스터 성능 개선, 전기적, 환경적 안정성이 높은 트랜지스터에 관한 것이다.The present invention relates to an IZO oxide transistor, and more particularly, an oxide transistor, a display backplane device, a flexible device, a transparent device, and a solution process. The present invention relates to a fabrication of multi-layer channel structure IZO thin films using solution process, improvement of transistor performance using oxygen plasma treatment, and high electrical and environmental stability.

액정표시장치(liquid crystal display, LCD)와 같은 평판표시장치(flat panel display, FPD)에서는 각각의 화소에 박막 트랜지스터와 같은 능동 소자가 구비되어 표시 소자를 구동한다. 이러한 방식의 표시소자의 구동 방식을 흔히 액티브 매트릭스(active matrix) 구동 방식이라 하는데 상기 액티브 매트릭스 방식에서는 상기 박막 트랜지스터가 각각의 화소에 배치되어 해당 화소를 구동하게 된다.In a flat panel display (FPD) such as a liquid crystal display (LCD), an active element such as a thin film transistor is provided in each pixel to drive the display element. This type of driving method of the display device is commonly referred to as an active matrix driving method. In the active matrix method, the thin film transistor is disposed in each pixel to drive the corresponding pixel.

한편, 일반적인 박막 트랜지스터는 반도체층으로 비정질 실리콘을 이용하여 왔으나, 비정질 실리콘은 전자 이동속도가 느려서 초대형 화면에서는 고해상도 및 고속 구동 능력을 실현하기가 어려웠다. 그래서 비정질 실리콘보다 전자 이동속도가 10배 이상 빠른 산화물 박막 트랜지스터가 등장하였고 이것은 최근 UD(ultra definition) 이상의 고해상도 및 240 Hz 이상의 고속구동에 적합한 소자로 각광받고 있다.On the other hand, general thin film transistors have used amorphous silicon as a semiconductor layer, but amorphous silicon has a slow electron movement speed, making it difficult to realize high resolution and high-speed driving capability on a very large screen. Therefore, oxide thin-film transistors, which have an electron transfer speed more than 10 times faster than that of amorphous silicon, have appeared, and these are recently spotlighted as devices suitable for high resolution over UD (ultra definition) and high-speed driving over 240 Hz.

액정표시장치는 포토리소그래피와 같은 공정에 의해 제작되는데, 포토리소그래피 공정은 패턴 대상 물질 및 포토레지스트의 증착, 마스크를 이용한 노광, 포토레지스트의 현상, 에칭 등의 일련의 과정을 통해 진행되는 공정이다.A liquid crystal display device is manufactured by a process such as photolithography. The photolithography process is a process performed through a series of processes such as deposition of a pattern target material and photoresist, exposure using a mask, development of a photoresist, and etching.

최근, 규소 기반 반도체 소자를 대신할 산화물 반도체에 대한 연구가 널리 진행되고 있다. 재료적인 측면에서는 인듐 산화물(In2O3), 아연 산화물(ZnO), 갈륨 산화물(Ga2O3) 기반의 단일, 이성분계, 삼성분계 화합물에 대한 연구 결과가 보고되고 있다. 한편, 공정적인 측면에서 기존의 진공 증착을 대신한 액상기반 공정에 대한 연구가 진행되고 있다.Recently, research on an oxide semiconductor to replace silicon-based semiconductor devices has been widely conducted. In terms of materials, research results on single, binary, and ternary compounds based on indium oxide (In 2 O 3 ), zinc oxide (ZnO), and gallium oxide (Ga 2 O 3 ) have been reported. On the other hand, in terms of the process, research on a liquid-based process is being conducted instead of the existing vacuum deposition.

산화물 반도체는 수소화된 비정질 규소에 비하여 똑같이 비정질 상을 보이지만, 매우 우수한 이동도(mobility)를 보이기 때문에 고화질 액정표시장치 (LCD)와 능동 유기 발광 다이오드(AMOLED)에 적합하다. 또한, 액상기반 공정을 이용한 산화물 반도체 제조 기술은 고비용의 진공 증착 방법에 비해서 저비용이라는 이점이 있다.Oxide semiconductors show the same amorphous phase as compared to hydrogenated amorphous silicon, but are suitable for high-definition liquid crystal displays (LCDs) and active organic light-emitting diodes (AMOLEDs) because they show very excellent mobility. In addition, the oxide semiconductor manufacturing technology using a liquid-based process has the advantage of being inexpensive compared to the expensive vacuum deposition method.

일반적으로 전자소자 제조 공정에서 박막은 형성된 후에 포토리소그래피 (photolithography)로 인하여 원하는 형태로 패턴화 된다. 통상적인 포토리소그래피 공정은 패턴화 대상 박막 위에 포토레지스트와 같은 감광성 물질을 코팅한 후 광노출 및 현상을 진행하여 포토레지스트 패턴을 형성하고 식각 마스크로 사용하여 패턴화 대상 박막을 식각하는 일련의 단계들을 포함한다. 광에 의해 노출된 포토레지스트 물질이 광화학적으로(photochemically) 변하게 되고 이에 따라 광에 의해 노출된 부분과 그렇지 않은 부분이 화학적으로 다른 구성을 나타내게 된다. 따라서, 적절한 현상 용액에 의해서 두 부분들 중 어느 한 부분이 선택적으로 제거되고 현상액(developing solution)에 의해서 제거되지 않은 부분이 포토레지스트 패턴이 된다.In general, in an electronic device manufacturing process, a thin film is formed and then patterned into a desired shape by photolithography. In a typical photolithography process, a photoresist pattern is formed by coating a photosensitive material such as a photoresist on a thin film to be patterned, followed by light exposure and development, and a series of steps of etching the thin film to be patterned using it as an etching mask. Include. The photoresist material exposed by light is changed photochemically, and thus, a portion exposed by light and a portion not exposed by light exhibit chemically different configurations. Accordingly, one of the two portions is selectively removed by an appropriate developing solution, and a portion not removed by a developing solution becomes a photoresist pattern.

이러한 포토리소그래피법은 박막의 형성, 패터닝, 성막 처리 및 에칭 처리시에 진공 장치 등의 대대적인 설비와 복잡한 공정을 필요로 한다. 또한, 재료 사용 효율이 수 % 정도에 지나지 않아 공정이 종료되면 재사용이 불가하고 폐기할 수 밖에 없으므로 제조 비용이 높고 불필요한 화학 폐기물을 다량 발생시킬 수 있다.Such a photolithography method requires extensive equipment such as a vacuum device and a complex process for forming, patterning, film forming, and etching a thin film. In addition, since the material use efficiency is only a few percent, when the process is finished, it cannot be reused and must be discarded, so manufacturing cost is high and a large amount of unnecessary chemical waste can be generated.

기존에 산화물 트랜지스터를 생산함에 있어서, UV(ultraviolet ray)나 펨토세컨드 레이저 처리(femtosecond laser treatment) 방식을 사용하는 경우, 이에 따른 소자별 성능이 비균등화 되는 문제점이 있다. 또한, 산소 처리(oxygen treatment)를 진행하지 않는 경우, 소자의 전기적 특성이 저하되는 문제점이 있다. 그리고, 산화물 트랜지스터는 전기 부하에 약한 특성을 보이고, IZO 산화물 박막 트랜지스터에서 차지 트랩(charge trap), 백 채널 효과(back channel effect) 등이 발생하는 문제점이 있다.In the conventional oxide transistor production, when an ultraviolet (UV) or femtosecond laser treatment method is used, there is a problem in that the performance of each device is uneven. In addition, when oxygen treatment is not performed, there is a problem in that electrical characteristics of the device are deteriorated. In addition, oxide transistors exhibit weak characteristics against an electric load, and there is a problem in that a charge trap and a back channel effect occur in the IZO oxide thin film transistor.

대한민국 공개특허 10-2008-0082616Republic of Korea Patent Publication 10-2008-0082616

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 진공 증착법이 아닌, 용액 공정법을 이용하여 산화물 박막 트랜지스터를 제작하는 기술을 제공하는데 그 목적이 있다.The present invention has been devised to solve the above problems, and an object thereof is to provide a technology for manufacturing an oxide thin film transistor using a solution process method, not a vacuum deposition method.

또한, 본 발명은 용액 공정 기법을 통해 다층 채널 구조로 제작된 IZO(indium-zinc oxide) 박막 트랜지스터를 제작하는데 그 다른 목적이 있다. In addition, the present invention has another object to fabricate an IZO (indium-zinc oxide) thin film transistor fabricated in a multi-layered channel structure through a solution process technique.

또한, 본 발명은 다층 채널 구조를 이용하여 인터페이스 차지 트랩(interface charge trap) 및 백 채널 효과(back-channel effect) 감소로 인한 우수한 전류 리텐션 스테빌러티(current retention stability)의 특성을 확보하도록 하는데 그 다른 목적이 있다. In addition, the present invention uses a multi-layered channel structure to secure characteristics of excellent current retention stability due to reduced interface charge trap and back-channel effect. It has a different purpose.

또한, 본 발명은 밴드갭이 큰 IZO 박막 트랜지스터 제작을 통해 스위칭 균일성을 확보하는데 그 다른 목적이 있다. In addition, the present invention has another object to secure switching uniformity by fabricating an IZO thin film transistor having a large band gap.

또한, 본 발명은 산소 플라즈마 처리(oxygen plasma treatment)를 이용한 박막의 표면 거칠기 감소를 통한 전기적 성능을 향상시키는데 그 다른 목적이 있다.In addition, another object of the present invention is to improve electrical performance by reducing the surface roughness of a thin film using oxygen plasma treatment.

또한, 본 발명은 전기적, 환경적 안정성이 높은 산화물 박막 트랜지스터를 제작하는데 그 다른 목적이 있다.In addition, the present invention has another object to fabricate an oxide thin film transistor having high electrical and environmental stability.

본 발명의 목적은 이상에서 언급한 목적으로 제한되지 않으며, 언급되지 않은 또 다른 목적들은 아래의 기재로부터 통상의 기술자에게 명확하게 이해될 수 있을 것이다.The object of the present invention is not limited to the above-mentioned object, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

이와 같은 목적을 달성하기 위한 본 발명의 다채널 IZO 산화물 박막 트랜지스터 제조 방법에서, 게이트 전극을 포함하는 기판 상에 절연막을 형성하는 단계, 상기 절연막 상에 활성층을 형성하는 단계, 상기 활성층에 대하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 수행하는 단계 및 상기 활성층 상에 소스 전극 및 드레인 전극을 형성하는 단계를 포함하되, 상기 활성층을 형성하는 단계에서, 2 레이어(layers) 이상의 IZO(indium-zinc oxide) 박막이 연속하여 적층 되도록 산화물 박막을 형성하고, 상기 산소 플라즈마 처리 공정을 수행하는 단계에서, 산소 플라즈마를 발생시키고, RF 파워를 인가하는 방식으로 산소 플라즈마 처리 공정을 수행한다.In the method of manufacturing a multi-channel IZO oxide thin film transistor of the present invention for achieving this object, forming an insulating film on a substrate including a gate electrode, forming an active layer on the insulating film, oxygen plasma for the active layer Including the step of performing an oxygen plasma treatment process and forming a source electrode and a drain electrode on the active layer, wherein in the step of forming the active layer, two or more layers of indium-zinc oxide (IZO) In the step of forming an oxide thin film so that the thin films are continuously stacked and performing the oxygen plasma treatment process, the oxygen plasma treatment process is performed by generating oxygen plasma and applying RF power.

상기 절연막을 형성하는 단계에서, 상기 기판 상에 SiO2를 성장시키는 방식으로 절연막을 형성할 수 있다. In the step of forming the insulating layer, the insulating layer may be formed by growing SiO 2 on the substrate.

상기 활성층을 형성하는 단계에서, IZO 박막을 형성하는 공정을 연속으로 3회 반복하여, 3개의 IZO 박막 레이어 (layer)가 균일하게 적층 되도록 형성할 수 있다. In the step of forming the active layer, the process of forming the IZO thin film may be repeated three times in succession to form three IZO thin film layers uniformly stacked.

본 발명의 다채널 IZO 산화물 박막 트랜지스터는 게이트 전극을 포함하는 기판, 상기 기판 상에 형성되는 절연막, 상기 절연막 상에 형성되는 활성층 및 상기 활성층 상에 형성되는 소스 전극 및 드레인 전극을 포함하되, 상기 활성층은 2 레이어(layers) 이상의 IZO(indium-zinc oxide) 박막이 연속하여 적층 되는 구조이고, 상기 활성층에 대하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 수행하되, 산소 플라즈마를 발생시키고, RF 파워를 인가하는 방식으로 산소 플라즈마 처리 공정을 수행한다. The multi-channel IZO oxide thin film transistor of the present invention includes a substrate including a gate electrode, an insulating film formed on the substrate, an active layer formed on the insulating film, and a source electrode and a drain electrode formed on the active layer, the active layer Is a structure in which two or more layers of IZO (indium-zinc oxide) thin films are continuously stacked, and an oxygen plasma treatment process is performed on the active layer, but oxygen plasma is generated and RF power is applied. In this way, the oxygen plasma treatment process is performed.

상기 절연막은 상기 기판 상에 SiO2를 성장시키는 방식으로 형성될 수 있다. The insulating layer may be formed by growing SiO 2 on the substrate.

상기 활성층은 IZO 박막을 형성하는 공정을 연속으로 3회 반복하여, 3개의 IZO 박막 레이어(layer)가 균일하게 적층 되도록 형성될 수 있다. The active layer may be formed such that a process of forming an IZO thin film is repeated three times in a row so that three IZO thin film layers are uniformly stacked.

본 발명에 의하면, 산소 플라즈마 처리를 통해 용액 공정형 다채널 IZO 박막 트랜지스터 소자를 제조함으로써, 전기적 성능 특성을 향상시킬 수 있다는 효과가 있다. According to the present invention, it is possible to improve electrical performance characteristics by manufacturing a solution-processed multi-channel IZO thin film transistor device through oxygen plasma treatment.

또한, 본 발명에 의하면, 박막의 표면 굴곡과 표면 거칠기가 개선되는 효과가 있다. Further, according to the present invention, there is an effect of improving the surface curvature and surface roughness of the thin film.

또한, 본 발명에 의하면, 산소 플라즈마 처리를 통해 인터페이스 차지 트랩(interface charge trap) 및 백 채널 효과(back-channel effect) 감소로 인한 우수한 전류 리텐션 스테빌러티(current retention stability)를 유지한다는 효과가 있다. In addition, according to the present invention, there is an effect of maintaining excellent current retention stability due to reduction of an interface charge trap and a back-channel effect through oxygen plasma treatment. .

도 1은 본 발명의 일 실시예에 따른 다채널 IZO 산화물 박막 트랜지스터의 제조 공정을 도시한 도면이다.
도 2는 본 발명의 일 실시예에 따른 다채널 IZO 산화물 박막 트랜지스터 소자 구조를 도시한 것이다.
도 3은 본 발명의 일 실시예에 따른 IZO 산화물 박막 트랜지스터의 제조 방법을 보여주는 흐름도이다.
도 4는 본 발명의 일 실시예에 따른 산소 플라즈마 처리 공정을 진행하였을 때, IZO 박막 채널 층의 격자 구조의 변화를 보여주는 도면이다.
도 5는 본 발명의 일 실시예에 따른 멀티 스택(multi stacked) IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 처리(oxygen plasma treatment) RF(radio frequency) 파워(power)에 따른 출력 커브(output curve) 결과를 도시한 그래프이다.
도 6은 본 발명의 일 실시예에 따른 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 처리 RF 파워에 따른 트랜스퍼 커브(transfer curve) 결과를 도시한 그래프이다.
도 7은 본 발명의 일 실시예에 따른 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 RF 파워에 따른 출력 커브와 트랜스퍼 커브를 통해 추출한 전기적 특성을 비교한 표이다.
도 8은 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 표면의 모폴로지(morphology)를 측정한 결과를 나타낸 것이다.
도 9는 본 발명의 일 실시예에 따른 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 처리 RF 파워에 따른 리텐션 스테빌러티 커브(retention stability curve)를 측정한 결과를 나타낸 그래프이다.1 is a diagram illustrating a manufacturing process of a multi-channel IZO oxide thin film transistor according to an embodiment of the present invention.
2 is a diagram illustrating a structure of a multi-channel IZO oxide thin film transistor device according to an embodiment of the present invention.
3 is a flowchart illustrating a method of manufacturing an IZO oxide thin film transistor according to an embodiment of the present invention.
4 is a view showing a change in a lattice structure of an IZO thin film channel layer when an oxygen plasma treatment process is performed according to an embodiment of the present invention.
5 is an output curve according to an oxygen plasma treatment RF (radio frequency) power of a multi-stacked IZO oxide thin film transistor device according to an embodiment of the present invention. It is a graph shown.
6 is a graph showing a result of a transfer curve according to an oxygen plasma treatment RF power of a multi-stack IZO oxide thin film transistor device according to an embodiment of the present invention.
7 is a table comparing electrical characteristics extracted through a transfer curve and an output curve according to an oxygen plasma RF power of a multi-stack IZO oxide thin film transistor device according to an embodiment of the present invention.
8 shows a result of measuring the morphology of the surface of a multi-stack IZO oxide thin film transistor device.
9 is a graph showing a measurement result of a retention stability curve according to RF power of oxygen plasma treatment of a multi-stack IZO oxide thin film transistor device according to an embodiment of the present invention.

본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다.In the present invention, various modifications may be made and various embodiments may be provided, and specific embodiments will be illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to a specific embodiment, it is to be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서 상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.

다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 갖고 있다. 일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥 상 갖는 의미와 일치하는 의미를 갖는 것으로 해석되어야 하며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

또한, 첨부 도면을 참조하여 설명함에 있어, 도면 부호에 관계없이 동일한 구성 요소는 동일한 참조 부호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다. 본 발명을 설명함에 있어서 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명을 생략한다.In addition, in the description with reference to the accompanying drawings, the same reference numerals are assigned to the same components regardless of the reference numerals, and redundant descriptions thereof will be omitted. In describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

도 1은 본 발명의 일 실시예에 따른 다채널 IZO 산화물 박막 트랜지스터의 제조 공정을 도시한 도면이고, 도 2는 본 발명의 일 실시예에 따른 다채널 IZO 산화물 박막 트랜지스터 소자 구조를 도시한 것이다. 1 is a diagram illustrating a manufacturing process of a multi-channel IZO oxide thin film transistor according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a structure of a multi-channel IZO oxide thin film transistor according to an embodiment of the present invention.

도 1 및 도 2를 참조하면, 본 발명의 다채널 IZO 산화물 박막 트랜지스터는 기판(substrate)(10), 절연막(insulator layer)(110), 활성층(active layer)(120), 소스 전극(source electrode)((130) 및 드레인 전극(drain electrode)(140)을 포함한다. 1 and 2, the multi-channel IZO oxide thin film transistor of the present invention includes a substrate 10, an insulating layer 110, an active layer 120, and a source electrode. ) (130) and a drain electrode (140).

본 발명의 일 실시예에서 산화물 박막 트랜지스터는 탑 컨택트 바텀 게이트(top-contact bottom-gate) 구조로 제작된다. In an embodiment of the present invention, the oxide thin film transistor is fabricated in a top-contact bottom-gate structure.

기판(10)은 게이트(gate) 전극을 포함한다. 본 발명의 일 실시예에서 기판(10)은 N형(n-type)으로 헤비하게(heavily) 도핑된(doped) 600 μm 두께의 실리콘(Si) 웨이퍼 기판으로 구현되며, 게이트 전극으로 사용된다.The substrate 10 includes a gate electrode. In an embodiment of the present invention, the substrate 10 is implemented as a 600 μm-thick silicon (Si) wafer substrate that is heavily doped with an n-type, and is used as a gate electrode.

절연막(110)은 기판(10) 상에 형성된다. 본 발명의 일 실시예에서 절연막(110)은 기판 상에 SiO2를 성장시키는 방식으로 형성될 수 있다. 예를 들어, 퍼니스(furnace)에서 열 산화(thermal oxidation) 공정을 통해 100 nm의 SiO2를 성장시키는 방식으로 형성될 수 있다.The insulating film 110 is formed on the substrate 10. In an embodiment of the present invention, the insulating layer 110 may be formed by growing SiO 2 on the substrate. For example, it may be formed by growing SiO 2 of 100 nm through a thermal oxidation process in a furnace.

절연막(110) 형성 후, 황산과 과산화수소를 3:1 비율로 하여 표준 세정 중 하나인 SPM(surfuric acid peroxide mixture) 클리닝(cleaning) 공정을 실시한다.After the insulating layer 110 is formed, a 3:1 ratio of sulfuric acid and hydrogen peroxide is used to perform a SPM (surfuric acid peroxide mixture) cleaning process.

SPM 클리닝(cleaning) 공정은 H2SO4와 H2O2의 비율을 3:1로 핫 플레이트(hot plate)에서 20분 동안 60 °C 로 진행하며, 남아있는 용액을 제거하기 위해 초청정수인 D.I 워터(water)로 린스(rinse) 후, 아세톤(acetone)과 IPA에 담가 20분간 소니케이팅(sonicating)을 실시한다. 소니케이팅(Sonicating) 실시 후 남아있는 IPA 용액을 N2 블로윙(blowing)을 통해 제거한 후, 완전한 드라잉(drying)을 위해 배큠 오븐(vacuum oven)에서 1시간 동안 150 °C에서 베이킹(baking)한다.In the SPM cleaning process, the ratio of H 2 SO 4 and H 2 O 2 is 3:1 and proceeds at 60 °C for 20 minutes on a hot plate, and DI water, which is ultra-clean water, is used to remove the remaining solution. After rinsing with water, soaking in acetone and IPA is performed for 20 minutes. After sonicating, the remaining IPA solution is removed through N 2 blowing, and then baking at 150 °C for 1 hour in a vacuum oven for complete drying. do.

활성층(120)은 절연막(110) 상에 형성된다. 본 발명에서 활성층(120)은 2 레이어(layers) 이상의 IZO(indium-zinc oxide) 박막이 연속하여 적층되는 구조이다. The active layer 120 is formed on the insulating layer 110. In the present invention, the active layer 120 has a structure in which two or more layers of indium-zinc oxide (IZO) thin films are continuously stacked.

본 발명의 일 실시예에서 활성층(120)은 IZO 박막을 형성하는 공정을 연속으로 3회 반복하여, 3개의 IZO 박막 레이어(layer)가 균일하게 적층되도록 형성될 수 있다. 더 상세하게는, IZO 용액을 1500 rpm의 속도로 스핀 코팅(spin-coating)을 진행하여, 30 nm 두께의 IZO 반도체 박막을 제작하고, 그 후 퍼니스(furnace)에서 400 ℃의 온도에서 2시간동안 어닐링(annealing)을 실시하는 과정을 통해 IZO 박막을 생성하고, 이러한 과정을 3회 반복하여 균일한 3 레이어의 연속적인 IZO 박막(채널)을 형성한다.In an embodiment of the present invention, the active layer 120 may be formed such that a process of forming an IZO thin film is repeated three times in a row so that three IZO thin film layers are uniformly stacked. More specifically, spin-coating the IZO solution at a speed of 1500 rpm to prepare an IZO semiconductor thin film with a thickness of 30 nm, and then in a furnace at a temperature of 400 °C for 2 hours. An IZO thin film is formed through an annealing process, and this process is repeated three times to form a continuous IZO thin film (channel) of three uniform layers.

소스 전극(130) 및 드레인 전극(140)은 활성층(120) 상에 형성된다. 본 발명에서 소스 전극(130) 및 드레인 전극(140)을 제작하기 위해, DC 마그네트론 스퍼터링 시스템(DC magnetron sputtering system)을 사용하여, Al 타겟(target)과 쉐도우 마스크(shadow mask)를 이용한 진공 증착을 통해, DC 파워(power)와, 챔버(chamber) 내에 실제 공정 압력을 각각 150 W, 1.5 × 10-2 Torr로 설정하고, 100 nm 두께의 알루미늄(Al) 상부 전극을 증착하는 방식으로 소스 전극(130) 및 드레인 전극(140)을 형성한다. The source electrode 130 and the drain electrode 140 are formed on the active layer 120. In order to manufacture the source electrode 130 and the drain electrode 140 in the present invention, vacuum deposition using an Al target and a shadow mask is performed using a DC magnetron sputtering system. Through this, DC power and the actual process pressure in the chamber are set to 150 W, 1.5 × 10 -2 Torr, respectively, and the source electrode ( 130) and a drain electrode 140 are formed.

본 발명에서 활성층(120)에 대하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 수행한다. In the present invention, an oxygen plasma treatment process is performed on the active layer 120.

도 3은 본 발명의 일 실시예에 따른 IZO 산화물 박막 트랜지스터의 제조 방법을 보여주는 흐름도이다.3 is a flowchart illustrating a method of manufacturing an IZO oxide thin film transistor according to an embodiment of the present invention.

도 3을 참조하면, 본 발명의 IZO 산화물 박막 트랜지스터 제조 방법은 게이트 전극을 포함하는 기판(10) 상에 절연막(110)을 형성하는 단계(S110), 절연막(110) 상에 활성층(120)을 형성하는 단계(S120), 활성층(120)에 산소 플라즈마 처리를 실시하는 단계(S130) 및 활성층(120) 상에 소스 전극(130) 및 드레인 전극(140)을 형성하는 단계(S140)를 포함한다.Referring to FIG. 3, in the method of manufacturing an IZO oxide thin film transistor of the present invention, the step of forming an insulating film 110 on a substrate 10 including a gate electrode (S110), and forming an active layer 120 on the insulating film 110 Forming (S120), performing oxygen plasma treatment on the active layer 120 (S130), and forming the source electrode 130 and the drain electrode 140 on the active layer 120 (S140). .

절연막을 형성하는 단계(S110)에서, 기판(10) 상에 SiO2를 성장시키는 방식으로 절연막을 형성할 수 있다.In the step of forming the insulating film (S110), the insulating film may be formed by growing SiO 2 on the substrate 10.

활성층을 형성하는 단계(S120)에서, 2 레이어(layers) 이상의 IZO(indium-zinc oxide) 박막이 연속하여 적층 되도록 활성층(120)을 형성한다. 본 발명의 일 실시예에서 활성층(120)은 IZO 박막을 형성하는 공정을 연속으로 3회 반복하여, 3개의 IZO 박막 레이어(layer)가 균일하게 적층 되도록 형성될 수 있다. 더 상세하게는, IZO 용액을 1500 rpm의 속도로 스핀 코팅(spin-coating)을 진행하여, 30nm 두께의 IZO 반도체 박막을 제작하고, 그 후 퍼니스(furnace)에서 400 ℃의 온도에서 2시간동안 어닐링(annealing)을 실시하는 과정을 통해 IZO 박막을 생성하고, 이러한 과정을 3회 반복하여 균일한 3 레이어의 연속적인 IZO 박막(채널)을 형성한다.In the step S120 of forming the active layer, the active layer 120 is formed so that two or more layers of indium-zinc oxide (IZO) thin films are successively stacked. In an embodiment of the present invention, the active layer 120 may be formed so that three IZO thin film layers are uniformly stacked by repeating the process of forming an IZO thin film three times in a row. More specifically, spin-coating the IZO solution at a speed of 1500 rpm to prepare a 30 nm-thick IZO semiconductor thin film, followed by annealing at a temperature of 400° C. for 2 hours in a furnace. An IZO thin film is formed through the process of performing (annealing), and this process is repeated three times to form a continuous three-layer IZO thin film (channel).

다음, 활성층(120)에 대하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 수행한다(S130). Next, an oxygen plasma treatment process is performed on the active layer 120 (S130).

소스 전극 및 드레인 전극을 형성하는 단계(S140)에서, 알루미늄(Al)을 증착하여 소스 전극 및 드레인 전극을 형성할 수 있다.In the step S140 of forming the source electrode and the drain electrode, aluminum (Al) may be deposited to form the source electrode and the drain electrode.

이제 도 1 내지 도 3을 참조하여, 본 발명에서 용액 공정형 다채널 IZO 산화물 박막 트랜지스터의 실제 제작 과정과 실험 과정을 예시하면 다음과 같다. Now, referring to FIGS. 1 to 3, an actual manufacturing process and an experimental process of the solution-processed multi-channel IZO oxide thin film transistor in the present invention will be illustrated as follows.

도 1 및 도 2는 본 발명의 산화물 트랜지스터를 실제로 제작하기 위한, 멀티 스택(multi stacked) IZO(indium-zinc oxide) 박막 트랜지스터의 구조를 나타낸다. 본 발명에서 산화물 트랜지스터는 탑 컨택트 바텀 게이트(top-contact bottom-gate) 구조로 제작된다. 그리고, 기판이자 게이트(gate) 전극으로 사용하기 위해 헤비하게(heavily) 도핑된(doped) n형(n-type) 실리콘 웨이퍼 기판(600 um)를 사용하였으며, 절연막 형성을 위해 퍼니스(furnace)에서 열 산화(thermal oxidation) 공정을 통해 100 nm의 SiO2를 성장시켰다. 그 후 그 후 황산과 과산화수소를 3:1 비율로 하여 표준 세정 중 하나인 SPM(surfuric acid peroxide mixture) 클리닝 공정을 실시하였다.1 and 2 show the structure of a multi-stacked indium-zinc oxide (IZO) thin film transistor for actually fabricating the oxide transistor of the present invention. In the present invention, the oxide transistor is fabricated in a top-contact bottom-gate structure. In addition, a heavily doped n-type silicon wafer substrate (600 um) was used for use as a substrate and a gate electrode, and in a furnace to form an insulating film. SiO 2 of 100 nm was grown through a thermal oxidation process. After that, the SPM (surfuric acid peroxide mixture) cleaning process was performed using sulfuric acid and hydrogen peroxide in a ratio of 3:1.

SPM 클리닝(cleaning) 공정은 H2SO4와 H2O2의 비율을 3:1로 핫 플레이트(hot plate)에서 20분 동안 60 °C 로 진행하며, 남아있는 용액을 제거하기 위해 초청정수인 D.I 워터(water)로 린스(rinse) 후, 아세톤(acetone)과 IPA에 담가 20분간 소니케이팅(sonicating)을 실시한다. 소니케이팅(Sonicating) 실시 후 남아있는 IPA 용액을 N2 블로잉(blowing)을 통해 제거한 후, 완전한 드라잉(drying)을 위해 진공 오븐(vacuum oven)에서 1시간 동안 150 °C로 베이킹(baking)한다.In the SPM cleaning process, the ratio of H 2 SO 4 and H 2 O 2 is 3:1 and proceeds at 60 °C for 20 minutes on a hot plate, and DI water, which is ultra-clean water, is used to remove the remaining solution. After rinsing with water, soaking in acetone and IPA is performed for 20 minutes. After sonicating, the remaining IPA solution is removed through N 2 blowing, and then baked at 150 °C for 1 hour in a vacuum oven for complete drying. do.

그리고, 용액 공정형 IZO 산화물 박막 트랜지스터를 제작하기 위해, 시약인 indium nitrate hydrate [In(NO3)3·xH2O], zinc acetate dihydrate [Zn(CH3COO)2·2H2O]를 용질로 사용한다. 그리고, 0.1M의 인듐(indium), 아연(zinc) 용액을 제작하기 위해 용매로써 2-methoxyethanol을 사용하고, 시약을 용해시키기 위해 안정제의 역할을 하는 acetylacetone을 인듐(indium) 용액과 아연(zinc) 용액에 각각 첨가하고, 인듐 용액에는 빠른 반응을 위해 촉매로 NH3를 첨가한다. In addition, in order to fabricate a solution-processed IZO oxide thin film transistor, indium nitrate hydrate [In(NO 3 ) 3 ·xH 2 O], zinc acetate dihydrate [Zn(CH 3 COO) 2 ·2H 2 O] are used as a Use as. In addition, 2-methoxyethanol is used as a solvent to prepare a 0.1M indium and zinc solution, and acetylacetone, which acts as a stabilizer to dissolve the reagent, is used as an indium solution and zinc. Each is added to the solution, and NH 3 is added to the indium solution as a catalyst for rapid reaction.

안정제와 촉매를 첨가하여 제작한 인듐(indium) 용액과 아연(zinc) 용액을 700 rpm의 속도로 1시간 동안 60 ℃에서 스터링(stirring)하였다. 이후 인듐(indium) 용액과 아연(zinc) 용액을 1 : 1의 비율로 혼합하여 IZO 용액을 제작하여 500 rpm의 속도로 2시간 동안 상온에서 스터링(stirring)을 진행하였다. 그리고, 웨이퍼에 박막을 제작하기 위해 IZO 용액을 1500 rpm의 속도로 스핀 코팅(spin-coating)을 진행해 30 nm 두께의 IZO 반도체 박막을 제작하였다. 그 후, 핫 플레이트(hot plate)에서 400 ℃의 온도에서 2시간동안 어닐링(annealing)을 실시하였다. 이후 위의 과정을 반복하여 총 3층의 IZO 박막(채널)을 균일하게 형성하였다.The indium solution and zinc solution prepared by adding a stabilizer and a catalyst were stirred at 60° C. for 1 hour at a speed of 700 rpm. Thereafter, an IZO solution was prepared by mixing an indium solution and a zinc solution in a ratio of 1:1, and stirring was performed at room temperature for 2 hours at a speed of 500 rpm. In addition, in order to form a thin film on the wafer, spin-coating of the IZO solution was performed at a speed of 1500 rpm to prepare a 30 nm-thick IZO semiconductor thin film. Thereafter, annealing was performed on a hot plate at a temperature of 400° C. for 2 hours. Thereafter, the above process was repeated to uniformly form a total of three IZO thin films (channels).

표준 세정을 마친 후, IZO 박막에 대하여 분자 빔 에피택시 시스템(molecular beam epitaxy system)을 이용하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 진행하였다. 이때 메인 프로세스 챔버(main process chamber)에 소자를 로딩(loading)한 후에 진공도를 1 × 10-3 torr가 될 때까지 펌핑 다운(pumping down)한 후, 산소(oxygen) 가스를 이용하여 퍼지(purge) 과정을 진행하다가 다시 1 × 10-3 torr까지 펌핑(pumping)시켰다. 그 후, RF 제너레이터(generator)와 매칭박스(matching box)를 이용하여 플라즈마(plasma)를 발생시킨 후에 RF(Radio Frequency) 제너레이터(generator)의 파워(power)를 120 W(105 W 이상 내지 135 W 미만), 150 W(135 W 이상 내지 165 W 미만), 180 W(165 W 이상 내지 195 W 미만), 210 W(195 W 이상 내지 225 W 미만)로 변경시키면서 3분 동안 인가하여 플라즈마 처리하였다. After completing the standard cleaning, the IZO thin film was subjected to an oxygen plasma treatment process using a molecular beam epitaxy system. At this time, after loading the element into the main process chamber, pumping down until the degree of vacuum becomes 1 × 10 -3 torr, and then purging using oxygen gas. ) During the process, it was pumped again to 1 × 10- 3 torr. After that, after generating plasma using an RF generator and a matching box, the power of the RF (Radio Frequency) generator is set to 120 W (105 W or more to 135 W). Less than), 150 W (more than 135 W to less than 165 W), 180 W (more than 165 W to less than 195 W), 210 W (more than 195 W to less than 225 W) was applied for 3 minutes while plasma treatment.

최종적으로 소스 전극(130) 및 드레인 전극(140)을 증착하기 위해, DC 마그네트론 스퍼터링 시스템(DC magnetron sputtering system)을 사용하여, 알루미늄(Al) 타겟(target)과 쉐도우 마스크(shadow mask)를 이용한 진공 증착을 실시하였다. 진공 증착을 위한 프로세스 챔버(process chamber)의 기본 압력(base pressure)를 1.0 x 10-2 torr의 압력까지 로터리 펌프(rotary pump)를 통해 펌핑 다운(pumping down)한 후, TMP를 구동하여 프로세스 챔버(process chamber)가 2.0 x 10-5 torr 이하의 고진공이 되도록 펌핑을 실시하였다. 박막의 질(quality)을 위해 2시간 이상 펌핑(pumping)한 후 아르곤 가스(Ar gas)를 30 sccm을 주입하면서 실제 공정 압력을 1.5 × 10-2 Torr로 맞춘 후, DC 파워를 150 W 인가하여 10분 동안 100 nm의 알루미늄(Al)을 증착하였다. 이후 반도체 파라미터 측정 장비인 keithley 4200을 사용하여 상온의 암실에서 소자의 전기적 특성을 측정하였다.In order to finally deposit the source electrode 130 and the drain electrode 140, a DC magnetron sputtering system was used, and a vacuum using an aluminum (Al) target and a shadow mask. Evaporation was carried out. After pumping down the base pressure of the process chamber for vacuum deposition to a pressure of 1.0 x 10 -2 torr through a rotary pump, the TMP is driven to the process chamber. Pumping was performed so that the (process chamber) became a high vacuum of 2.0 x 10 -5 torr or less. After pumping for more than 2 hours for the quality of the thin film, 30 sccm is injected with Ar gas, and the actual process pressure is set to 1.5 × 10 -2 Torr, and then DC power is applied to 150 W. 100 nm of aluminum (Al) was deposited for 10 minutes. After that, the electrical properties of the device were measured in a dark room at room temperature using a semiconductor parameter measuring device, keithley 4200.

도 4는 본 발명의 일 실시예에 따른 산소 플라즈마 처리 공정을 진행하였을 때, IZO 박막 채널 층의 격자 구조의 변화를 보여주는 도면이다. 4 is a view showing a change in a lattice structure of an IZO thin film channel layer when an oxygen plasma treatment process is performed according to an embodiment of the present invention.

도 4를 참조하면, IZO 박막 채널 층은 산소 원자와 금속 원자 간의 결합으로 이루어져 있는데, 산소 원자가 빠져나간 자리에 산소 결함(oxygen vacancy)이 생기게 된다. 본 발명에서는 산소 플라즈마 처리(oxygen plasma treatment)를 통해 산소 결함에 산소 원자가 결합할 수 있게 하고, 다른 산소 원자와 금속 원자의 결합물과의 결합을 촉구한다.Referring to FIG. 4, the IZO thin film channel layer consists of a bond between an oxygen atom and a metal atom, and an oxygen vacancy occurs at a site where the oxygen atom escapes. In the present invention, oxygen atoms can be bonded to oxygen defects through oxygen plasma treatment, and bonding of other oxygen atoms and metal atoms is promoted.

도 5는 본 발명의 일 실시예에 따른 멀티 스택(multi stacked) IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 처리(oxygen plasma treatment) RF 파워(power)에 따른 출력 커브(output curve) 결과를 도시한 그래프이다. FIG. 5 is a graph showing output curve results according to RF power of oxygen plasma treatment of a multi-stacked IZO oxide thin film transistor device according to an embodiment of the present invention. .

도 5에서 산소 플라즈마 처리(oxygen plasma treatment)를 산소 10 sccm으로 3분 동안 RF 파워를 인가하여 플라즈마 처리를 진행하였는데, 이때 RF 파워를 각각 (a) 120 W(105 W 이상 내지 135 W 미만), (b) 150 W(135 W 이상 내지 165 W 미만), (c) 180 W(165 W 이상 내지 195 W 미만), (d) 210 W(195 W 이상 내지 225 W 미만)로 인가하여 플라즈마 처리를 진행한 결과를 도시한 그래프이다. In FIG. 5, plasma treatment was performed by applying RF power for 3 minutes with oxygen plasma treatment of 10 sccm of oxygen, and at this time, the RF power was respectively (a) 120 W (105 W to less than 135 W), (b) 150 W (more than 135 W to less than 165 W), (c) 180 W (more than 165 W to less than 195 W), (d) 210 W (more than 195 W to less than 225 W) plasma treatment It is a graph showing the result of progress.

도 5를 참조하면, RF 파워를 120 W(105 W 이상 내지 135 W 미만) 인가하여 플라즈마 처리를 진행한 소자의 전기적 성능(a)에 비해 RF 파워를 150 W(135 W 이상 내지 165 W 미만) 인가하여 플라즈마 처리를 진행한 소자의 전기적 성능(b)이 월등히 향상된 것을 알 수 있다.Referring to FIG. 5, the RF power is 150 W (135 W or more to less than 165 W) compared to the electrical performance (a) of the plasma-treated device by applying RF power of 120 W (105 W to less than 135 W). It can be seen that the electrical performance (b) of the device subjected to plasma treatment by applying it is remarkably improved.

도 6은 본 발명의 일 실시예에 따른 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 처리 RF 파워에 따른 트랜스퍼 커브(transfer curve) 결과를 도시한 그래프이다.6 is a graph showing a result of a transfer curve according to an oxygen plasma treatment RF power of a multi-stack IZO oxide thin film transistor device according to an embodiment of the present invention.

도 6에서, 산소 플라즈마 처리(oxygen plasma treatment)를 산소 10 sccm으로 3분 동안 RF 파워를 인가하여 플라즈마 처리를 진행하였는데, 이때 RF 파워를 각각 (a) 120 W(105 W 이상 내지 135 W 미만), (b) 150 W(135 W 이상 내지 165 W 미만), (c) 180 W(165 W 이상 내지 195 W 미만), (d) 210 W(195 W 이상 내지 225 W 미만)로 인가하여 플라즈마 처리를 진행한 결과를 도시한 그래프이다. In FIG. 6, plasma treatment was performed by applying RF power for 3 minutes with oxygen plasma treatment of 10 sccm of oxygen, and at this time, the RF power was respectively (a) 120 W (over 105 W to less than 135 W) , (b) 150 W (more than 135 W to less than 165 W), (c) 180 W (more than 165 W to less than 195 W), (d) plasma treatment by applying at 210 W (more than 195 W to less than 225 W) It is a graph showing the result of proceeding.

도 6에서 바이어스 전압(bias voltage)를 30 V 인가하였으며, 게이트 전압(Vgs)를 -10 ~ 30 V까지 스윕(sweep)하였다. In FIG. 6, a bias voltage of 30 V was applied, and a gate voltage Vgs was swept from -10 to 30 V.

도 6을 참조하면, RF 파워를 150 W(135 W 이상 내지 165 W 미만)를 인가하여 플라즈마 처리(plasma treatment)를 진행한 소자의 경우(b), 다른 소자에 비해 0 V 근처에서 빠르게 턴온(turn-on)되어 트랜스퍼 커브(transfer curve)를 이루고 있으며, 전자 이동도(electron mobility)와 문턱전압(threshold voltage) 역시 향상된 것을 알 수 있다.Referring to FIG. 6, in the case of a device subjected to plasma treatment by applying RF power of 150 W (more than 135 W to less than 165 W) (b), it turns on faster near 0 V than other devices ( It can be seen that it is turned on to form a transfer curve, and electron mobility and threshold voltage are also improved.

도 7은 본 발명의 일 실시예에 따른 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 RF 파워에 따른 출력 커브와 트랜스퍼 커브를 통해 추출한 전기적 특성을 비교한 표이다. 7 is a table comparing electrical characteristics extracted through a transfer curve and an output curve according to an oxygen plasma RF power of a multi-stack IZO oxide thin film transistor device according to an embodiment of the present invention.

도 7에서는 각 소자들의 전기적 성능 측정은 반도체 파라미터 측정 장비인 keithley 4200을 사용하여 상온의 암실에서 전기적 특성을 측정하였다. 그리고, RF 파워를 150 W (135 W 이상 내지 165 W 미만)를 인가하여 플라즈마 처리를 진행한 IZO 소자는 RF 파워를 120 W (105 W 이상 내지 135 W 미만) 인가하여 플라즈마 처리를 진행한 IZO 소자에 비해 전자 이동도, 전류 점멸비(on-off current ratio), 문턱전압, 서브쓰레드홀드 스윙(subthreshold swing, SS)값 모두 향상된 것을 알 수 있다.In FIG. 7, electrical properties of each device were measured in a dark room at room temperature using a semiconductor parameter measuring device, keithley 4200. In addition, the IZO device subjected to plasma treatment by applying RF power of 150 W (over 135 W to less than 165 W) is the IZO device subjected to plasma treatment by applying RF power of 120 W (over 105 W to less than 135 W) Compared to that, it can be seen that electron mobility, on-off current ratio, threshold voltage, and subthreshold swing (SS) values are all improved.

도 8은 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 표면의 모폴로지(morphology)를 측정한 결과를 나타낸 것이다.8 shows a result of measuring the morphology of the surface of a multi-stack IZO oxide thin film transistor device.

도 8은 BRUKER사의 ICON AFM(atomic force microscope)을 사용하여 제작한 멀티 스택(multi stacked) IZO 산화물 박막 트랜지스터 소자의 표면의 모폴로지(morphology)를 500 nm × 500 nm 크기로 측정한 결과이다. 8 is a result of measuring the morphology of the surface of a multi-stacked IZO oxide thin film transistor device manufactured using BRUKER's ICON atomic force microscope (AFM) in a size of 500 nm × 500 nm.

도 8 (a)는 RF 파워를 120 W(105 W 이상 내지 135 W 미만) 인가하여 산소 플라즈마 처리(oxygen plasma treatment)를 진행한 멀티 레이어(multi-layers) IZO 박막의 표면을 측정한 것이며, 도 8 (b)는 RF 파워를 150 W(135 W 이상 내지 165 W 미만) 인가하여 산소 플라즈마 처리를 진행한 멀티 레이어 IZO 박막의 표면을 측정한 것이다. 또한 도 8 (c)는 RF 파워를 180 W(165 W 이상 내지 195 W 미만) 인가하여 산소 플라즈마 처리를 진행한 멀티 레이어 IZO 박막의 표면을 측정한 것이며, 도 8 (d)는 RF 파워를 210 W(195 W 이상 내지 225 W 미만) 인가하여 산소 플라즈마 처리를 진행한 멀티 레이어 IZO 박막의 표면을 측정한 것이다. 8 (a) is a measurement of the surface of a multi-layers IZO thin film subjected to oxygen plasma treatment by applying RF power of 120 W (over 105 W to less than 135 W). 8 (b) is a measurement of the surface of a multi-layer IZO thin film subjected to oxygen plasma treatment by applying RF power of 150 W (more than 135 W to less than 165 W). In addition, FIG. 8 (c) is a measurement of the surface of a multi-layer IZO thin film subjected to oxygen plasma treatment by applying RF power of 180 W (more than 165 W to less than 195 W), and FIG. 8 (d) shows RF power of 210 W (195 W or more to 225 W) was applied to measure the surface of a multi-layer IZO thin film treated with oxygen plasma.

도 8 (e)는 (a), (b), (c), (d) 의 RMS 거칠기(roughness)를 요약한 그래프이다. 8 (e) is a graph summarizing the RMS roughness of (a), (b), (c), and (d).

결과적으로 120 W 보다 높은 RF 파워를 인가하여 산소 플라즈마 처리를 진행하면 표면의 굴곡이 적게 나타나는 것을 볼 수 있으며, 박막의 표면 거칠기(root mean square : RMS) 또한 감소하여 트랜지스터의 전기적 성능 향상에 효과가 있음을 알 수 있다. 그리고, AFM 측정 분석 결과 RF 파워를 150 W(135 W 이상 내지 165 W 미만) 인가하였을 때 IZO 채널 층의 표면의 굴곡과 표면 거칠기가 가장 개선되었다는 것을 알 수 있다.As a result, it can be seen that when oxygen plasma treatment is performed by applying RF power higher than 120 W, the surface curvature appears less, and the surface roughness (root mean square: RMS) of the thin film is also reduced, which is effective in improving the electrical performance of the transistor. You can see that there is. And, as a result of AFM measurement analysis, it can be seen that when the RF power is applied at 150 W (over 135 W to less than 165 W), the curvature and surface roughness of the surface of the IZO channel layer are most improved.

도 9는 본 발명의 일 실시예에 따른 멀티 스택 IZO 산화물 박막 트랜지스터 소자의 산소 플라즈마 처리 RF 파워에 따른 리텐션 스테빌러티 커브(retention stability curve)를 측정한 결과를 나타낸 그래프이다.9 is a graph showing a measurement result of a retention stability curve according to RF power of oxygen plasma treatment of a multi-stack IZO oxide thin film transistor device according to an embodiment of the present invention.

도 9를 참조하면, RF 파워를 120 W(105 W 이상 내지 135 W 미만) 인가하여 산소 플라즈마 처리를 진행한 소자는 전류가 유지되지 못하고 증가했다가 감소하는 모습을 볼 수 있었지만, RF 파워를 150 W(135 W 이상 내지 165 W 미만) 인가하여 산소 플라즈마를 진행한 소자는 시간이 증가하여도 거의 비슷하게 유지되는 모습을 확인할 수 있다.Referring to FIG. 9, in the device subjected to oxygen plasma treatment by applying RF power of 120 W (over 105 W to less than 135 W), the current was not maintained and increased and decreased, but the RF power was increased to 150 It can be seen that the device in which the oxygen plasma was applied by applying W (more than 135 W to less than 165 W) maintains almost the same as the time increases.

이상 본 발명을 몇 가지 바람직한 실시예를 사용하여 설명하였으나, 이들 실시예는 예시적인 것이며 한정적인 것이 아니다. 본 발명이 속하는 기술분야에서 통상의 지식을 지닌 자라면 본 발명의 사상과 첨부된 특허청구범위에 제시된 권리범위에서 벗어나지 않으면서 다양한 변화와 수정을 가할 수 있음을 이해할 것이다.The present invention has been described above using several preferred embodiments, but these embodiments are illustrative and not limiting. Those of ordinary skill in the art to which the present invention pertains will understand that various changes and modifications can be made without departing from the spirit of the present invention and the scope of the rights presented in the appended claims.

10 기판 110 절연막
120 활성층 130 소스 전극
140 드레인 전극10 Substrate 110 Insulation film
120 active layer 130 source electrode
140 drain electrode

Claims (6)

게이트 전극을 포함하는 기판 상에 절연막을 형성하는 단계;
상기 절연막 상에 활성층을 형성하는 단계;
상기 활성층에 대하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 수행하는 단계; 및
상기 활성층 상에 소스 전극 및 드레인 전극을 형성하는 단계를 포함하되,
상기 활성층을 형성하는 단계에서, 2 레이어(layers) 이상의 IZO(indium-zinc oxide) 박막이 연속하여 적층되도록 산화물 박막을 형성하고,
상기 산소 플라즈마 처리 공정을 수행하는 단계에서, 산소 플라즈마를 발생시키고, RF 파워를 인가하는 방식으로 산소 플라즈마 처리 공정을 수행하는 것을 특징으로 하는 다채널 IZO 산화물 박막 트랜지스터 제조 방법.
Forming an insulating film on a substrate including a gate electrode;
Forming an active layer on the insulating layer;
Performing an oxygen plasma treatment process on the active layer; And
Including the step of forming a source electrode and a drain electrode on the active layer,
In the step of forming the active layer, an oxide thin film is formed such that two or more layers of indium-zinc oxide (IZO) thin films are continuously stacked,
In the step of performing the oxygen plasma treatment process, the oxygen plasma treatment process is performed by generating oxygen plasma and applying RF power to the multi-channel IZO oxide thin film transistor manufacturing method.
 청구항 1에 있어서,
상기 절연막을 형성하는 단계에서, 상기 기판 상에 SiO2를 성장시키는 방식으로 절연막을 형성하는 것을 특징으로 하는 다채널 IZO 산화물 박막 트랜지스터 제조 방법.
The method according to claim 1,
In the step of forming the insulating film, the method of manufacturing a multi-channel IZO oxide thin film transistor, characterized in that forming an insulating film by growing SiO 2 on the substrate.
 청구항 1에 있어서,
상기 활성층을 형성하는 단계에서, IZO 박막을 형성하는 공정을 연속으로 3회 반복하여, 3개의 IZO 박막 레이어(layer)가 균일하게 적층되도록 형성하는 것을 특징으로 하는 다채널 IZO 산화물 박막 트랜지스터 제조 방법.
The method according to claim 1,
In the step of forming the active layer, a process of forming an IZO thin film is repeated three times in succession to form three IZO thin film layers uniformly stacked.
 게이트 전극을 포함하는 기판;
상기 기판 상에 형성되는 절연막;
상기 절연막 상에 형성되는 활성층; 및
상기 활성층 상에 형성되는 소스 전극 및 드레인 전극을 포함하되,
상기 활성층은 2 레이어(layers) 이상의 IZO(indium-zinc oxide) 박막이 연속하여 적층 되는 구조이고,
상기 활성층에 대하여 산소 플라즈마 처리(oxygen plasma treatment) 공정을 수행하되, 산소 플라즈마를 발생시키고, RF 파워를 인가하는 방식으로 산소 플라즈마 처리 공정을 수행하는 것을 특징으로 하는 다채널 IZO 산화물 박막 트랜지스터.
A substrate including a gate electrode;
An insulating film formed on the substrate;
An active layer formed on the insulating layer; And
Including a source electrode and a drain electrode formed on the active layer,
The active layer has a structure in which two or more layers of indium-zinc oxide (IZO) thin films are continuously stacked,
A multi-channel IZO oxide thin film transistor, characterized in that an oxygen plasma treatment process is performed on the active layer, and an oxygen plasma treatment process is performed by generating oxygen plasma and applying RF power.
 청구항 4에 있어서,
상기 절연막은 상기 기판 상에 SiO2를 성장시키는 방식으로 형성되는 것임을 특징으로 하는 다채널 IZO 산화물 박막 트랜지스터.
The method of claim 4,
The insulating layer is a multi-channel IZO oxide thin film transistor, characterized in that formed by growing SiO 2 on the substrate.
 청구항 4에 있어서,
상기 활성층은 IZO 박막을 형성하는 공정을 연속으로 3회 반복하여, 3개의 IZO 박막 레이어(layer)가 균일하게 적층 되도록 형성되는 것임을 다채널 IZO 산화물 박막 트랜지스터.
The method of claim 4,
The active layer is a multi-channel IZO oxide thin film transistor that is formed so that three IZO thin film layers are uniformly stacked by repeating a process of forming an IZO thin film three times in a row.
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