KR102431926B1 - Oxide thin-film transistors - Google Patents

Abstract

The present invention relates to an oxide thin film transistor, comprising: a substrate including a function of a gate lower electrode; an insulating film formed on the substrate; an oxide active layer having a multilayer structure formed on the insulating film; and a source electrode formed on the oxide active layer; A drain electrode is included.
According to the present invention, by providing an oxide thin film transistor that has been subjected to femtosecond laser annealing on a multilayered oxide active layer film, applied thermal damage can be alleviated, which is advantageous for microprocessing and the oxide material according to the interaction between the laser and the surface. It has the effect of preventing structural change.

Description

Oxide thin-film transistors

The present invention relates to an oxide thin-film transistor, and more particularly, using oxide thin-film transistors, a display backplane electronic device, a next generation electronic device, and a solution process. Fabrication of multi-layer channel structure IZO thin-films using solution process, and relates to an oxide thin film transistor with high electrical and environmental stability.

In a flat panel display (FPD) such as a liquid crystal display (LCD), an active element such as a thin film transistor is provided in each pixel to drive the display element. This type of driving method of the display device is often referred to as an active matrix driving method. In the active matrix method, the thin film transistor is disposed in each pixel to drive the corresponding pixel.

On the other hand, general thin film transistors have used amorphous silicon as a semiconductor layer, but amorphous silicon has a slow electron movement speed, so it is difficult to realize high resolution and high speed driving capability on a very large screen. Therefore, an oxide thin film transistor with an electron transfer speed more than 10 times faster than that of amorphous silicon has appeared, and it is recently spotlighted as a device suitable for high resolution above UD (ultra definition) and high speed operation of 240 Hz or more.

A liquid crystal display device is manufactured by the same process as photolithography. The photolithography process is a process performed through a series of processes such as deposition of a pattern target material and photoresist, exposure using a mask, development of the photoresist, and etching.

Recently, research on oxide semiconductors to replace silicon-based semiconductor devices has been widely conducted. In terms of materials, research results on single, binary, and ternary compounds based on indium oxide (In ₂ O ₃ ), zinc oxide (ZnO), and gallium oxide (Ga ₂ O ₃ ) have been reported. On the other hand, in terms of the process, research on a liquid-based process instead of the conventional vacuum deposition is being conducted.

Oxide semiconductors show the same amorphous phase compared to hydrogenated amorphous silicon, but exhibit very good mobility, so they are suitable for high-definition liquid crystal displays (LCDs) and active organic light-emitting diodes (AMOLEDs). In addition, the oxide semiconductor manufacturing technology using the liquid phase-based process has an advantage of low cost compared to the high-cost vacuum deposition method.

Currently, oxide thin film transistors have low performance to be applied to next-generation large-area displays. In addition, it includes an active layer having a high root-mean square (RMS) value and surface defects, and there is instability when only thermal annealing is used as a post-process after the deposition of the active layer. In addition, the oxide transistor is weak to an electrical load, has a low density structure as a single-layer structure, and has a problem in that electrical characteristics and electrical stability are low due to the single-layer structure.

Republic of Korea Patent Publication 10-2008-0082616

The present invention has been devised to solve the above problems, and an object of the present invention is to provide an oxide thin film transistor in which an oxide thin film is formed by using a solution process method instead of a vacuum deposition method.

Another object of the present invention is to fabricate an indium-zinc oxide (IZO) transistor fabricated with a multi-layered channel structure through a solution process technique.

In addition, the present invention uses a multi-layered channel structure to maintain stability of excellent current retention stability due to reduction of an interface charge trap and a back-channel effect. There is a purpose.

In addition, the present invention can alleviate the applied thermal damage by irradiating a laser in a special range in the form of a spot using a femtosecond laser and heat-treating the penetrating layers, which is advantageous for microprocessing and the interaction between the laser and the surface. Another purpose is to prevent the structural change of the oxide material according to the reaction.

Objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

The present invention for achieving the above object relates to an oxide thin film transistor, and relates to a substrate including a function of a gate lower electrode, an insulating film formed on the substrate, an oxide active layer having a multilayer structure formed on the insulating film, and the oxide active layer and a source electrode and a drain electrode formed thereon.

The oxide active layer has a structure in which two or more indium-zinc oxide (IZO) thin films are continuously stacked, and after the oxide active layer of the multi-layer structure is formed, femtosecond laser post-process annealing is performed.

The oxide active layer may be formed so that three IZO thin film layers are uniformly stacked by repeating the process of forming the IZO thin film three times in succession.

The oxide active layer may be implemented such that a three-layer stacked structure is formed by stacking an IZO thin film layer on the insulating film by a spin coating method.

The substrate, the insulating layer, and the oxide active layer may be formed in a stepped structure in which a stacked area is decreased in the order.

According to the present invention, by providing an oxide thin film transistor that has been subjected to femtosecond laser annealing on a multilayered oxide active layer film, applied thermal damage can be alleviated, which is advantageous for microprocessing and the oxide material according to the interaction between the laser and the surface. It has the effect of preventing structural change.

1 illustrates a stacked structure of an oxide thin film transistor according to an embodiment of the present invention.
Figure 2 shows the results of analyzing the surface appearance of the multi-layer IZO thin film layer that has not been subjected to the femtosecond laser post-process annealing treatment and the multi-layer IZO thin film layer subjected to the femtosecond laser post-process annealing treatment.
3 is a graph showing output characteristic curves of TFTs based on a multi-layered IZO thin film layer that has not been subjected to femtosecond laser post-process annealing and a multi-layered IZO thin film layer that has been subjected to femtosecond laser post-process annealing.
4 is a graph showing the current stability of multi-layered IZO TFTs subjected to femtosecond laser post-process annealing at different times.
5 is a graph showing the results of measuring electrical characteristics after leaving the multi-layered IZO TFT in an atmospheric environment for 14 days.

Advantages and features of the embodiments disclosed herein, and methods for achieving them will become apparent with reference to the embodiments described below in conjunction with the accompanying drawings. However, the embodiments to be proposed in the present disclosure are not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments are provided to those of ordinary skill in the art. It is only provided to fully indicate the category.

Terms used in this specification will be briefly described, and the disclosed embodiments will be described in detail.

Terms used in this specification have been selected as currently widely used general terms as possible while considering the functions of the disclosed embodiments, but may vary depending on the intention or precedent of a person skilled in the art, the emergence of new technology, and the like. In addition, in a specific case, there are also terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the detailed description of the corresponding specification. Therefore, the terms used in the present disclosure should be defined based on the meaning of the term and the content throughout the present specification, rather than the name of a simple term.

References in the singular herein include plural expressions unless the context clearly dictates the singular.

When a part "includes" a certain component throughout the specification, this means that other components may be further included, rather than excluding other components, unless otherwise stated. Also, as used herein, the term “unit” refers to a hardware component such as software, FPGA, or ASIC, and “unit” performs certain roles. However, "part" is not meant to be limited to software or hardware. A “unit” may be configured to reside on an addressable storage medium and may be configured to refresh one or more processors. Thus, by way of example, “part” refers to components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays and variables. The functionality provided within components and “parts” may be combined into a smaller number of components and “parts” or further divided into additional components and “parts”.

In addition, in the description with reference to the accompanying drawings, the same components are assigned the same reference numerals regardless of the reference numerals, and the overlapping description thereof will be omitted. In describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 illustrates a stacked structure of an oxide thin film transistor according to an embodiment of the present invention.

1, the oxide thin film transistor of the present invention has a substrate 10, an insulating layer 110, an oxide active layer 120, a source electrode 130, a drain ( Drain) electrode 140 is included.

In an embodiment of the present invention, the oxide thin film transistor is manufactured in a top-contact bottom-gate structure.

The substrate 10 includes a function of a gate lower electrode. In an embodiment of the present invention, the substrate 10 is implemented as a 600 μm thick silicon (Si) wafer substrate heavily doped with an N-type, and is used as a gate lower electrode. .

The insulating film 110 is formed on the substrate. In an embodiment of the present invention, the insulating film 110 may be formed by growing SiO ₂ on the substrate. For example, it may be formed by growing 100 nm of SiO ₂ through a thermal oxidation process in a furnace.

The oxide active layer 120 is formed on the insulating layer 110 and has a multilayer structure.

The source electrode 130 and the drain electrode 140 are formed on the oxide active layer 120 .

In the present invention, the oxide active layer 120 has a structure in which two or more indium-zinc oxide (IZO) thin films are continuously stacked.

Then, after the oxide active layer 120 having a multilayer structure is formed, femtosecond laser post-annealing is performed.

In an embodiment of the present invention, the oxide active layer 120 may be formed such that three IZO thin film layers are uniformly stacked by repeating the process of forming the IZO thin film three times in a row. More specifically, spin-coating the IZO solution at a speed of 1500 rpm to form an IZO semiconductor thin film with a thickness of 20 to 30 nm, and then on a hot plate at a temperature of 400 ° C. An IZO thin film is produced through the process of annealing for 1 hour and 30 minutes in a , and this process is repeated three times to form a continuous high-integration IZO thin film of 3 uniform layers.

As shown in FIG. 1 , in an embodiment of the present invention, the substrate 10 , the insulating layer 110 , and the oxide active layer 120 may be formed in a stepped structure in which the stacked area is decreased in the order.

Figure 1 shows the structure of the oxygen plasma surface treatment-based three-layer multi-layer structure oxide layer (multi-active layers) IZO TFTs fabricated according to an embodiment of the present invention. A highly doped n-type silicon wafer with a thickness of about 600 μm was used as a substrate and a lower gate electrode, and a SiO ₂ layer with a thickness of about 100 nm was formed through thermal oxidation.

Contaminants generated during the semiconductor device manufacturing process cause distortion of the structural shape of the device and deterioration of electrical characteristics, and thus greatly affect device performance, reliability, yield, and the like. Therefore, before depositing the active layer, for cleaning the substrate, about 60 ml of sulfuric acid (H ₂ SO ₄ ) and about 20 ml of hydrogen peroxide (H ₂ O ₂ ) were mixed 3:1 and heated at about 60 ° C. By performing piranha cleaning, organic contaminants were removed. Thereafter, the substrate was washed with deionized water for about 10 minutes to remove the piranha cleaning solution that may remain on the substrate. In addition, in order to remove the remaining inorganic and organic impurities, contaminants were separated from the substrate using an ultra-sonicator using acetone and isopropyl alcohol (IPA) and washed. Finally, to remove the moisture remaining on the surface, baking was carried out for about 1 hour at about 150 ℃ in a vacuum oven in a low vacuum state.

After that, in order to fabricate a multi-active layer on the SiO ₂ insulating film after wafer cleaning, 0.1 M of indium nitrate hydrate [In(NO ₃ ) ₃ ·xH ₂ O] and 0.1 M of zinc acetate dihydrate [Zn(CH ₃ ) COO) ₂ ·2H ₂ O] was used to form an IZO thin film using the Zol-gel reaction of the precursor solution prepared using. To form a stable indium nitrate hydrate solution, 2-methoxyethanol, acetylacetone, and NH ₃ were mixed with indium powder in a reagent bottle. Then, 2-methoxyethanol and acetylacetone were mixed in another reagent bottle, set to act as an accelerator, and a zinc acetate dihydrate solution was formed. The two solutions were stirred at 60° C. at a speed of about 700 rpm on a stirrer for about 1 hour, and then the fabrication was completed.

Indium nitrate hydrate solution and zinc acetate dihydrate solution were mixed in a 1:1 ratio, and after stirring at a speed of about 500 rpm on a stirrer at 27 °C (room temperature) for about 2 hours until the solution in the reagent bottle changes to a transparent state. production was completed.

As above, multi-active layers IZO were prepared by spin-coating the prepared IZO solution three times sequentially at a speed of 1,500 rpm for about 30 seconds. Between spin-coating each IZO thin film, it was annealed at a temperature of about 200° C. for about 30 minutes on a hot plate. After the process of manufacturing the three-layer IZO thin film is finished, hard baking is performed on a hot plate at a temperature of about 200 ° C for about 2 hours to remove impurities on the IZO thin film and surface It was hardened by removing the defects of the phase.

Then, to prevent thermal damage and structural change, a femtosecond laser was irradiated onto the multi-layered IZO thin film for about 50, 100, and 200 seconds, respectively, using a Ti:Sapphire laser system (Coherent, Chameleon Ultra-II). On average, laser pulses were generated at a high repetition rate of about 80 MHz at a power of about 3 W, and the center wavelength was maintained at about 800 nm and the pulse width at about 140 fs. The femtosecond laser uses a lens to prevent the beam from spreading after passing through a spatial filter. Then, the irradiated beam passed through the beam expander and the beam was spread to an appropriate size so that the substrate was completely irradiated with femtosecond laser pulses.

Finally, an Al electrode with a thickness of about 100 nm was fabricated using a thermal evaporator system, and deposited on the multi-layered IZO thin film as a source/drain electrode of an oxide thin film transistor.

Then, using AFM (Atomic force microscopy) to investigate the surface properties of the thin film, and for comparative analysis of the electrical performance change of the multi-layer IZO TFT at room temperature and in the dark, each through a semiconductor parameter analyzer (Keithley, Keithley 4200) in the dark The electrical performance was measured by extracting the parameters of

Figure 2 shows the results of analysis of the surface appearance of the multi-layer IZO thin film layer not subjected to femtosecond laser post-process annealing treatment and the multi-layer IZO thin film layer subjected to femtosecond laser post-process annealing treatment.

2 shows the results of analysis through AFM for the multi-layered IZO thin film layer that has not been subjected to femtosecond laser post-processing annealing and the thin film layer treated for about 50, 100, and 200 seconds, respectively.

Average grain diameters in FIG. 2 were measured through AFM software. As the femtosecond laser annealing time increases, it can be seen that the particle diameter of the multi-layered IZO thin film gradually increases. The average particle diameter of the multi-layered IZO thin film layer not subjected to femtosecond laser post-processing annealing was about 8.3 nm, and the thin film after femtosecond laser treatment for 50 seconds was about 8.2 nm. This means that the femtosecond laser treatment for about 50 seconds did not have an obvious effect on the surface appearance. However, the average particle diameter of the multi-layered IZO thin film layer treated with the femtosecond laser for about 100 and 200 seconds, respectively, was about 11.7 and 11.5 nm, and the longer the femtosecond laser time, the more regular the particle shape changed and the more uniform the particle size. It can be seen that the surface becomes smoother.

3 is a graph showing output characteristic curves of TFTs based on a multi-layer IZO thin film layer that is not subjected to femtosecond laser post-process annealing and a multi-layer IZO thin film layer that has been subjected to femtosecond laser post-process annealing.

Fig. 3 (a) shows the output characteristic curves of the multi-layer IZO thin film layer not subjected to femtosecond laser post-processing annealing and the thin film layer-based TFT treated for 50, 100, and 200 sec, respectively.

In FIG. 3 (a), I _ds was measured when V _ds was applied by sweeping a step voltage of 0.5 V from 0 to 30 V, respectively, and the gate bias voltage was applied by applying a step voltage from 0 to 30 V by 10 V. did. It can be seen that the source-drain current of the multi-layered IZO TFT without any treatment is almost 0 when the gate voltage is 0. When the gate voltage increases in the positive direction, electrons from the channel layer move to the insulating layer. When the gate voltage is greater than the threshold voltage, a conductive channel begins to form. The channel current increases as the gate voltage increases, indicating that the TFT operates as an n-type channel.

When the drain voltage is gradually increased, the TFT changes from the linear region to the saturation region, showing better saturation characteristics. These characteristics are slightly different depending on the femtosecond laser annealing time. The current movement in the saturation state of the TFT treated for about 100 seconds is relatively better than that of the TFT not treated with the femtosecond laser and the TFT treated for about 50 seconds. This can be explained by the multi-layer IZO TFT operating in the accumulated state, and the drain current is composed of the channel current and the magnetic current in the on-state. Therefore, increasing the magnetoresistance has a positive effect in improving the saturation characteristic of the drain current. The TFT treated with a femtosecond laser for about 200 seconds shows a decrease in output characteristics, which seems to be because the internal structure of the channel layer is damaged and the electrical performance is directly affected if treated with a femtosecond laser for a longer period of time.

3(b) shows the transfer characteristic curves of a multi-layered IZO thin film layer not subjected to femtosecond laser post-processing annealing and a thin film layer-based TFT treated for about 50, 100, and 200 sec, respectively.

3(b) shows IV curves of I _ds and V _ds treated with SQRT after applying V _ds = 30 V. It can be confirmed that all multi-layered IZO TFTs exhibit typical n-type characteristics with a clear transition of I _ds from off-state to on-state as the V _gs value increases. Four parameters of the electrical characteristics of the TFT were measured and analyzed using such a transfer characteristic curve. Electron mobility of multi-layered IZO without femtosecond laser annealing and TFT treated for about 50, 100, and 200 seconds, respectively, was about 3.87, 4.93, 5.23, and 1.88 cm ² /Vs. Also, the on-off current ratio is about 1.8 × 106, 3.1 × 106, 2.1 × 106, and 1.1 × 103, respectively, and the threshold voltage values are about 1.48, 1.67, -0.26, and 5.22 V, respectively. It was.

Finally, the threshold swing values below the threshold voltage were about 1.53, 1.11, 0.81, and 1.77 V/dec, respectively. In conclusion, it can be seen that the electrical performance of the multi-layered IZO TFT is very deteriorated when the femtosecond laser is excessively processed.

4 is a graph showing the current stability of multi-layered IZO TFTs subjected to femtosecond laser post-process annealing at different times, respectively. .

In Fig. 4, the attenuation curve of the source-drain current of the multilayer IZO TFT without femtosecond laser treatment is not smooth and does not follow the attenuation law, but the attenuation curve of the multilayer IZO TFT treated with the femtosecond laser post-process annealing is smooth and regular decrease can be seen. The attenuation rates of the source-drain current of the multi-layered IZO TFT, which were subjected to femtosecond laser annealing for about 50 and 100 seconds, respectively, were about 29% and 22%, respectively. In addition, there are signs of saturation over time, confirming that the femtosecond laser post-process annealing process improves the electrical stability of the multi-layered IZO TFT.

When the multilayer IZO TFT is exposed to air, the multilayer IZO thin film comes into contact with moisture and oxygen. Positive voltage generates hydroxide ions (OH ⁻ ) that form negative charges on the TFT channel layer surface, thereby suppressing carriers with positive charges. Due to this, the multi-layered IZO TFT does not work normally.

5 is a graph showing the results of measuring electrical characteristics after leaving the multi-layered IZO TFT in an atmospheric environment for 14 days.

In FIG. 5 , it can be seen that the overall effect of controlling the current after femtosecond laser annealing is not good. The electron mobility of the multilayer IZO without femtosecond laser annealing and the TFT treated for 50, 100, and 200 seconds, respectively, was about 0.78, 0.56, 3.82, and 1.09 cm ² /Vs, respectively. In addition, the on-off current flashing ratios were about 1.0 × 103, 4.4 × 102, 1.5 × 104, and 1.9 × 102, respectively, and the threshold voltage values were about -0.32, -0.30, -0.25, and -0.68 V, respectively. Finally, the slope values below the threshold voltage were about 1.24, 1.15, 1.60, and 1.90 V/dec, respectively. In conclusion, it can be seen that the electrical performance of the multi-layered IZO TFT is very deteriorated even after 14 days when the femtosecond laser is excessively treated.

The present invention has been described above using several preferred embodiments, but these embodiments are illustrative and not restrictive. Those of ordinary skill in the art to which the present invention pertains will understand that various changes and modifications can be made without departing from the spirit of the present invention and the scope of the appended claims.

10 Substrate 110 Insulation Film
120 oxide active layer 130 source electrode
140 drain electrode

Claims (4)

a substrate comprising the function of a gate lower electrode;
an insulating film formed on the substrate;
an oxide active layer having a multilayer structure formed on the insulating layer; and
Including a source electrode and a drain electrode formed on the oxide active layer,
The oxide active layer has a structure in which two or more layers of indium-zinc oxide (IZO) thin films are continuously stacked,
After the oxide active layer of the multilayer structure is formed, femtosecond laser post-process annealing is performed,
The oxide active layer is formed by repeating the process of forming the IZO thin film three times in a row, so that three IZO thin film layers are uniformly stacked,
The oxide active layer is formed by stacking an IZO thin film layer on the insulating film in a spin coating method to form a three-layer stacked structure,
In the femtosecond laser post-process annealing, a laser pulse is generated at a repetition rate of 80 MHz at a power of 3 W, a femtosecond laser having a center wavelength of 800 nm and a pulse width of 140 fs for 100 seconds Oxide thin film transistor, characterized in that irradiated to the IZO thin film layer during.
delete delete The method according to claim 1,
Oxide thin film transistor, characterized in that formed in a stepped structure in which the stacked area is decreased in the order of the substrate, the insulating film, and the oxide active layer.

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