WO2019021672A1 - Support glass substrate and laminated substrate using same - Google Patents

Support glass substrate and laminated substrate using same Download PDF

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Publication number
WO2019021672A1
WO2019021672A1 PCT/JP2018/022828 JP2018022828W WO2019021672A1 WO 2019021672 A1 WO2019021672 A1 WO 2019021672A1 JP 2018022828 W JP2018022828 W JP 2018022828W WO 2019021672 A1 WO2019021672 A1 WO 2019021672A1
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WO
WIPO (PCT)
Prior art keywords
substrate
glass substrate
processing
supporting
supporting glass
Prior art date
Application number
PCT/JP2018/022828
Other languages
French (fr)
Japanese (ja)
Inventor
哲哉 村田
美紅 藤井
鈴木　良太
Original Assignee
日本電気硝子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気硝子株式会社 filed Critical 日本電気硝子株式会社
Priority to CN202310383937.0A priority Critical patent/CN116462406A/en
Priority to CN202310383158.0A priority patent/CN116462405A/en
Priority to CN201880043070.1A priority patent/CN110831908A/en
Priority to JP2019532431A priority patent/JP7265224B2/en
Publication of WO2019021672A1 publication Critical patent/WO2019021672A1/en
Priority to JP2023044528A priority patent/JP2023076509A/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/083—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound
    • C03C3/085—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal
    • C03C3/087—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal containing calcium oxide, e.g. common sheet or container glass
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/089—Glass compositions containing silica with 40% to 90% silica, by weight containing boron
    • C03C3/091—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/089—Glass compositions containing silica with 40% to 90% silica, by weight containing boron
    • C03C3/091—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
    • C03C3/093—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium containing zinc or zirconium
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/095—Glass compositions containing silica with 40% to 90% silica, by weight containing rare earths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

Definitions

  • the present invention relates to a supporting glass substrate and a laminated substrate using the same, and more specifically, a supporting glass substrate used for supporting a processed substrate in which a semiconductor chip is molded to a resin in a manufacturing process of a semiconductor package and lamination using the same It relates to a substrate.
  • a conventional wafer level package is manufactured by forming bumps in the form of a wafer and then singulating by dicing.
  • the conventional WLP is mounted in a state where the back surface of the semiconductor chip is exposed, and therefore, there is a problem that the semiconductor chip is easily chipped.
  • fan-out type WLP has been proposed as a new WLP.
  • the fan-out type WLP can increase the number of pins, and by protecting the end of the semiconductor chip, chipping or the like of the semiconductor chip can be prevented.
  • the fan-out type WLP includes a chip first type and a chip last type manufacturing method.
  • the chip first type for example, after forming a processed substrate by molding a plurality of semiconductor chips with a resin sealing material, there is a step of wiring on one surface of the processed substrate, a step of forming solder bumps, and the like.
  • the chip last type for example, after arranging a wiring layer on a support substrate, arranging a plurality of semiconductor chips, molding with a resin sealing material to form a processed substrate, and then forming solder bumps, etc. Have.
  • PLPs panel level packages
  • the sealing material may be deformed, and the processed substrate may be warped.
  • warpage occurs in the processed substrate, it becomes difficult to wire with high density on one surface of the processed substrate, and it becomes difficult to form solder bumps accurately.
  • the glass substrate is easy to smooth the surface and has rigidity. Therefore, when a glass substrate is used as the supporting substrate, the processed substrate can be firmly and accurately supported. In addition, the glass substrate easily transmits light such as ultraviolet light and infrared light. Therefore, when a glass substrate is used as the supporting substrate, the processed substrate can be easily fixed by providing an adhesive layer or the like such as an ultraviolet curing adhesive. Furthermore, the processing substrate can be easily separated by providing a peeling layer or the like that absorbs infrared light. As another method, a processing substrate can be easily fixed and separated by providing an adhesive layer or the like with an ultraviolet ray curable tape or the like.
  • the sealing material may be deformed and the processed substrate may undergo dimensional change.
  • the dimension of the processed substrate changes, it becomes difficult to wire densely to one surface of the processed substrate, and it becomes difficult to form solder bumps accurately.
  • the present invention has been made in view of the above circumstances, and the technical problem is to contribute to high density mounting of a semiconductor package by creating a supporting glass substrate which hardly causes dimensional change of a processed substrate. .
  • the inventor has found that the above technical problems can be solved by strictly controlling the thermal expansion coefficient of the supporting glass substrate and increasing the Young's modulus of the supporting glass substrate. It is proposed as the present invention. That is, the supporting glass substrate of the present invention has an average linear thermal expansion coefficient of 30 ⁇ 10 ⁇ 7 / ° C. or more and 55 ⁇ 10 ⁇ 7 / ° C. or less in the temperature range of 30 to 380 ° C., and has a Young's modulus It is characterized by being 80 GPa or more.
  • the “average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C.” can be measured by a dilatometer.
  • Youngng's modulus can be measured by the well-known resonance method.
  • the average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. is regulated to 30 ⁇ 10 ⁇ 7 / ° C. or more and 55 ⁇ 10 ⁇ 7 / ° C. or less.
  • the thermal expansion coefficients of the processing substrate and the supporting glass substrate can be easily matched.
  • wiring can be performed at high density on one surface of the processing substrate, and solder bumps can be formed accurately.
  • Young's modulus is regulated to 80 GPa or more.
  • the rigidity of the laminated substrate is improved, so dimensional change (particularly, warpage deformation) of the processed substrate can be easily suppressed, and the processed substrate can be firmly and accurately supported.
  • total plate thickness deviation is less than 2.0 micrometers. This makes it easy to increase the accuracy of the processing. In particular, since the wiring accuracy can be improved, high density wiring can be achieved. Furthermore, the number of times of reuse of the supporting glass substrate can be increased.
  • TTV total thickness deviation
  • the “total thickness deviation (TTV)” is the difference between the maximum thickness and the minimum thickness of the whole, and can be measured, for example, by SBW-331ML / d manufactured by Kobelco Research Institute.
  • the supporting glass substrate of the present invention is composed of SiO 2 50 to 66%, Al 2 O 3 7 to 34%, B 2 O 3 0 to 8%, MgO 0 to 22%, CaO by mass as a glass composition. It is preferable to contain 1 to 15%, and Y 2 O 3 + La 2 O 3 + ZrO 2 0 to 20%.
  • Y 2 O 3 + La 2 O 3 + ZrO 2 refers to the total amount of Y 2 O 3 , La 2 O 3 and ZrO 2 .
  • the support glass substrate of this invention for support of the process board
  • the laminated substrate of the present invention is preferably a laminated substrate provided with at least a processing substrate and a supporting glass substrate for supporting the processing substrate, and the supporting glass substrate is preferably the above supporting glass substrate.
  • the processed substrate is preferably a processed substrate in which a semiconductor chip is molded in a resin.
  • a process of preparing a laminated substrate including at least a processed substrate and a supporting glass substrate for supporting the processed substrate, a process of performing processing on the processed substrate,
  • the supporting glass substrate is the above supporting glass substrate.
  • the processing includes a step of wiring on one surface of a processing substrate.
  • the processing includes the step of forming a solder bump on one surface of the processing substrate.
  • FIG. 14 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP chip-first type. It is a conceptual sectional view showing a process of thinning a processed substrate by using a supporting glass substrate as a back grind substrate.
  • the average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. is 30 ⁇ 10 ⁇ 7 / ° C. or more and 55 ⁇ 10 ⁇ 7 / ° C. or less, preferably 32 ⁇ 10 10 ⁇ 7 / ° C. or higher and 52 ⁇ 10 ⁇ 7 / ° C. or lower, preferably 33 ⁇ 10 ⁇ 7 / ° C. or higher and 49 ⁇ 10 ⁇ 7 / ° C. or lower, particularly preferably 34 ⁇ 10 ⁇ 7 / ° C. or higher 44 ⁇ 10 ⁇ 7 / ° C. or less.
  • Young's modulus is preferably 80 GPa or more, 85 GPa or more, 90 GPa or more, 95 GPa or more, and particularly 96 to 130 GPa. If the Young's modulus is too low, it is difficult to maintain the rigidity of the laminate, and dimensional change (especially, warpage deformation) of the processed substrate is likely to occur.
  • the overall thickness deviation (TTV) is preferably less than 2.0 ⁇ m, 1.5 ⁇ m or less, 1.0 ⁇ m or less, and particularly 0.1 to less than 1.0 ⁇ m. If the overall thickness deviation (TTV) is too large, the accuracy of the processing tends to be reduced. Furthermore, it becomes difficult to reuse the supporting glass substrate.
  • the entire surface of the supporting glass substrate of the present invention is preferably a polished surface.
  • the overall thickness deviation (TTV) can be easily regulated to less than 2.0 ⁇ m, 1.5 ⁇ m or less, 1.0 ⁇ m or less, particularly less than 1.0 ⁇ m.
  • various methods can be adopted as the method of polishing treatment, both sides of the glass substrate are sandwiched by a pair of polishing pads, and the glass substrate is polished while rotating the glass substrate and the pair of polishing pads together. Is preferred.
  • the pair of polishing pads have different outer diameters, and it is preferable to perform polishing treatment so that a part of the glass substrate is intermittently ejected from the polishing pad during polishing.
  • the polishing depth is not particularly limited, the polishing depth is preferably 50 ⁇ m or less, 30 ⁇ m or less, 20 ⁇ m or less, particularly 10 ⁇ m or less. As the polishing depth is smaller, the productivity of the supporting glass substrate is improved.
  • Supporting glass substrate of the present invention has a glass composition, in mass%, SiO 2 50 ⁇ 66% , Al 2 O 3 7 ⁇ 34%, B 2 O 3 0 ⁇ 8%, MgO 0 ⁇ 22%, CaO 1 ⁇ More preferably, it contains 15% of Y 2 O 3 + La 2 O 3 + ZrO 2 0 to 20%.
  • the reason which limited content of each component as mentioned above is shown below.
  • % display represents mass%, unless there is particular notice.
  • SiO 2 is a component that forms a glass network.
  • the content of SiO 2 is preferably 50 to 66%, 51 to 65%, 52 to 64%, 53 to 63%, 54 to 62.5%, 56 to 62%, in particular 58 to 61%.
  • the content of SiO 2 is too small, it is difficult to vitrify and the weather resistance is easily lowered. Furthermore, the thermal expansion coefficient becomes too high.
  • the content of SiO 2 is too large, the meltability and the formability tend to be lowered, and the thermal expansion coefficient becomes too low.
  • Al 2 O 3 is a component that enhances Young's modulus and weather resistance.
  • the content of Al 2 O 3 is preferably 7 to 34%, 8 to 26%, 9 to 24%, 11 to 23%, 12 to 22%, 14 to 21%, particularly 16 to 21%.
  • Young's modulus and weather resistance tend to be lowered.
  • the content of Al 2 O 3 is too large, the meltability, the formability and the devitrification resistance tend to be lowered.
  • B 2 O 3 is a component that forms a network of glass, but is a component that reduces Young's modulus and weather resistance. Therefore, the content of B 2 O 3 is preferably 0 to 8%, 0.1 to 7%, 1 to 6%, particularly 3 to 5%.
  • MgO is a component that greatly enhances the Young's modulus, and is also a component that reduces the high temperature viscosity to enhance the meltability and the formability.
  • the content of MgO is preferably 0 to 22%, 0.5 to 21%, 1 to 20.5%, 2 to 20%, 4 to 19.5%, 5 to 19%, 7 to 19%, 8 18%, 8.5-16%, 9-16%, 9-14%, especially 9-12%.
  • the content of MgO is too small, it becomes difficult to receive the above effect.
  • the content of MgO is too large, the devitrification resistance tends to decrease.
  • CaO is a component that reduces the high temperature viscosity to enhance the meltability and the formability.
  • the content of CaO is preferably 1 to 15%, 2 to 12%, 3 to 10%, in particular 5 to 8%.
  • the content of CaO is too small, it becomes difficult to receive the above effect.
  • the content of CaO is too large, the devitrification resistance tends to decrease.
  • the molar ratio MgO / (MgO + CaO + SrO + BaO) is preferably 0 or more, 0.1 or more, 0.2 or more, 0.3 or more, 0.4 or more, 0.4 or more, 0.5 or more, 0.6 or more , Especially 0.7 or more.
  • MgO / (MgO + CaO + SrO + BaO) is a value obtained by dividing the content of MgO by the total amount of MgO, CaO, SrO and BaO.
  • Y 2 O 3 , La 2 O 3 and ZrO 2 are components that increase the Young's modulus.
  • the total amount of Y 2 O 3 , La 2 O 3 and ZrO 2 is preferably 0 to 20%, 0.1 to 18%, 0.5 to 16%, 1 to 15%, 1 to 14%, 1 to 12%, 1.2 to 10%, 1.3 to 8%, especially 1.5 to 5%. If the total amount of Y 2 O 3 , La 2 O 3 and ZrO 2 is too large, the devitrification resistance tends to be reduced.
  • the content of Y 2 O 3 is preferably 0 to 15%, 0.1 to 14%, 0.5 to 13%, 0.5 to 12%, 0.5 to 10%, and 0.5 to 8%.
  • the content of La 2 O 3 is preferably 0 to 6%, 0 to 4%, in particular 0 to 2%.
  • the content of ZrO 2 is preferably 0 to 10%, 0.1 to 6%, 0.5 to 4%, in particular 1 to 3%. If the content of Y 2 O 3 is too large, the devitrification resistance is likely to be reduced, and the raw material cost is likely to be increased. When the content of La 2 O 3 is too large, the devitrification resistance is apt to decrease, and the cost of the raw material tends to increase. When the content of ZrO 2 is too large, the devitrification resistance tends to be reduced.
  • SrO and BaO are components that lower the high temperature viscosity to enhance the meltability and the formability. SrO and BaO are each 0 to 15%, 0.1 to 12%, especially 0.5 to 10%.
  • ZnO is a component that lowers the high temperature viscosity and significantly enhances the meltability.
  • the content of ZnO is preferably 0 to 7%, 0.1 to 5%, in particular 0.5 to 3%. When the content of ZnO is too small, it becomes difficult to receive the above effect. When the content of ZnO is too large, the glass is easily devitrified.
  • Li 2 O, Na 2 O and K 2 O are components that reduce the high temperature viscosity to improve the meltability and the formability, but are components that increase the thermal expansion coefficient.
  • the total amount of Li 2 O, Na 2 O and K 2 O is preferably 0 to 15%, preferably 0 to 15%, in order to lower the high temperature viscosity and to enhance the meltability and the formability and to increase the thermal expansion coefficient. It is from 01 to 10%, from 0.05 to 8%, in particular from 0.1 to 5%.
  • the respective content of Li 2 O, Na 2 O and K 2 O is preferably 0 to 10%, 0.01 to 5%, 0.05 to 4%, in particular 0.1 to less than 3%.
  • the total amount of Li 2 O, Na 2 O and K 2 O is preferably 0 to 15%, 0 to 10%, 0 to 5%, 0 to 1%, 0 to 0.1%, 0 to 0.05%, in particular 0 to less than 0.01%.
  • the content of each of Li 2 O, Na 2 O and K 2 O is preferably 0 to 15%, 0 to 10%, 0 to 5%, 0 to 1%, 0 to 0.1%, 0 to 0 .05%, in particular 0 to less than 0.01%.
  • TiO 2 is a component that enhances the weather resistance, but is a component that colors the glass.
  • the content of TiO 2 is preferably 0 to 0.5%, in particular 0 to less than 0.1%.
  • 0.05 to 0.5% of one or more selected from the group of SnO 2 , Cl, SO 3 , CeO 2 may be added as a clarifier .
  • Fe 2 O 3 is a component which is inevitably mixed as an impurity into a glass raw material and is a coloring component. Therefore, the content of Fe 2 O 3 is preferably 0.5% or less, 0.001 to 0.1%, 0.005 to 0.07%, 0.008 to 0.03%, particularly 0.01. It is -0.025%.
  • V 2 O 5 , Cr 2 O 3 , CoO 3 and NiO are coloring components.
  • the content of each of V 2 O 5 , Cr 2 O 3 , CoO 3 and NiO is preferably at most 0.1%, in particular less than 0.01%.
  • the glass composition substantially does not contain As 2 O 3 , Sb 2 O 3 , PbO, Bi 2 O 3 and F.
  • does not substantially contain is a concept that does not positively add an explicit component as a glass component, but allows the case of mixing as an impurity, and more specifically, It indicates that the content is less than 0.05%.
  • the supporting glass substrate of the present invention preferably has the following characteristics.
  • the strain point is preferably 580 ° C. or more, 620 ° C. or more, 650 ° C. or more, 680 ° C. or more, particularly 700 to 850 ° C.
  • the higher the strain point the easier it is to reduce the thermal contraction of the supporting glass substrate in the manufacturing process of the semiconductor package. As a result, it becomes easy to improve the accuracy of processing.
  • a "distortion point" points out the value measured based on the method of ASTMC336.
  • the liquidus temperature is preferably 1300 ° C. or less, 1280 ° C. or less, 1250 ° C. or less, 1160 ° C. or less, 1130 ° C. or less, particularly 1100 ° C. or less.
  • TTV overall thickness deviation
  • liquidus temperature is passed through a standard sieve of 30 mesh (500 ⁇ m) and the glass powder remaining on 50 mesh (300 ⁇ m) is put in a platinum boat and then held in a temperature gradient furnace for 24 hours to It is computable by measuring the temperature which precipitates.
  • the liquid phase viscosity is preferably 10 3.8 dPa ⁇ s or more, 10 4.0 dPa ⁇ s or more, 10 4.2 dPa ⁇ s or more, 10 4.4 dPa ⁇ s or more, particularly 10 4.6 dPa ⁇ s or more.
  • TTV thickness deviation
  • the "liquid phase viscosity" can be measured by a platinum ball pulling method.
  • the temperature at 10 2.5 dPa ⁇ s is preferably 1550 ° C. or less, 1500 ° C. or less, 1480 ° C. or less, 1450 ° C. or less, in particular 1200 to 1400 ° C. or less.
  • temperature at 10 2.5 dPa ⁇ s can be measured by a platinum ball pulling method.
  • the plate thickness is preferably 1.5 mm or less, 1.2 mm or less, 1.0 mm or less, particularly 0.9 mm or less.
  • the plate thickness of the supporting glass substrate is preferably 0.5 mm or more, 0.6 mm or more, particularly preferably 0.7 mm or more.
  • the amount of warpage is preferably 60 ⁇ m or less, 55 ⁇ m or less, 50 ⁇ m or less, 1 to 45 ⁇ m, and particularly 5 to 40 ⁇ m.
  • the smaller the amount of warpage the easier it is to improve the processing accuracy. In particular, since the wiring accuracy can be improved, high density wiring can be achieved.
  • the "warpage amount” refers to the sum of the absolute value of the maximum distance between the highest position and the least square focal plane in the entire support glass substrate and the absolute value of the lowest position and the least square focal plane, For example, it can be measured by SBW-331ML / d manufactured by Kobelco Research Institute.
  • the support glass substrate of the present invention is preferably in the form of a wafer (substantially round), and the diameter is preferably 100 mm to 500 mm, more preferably 150 mm to 450 mm, and its roundness (excluding the notch portion) is 1 mm or less 0.1 mm or less, 0.05 mm or less, particularly 0.03 mm or less is preferable. This makes it easy to apply to the manufacturing process of the semiconductor package.
  • the “roundness” is a value obtained by subtracting the minimum value from the maximum value of the outer shape of the wafer.
  • the supporting glass substrate of the present invention preferably has a notch portion (notch-shaped alignment portion), and the deep portion of the notch portion is more preferably substantially circular or substantially V-shaped in a plan view.
  • a positioning member such as a positioning pin
  • alignment of the supporting glass substrate and the processing substrate is facilitated.
  • notches are also formed on the processing substrate and the positioning member is made to abut, alignment of the entire laminate becomes easy.
  • the positioning member abuts on the notch portion of the support glass substrate, stress is easily concentrated on the notch portion, and the support glass substrate is easily broken starting from the notch portion.
  • the supporting glass substrate is curved by an external force, the tendency becomes remarkable. Therefore, it is preferable that the whole or one part of the edge area
  • At least 50% of the edge region where the surface of the notch crosses the end surface is chamfered, and at least 90% of the edge region where the surface of the notch crosses the end surface is chamfered It is particularly preferable that the entire edge area where the surface of the notch and the end face intersect is chamfered. The larger the chamfered area in the notch, the lower the probability of breakage starting from the notch can be reduced.
  • the chamfering width in the front surface direction of the notch portion (also the chamfering width in the back surface direction is the same) is preferably 50 to 900 ⁇ m, 200 to 800 ⁇ m, 300 to 700 ⁇ m, 400 to 650 ⁇ m, particularly 500 to 600 ⁇ m. If the chamfering width in the surface direction of the notch portion is too small, the supporting glass substrate is likely to be broken starting from the notch portion. On the other hand, if the chamfering width in the front surface direction of the notch portion is too large, the chamfering efficiency is reduced, and the manufacturing cost of the supporting glass substrate is easily increased.
  • the chamfering width in the plate thickness direction of the notch (total of the chamfering widths on the front and back surfaces) is preferably 5 to 80%, 20 to 75%, 30 to 70%, 35 to 65% of the plate thickness, in particular 40 to 60%.
  • the chamfering width in the plate thickness direction of the notch portion is too small, the supporting glass substrate is easily broken starting from the notch portion.
  • the chamfering width in the plate thickness direction of the notch portion is too large, the external force is easily concentrated on the end surface of the notch portion, and the supporting glass substrate is easily damaged starting from the end surface of the notch portion.
  • the support glass substrate of the present invention is not chemically strengthened. That is, it is preferable not to have a compressive stress layer on the surface.
  • Various methods can be adopted as a method of forming the supporting glass substrate. For example, a slot down method, a roll out method, a redraw method, a float method, an ingot forming method, etc. can be adopted.
  • the layered substrate of the present invention is a layered substrate provided with at least a processing substrate and a supporting glass substrate for supporting the processing substrate, and the supporting glass substrate is the above supporting glass substrate.
  • the technical features (preferred configuration, effects) of the laminated substrate of the present invention overlap with the technical features of the supporting glass substrate of the present invention. Therefore, in the present specification, the detailed description of the overlapping portions is omitted.
  • the laminated substrate of the present invention preferably has an adhesive layer between the processing substrate and the supporting glass substrate.
  • the adhesive layer is preferably a resin, and for example, a thermosetting resin, a photocurable resin (in particular, an ultraviolet curable resin), and the like are preferable.
  • the laminated substrate of the present invention further comprises a release layer between the processing substrate and the supporting glass substrate, more specifically between the processing substrate and the adhesive layer, or peeling between the supporting glass substrate and the adhesive layer. It is preferred to have a layer. In this way, the processed substrate is easily peeled off from the supporting glass substrate after the processed substrate is subjected to predetermined processing. It is preferable to perform peeling of a process board
  • the peeling layer is made of a material that causes “in-layer peeling” or “interface peeling” by irradiation light such as laser light. That is, when irradiated with light of a certain intensity, the bonding force between atoms or molecules in atoms or molecules disappears or decreases, causing ablation and the like, and is made of a material causing ablation.
  • the component contained in a peeling layer is released as a gas by irradiation of irradiation light and it separates and it separates, and when a peeling layer absorbs light and becomes gas and the vapor is discharge
  • the supporting glass substrate is preferably larger than the processing substrate.
  • the method for manufacturing a semiconductor package according to the present invention includes the steps of preparing a laminated substrate including at least a processing substrate and a supporting glass substrate for supporting the processing substrate, and performing a processing process on the processing substrate.
  • the supporting glass substrate is the above supporting glass substrate.
  • the method for manufacturing a semiconductor package of the present invention has a step of preparing a laminated substrate including at least a processing substrate and a supporting glass substrate for supporting the processing substrate.
  • a laminated substrate comprising at least a processing substrate and a support glass substrate for supporting the processing substrate has the above-described material configuration.
  • molding method can be adopted as a shaping
  • the method for manufacturing a semiconductor package according to the present invention preferably further comprises the step of transporting the laminated substrate.
  • the processing efficiency of processing can be improved.
  • the “step of transporting the laminated substrate” and the “step of processing the processed substrate” do not need to be separately performed, and may be performed simultaneously.
  • the processing is preferably a process of wiring on one surface of a processed substrate or a process of forming a solder bump on one surface of the processed substrate.
  • the size of the processed substrate is unlikely to change during these processes, so that these steps can be properly performed.
  • processing of mechanically polishing one surface of the processing substrate (usually, the surface opposite to the supporting glass substrate) other than the above, one surface of the processing substrate (usually the supporting glass substrate)
  • the process of dry-etching the opposite surface) or the process of wet-etching one surface of the processed substrate (usually, the surface opposite to the supporting glass substrate) may be used.
  • warpage of the processed substrate is unlikely to occur, and the rigidity of the laminated substrate can be maintained. As a result, the above processing can be properly performed.
  • FIG. 1 is a conceptual perspective view showing an example of the laminated substrate 1 of the present invention.
  • the laminated substrate 1 includes a support glass substrate 10 and a processing substrate 11.
  • the supporting glass substrate 10 is attached to the processing substrate 11 in order to prevent the dimensional change of the processing substrate 11.
  • the supporting glass substrate 10 has an average linear thermal expansion coefficient of 32 ⁇ 10 ⁇ 7 / ° C. or more and 55 ⁇ 10 ⁇ 7 / ° C. or less in a temperature range of 30 to 380 ° C., and a Young's modulus of 80 GPa or more It is.
  • the peeling layer 12 and the adhesive layer 13 are disposed between the supporting glass substrate 10 and the processing substrate 11. The peeling layer 12 is in contact with the support glass substrate 10, and the adhesive layer 13 is in contact with the processing substrate 11.
  • the laminated substrate 1 is laminated and arranged in the order of the supporting glass substrate 10, the peeling layer 12, the adhesive layer 13, and the processing substrate 11.
  • the shape of the supporting glass substrate 10 is determined according to the processing substrate 11. However, in FIG. 1, the shapes of the supporting glass substrate 10 and the processing substrate 11 are both wafer shapes.
  • amorphous silicon (a-Si) silicon oxide, a silicate compound, silicon nitride, aluminum nitride, titanium nitride or the like is used for the peeling layer 12.
  • the peeling layer 12 is formed by plasma CVD, spin coating by a sol-gel method, or the like.
  • the adhesive layer 13 is made of a resin, and is formed by, for example, various printing methods, an inkjet method, a spin coating method, a roll coating method, or the like.
  • the adhesive layer 13 is dissolved and removed by a solvent or the like after the supporting glass substrate 10 is peeled off from the processed substrate 11 by the peeling layer 12.
  • FIG. 2 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP chip-first type.
  • FIG. 2A shows a state in which the adhesive layer 21 is formed on one surface of the support member 20. If necessary, a release layer may be formed between the support member 20 and the adhesive layer 21.
  • FIG. 2 (b) a plurality of semiconductor chips 22 are attached on the adhesive layer 21. At this time, the surface on the active side of the semiconductor chip 22 is brought into contact with the adhesive layer 21.
  • the semiconductor chip 22 is molded with a sealing material 23 of resin.
  • the sealing material 23 a material having a small dimensional change after compression molding and a small dimensional change at the time of molding a wiring is used.
  • the processed substrate 24 on which the semiconductor chip 22 is molded is separated from the support member 20, and then bonded and fixed to the support glass substrate 26 through the adhesive layer 25.
  • the surface of the processing substrate 24 opposite to the surface on which the semiconductor chip 22 is buried is disposed on the supporting glass substrate 26 side.
  • the laminated substrate 27 can be obtained.
  • a plurality of solder bumps 29 are obtained after transporting the obtained laminated substrate 27, as shown in FIG. 2F.
  • the processing substrate 24 is cut into each semiconductor chip 22 and subjected to the subsequent packaging process (FIG. 2 (g)).
  • FIG. 3 is a conceptual cross-sectional view showing a process of thinning a processed substrate by using a supporting glass substrate as a back grind substrate.
  • FIG. 3A shows a laminated substrate 30.
  • the laminated substrate 30 is laminated and arranged in order of the support glass substrate 31, the peeling layer 32, the adhesive layer 33, and the processed substrate (silicon wafer) 34.
  • a plurality of semiconductor chips 35 are formed by photolithography or the like on the surface of the processing substrate in contact with the adhesive layer 33.
  • FIG. 3B shows a process of thinning the processed substrate 34 by the polishing apparatus 36. By this process, the processing substrate 34 is mechanically polished and thinned to, for example, several tens of ⁇ m.
  • FIG. 3A shows a laminated substrate 30.
  • the laminated substrate 30 is laminated and arranged in order of the support glass substrate 31, the peeling layer 32, the adhesive layer 33, and the processed substrate (silicon wafer) 34.
  • a plurality of semiconductor chips 35 are formed
  • FIG. 3C shows a step of irradiating the peeling layer 32 with the ultraviolet light 37 through the supporting glass substrate 31.
  • the supporting glass substrate 31 can be separated.
  • the separated supporting glass substrate 31 is reused as needed.
  • FIG. 3E shows the process of removing the adhesive layer 33 from the processing substrate 34. Through this process, the thinned processed substrate 34 can be collected.
  • Tables 1 to 9 show Examples (Sample Nos. 1 to 86) and Comparative Examples (Sample No. 87) of the present invention.
  • a glass batch prepared with glass raw materials was put in a platinum crucible so as to obtain the glass composition in the table, and then melted, clarified, and homogenized at 1500 to 1700 ° C. for 24 hours. At the time of melting of the glass batch, it was stirred using a platinum stirrer and homogenized. Next, the molten glass was poured out onto a carbon plate, formed into a plate, and then annealed for 30 minutes at a temperature near the annealing point. About each obtained glass substrate, density, average linear thermal expansion coefficient CTE in a temperature range of 30 to 380 ° C. 30 to 380 ° C.
  • the density is a value measured by the Archimedes method.
  • the average linear thermal expansion coefficient CTE of 30 to 380 ° C. in the temperature range of 30 to 380 ° C. is a value measured by a dilatometer.
  • Young's modulus refers to the value measured by the resonance method.
  • strain point Ps, the annealing point Ta, and the softening point Ts are values measured based on the method of ASTM C336 and C338.
  • the temperatures at high temperature viscosity of 10 4.0 dPa ⁇ s, 10 3.0 dPa ⁇ s and 10 2.5 dPa ⁇ s are values measured by a platinum ball pulling method.
  • sample Nos. 1-86 are 30 average linear thermal expansion coefficient CTE 30 ⁇ 380 ° C. in a temperature range of ⁇ 380 ° C. is 33.2 ⁇ 10 -7 /°C ⁇ 48.0 ⁇ 10 -7 / °C , Young's modulus 80.0 Since it is ⁇ 101.2 GPa, it is considered to be suitable as a supporting glass substrate.
  • sample no. 87 has an average linear thermal expansion coefficient CTE of 30 to 380 ° C. of 35 ⁇ 10 ⁇ 7 / ° C. in the temperature range of 30 to 380 ° C., but because the Young's modulus is 76 GPa, it is considered unsuitable as a supporting glass substrate Be
  • both surfaces thereof were polished by a polishing apparatus. Specifically, both surfaces of the glass substrate were sandwiched between a pair of polishing pads having different outer diameters, and both surfaces of the glass substrate were polished while rotating the glass substrate and the pair of polishing pads together. During the polishing process, occasionally, a part of the glass substrate was controlled to protrude from the polishing pad.
  • the polishing pad was made of urethane, and the average particle size of the polishing slurry used in the polishing treatment was 2.5 ⁇ m, and the polishing rate was 15 m / min.
  • the thickness deviation (TTV) and the amount of warpage of each polished glass substrate thus obtained were measured by SBW-331ML / d manufactured by Kobelco Research Institute. As a result, the total plate thickness deviation (TTV) was 0.45 ⁇ m, and the amount of warpage was 35 ⁇ m.

Abstract

A support glass substrate according to the present invention is characterized by having an average linear thermal expansion coefficient of 30 × 10-7 to 55 × 10-7/°C inclusive in a temperature range from 30 to 380°C and a Young's modulus of 80 GPa or more.

Description

支持ガラス基板及びこれを用いた積層基板Support glass substrate and laminated substrate using the same
　本発明は、支持ガラス基板及びこれを用いた積層基板に関し、具体的には、半導体パッケージの製造工程で半導体チップが樹脂にモールドされた加工基板の支持に用いる支持ガラス基板及びこれを用いた積層基板に関する。 The present invention relates to a supporting glass substrate and a laminated substrate using the same, and more specifically, a supporting glass substrate used for supporting a processed substrate in which a semiconductor chip is molded to a resin in a manufacturing process of a semiconductor package and lamination using the same It relates to a substrate.
　携帯電話、ノート型パーソナルコンピュータ、ＰＤＡ（Ｐｅｒｓｏｎａｌ　Ｄａｔａ　Ａｓｓｉｓｔａｎｃｅ）等の携帯型電子機器には、小型化及び軽量化が要求されている。これに伴い、これらの電子機器に用いられる半導体チップの実装スペースも厳しく制限されており、半導体チップの高密度な実装が課題になっている。そこで、近年では、三次元実装技術、すなわち半導体チップ同士を積層し、各半導体チップ間を配線接続することにより、半導体パッケージの高密度実装を図っている。 Miniaturization and weight reduction are required for portable electronic devices such as mobile phones, laptop personal computers, and PDAs (Personal Data Assistance). Along with this, the mounting space for semiconductor chips used in these electronic devices is also strictly limited, and high-density mounting of semiconductor chips has become an issue. Therefore, in recent years, high density mounting of semiconductor packages has been achieved by three-dimensional mounting technology, that is, by stacking semiconductor chips and wiring connection between the semiconductor chips.
　また、従来のウエハレベルパッケージ（ＷＬＰ）は、バンプをウエハの状態で形成した後、ダイシングで個片化することにより作製されている。しかし、従来のＷＬＰは、ピン数を増加させ難いことに加えて、半導体チップの裏面が露出した状態で実装されるため、半導体チップの欠け等が発生し易いという問題があった。 In addition, a conventional wafer level package (WLP) is manufactured by forming bumps in the form of a wafer and then singulating by dicing. However, in addition to the difficulty in increasing the number of pins, the conventional WLP is mounted in a state where the back surface of the semiconductor chip is exposed, and therefore, there is a problem that the semiconductor chip is easily chipped.
　そこで、新たなＷＬＰとして、ｆａｎ　ｏｕｔ型のＷＬＰが提案されている。ｆａｎ　ｏｕｔ型のＷＬＰは、ピン数を増加させることが可能であり、また半導体チップの端部を保護することにより、半導体チップの欠け等を防止することができる。 Therefore, fan-out type WLP has been proposed as a new WLP. The fan-out type WLP can increase the number of pins, and by protecting the end of the semiconductor chip, chipping or the like of the semiconductor chip can be prevented.
　ｆａｎ　ｏｕｔ型のＷＬＰには、チップファースト型とチップラスト型の製造方法がある。チップファースト型では、例えば、複数の半導体チップを樹脂の封止材でモールドして、加工基板を形成した後に、加工基板の一方の表面に配線する工程、半田バンプを形成する工程等を有する。チップラスト型では、例えば、支持基板上に配線層を設置した上で、複数の半導体チップを配列し、樹脂の封止材でモールドして加工基板を形成した後に、半田バンプを形成する工程等を有する。 The fan-out type WLP includes a chip first type and a chip last type manufacturing method. In the chip first type, for example, after forming a processed substrate by molding a plurality of semiconductor chips with a resin sealing material, there is a step of wiring on one surface of the processed substrate, a step of forming solder bumps, and the like. In the chip last type, for example, after arranging a wiring layer on a support substrate, arranging a plurality of semiconductor chips, molding with a resin sealing material to form a processed substrate, and then forming solder bumps, etc. Have.
　更に、最近では、パネルレベルパッケージ(ＰＬＰ)と呼ばれる半導体パッケージも検討されている。ＰＬＰでは、支持基板１枚当たりの半導体パッケージの取れ数を増加させつつ、製造コストを低下させるために、ウエハ状ではなく矩形状の支持基板が使用される。 Furthermore, recently, semiconductor packages called panel level packages (PLPs) have also been considered. In PLP, in order to reduce the manufacturing cost while increasing the number of semiconductor packages obtained per supporting substrate, a rectangular supporting substrate is used instead of a wafer shape.
　これらの半導体パッケージの製造工程では、約２００℃の熱処理を伴うため、封止材が変形して、加工基板に反りが発生する虞がある。加工基板に反りが発生すると、加工基板の一方の表面に対して、高密度に配線することが困難になり、また半田バンプを正確に形成することも困難になる。 In the manufacturing process of these semiconductor packages, since the heat treatment is performed at about 200 ° C., the sealing material may be deformed, and the processed substrate may be warped. When warpage occurs in the processed substrate, it becomes difficult to wire with high density on one surface of the processed substrate, and it becomes difficult to form solder bumps accurately.
　このような事情から、加工基板の反りを抑制するために、加工基板を支持するガラス基板を用いることが検討されている（特許文献１参照）。 From such a situation, in order to suppress the curvature of a process board | substrate, using a glass substrate which supports a process board | substrate is examined (refer patent document 1).
　ガラス基板は、表面を平滑化し易く、且つ剛性を有する。よって、支持基板としてガラス基板を用いると、加工基板を強固、且つ正確に支持することが可能になる。またガラス基板は、紫外光、赤外光等の光を透過し易い。よって、支持基板としてガラス基板を用いると、紫外線硬化型接着剤等の接着層等を設けることにより、加工基板を容易に固定することができる。更に赤外線を吸収する剥離層等を設けることにより、加工基板を容易に分離することもできる。別の方式として紫外線硬化型テープ等により接着層等を設けることにより、加工基板を容易に固定、分離することもできる。 The glass substrate is easy to smooth the surface and has rigidity. Therefore, when a glass substrate is used as the supporting substrate, the processed substrate can be firmly and accurately supported. In addition, the glass substrate easily transmits light such as ultraviolet light and infrared light. Therefore, when a glass substrate is used as the supporting substrate, the processed substrate can be easily fixed by providing an adhesive layer or the like such as an ultraviolet curing adhesive. Furthermore, the processing substrate can be easily separated by providing a peeling layer or the like that absorbs infrared light. As another method, a processing substrate can be easily fixed and separated by providing an adhesive layer or the like with an ultraviolet ray curable tape or the like.
特開２０１５－７８１１３号公報JP, 2015-78113, A
　ｆａｎ　ｏｕｔ型のＷＬＰとＰＬＰでは、複数の半導体チップを樹脂の封止材でモールドして、加工基板を形成した後に、加工基板の一方の表面に配線する工程、半田バンプを形成する工程等を有する。 In the fan-out type WLP and PLP, after a plurality of semiconductor chips are molded with a resin sealing material to form a processed substrate, the process of wiring on one surface of the processed substrate, the process of forming solder bumps, etc. Have.
　これらの工程は、約２００～３００℃の熱処理を伴うため、封止材が変形して、加工基板が寸法変化する虞がある。加工基板が寸法変化すると、加工基板の一方の表面に対して、高密度に配線することが困難になり、また半田バンプを正確に形成することも困難になる。 Since these steps involve heat treatment at about 200 to 300 ° C., the sealing material may be deformed and the processed substrate may undergo dimensional change. When the dimension of the processed substrate changes, it becomes difficult to wire densely to one surface of the processed substrate, and it becomes difficult to form solder bumps accurately.
　加工基板の寸法変化を抑制するために、支持基板としてガラス基板を用いることが有効である。しかし、ガラス基板を用いた場合であっても、加工基板の寸法変化が生じる場合があった。 In order to suppress the dimensional change of the processing substrate, it is effective to use a glass substrate as a supporting substrate. However, even when a glass substrate is used, dimensional change of the processed substrate may occur.
　本発明は、上記事情に鑑みなされたものであり、その技術的課題は、加工基板の寸法変化を生じさせ難い支持ガラス基板を創案することにより、半導体パッケージの高密度実装に寄与することである。 The present invention has been made in view of the above circumstances, and the technical problem is to contribute to high density mounting of a semiconductor package by creating a supporting glass substrate which hardly causes dimensional change of a processed substrate. .
　本発明者は、種々の実験を繰り返した結果、支持ガラス基板の熱膨張係数を厳密に規制すると共に、支持ガラス基板のヤング率を高めることにより、上記技術的課題を解決し得ることを見出し、本発明として、提案するものである。すなわち、本発明の支持ガラス基板は、３０～３８０℃の温度範囲における平均線熱膨張係数が３０×１０－７／℃以上であり、且つ５５×１０－７／℃以下であり、ヤング率が８０ＧＰａ以上であることを特徴とする。ここで、「３０～３８０℃の温度範囲における平均線熱膨張係数」は、ディラトメーターで測定可能である。「ヤング率」は、周知の共振法で測定可能である。 As a result of repeating various experiments, the inventor has found that the above technical problems can be solved by strictly controlling the thermal expansion coefficient of the supporting glass substrate and increasing the Young's modulus of the supporting glass substrate. It is proposed as the present invention. That is, the supporting glass substrate of the present invention has an average linear thermal expansion coefficient of 30 × 10 −7 / ° C. or more and 55 × 10 −7 / ° C. or less in the temperature range of 30 to 380 ° C., and has a Young's modulus It is characterized by being 80 GPa or more. Here, the “average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C.” can be measured by a dilatometer. "Young's modulus" can be measured by the well-known resonance method.
　本発明の支持ガラス基板では、３０～３８０℃の温度範囲における平均線熱膨張係数が３０×１０－７／℃以上であり、且つ５５×１０－７／℃以下に規制されている。このようにすれば、加工基板と支持ガラス基板の熱膨張係数を整合させ易くなる。そして、両者の熱膨張係数が整合すると、加工処理時に加工基板の寸法変化（特に、反り変形）を抑制し易くなる。結果として、加工基板の一方の表面に対して、高密度に配線することが可能になり、また半田バンプを正確に形成することも可能になる。 In the supporting glass substrate of the present invention, the average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. is regulated to 30 × 10 −7 / ° C. or more and 55 × 10 −7 / ° C. or less. In this way, the thermal expansion coefficients of the processing substrate and the supporting glass substrate can be easily matched. Then, when the thermal expansion coefficients of the two match, it is easy to suppress the dimensional change (in particular, the warpage deformation) of the processing substrate at the time of processing. As a result, wiring can be performed at high density on one surface of the processing substrate, and solder bumps can be formed accurately.
　更に、本発明の支持ガラス基板では、ヤング率が８０ＧＰａ以上に規制されている。このようにすれば、積層基板の剛性が向上するため、加工基板の寸法変化（特に、反り変形）を抑制し易くなり、加工基板を強固、且つ正確に支持することが可能になる。 Furthermore, in the supporting glass substrate of the present invention, Young's modulus is regulated to 80 GPa or more. In this way, the rigidity of the laminated substrate is improved, so dimensional change (particularly, warpage deformation) of the processed substrate can be easily suppressed, and the processed substrate can be firmly and accurately supported.
　また、本発明の支持ガラス基板は、全体板厚偏差（ＴＴＶ）が２．０μｍ未満であることが好ましい。このようにすれば、加工処理の精度を高め易くなる。特に配線精度を高めることができるため、高密度の配線が可能になる。更に支持ガラス基板の再利用回数を増やすことができる。ここで、「全体板厚偏差（ＴＴＶ）」は、全体の最大板厚と最小板厚の差であり、例えばコベルコ科研社製のＳＢＷ－３３１ＭＬ／ｄにより測定可能である。 Moreover, as for the support glass substrate of this invention, it is preferable that total plate thickness deviation (TTV) is less than 2.0 micrometers. This makes it easy to increase the accuracy of the processing. In particular, since the wiring accuracy can be improved, high density wiring can be achieved. Furthermore, the number of times of reuse of the supporting glass substrate can be increased. Here, the “total thickness deviation (TTV)” is the difference between the maximum thickness and the minimum thickness of the whole, and can be measured, for example, by SBW-331ML / d manufactured by Kobelco Research Institute.
　また、本発明の支持ガラス基板は、ガラス組成として、質量％で、ＳｉＯ２　５０～６６％、Ａｌ２Ｏ３　７～３４％、Ｂ２Ｏ３　０～８％、ＭｇＯ　０～２２％、ＣａＯ　１～１５％、Ｙ２Ｏ３＋Ｌａ２Ｏ３＋ＺｒＯ２　０～２０％を含有することが好ましい。ここで、「Ｙ２Ｏ３＋Ｌａ２Ｏ３＋ＺｒＯ２」は、Ｙ２Ｏ３、Ｌａ２Ｏ３及びＺｒＯ２の合量を指す。 In addition, the supporting glass substrate of the present invention is composed of SiO 2 50 to 66%, Al 2 O 3 7 to 34%, B 2 O 3 0 to 8%, MgO 0 to 22%, CaO by mass as a glass composition. It is preferable to contain 1 to 15%, and Y 2 O 3 + La 2 O 3 + ZrO 2 0 to 20%. Here, “Y 2 O 3 + La 2 O 3 + ZrO 2 ” refers to the total amount of Y 2 O 3 , La 2 O 3 and ZrO 2 .
　また、本発明の支持ガラス基板は、半導体パッケージの製造工程で、半導体チップが樹脂にモールドされた加工基板の支持に用いることが好ましい。 Moreover, it is preferable to use the support glass substrate of this invention for support of the process board | substrate by which the semiconductor chip was molded by resin at the manufacturing process of a semiconductor package.
　また、本発明の積層基板は、少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板であって、支持ガラス基板が上記の支持ガラス基板であることが好ましい。 The laminated substrate of the present invention is preferably a laminated substrate provided with at least a processing substrate and a supporting glass substrate for supporting the processing substrate, and the supporting glass substrate is preferably the above supporting glass substrate.
　また、本発明の積層基板は、加工基板が、半導体チップが樹脂にモールドされた加工基板であることが好ましい。 Further, in the laminated substrate of the present invention, the processed substrate is preferably a processed substrate in which a semiconductor chip is molded in a resin.
　また、本発明の半導体パッケージの製造方法は、少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板を用意する工程と、加工基板に対して、加工処理を行う工程と、を有すると共に、支持ガラス基板が上記の支持ガラス基板であることが好ましい。 Further, according to a method of manufacturing a semiconductor package of the present invention, a process of preparing a laminated substrate including at least a processed substrate and a supporting glass substrate for supporting the processed substrate, a process of performing processing on the processed substrate, Preferably, the supporting glass substrate is the above supporting glass substrate.
　また、本発明の半導体パッケージの製造方法は、加工処理が、加工基板の一方の表面に配線する工程を含むことが好ましい。 Preferably, in the method of manufacturing a semiconductor package according to the present invention, the processing includes a step of wiring on one surface of a processing substrate.
　また、本発明の半導体パッケージの製造方法は、加工処理が、加工基板の一方の表面に半田バンプを形成する工程を含むことが好ましい。 Preferably, in the method of manufacturing a semiconductor package according to the present invention, the processing includes the step of forming a solder bump on one surface of the processing substrate.
本発明の積層基板の一例を示す概念斜視図である。It is a conceptual perspective view which shows an example of the laminated substrate of this invention. ｆａｎ　ｏｕｔ型のＷＬＰのチップファースト型の製造工程を示す概念断面図である。FIG. 14 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP chip-first type. 支持ガラス基板をバックグラインド基板に用いて、加工基板を薄型化する工程を示す概念断面図である。It is a conceptual sectional view showing a process of thinning a processed substrate by using a supporting glass substrate as a back grind substrate.
　本発明の支持ガラス基板において、３０～３８０℃の温度範囲における平均線熱膨張係数は３０×１０－７／℃以上であり、且つ５５×１０－７／℃以下であり、好ましくは３２×１０－７／℃以上、且つ５２×１０－７／℃以下、好ましくは３３×１０－７／℃以上、且つ４９×１０－７／℃以下、特に好ましくは３４×１０－７／℃以上、且つ４４×１０－７／℃以下である。３０～３８０℃の温度範囲における平均線熱膨張係数が上記範囲外になると、加工基板と支持ガラス基板の熱膨張係数が整合し難くなる。そして、両者の熱膨張係数が不整合になると、加工処理時に加工基板の寸法変化（特に、反り変形）が生じ易くなる。 In the supporting glass substrate of the present invention, the average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. is 30 × 10 −7 / ° C. or more and 55 × 10 −7 / ° C. or less, preferably 32 × 10 10 −7 / ° C. or higher and 52 × 10 −7 / ° C. or lower, preferably 33 × 10 −7 / ° C. or higher and 49 × 10 −7 / ° C. or lower, particularly preferably 34 × 10 −7 / ° C. or higher 44 × 10 −7 / ° C. or less. When the average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. is out of the above range, it becomes difficult to match the thermal expansion coefficients of the processed substrate and the supporting glass substrate. Then, if the thermal expansion coefficients of the two are mismatched, dimensional change (in particular, warpage deformation) of the processed substrate is likely to occur during processing.
　本発明の支持ガラス基板において、ヤング率は、好ましくは８０ＧＰａ以上、８５ＧＰａ以上、９０ＧＰａ以上、９５ＧＰａ以上、特に９６～１３０ＧＰａである。ヤング率が低過ぎると、積層体の剛性を維持し難くなり、加工基板の寸法変化（特に反り変形）が発生し易くなる。 In the supporting glass substrate of the present invention, Young's modulus is preferably 80 GPa or more, 85 GPa or more, 90 GPa or more, 95 GPa or more, and particularly 96 to 130 GPa. If the Young's modulus is too low, it is difficult to maintain the rigidity of the laminate, and dimensional change (especially, warpage deformation) of the processed substrate is likely to occur.
　本発明の支持ガラス基板において、全体板厚偏差（ＴＴＶ）は、好ましくは２．０μｍ未満、１．５μｍ以下、１．０μｍ以下、特に０．１～１．０μｍ未満である。全体板厚偏差（ＴＴＶ）が大き過ぎると、加工処理の精度が低下し易くなる。更に支持ガラス基板を再利用し難くなる。 In the supporting glass substrate of the present invention, the overall thickness deviation (TTV) is preferably less than 2.0 μm, 1.5 μm or less, 1.0 μm or less, and particularly 0.1 to less than 1.0 μm. If the overall thickness deviation (TTV) is too large, the accuracy of the processing tends to be reduced. Furthermore, it becomes difficult to reuse the supporting glass substrate.
　本発明の支持ガラス基板は、表面全体が研磨面であることが好ましい。このようにすれば、全体板厚偏差（ＴＴＶ）を２．０μｍ未満、１．５μｍ以下、１．０μｍ以下、特に１．０μｍ未満に規制し易くなる。研磨処理の方法としては、種々の方法を採用することができるが、ガラス基板の両面を一対の研磨パッドで挟み込み、ガラス基板と一対の研磨パッドを共に回転させながら、ガラス基板を研磨処理する方法が好ましい。更に一対の研磨パッドは外径が異なることが好ましく、研磨の際に間欠的にガラス基板の一部が研磨パッドから食み出すように研磨処理することが好ましい。これにより、全体板厚偏差（ＴＴＶ）を低減し易くなり、また反り量も低減し易くなる。なお、研磨処理において、研磨深さは特に限定されないが、研磨深さは、好ましくは５０μｍ以下、３０μｍ以下、２０μｍ以下、特に１０μｍ以下である。研磨深さが小さい程、支持ガラス基板の生産性が向上する。 The entire surface of the supporting glass substrate of the present invention is preferably a polished surface. In this way, the overall thickness deviation (TTV) can be easily regulated to less than 2.0 μm, 1.5 μm or less, 1.0 μm or less, particularly less than 1.0 μm. Although various methods can be adopted as the method of polishing treatment, both sides of the glass substrate are sandwiched by a pair of polishing pads, and the glass substrate is polished while rotating the glass substrate and the pair of polishing pads together. Is preferred. Furthermore, it is preferable that the pair of polishing pads have different outer diameters, and it is preferable to perform polishing treatment so that a part of the glass substrate is intermittently ejected from the polishing pad during polishing. As a result, the overall thickness deviation (TTV) can be easily reduced, and the amount of warpage can also be easily reduced. In the polishing treatment, although the polishing depth is not particularly limited, the polishing depth is preferably 50 μm or less, 30 μm or less, 20 μm or less, particularly 10 μm or less. As the polishing depth is smaller, the productivity of the supporting glass substrate is improved.
　本発明の支持ガラス基板は、ガラス組成として、質量％で、ＳｉＯ２　５０～６６％、Ａｌ２Ｏ３　７～３４％、Ｂ２Ｏ３　０～８％、ＭｇＯ　０～２２％、ＣａＯ　１～１５％、Ｙ２Ｏ３＋Ｌａ２Ｏ３＋ＺｒＯ２　０～２０％を含有することが更に好ましい。上記のように各成分の含有量を限定した理由を以下に示す。なお、各成分の含有量の説明において、％表示は、特に断りがある場合を除き、質量％を表す。 Supporting glass substrate of the present invention has a glass composition, in mass%, SiO 2 50 ~ 66% , Al 2 O 3 7 ~ 34%, B 2 O 3 0 ~ 8%, MgO 0 ~ 22%, CaO 1 ~ More preferably, it contains 15% of Y 2 O 3 + La 2 O 3 + ZrO 2 0 to 20%. The reason which limited content of each component as mentioned above is shown below. In addition, in description of content of each component,% display represents mass%, unless there is particular notice.
　ＳｉＯ２は、ガラスのネットワークを形成する成分である。ＳｉＯ２の含有量は、好ましくは５０～６６％、５１～６５％、５２～６４％、５３～６３％、５４～６２．５％、５６～６２％、特に５８～６１％である。ＳｉＯ２の含有量が少な過ぎると、ガラス化し難くなり、また耐候性が低下し易くなる。更に熱膨張係数が高くなり過ぎる。一方、ＳｉＯ２の含有量が多過ぎると、溶融性や成形性が低下し易くなり、また熱膨張係数が低くなり過ぎる。 SiO 2 is a component that forms a glass network. The content of SiO 2 is preferably 50 to 66%, 51 to 65%, 52 to 64%, 53 to 63%, 54 to 62.5%, 56 to 62%, in particular 58 to 61%. When the content of SiO 2 is too small, it is difficult to vitrify and the weather resistance is easily lowered. Furthermore, the thermal expansion coefficient becomes too high. On the other hand, when the content of SiO 2 is too large, the meltability and the formability tend to be lowered, and the thermal expansion coefficient becomes too low.
　Ａｌ２Ｏ３は、ヤング率や耐候性を高める成分である。Ａｌ２Ｏ３の含有量は、好ましくは７～３４％、８～２６％、９～２４％、１１～２３％、１２～２２％、１４～２１％、特に１６～２１％である。Ａｌ２Ｏ３の含有量が少な過ぎると、ヤング率や耐候性が低下し易くなる。一方、Ａｌ２Ｏ３の含有量が多過ぎると、溶融性、成形性及び耐失透性が低下し易くなる。 Al 2 O 3 is a component that enhances Young's modulus and weather resistance. The content of Al 2 O 3 is preferably 7 to 34%, 8 to 26%, 9 to 24%, 11 to 23%, 12 to 22%, 14 to 21%, particularly 16 to 21%. When the content of Al 2 O 3 is too small, Young's modulus and weather resistance tend to be lowered. On the other hand, when the content of Al 2 O 3 is too large, the meltability, the formability and the devitrification resistance tend to be lowered.
　Ｂ２Ｏ３は、ガラスのネットワークを形成する成分であるが、ヤング率や耐候性を低下させる成分である。よって、Ｂ２Ｏ３の含有量は、好ましくは０～８％、０．１～７％、１～６％、特に３～５％である。 B 2 O 3 is a component that forms a network of glass, but is a component that reduces Young's modulus and weather resistance. Therefore, the content of B 2 O 3 is preferably 0 to 8%, 0.1 to 7%, 1 to 6%, particularly 3 to 5%.
　ＭｇＯは、ヤング率を大幅に高める成分であり、また高温粘度を低下させて、溶融性や成形性を高める成分である。ＭｇＯの含有量は、好ましくは０～２２％、０．５～２１％、１～２０．５％、２～２０％、４～１９．５％、５～１９％、７～１９％、８～１８％、８．５～１６％、９～１６％、９～１４％、特に９～１２％である。ＭｇＯの含有量が少な過ぎると、上記効果を享受し難くなる。一方、ＭｇＯの含有量が多過ぎると、耐失透性が低下し易くなる。 MgO is a component that greatly enhances the Young's modulus, and is also a component that reduces the high temperature viscosity to enhance the meltability and the formability. The content of MgO is preferably 0 to 22%, 0.5 to 21%, 1 to 20.5%, 2 to 20%, 4 to 19.5%, 5 to 19%, 7 to 19%, 8 18%, 8.5-16%, 9-16%, 9-14%, especially 9-12%. When the content of MgO is too small, it becomes difficult to receive the above effect. On the other hand, when the content of MgO is too large, the devitrification resistance tends to decrease.
　ＣａＯは、高温粘度を低下させて、溶融性及び成形性を高める成分である。ＣａＯの含有量は、好ましくは１～１５％、２～１２％、３～１０％、特に５～８％である。ＣａＯの含有量が少な過ぎると、上記効果を享受し難くなる。一方、ＣａＯの含有量が多過ぎると、耐失透性が低下し易くなる。 CaO is a component that reduces the high temperature viscosity to enhance the meltability and the formability. The content of CaO is preferably 1 to 15%, 2 to 12%, 3 to 10%, in particular 5 to 8%. When the content of CaO is too small, it becomes difficult to receive the above effect. On the other hand, when the content of CaO is too large, the devitrification resistance tends to decrease.
　ヤング率を高める観点から、モル比ＭｇＯ／（ＭｇＯ＋ＣａＯ＋ＳｒＯ＋ＢａＯ）は、好ましくは０以上、０．１以上、０．２以上、０．３以上、０．４以上、０．５以上、０．６以上、特に０．７以上である。なお、「ＭｇＯ／（ＭｇＯ＋ＣａＯ＋ＳｒＯ＋ＢａＯ）」は、ＭｇＯの含有量をＭｇＯ、ＣａＯ、ＳｒＯ及びＢａＯの合量で割った値である。 From the viewpoint of increasing the Young's modulus, the molar ratio MgO / (MgO + CaO + SrO + BaO) is preferably 0 or more, 0.1 or more, 0.2 or more, 0.3 or more, 0.4 or more, 0.4 or more, 0.5 or more, 0.6 or more , Especially 0.7 or more. "MgO / (MgO + CaO + SrO + BaO)" is a value obtained by dividing the content of MgO by the total amount of MgO, CaO, SrO and BaO.
　Ｙ２Ｏ３、Ｌａ２Ｏ３及びＺｒＯ２は、ヤング率を高める成分である。Ｙ２Ｏ３、Ｌａ２Ｏ３及びＺｒＯ２の合量は、好ましくは０～２０％、０．１～１８％、０．５～１６％、１～１５％、１～１４％、１～１２％、１．２～１０％、１．３～８％、特に１．５～５％である。Ｙ２Ｏ３、Ｌａ２Ｏ３及びＺｒＯ２の合量が多過ぎると、耐失透性が低下し易くなる。Ｙ２Ｏ３の含有量は、好ましくは０～１５％、０．１～１４％、０．５～１３％、０．５～１２％、０．５～１０％、０．５～８％、０．５～６％、特に１～４％である。Ｌａ２Ｏ３の含有量は、好ましくは０～６％、０～４％、特に０～２％である。ＺｒＯ２の含有量は、好ましくは０～１０％、０．１～６％、０．５～４％、特に１～３％である。Ｙ２Ｏ３の含有量が多過ぎると、耐失透性が低下し易くなり、また原料コストが高騰し易くなる。Ｌａ２Ｏ３の含有量が多過ぎると、耐失透性が低下し易くなり、また原料コストが高騰し易くなる。ＺｒＯ２の含有量が多過ぎると、耐失透性が低下し易くなる。 Y 2 O 3 , La 2 O 3 and ZrO 2 are components that increase the Young's modulus. The total amount of Y 2 O 3 , La 2 O 3 and ZrO 2 is preferably 0 to 20%, 0.1 to 18%, 0.5 to 16%, 1 to 15%, 1 to 14%, 1 to 12%, 1.2 to 10%, 1.3 to 8%, especially 1.5 to 5%. If the total amount of Y 2 O 3 , La 2 O 3 and ZrO 2 is too large, the devitrification resistance tends to be reduced. The content of Y 2 O 3 is preferably 0 to 15%, 0.1 to 14%, 0.5 to 13%, 0.5 to 12%, 0.5 to 10%, and 0.5 to 8%. 0.5 to 6%, in particular 1 to 4%. The content of La 2 O 3 is preferably 0 to 6%, 0 to 4%, in particular 0 to 2%. The content of ZrO 2 is preferably 0 to 10%, 0.1 to 6%, 0.5 to 4%, in particular 1 to 3%. If the content of Y 2 O 3 is too large, the devitrification resistance is likely to be reduced, and the raw material cost is likely to be increased. When the content of La 2 O 3 is too large, the devitrification resistance is apt to decrease, and the cost of the raw material tends to increase. When the content of ZrO 2 is too large, the devitrification resistance tends to be reduced.
　上記成分以外にも、例えば以下の成分を添加してもよい。 Besides the above components, for example, the following components may be added.
　ＳｒＯ及びＢａＯは、高温粘度を低下させて、溶融性及び成形性を高める成分である。ＳｒＯ及びＢａＯは、それぞれ０～１５％、０．１～１２％、特に０．５～１０％である。 SrO and BaO are components that lower the high temperature viscosity to enhance the meltability and the formability. SrO and BaO are each 0 to 15%, 0.1 to 12%, especially 0.5 to 10%.
　ＺｎＯは、高温粘性を下げて、溶融性を顕著に高める成分である。ＺｎＯの含有量は、好ましくは０～７％、０．１～５％、特に０．５～３％である。ＺｎＯの含有量が少な過ぎると、上記効果を享受し難くなる。なお、ＺｎＯの含有量が多過ぎると、ガラスが失透し易くなる。 ZnO is a component that lowers the high temperature viscosity and significantly enhances the meltability. The content of ZnO is preferably 0 to 7%, 0.1 to 5%, in particular 0.5 to 3%. When the content of ZnO is too small, it becomes difficult to receive the above effect. When the content of ZnO is too large, the glass is easily devitrified.
　Ｌｉ２Ｏ、Ｎａ２Ｏ及びＫ２Ｏは、高温粘度を低下させて、溶融性及び成形性を高める成分であるが、熱膨張係数を上昇させる成分である。高温粘度を低下させて、溶融性及び成形性を高めると共に、熱膨張係数を上昇させるには、Ｌｉ２Ｏ、Ｎａ２Ｏ及びＫ２Ｏの合量は、好ましくは０～１５％、０．０１～１０％、０．０５～８％、特に０．１～５％である。Ｌｉ２Ｏ、Ｎａ２Ｏ及びＫ２Ｏのそれぞれの含有量は、好ましくは０～１０％、０．０１～５％、０．０５～４％、特に０．１～３％未満である。熱膨張係数を低下させるためには、Ｌｉ２Ｏ、Ｎａ２Ｏ及びＫ２Ｏの合量は、好ましくは０～１５％、０～１０％、０～５％、０～１％、０～０．１％、０～０．０５％、特に０～０．０１％未満である。Ｌｉ２Ｏ、Ｎａ２Ｏ及びＫ２Ｏのそれぞれの含有量は、好ましくは０～１５％、０～１０％、０～５％、０～１％、０～０．１％、０～０．０５％、特に０～０．０１％未満である。 Li 2 O, Na 2 O and K 2 O are components that reduce the high temperature viscosity to improve the meltability and the formability, but are components that increase the thermal expansion coefficient. The total amount of Li 2 O, Na 2 O and K 2 O is preferably 0 to 15%, preferably 0 to 15%, in order to lower the high temperature viscosity and to enhance the meltability and the formability and to increase the thermal expansion coefficient. It is from 01 to 10%, from 0.05 to 8%, in particular from 0.1 to 5%. The respective content of Li 2 O, Na 2 O and K 2 O is preferably 0 to 10%, 0.01 to 5%, 0.05 to 4%, in particular 0.1 to less than 3%. In order to reduce the thermal expansion coefficient, the total amount of Li 2 O, Na 2 O and K 2 O is preferably 0 to 15%, 0 to 10%, 0 to 5%, 0 to 1%, 0 to 0.1%, 0 to 0.05%, in particular 0 to less than 0.01%. The content of each of Li 2 O, Na 2 O and K 2 O is preferably 0 to 15%, 0 to 10%, 0 to 5%, 0 to 1%, 0 to 0.1%, 0 to 0 .05%, in particular 0 to less than 0.01%.
　ＴｉＯ２は、耐候性を高める成分であるが、ガラスを着色させる成分である。よって、ＴｉＯ２の含有量は、好ましくは０～０．５％、特に０～０．１％未満である。 TiO 2 is a component that enhances the weather resistance, but is a component that colors the glass. Thus, the content of TiO 2 is preferably 0 to 0.5%, in particular 0 to less than 0.1%.
　清澄剤として、ＳｎＯ２、Ｃｌ、ＳＯ３、ＣｅＯ２の群（好ましくはＳｎＯ２、ＳＯ３の群）から選択された一種又は二種以上を０．０５～０．５％添加してもよい。 0.05 to 0.5% of one or more selected from the group of SnO 2 , Cl, SO 3 , CeO 2 (preferably a group of SnO 2 , SO 3 ) may be added as a clarifier .
　Ｆｅ２Ｏ３は、ガラス原料に不純物として不可避的に混入する成分であり、着色成分である。よって、Ｆｅ２Ｏ３の含有量は、好ましくは０．５％以下、０．００１～０．１％、０．００５～０．０７％、０．００８～０．０３％、特に０．０１～０．０２５％である。 Fe 2 O 3 is a component which is inevitably mixed as an impurity into a glass raw material and is a coloring component. Therefore, the content of Fe 2 O 3 is preferably 0.5% or less, 0.001 to 0.1%, 0.005 to 0.07%, 0.008 to 0.03%, particularly 0.01. It is -0.025%.
　Ｖ２Ｏ５、Ｃｒ２Ｏ３、ＣｏＯ３及びＮｉＯは、着色成分である。よって、Ｖ２Ｏ５、Ｃｒ２Ｏ３、ＣｏＯ３及びＮｉＯのそれぞれの含有量は、好ましくは０．１％以下、特に０．０１％未満である。 V 2 O 5 , Cr 2 O 3 , CoO 3 and NiO are coloring components. Thus, the content of each of V 2 O 5 , Cr 2 O 3 , CoO 3 and NiO is preferably at most 0.1%, in particular less than 0.01%.
　環境的配慮から、ガラス組成として、実質的にＡｓ２Ｏ３、Ｓｂ２Ｏ３、ＰｂＯ、Ｂｉ２Ｏ３及びＦを含有しないことが好ましい。ここで、「実質的に～を含有しない」とは、ガラス成分として積極的に明示の成分を添加しないものの、不純物として混入する場合を許容する趣旨であり、具体的には、明示の成分の含有量が０．０５％未満であることを指す。 From the environmental consideration, it is preferable that the glass composition substantially does not contain As 2 O 3 , Sb 2 O 3 , PbO, Bi 2 O 3 and F. Here, "does not substantially contain ..." is a concept that does not positively add an explicit component as a glass component, but allows the case of mixing as an impurity, and more specifically, It indicates that the content is less than 0.05%.
　本発明の支持ガラス基板は、以下の特性を有することが好ましい。 The supporting glass substrate of the present invention preferably has the following characteristics.
　歪点は、好ましくは５８０℃以上、６２０℃以上、６５０℃以上、６８０℃以上、特に７００～８５０℃である。歪点が高い程、半導体パッケージの製造工程において支持ガラス基板の熱収縮を低減し易くなる。結果として、加工処理の精度を高め易くなる。なお、「歪点」は、ＡＳＴＭ　Ｃ３３６の方法に基づいて測定した値を指す。 The strain point is preferably 580 ° C. or more, 620 ° C. or more, 650 ° C. or more, 680 ° C. or more, particularly 700 to 850 ° C. The higher the strain point, the easier it is to reduce the thermal contraction of the supporting glass substrate in the manufacturing process of the semiconductor package. As a result, it becomes easy to improve the accuracy of processing. In addition, a "distortion point" points out the value measured based on the method of ASTMC336.
　液相温度は、好ましくは１３００℃以下、１２８０℃以下、１２５０℃以下、１１６０℃以下、１１３０℃以下、特に１１００℃以下である。このようにすれば、板状に成形し易くなるため、表面を研磨しなくても、或いは少量の研磨によって、全体板厚偏差（ＴＴＶ）を２．０μｍ未満、特に１．０μｍ未満まで低減することができ、結果として、支持ガラス基板の製造コストを低廉化することができる。更に、成形時に失透結晶が発生する事態を防止し易くなる。ここで、「液相温度」は、標準篩３０メッシュ（５００μｍ）を通過し、５０メッシュ（３００μｍ）に残るガラス粉末を白金ボートに入れた後、温度勾配炉中に２４時間保持して、結晶が析出する温度を測定することにより算出可能である。 The liquidus temperature is preferably 1300 ° C. or less, 1280 ° C. or less, 1250 ° C. or less, 1160 ° C. or less, 1130 ° C. or less, particularly 1100 ° C. or less. In this way, since it becomes easy to form in a plate shape, the overall thickness deviation (TTV) can be reduced to less than 2.0 μm, particularly less than 1.0 μm, without polishing the surface or by a small amount of polishing. As a result, the manufacturing cost of the supporting glass substrate can be reduced. Furthermore, it is easy to prevent the occurrence of devitrified crystals at the time of molding. Here, “liquidus temperature” is passed through a standard sieve of 30 mesh (500 μm) and the glass powder remaining on 50 mesh (300 μm) is put in a platinum boat and then held in a temperature gradient furnace for 24 hours to It is computable by measuring the temperature which precipitates.
　液相粘度は、好ましくは１０３．８ｄＰａ・ｓ以上、１０４．０ｄＰａ・ｓ以上、１０４．２ｄＰａ・ｓ以上、１０４．４ｄＰａ・ｓ以上、特に１０４．６ｄＰａ・ｓ以上である。このようにすれば、板状に成形し易くなるため、表面を研磨しなくても、或いは少量の研磨によって、全体板厚偏差（ＴＴＶ）を２．０μｍ未満、特に１．０μｍ未満まで低減することができ、結果として、支持ガラス基板の製造コストを低廉化することができる。ここで、「液相粘度」は、白金球引き上げ法で測定可能である。 The liquid phase viscosity is preferably 10 3.8 dPa · s or more, 10 4.0 dPa · s or more, 10 4.2 dPa · s or more, 10 4.4 dPa · s or more, particularly 10 4.6 dPa · s or more. In this way, since it becomes easy to form in a plate shape, the overall thickness deviation (TTV) can be reduced to less than 2.0 μm, particularly less than 1.0 μm, without polishing the surface or by a small amount of polishing. As a result, the manufacturing cost of the supporting glass substrate can be reduced. Here, the "liquid phase viscosity" can be measured by a platinum ball pulling method.
　１０２．５ｄＰａ・ｓにおける温度は、好ましくは１５５０℃以下、１５００℃以下、１４８０℃以下、１４５０℃以下、特に１２００～１４００℃以下である。１０２．５ｄＰａ・ｓにおける温度が高くなると、溶融性が低下して、支持ガラス基板の製造コストが高騰する。ここで、「１０２．５ｄＰａ・ｓにおける温度」は、白金球引き上げ法で測定可能である。 The temperature at 10 2.5 dPa · s is preferably 1550 ° C. or less, 1500 ° C. or less, 1480 ° C. or less, 1450 ° C. or less, in particular 1200 to 1400 ° C. or less. As the temperature at 10 2.5 dPa · s increases, the meltability decreases and the manufacturing cost of the supporting glass substrate rises. Here, “temperature at 10 2.5 dPa · s” can be measured by a platinum ball pulling method.
　板厚は、好ましくは１．５ｍｍ以下、１．２ｍｍ以下、１．０ｍｍ以下、特に０．９ｍｍ以下である。一方、板厚が薄過ぎると、支持ガラス基板自体の強度が低下して、支持基板としての機能を果たし難くなる。よって、支持ガラス基板の板厚は、好ましくは０．５ｍｍ以上、０．６ｍｍ以上、特に０．７ｍｍ超である。 The plate thickness is preferably 1.5 mm or less, 1.2 mm or less, 1.0 mm or less, particularly 0.9 mm or less. On the other hand, when the plate thickness is too thin, the strength of the supporting glass substrate itself is reduced, and it becomes difficult to fulfill the function as the supporting substrate. Therefore, the plate thickness of the supporting glass substrate is preferably 0.5 mm or more, 0.6 mm or more, particularly preferably 0.7 mm or more.
　反り量は、好ましくは６０μｍ以下、５５μｍ以下、５０μｍ以下、１～４５μｍ、特に５～４０μｍである。反り量が小さい程、加工処理の精度を高め易くなる。特に配線精度を高めることができるため、高密度の配線が可能になる。なお、反り量を低減するためには、複数のガラス基板を積層させて熱処理を行うことが好ましい。なお、「反り量」は、支持ガラス基板全体における最高位点と最小二乗焦点面との間の最大距離の絶対値と、最低位点と最小二乗焦点面との絶対値との合計を指し、例えばコベルコ科研社製のＳＢＷ－３３１ＭＬ／ｄにより測定可能である。 The amount of warpage is preferably 60 μm or less, 55 μm or less, 50 μm or less, 1 to 45 μm, and particularly 5 to 40 μm. The smaller the amount of warpage, the easier it is to improve the processing accuracy. In particular, since the wiring accuracy can be improved, high density wiring can be achieved. In order to reduce the amount of warpage, it is preferable to perform heat treatment by laminating a plurality of glass substrates. The "warpage amount" refers to the sum of the absolute value of the maximum distance between the highest position and the least square focal plane in the entire support glass substrate and the absolute value of the lowest position and the least square focal plane, For example, it can be measured by SBW-331ML / d manufactured by Kobelco Research Institute.
　本発明の支持ガラス基板は、ウエハ状（略真円状）が好ましく、その直径は１００ｍｍ以上５００ｍｍ以下、特に１５０ｍｍ以上４５０ｍｍ以下が好ましく、その真円度（但し、ノッチ部を除く）は１ｍｍ以下、０．１ｍｍ以下、０．０５ｍｍ以下、特に０．０３ｍｍ以下が好ましい。このようにすれば、半導体パッケージの製造工程に適用し易くなる。なお、「真円度」は、ウエハの外形の最大値から最小値を減じた値である。 The support glass substrate of the present invention is preferably in the form of a wafer (substantially round), and the diameter is preferably 100 mm to 500 mm, more preferably 150 mm to 450 mm, and its roundness (excluding the notch portion) is 1 mm or less 0.1 mm or less, 0.05 mm or less, particularly 0.03 mm or less is preferable. This makes it easy to apply to the manufacturing process of the semiconductor package. The “roundness” is a value obtained by subtracting the minimum value from the maximum value of the outer shape of the wafer.
　本発明の支持ガラス基板は、ノッチ部（ノッチ形状の位置合わせ部）を有することが好ましく、ノッチ部の深部は平面視で略円形状又は略Ｖ溝形状であることがより好ましい。これにより、支持ガラス基板のノッチ部に位置決めピン等の位置決め部材を当接させて、支持ガラス基板の位置を固定し易くなる。結果として、支持ガラス基板と加工基板の位置合わせが容易になる。特に、加工基板にもノッチ部を形成して、位置決め部材を当接させると、積層体全体の位置合わせが容易になる。 The supporting glass substrate of the present invention preferably has a notch portion (notch-shaped alignment portion), and the deep portion of the notch portion is more preferably substantially circular or substantially V-shaped in a plan view. This makes it easy to fix the position of the support glass substrate by bringing a positioning member such as a positioning pin into contact with the notch portion of the support glass substrate. As a result, alignment of the supporting glass substrate and the processing substrate is facilitated. In particular, when notches are also formed on the processing substrate and the positioning member is made to abut, alignment of the entire laminate becomes easy.
　一方、支持ガラス基板のノッチ部に位置決め部材を当接すると、ノッチ部に応力が集中し易くなり、ノッチ部を起点にして、支持ガラス基板が破損し易くなる。特に、支持ガラス基板が外力により湾曲した時に、その傾向が顕著になる。よって、ノッチ部の表面と端面とが交差する端縁領域の全部又は一部が面取りされていることが好ましい。これにより、ノッチ部を起点にした破損を有効に回避することができる。 On the other hand, when the positioning member abuts on the notch portion of the support glass substrate, stress is easily concentrated on the notch portion, and the support glass substrate is easily broken starting from the notch portion. In particular, when the supporting glass substrate is curved by an external force, the tendency becomes remarkable. Therefore, it is preferable that the whole or one part of the edge area | region where the surface and end surface of a notch cross | intersect is chamfered. In this way, damage originating from the notch can be effectively avoided.
　ノッチ部の表面と端面とが交差する端縁領域の５０％以上が面取りされていることが更に好ましく、ノッチ部の表面と端面とが交差する端縁領域の９０％以上が面取りされていることが特に好ましく、ノッチ部の表面と端面とが交差する端縁領域の全部が面取りされていることが最も好ましい。ノッチ部において面取りされている領域が大きい程、ノッチ部を起点にした破損の確率を低減することができる。 More preferably, at least 50% of the edge region where the surface of the notch crosses the end surface is chamfered, and at least 90% of the edge region where the surface of the notch crosses the end surface is chamfered It is particularly preferable that the entire edge area where the surface of the notch and the end face intersect is chamfered. The larger the chamfered area in the notch, the lower the probability of breakage starting from the notch can be reduced.
　ノッチ部のおもて面方向の面取り幅（裏面方向の面取り幅も同様）は、好ましくは５０～９００μｍ、２００～８００μｍ、３００～７００μｍ、４００～６５０μｍ、特に５００～６００μｍである。ノッチ部の表面方向の面取り幅が小さ過ぎると、ノッチ部を起点にして、支持ガラス基板が破損し易くなる。一方、ノッチ部のおもて面方向の面取り幅が大き過ぎると、面取り効率が低下して、支持ガラス基板の製造コストが高騰し易くなる。 The chamfering width in the front surface direction of the notch portion (also the chamfering width in the back surface direction is the same) is preferably 50 to 900 μm, 200 to 800 μm, 300 to 700 μm, 400 to 650 μm, particularly 500 to 600 μm. If the chamfering width in the surface direction of the notch portion is too small, the supporting glass substrate is likely to be broken starting from the notch portion. On the other hand, if the chamfering width in the front surface direction of the notch portion is too large, the chamfering efficiency is reduced, and the manufacturing cost of the supporting glass substrate is easily increased.
　ノッチ部の板厚方向の面取り幅（おもて面と裏面の面取り幅の合計）は、好ましくは板厚の５～８０％、２０～７５％、３０～７０％、３５～６５％、特に４０～６０％である。ノッチ部の板厚方向の面取り幅が小さ過ぎると、ノッチ部を起点にして、支持ガラス基板が破損し易くなる。一方、ノッチ部の板厚方向の面取り幅が大き過ぎると、外力がノッチ部の端面に集中し易くなり、ノッチ部の端面を起点にして、支持ガラス基板が破損し易くなる。 The chamfering width in the plate thickness direction of the notch (total of the chamfering widths on the front and back surfaces) is preferably 5 to 80%, 20 to 75%, 30 to 70%, 35 to 65% of the plate thickness, in particular 40 to 60%. When the chamfering width in the plate thickness direction of the notch portion is too small, the supporting glass substrate is easily broken starting from the notch portion. On the other hand, when the chamfering width in the plate thickness direction of the notch portion is too large, the external force is easily concentrated on the end surface of the notch portion, and the supporting glass substrate is easily damaged starting from the end surface of the notch portion.
　本発明の支持ガラス基板は、全体板厚偏差（ＴＴＶ）を低減する観点から、化学強化処理がなされていないことが好ましい。つまり表面に圧縮応力層を有しないことが好ましい。 From the viewpoint of reducing the overall thickness deviation (TTV), it is preferable that the support glass substrate of the present invention is not chemically strengthened. That is, it is preferable not to have a compressive stress layer on the surface.
　支持ガラス基板の成形方法として、種々の方法を採択することができる。例えば、スロットダウン法、ロールアウト法、リドロー法、フロート法、インゴット成型法等を採択することができる。 Various methods can be adopted as a method of forming the supporting glass substrate. For example, a slot down method, a roll out method, a redraw method, a float method, an ingot forming method, etc. can be adopted.
　本発明の積層基板は、少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板であって、支持ガラス基板が上記の支持ガラス基板であることを特徴とする。ここで、本発明の積層基板の技術的特徴（好適な構成、効果）は、本発明の支持ガラス基板の技術的特徴と重複する。よって、本明細書では、その重複部分について、詳細な記載を省略する。 The layered substrate of the present invention is a layered substrate provided with at least a processing substrate and a supporting glass substrate for supporting the processing substrate, and the supporting glass substrate is the above supporting glass substrate. Here, the technical features (preferred configuration, effects) of the laminated substrate of the present invention overlap with the technical features of the supporting glass substrate of the present invention. Therefore, in the present specification, the detailed description of the overlapping portions is omitted.
　本発明の積層基板は、加工基板と支持ガラス基板の間に、接着層を有することが好ましい。接着層は、樹脂であることが好ましく、例えば、熱硬化性樹脂、光硬化性樹脂（特に紫外線硬化樹脂）等が好ましい。また半導体パッケージの製造工程における熱処理に耐える耐熱性を有するものが好ましい。これにより、半導体パッケージの製造工程で接着層が融解し難くなり、加工処理の精度を高めることができる。 The laminated substrate of the present invention preferably has an adhesive layer between the processing substrate and the supporting glass substrate. The adhesive layer is preferably a resin, and for example, a thermosetting resin, a photocurable resin (in particular, an ultraviolet curable resin), and the like are preferable. In addition, it is preferable to have heat resistance that can withstand the heat treatment in the manufacturing process of the semiconductor package. As a result, the adhesive layer becomes difficult to melt in the manufacturing process of the semiconductor package, and the processing accuracy can be increased.
　本発明の積層基板は、更に加工基板と支持ガラス基板の間に、より具体的には加工基板と接着層の間に、剥離層を有すること、或いは支持ガラス基板と接着層の間に、剥離層を有することが好ましい。このようにすれば、加工基板に対して、所定の加工処理を行った後に、加工基板を支持ガラス基板から剥離し易くなる。加工基板の剥離は、生産性の観点から、レーザー光等の照射光により行うことが好ましい。 The laminated substrate of the present invention further comprises a release layer between the processing substrate and the supporting glass substrate, more specifically between the processing substrate and the adhesive layer, or peeling between the supporting glass substrate and the adhesive layer. It is preferred to have a layer. In this way, the processed substrate is easily peeled off from the supporting glass substrate after the processed substrate is subjected to predetermined processing. It is preferable to perform peeling of a process board | substrate by irradiation lights, such as a laser beam, from a viewpoint of productivity.
　剥離層は、レーザー光等の照射光により「層内剥離」又は「界面剥離」が生じる材料で構成される。つまり一定の強度の光を照射すると、原子又は分子における原子間又は分子間の結合力が消失又は減少して、アブレーション（ａｂｌａｔｉｏｎ）等を生じ、剥離を生じさせる材料で構成される。なお、照射光の照射により、剥離層に含まれる成分が気体となって放出されて分離に至る場合と、剥離層が光を吸収して気体になり、その蒸気が放出されて分離に至る場合とがある。 The peeling layer is made of a material that causes “in-layer peeling” or “interface peeling” by irradiation light such as laser light. That is, when irradiated with light of a certain intensity, the bonding force between atoms or molecules in atoms or molecules disappears or decreases, causing ablation and the like, and is made of a material causing ablation. In addition, when the component contained in a peeling layer is released as a gas by irradiation of irradiation light and it separates and it separates, and when a peeling layer absorbs light and becomes gas and the vapor is discharge | released and leads to isolation There is.
　本発明の積層基板において、支持ガラス基板は、加工基板よりも大きいことが好ましい。これにより、加工基板と支持ガラス基板を支持する際に、両者の中心位置が僅かに離間した場合でも、支持ガラス基板から加工基板の縁部が食み出し難くなる。 In the laminated substrate of the present invention, the supporting glass substrate is preferably larger than the processing substrate. Thereby, when supporting a process board | substrate and a support glass substrate, even when the center position of both mutually separates, it becomes difficult to protrude the edge of a process board | substrate from a support glass substrate.
　本発明の半導体パッケージの製造方法は、少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板を用意する工程と、加工基板に対して、加工処理を行う工程と、を有すると共に、支持ガラス基板が上記の支持ガラス基板であることを特徴とする。ここで、本発明の半導体パッケージの製造方法の技術的特徴（好適な構成、効果）は、本発明の支持ガラス基板及び積層基板の技術的特徴と重複する。よって、本明細書では、その重複部分について、詳細な記載を省略する。 The method for manufacturing a semiconductor package according to the present invention includes the steps of preparing a laminated substrate including at least a processing substrate and a supporting glass substrate for supporting the processing substrate, and performing a processing process on the processing substrate. And the supporting glass substrate is the above supporting glass substrate. Here, the technical features (preferred configuration and effects) of the method for producing a semiconductor package of the present invention overlap with the technical features of the supporting glass substrate and the laminated substrate of the present invention. Therefore, in the present specification, the detailed description of the overlapping portions is omitted.
　本発明の半導体パッケージの製造方法は、少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板を用意する工程を有する。少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板は、上記の材料構成を有している。なお、ガラス基板の成形方法として、上記成形方法を採択することができる。 The method for manufacturing a semiconductor package of the present invention has a step of preparing a laminated substrate including at least a processing substrate and a supporting glass substrate for supporting the processing substrate. A laminated substrate comprising at least a processing substrate and a support glass substrate for supporting the processing substrate has the above-described material configuration. In addition, the said shaping | molding method can be adopted as a shaping | molding method of a glass substrate.
　本発明の半導体パッケージの製造方法は、更に積層基板を搬送する工程を有することが好ましい。これにより、加工処理の処理効率を高めることができる。なお、「積層基板を搬送する工程」と「加工基板に対して、加工処理を行う工程」とは、別途に行う必要はなく、同時であってもよい。 The method for manufacturing a semiconductor package according to the present invention preferably further comprises the step of transporting the laminated substrate. Thereby, the processing efficiency of processing can be improved. The “step of transporting the laminated substrate” and the “step of processing the processed substrate” do not need to be separately performed, and may be performed simultaneously.
　本発明の半導体パッケージの製造方法において、加工処理は、加工基板の一方の表面に配線する処理、或いは加工基板の一方の表面に半田バンプを形成する処理が好ましい。本発明の半導体パッケージの製造方法では、これらの処理時に加工基板が寸法変化し難いため、これらの工程を適正に行うことができる。 In the method for manufacturing a semiconductor package according to the present invention, the processing is preferably a process of wiring on one surface of a processed substrate or a process of forming a solder bump on one surface of the processed substrate. In the method for manufacturing a semiconductor package according to the present invention, the size of the processed substrate is unlikely to change during these processes, so that these steps can be properly performed.
　加工処理として、上記以外にも、加工基板の一方の表面（通常、支持ガラス基板とは反対側の表面）を機械的に研磨する処理、加工基板の一方の表面（通常、支持ガラス基板とは反対側の表面）をドライエッチングする処理、加工基板の一方の表面（通常、支持ガラス基板とは反対側の表面）をウェットエッチングする処理の何れかであってもよい。なお、本発明の半導体パッケージの製造方法では、加工基板に反りが発生し難いと共に、積層基板の剛性を維持することができる。結果として、上記加工処理を適正に行うことができる。 As processing, processing of mechanically polishing one surface of the processing substrate (usually, the surface opposite to the supporting glass substrate) other than the above, one surface of the processing substrate (usually the supporting glass substrate) The process of dry-etching the opposite surface) or the process of wet-etching one surface of the processed substrate (usually, the surface opposite to the supporting glass substrate) may be used. In the method of manufacturing a semiconductor package according to the present invention, warpage of the processed substrate is unlikely to occur, and the rigidity of the laminated substrate can be maintained. As a result, the above processing can be properly performed.
　図面を参酌しながら、本発明を更に説明する。 The invention will be further described with reference to the drawings.
　図１は、本発明の積層基板１の一例を示す概念斜視図である。図１では、積層基板１は、支持ガラス基板１０と加工基板１１とを備えている。支持ガラス基板１０は、加工基板１１の寸法変化を防止するために、加工基板１１に貼着されている。そして、支持ガラス基板１０は、３０～３８０℃の温度範囲における平均線熱膨張係数が３２×１０－７／℃以上であり、且つ５５×１０－７／℃以下であり、ヤング率が８０ＧＰａ以上である。また、支持ガラス基板１０と加工基板１１との間には、剥離層１２と接着層１３が配置されている。剥離層１２は、支持ガラス基板１０と接触しており、接着層１３は、加工基板１１と接触している。 FIG. 1 is a conceptual perspective view showing an example of the laminated substrate 1 of the present invention. In FIG. 1, the laminated substrate 1 includes a support glass substrate 10 and a processing substrate 11. The supporting glass substrate 10 is attached to the processing substrate 11 in order to prevent the dimensional change of the processing substrate 11. The supporting glass substrate 10 has an average linear thermal expansion coefficient of 32 × 10 −7 / ° C. or more and 55 × 10 −7 / ° C. or less in a temperature range of 30 to 380 ° C., and a Young's modulus of 80 GPa or more It is. In addition, the peeling layer 12 and the adhesive layer 13 are disposed between the supporting glass substrate 10 and the processing substrate 11. The peeling layer 12 is in contact with the support glass substrate 10, and the adhesive layer 13 is in contact with the processing substrate 11.
　図１から分かるように、積層基板１は、支持ガラス基板１０、剥離層１２、接着層１３、加工基板１１の順に積層配置されている。支持ガラス基板１０の形状は、加工基板１１に応じて決定されるが、図１では、支持ガラス基板１０及び加工基板１１の形状は、何れもウエハ形状である。剥離層１２は、非晶質シリコン（ａ－Ｓｉ）以外にも、酸化ケイ素、ケイ酸化合物、窒化ケイ素、窒化アルミ、窒化チタン等が用いられる。剥離層１２は、プラズマＣＶＤ、ゾル－ゲル法によるスピンコート等により形成される。接着層１３は、樹脂で構成されており、例えば、各種印刷法、インクジェット法、スピンコート法、ロールコート法等により塗布形成される。接着層１３は、剥離層１２により加工基板１１から支持ガラス基板１０が剥離された後、溶剤等により溶解除去される。 As can be seen from FIG. 1, the laminated substrate 1 is laminated and arranged in the order of the supporting glass substrate 10, the peeling layer 12, the adhesive layer 13, and the processing substrate 11. The shape of the supporting glass substrate 10 is determined according to the processing substrate 11. However, in FIG. 1, the shapes of the supporting glass substrate 10 and the processing substrate 11 are both wafer shapes. In addition to amorphous silicon (a-Si), silicon oxide, a silicate compound, silicon nitride, aluminum nitride, titanium nitride or the like is used for the peeling layer 12. The peeling layer 12 is formed by plasma CVD, spin coating by a sol-gel method, or the like. The adhesive layer 13 is made of a resin, and is formed by, for example, various printing methods, an inkjet method, a spin coating method, a roll coating method, or the like. The adhesive layer 13 is dissolved and removed by a solvent or the like after the supporting glass substrate 10 is peeled off from the processed substrate 11 by the peeling layer 12.
　図２は、ｆａｎ　ｏｕｔ型のＷＬＰのチップファースト型の製造工程を示す概念断面図である。図２（ａ）は、支持部材２０の一方の表面上に接着層２１を形成した状態を示している。必要に応じて、支持部材２０と接着層２１の間に剥離層を形成してもよい。次に、図２（ｂ）に示すように、接着層２１の上に複数の半導体チップ２２を貼付する。その際、半導体チップ２２のアクティブ側の面を接着層２１に接触させる。次に、図２（ｃ）に示すように、半導体チップ２２を樹脂の封止材２３でモールドする。封止材２３は、圧縮成形後の寸法変化、配線を成形する際の寸法変化が少ない材料が使用される。続いて、図２（ｄ）、（ｅ）に示すように、支持部材２０から半導体チップ２２がモールドされた加工基板２４を分離した後、接着層２５を介して、支持ガラス基板２６と接着固定させる。その際、加工基板２４の表面の内、半導体チップ２２が埋め込まれた側の表面とは反対側の表面が支持ガラス基板２６側に配置される。このようにして、積層基板２７を得ることができる。なお、必要に応じて、接着層２５と支持ガラス基板２６の間に剥離層を形成してもよい。更に、得られた積層基板２７を搬送した後に、図２（ｆ）に示すように、加工基板２４の半導体チップ２２が埋め込まれた側の表面に配線２８を形成した後、複数の半田バンプ２９を形成する。最後に、支持ガラス基板２６から加工基板２４を分離した後に、加工基板２４を半導体チップ２２毎に切断し、後のパッケージング工程に供される（図２（ｇ））。 FIG. 2 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP chip-first type. FIG. 2A shows a state in which the adhesive layer 21 is formed on one surface of the support member 20. If necessary, a release layer may be formed between the support member 20 and the adhesive layer 21. Next, as shown in FIG. 2 (b), a plurality of semiconductor chips 22 are attached on the adhesive layer 21. At this time, the surface on the active side of the semiconductor chip 22 is brought into contact with the adhesive layer 21. Next, as shown in FIG. 2C, the semiconductor chip 22 is molded with a sealing material 23 of resin. As the sealing material 23, a material having a small dimensional change after compression molding and a small dimensional change at the time of molding a wiring is used. Subsequently, as shown in FIGS. 2D and 2E, the processed substrate 24 on which the semiconductor chip 22 is molded is separated from the support member 20, and then bonded and fixed to the support glass substrate 26 through the adhesive layer 25. Let At this time, the surface of the processing substrate 24 opposite to the surface on which the semiconductor chip 22 is buried is disposed on the supporting glass substrate 26 side. Thus, the laminated substrate 27 can be obtained. In addition, you may form a peeling layer between the contact bonding layer 25 and the support glass substrate 26, as needed. Furthermore, after transporting the obtained laminated substrate 27, as shown in FIG. 2F, after forming the wiring 28 on the surface of the processed substrate 24 on the side where the semiconductor chip 22 is embedded, a plurality of solder bumps 29 are obtained. Form Finally, after the processing substrate 24 is separated from the supporting glass substrate 26, the processing substrate 24 is cut into each semiconductor chip 22 and subjected to the subsequent packaging process (FIG. 2 (g)).
　図３は、支持ガラス基板をバックグラインド基板に用いて、加工基板を薄型化する工程を示す概念断面図である。図３（ａ）は、積層基板３０を示している。積層基板３０は、支持ガラス基板３１、剥離層３２、接着層３３、加工基板（シリコンウェハ）３４の順に積層配置されている。加工基板の接着層３３に接する側の表面には、半導体チップ３５がフォトリソグラフィー法等により複数形成されている。図３（ｂ）は、加工基板３４を研磨装置３６により薄型化する工程を示している。この工程により、加工基板３４は、機械的に研磨されて、例えば数十μｍまで薄型化される。図３（ｃ）は、支持ガラス基板３１を通して、剥離層３２に紫外光３７を照射する工程を示している。この工程を経ると、図３（ｄ）に示す通り、支持ガラス基板３１を分離することが可能になる。分離された支持ガラス基板３１は、必要に応じて、再利用される。図３（ｅ）は、加工基板３４から接着層３３を取り除く工程を示している。この工程を経ると、薄型化した加工基板３４を採取することができる。 FIG. 3 is a conceptual cross-sectional view showing a process of thinning a processed substrate by using a supporting glass substrate as a back grind substrate. FIG. 3A shows a laminated substrate 30. The laminated substrate 30 is laminated and arranged in order of the support glass substrate 31, the peeling layer 32, the adhesive layer 33, and the processed substrate (silicon wafer) 34. A plurality of semiconductor chips 35 are formed by photolithography or the like on the surface of the processing substrate in contact with the adhesive layer 33. FIG. 3B shows a process of thinning the processed substrate 34 by the polishing apparatus 36. By this process, the processing substrate 34 is mechanically polished and thinned to, for example, several tens of μm. FIG. 3C shows a step of irradiating the peeling layer 32 with the ultraviolet light 37 through the supporting glass substrate 31. Through this process, as shown in FIG. 3D, the supporting glass substrate 31 can be separated. The separated supporting glass substrate 31 is reused as needed. FIG. 3E shows the process of removing the adhesive layer 33 from the processing substrate 34. Through this process, the thinned processed substrate 34 can be collected.
　以下、本発明を実施例に基づいて説明する。なお、以下の実施例は単なる例示である。本発明は、以下の実施例に何ら限定されない。 Hereinafter, the present invention will be described based on examples. The following embodiments are merely illustrative. The present invention is not limited in any way to the following examples.
　表１～９は、本発明の実施例（試料Ｎｏ．１～８６）及び比較例（試料Ｎｏ．８７）を示している。 Tables 1 to 9 show Examples (Sample Nos. 1 to 86) and Comparative Examples (Sample No. 87) of the present invention.
Figure JPOXMLDOC01-appb-T000001
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Figure JPOXMLDOC01-appb-T000005
Figure JPOXMLDOC01-appb-T000006
Figure JPOXMLDOC01-appb-T000006
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Figure JPOXMLDOC01-appb-T000009
Figure JPOXMLDOC01-appb-T000009
　まず表中のガラス組成になるように、ガラス原料を調合したガラスバッチを白金坩堝に入れた後、１５００～１７００℃で２４時間溶融、清澄、均質化を行った。ガラスバッチの溶解に際しては、白金スターラーを用いて攪拌し、均質化を行った。次いで、溶融ガラスをカーボン板上に流し出して、板状に成形した後、徐冷点付近の温度で３０分間徐冷した。得られた各ガラス基板について、密度、３０～３８０℃の温度範囲における平均線熱膨張係数ＣＴＥ３０～３８０℃、ヤング率、歪点Ｐｓ、徐冷点Ｔａ、軟化点Ｔｓ、高温粘度１０４．０ｄＰａ・ｓにおける温度、高温粘度１０３．０ｄＰａ・ｓにおける温度、高温粘度１０２．５ｄＰａ・ｓにおける温度を評価した。なお、表中の「Ｎ．Ａ．」は、未測定を表している。 First, a glass batch prepared with glass raw materials was put in a platinum crucible so as to obtain the glass composition in the table, and then melted, clarified, and homogenized at 1500 to 1700 ° C. for 24 hours. At the time of melting of the glass batch, it was stirred using a platinum stirrer and homogenized. Next, the molten glass was poured out onto a carbon plate, formed into a plate, and then annealed for 30 minutes at a temperature near the annealing point. About each obtained glass substrate, density, average linear thermal expansion coefficient CTE in a temperature range of 30 to 380 ° C. 30 to 380 ° C. , Young's modulus, strain point Ps, annealing point Ta, softening point Ts, high temperature viscosity 10 4. The temperature at 0 dPa · s, the temperature at high temperature viscosity 10 3.0 dPa · s, and the temperature at high temperature viscosity 10 2 .5 dPa · s were evaluated. Note that "NA" in the table represents unmeasured.
　密度は、アルキメデス法によって測定した値である。 The density is a value measured by the Archimedes method.
　３０～３８０℃の温度範囲における平均線熱膨張係数ＣＴＥ３０～３８０℃は、ディラトメーターで測定した値である。 The average linear thermal expansion coefficient CTE of 30 to 380 ° C. in the temperature range of 30 to 380 ° C. is a value measured by a dilatometer.
　ヤング率は、共振法により測定した値を指す。 Young's modulus refers to the value measured by the resonance method.
　歪点Ｐｓ、徐冷点Ｔａ、軟化点Ｔｓは、ＡＳＴＭ　Ｃ３３６及びＣ３３８の方法に基づいて測定した値である。 The strain point Ps, the annealing point Ta, and the softening point Ts are values measured based on the method of ASTM C336 and C338.
　高温粘度１０４．０ｄＰａ・ｓ、１０３．０ｄＰａ・ｓ、１０２．５ｄＰａ・ｓにおける温度は、白金球引き上げ法で測定した値である。 The temperatures at high temperature viscosity of 10 4.0 dPa · s, 10 3.0 dPa · s and 10 2.5 dPa · s are values measured by a platinum ball pulling method.
　表１～９から明らかなように、試料Ｎｏ．１～８６は、３０～３８０℃の温度範囲における平均線熱膨張係数ＣＴＥ３０～３８０℃が３３．２×１０－７／℃～４８．０×１０－７／℃、ヤング率が８０．０～１０１．２ＧＰａであるため、支持ガラス基板として好適であると考えられる。一方、試料Ｎｏ．８７は、３０～３８０℃の温度範囲における平均線熱膨張係数ＣＴＥ３０～３８０℃が３５×１０－７／℃であるが、ヤング率が７６ＧＰａであるため、支持ガラス基板として好適ではないと考えられる。 As apparent from Tables 1 to 9, sample Nos. 1-86 are 30 average linear thermal expansion coefficient CTE 30 ~ 380 ° C. in a temperature range of ~ 380 ° C. is 33.2 × 10 -7 /℃~48.0×10 -7 / ℃ , Young's modulus 80.0 Since it is ̃101.2 GPa, it is considered to be suitable as a supporting glass substrate. On the other hand, for sample no. 87 has an average linear thermal expansion coefficient CTE of 30 to 380 ° C. of 35 × 10 −7 / ° C. in the temperature range of 30 to 380 ° C., but because the Young's modulus is 76 GPa, it is considered unsuitable as a supporting glass substrate Be
　続いて、試料Ｎｏ．１～８６に係るガラス基板をφ３００ｍｍ×０．８ｍｍ厚に加工した後、その両表面を研磨装置により研磨処理した。具体的には、ガラス基板の両表面を外径が相違する一対の研磨パットで挟み込み、ガラス基板と一対の研磨パッドを共に回転させながらガラス基板の両表面を研磨処理した。研磨処理の際、時折、ガラス基板の一部が研磨パッドから食み出すように制御した。なお、研磨パッドはウレタン製、研磨処理の際に使用した研磨スラリーの平均粒径は２．５μｍ、研磨速度は１５ｍ／分であった。得られた各研磨処理済みガラス基板について、コベルコ科研社製のＳＢＷ－３３１ＭＬ／ｄにより全体板厚偏差（ＴＴＶ）と反り量を測定した。その結果、全体板厚偏差（ＴＴＶ）がそれぞれ０．４５μｍであり、反り量がそれぞれ３５μｍであった。 Subsequently, for sample no. After the glass substrate according to 1 to 86 was processed to a thickness of φ300 mm × 0.8 mm, both surfaces thereof were polished by a polishing apparatus. Specifically, both surfaces of the glass substrate were sandwiched between a pair of polishing pads having different outer diameters, and both surfaces of the glass substrate were polished while rotating the glass substrate and the pair of polishing pads together. During the polishing process, occasionally, a part of the glass substrate was controlled to protrude from the polishing pad. The polishing pad was made of urethane, and the average particle size of the polishing slurry used in the polishing treatment was 2.5 μm, and the polishing rate was 15 m / min. The thickness deviation (TTV) and the amount of warpage of each polished glass substrate thus obtained were measured by SBW-331ML / d manufactured by Kobelco Research Institute. As a result, the total plate thickness deviation (TTV) was 0.45 μm, and the amount of warpage was 35 μm.
１、２７、３０　積層基板
１０、２６、３１　支持ガラス基板
１１、２４、３４　加工基板
１２、３２　剥離層
１３、２１、２５、３３　接着層
２０　支持部材
２２、３５　半導体チップ
２３　封止材
２８　配線
２９　半田バンプ
３６　研磨装置
３７　紫外光 Reference numerals 1, 27, 30 Laminated substrate 10, 26, 31 Support glass substrate 11, 24, 34 Processed substrate 12, 32 Peeling layer 13, 21, 25, 33 Adhesive layer 20 Support member 22, 35 Semiconductor chip 23 Sealing material 28 Wiring 29 solder bumps 36 polishing apparatus 37 ultraviolet light

Claims (9)

  1. 　３０～３８０℃の温度範囲における平均線熱膨張係数が３０×１０－７／℃以上であり、且つ５５×１０－７／℃以下であり、ヤング率が８０ＧＰａ以上であることを特徴とする支持ガラス基板。 Support having an average linear thermal expansion coefficient of 30 × 10 −7 / ° C. or more and 55 × 10 −7 / ° C. or less in a temperature range of 30 to 380 ° C. and a Young's modulus of 80 GPa or more Glass substrate.
  2. 　全体板厚偏差（ＴＴＶ）が２．０μｍ未満であることを特徴とする請求項１に記載の支持ガラス基板。 The supporting glass substrate according to claim 1, wherein a total thickness deviation (TTV) is less than 2.0 μm.
  3. 　ガラス組成として、質量％で、ＳｉＯ２　５０～６６％、Ａｌ２Ｏ３　７～３４％、Ｂ２Ｏ３　０～８％、ＭｇＯ　０～２２％、ＣａＯ　１～１５％、Ｙ２Ｏ３＋Ｌａ２Ｏ３＋ＺｒＯ２　０～２０％を含有することを特徴とする請求項１又は２に記載の支持ガラス基板。 As a glass composition, SiO 2 50 to 66%, Al 2 O 3 7 to 34%, B 2 O 3 0 to 8%, MgO 0 to 22%, CaO 1 to 15%, Y 2 O 3 + La, in mass%. 3. The supporting glass substrate according to claim 1, which contains 0 to 20% of 2 O 3 + ZrO 2 .
  4. 　半導体パッケージの製造工程で、半導体チップが樹脂にモールドされた加工基板の支持に用いることを特徴とする請求項１～３の何れかに記載の支持ガラス基板。 The supporting glass substrate according to any one of claims 1 to 3, wherein the supporting glass substrate is used for supporting a processed substrate in which a semiconductor chip is molded in a resin in a manufacturing process of a semiconductor package.
  5. 　少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板であって、支持ガラス基板が請求項１～４の何れかに記載の支持ガラス基板であることを特徴とする積層基板。 A laminated substrate comprising at least a processing substrate and a supporting glass substrate for supporting the processing substrate, wherein the supporting glass substrate is the supporting glass substrate according to any one of claims 1 to 4. .
  6. 　加工基板が、半導体チップが樹脂にモールドされた加工基板であることを特徴とする請求項５に記載の積層基板。 The laminated substrate according to claim 5, wherein the processed substrate is a processed substrate in which a semiconductor chip is molded in a resin.
  7. 　少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える積層基板を用意する工程と、
    　加工基板に対して、加工処理を行う工程と、を有すると共に、支持ガラス基板が請求項１～４の何れかに記載の支持ガラス基板であることを特徴とする半導体パッケージの製造方法。     Providing a laminated substrate comprising at least a processing substrate and a supporting glass substrate for supporting the processing substrate;
    5. A method of manufacturing a semiconductor package, comprising the step of performing processing on a processed substrate, wherein the supporting glass substrate is the supporting glass substrate according to any one of claims 1 to 4.
  8. 　加工処理が、加工基板の一方の表面に配線する工程を含むことを特徴とする請求項７に記載の半導体パッケージの製造方法。 8. The method of manufacturing a semiconductor package according to claim 7, wherein the processing includes wiring on one surface of the processing substrate.
  9. 　加工処理が、加工基板の一方の表面に半田バンプを形成する工程を含むことを特徴とする請求項７又は８に記載の半導体パッケージの製造方法。 9. The method of manufacturing a semiconductor package according to claim 7, wherein the processing includes the step of forming a solder bump on one surface of a processing substrate.
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