WO2019019691A1 - 一种用于多结 led 的隧穿结、多结 led 及其制备方法 - Google Patents

一种用于多结 led 的隧穿结、多结 led 及其制备方法 Download PDF

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WO2019019691A1
WO2019019691A1 PCT/CN2018/081671 CN2018081671W WO2019019691A1 WO 2019019691 A1 WO2019019691 A1 WO 2019019691A1 CN 2018081671 W CN2018081671 W CN 2018081671W WO 2019019691 A1 WO2019019691 A1 WO 2019019691A1
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junction
layer
led
type
band gap
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French (fr)
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毕京锋
吴超瑜
王笃祥
李森林
吴俊毅
连恺熙
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厦门三安光电有限公司
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Publication of WO2019019691A1 publication Critical patent/WO2019019691A1/zh
Priority to US16/711,721 priority Critical patent/US11011674B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H01L33/0016—Devices characterised by their operation having p-n or hi-lo junctions having at least two p-n junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table

Definitions

  • the present invention relates to a tunnel junction for a multi-junction LED, a multi-junction LED, and a method of fabricating the same, and belongs to the technical field of semiconductor materials.
  • the commercial iris recognition system mainly uses near-infrared LEDs of 700 ⁇ 900nm, which can be used to capture the characteristics of depth of field and stereoscopic images, and assist the camera system to acquire iris image images.
  • This system has high brightness requirements for IR LEDs.
  • a common solution is to connect multiple LEDs in series, that is, to connect the sub-devices in series during the epitaxial growth process.
  • the key technology is high peak current density.
  • the epitaxial growth of the tunneling junction is usually introduced by the concept of a tunneling junction peak current to describe its characteristics.
  • the tunneling junction between the sub-cells should be an ultra-thin and high-zero "zero voltage drop" ohmic connection: 1.
  • the p/n junction has a high concentration on both sides, which makes the semiconductor enter a degenerate state.
  • the impurity concentration distribution at the p/n junction interface should be as steep as possible to avoid impurity compensation caused by mutual diffusion of impurities; 3.
  • the thickness of the tunneling junction p and n regions should be as thin as possible (less than 15 nm) ).
  • the choice of tunneling material, the choice of miscellaneous source, the impurity concentration and the material growth process must all be considered.
  • the memory effect of the ordered disintegrator and the diffusion of the impurity impurities should be avoided to affect the p/n junction quality, thereby deteriorating the device performance.
  • the tunneling current calculation formula is:
  • the relationship between the peak current and the peak value of the tunneling junction is the impurity concentration, which is also related to the band gap of the material.
  • GalnAs with a lower band gap for tunneling 4" piece / p ⁇ i> lkA/ C m 2.
  • the present invention is directed to providing a tunnel junction for a multi-junction LED, a multi-junction LED, and a method of fabricating the same.
  • a tunnel junction of a high peak current density for a multi-junction LED includes: a P-type impurity isolation layer; a heavily miscellaneous P-type layer; a metal atomic layer; Miscellaneous N-type layer; N-type miscellaneous isolation layer.
  • the heavily doped P-type layer has a first band gap larger than an LED band gap on the upper and lower sides of the tunneling junction, and the heavily doped N-type layer has a larger band gap than the upper and lower sides of the tunneling junction.
  • the thickness and the complexity of the heavily miscellaneous N and P-type layers are key parameters for effectively regulating the thickness of the depletion layer of the PN junction region, and are a guarantee of tunneling junction tunneling effect and high peak current density.
  • the heavily miscellaneous P-type layer has a thickness of 5-20 nm, and the impurity concentration is greater than 1 ⁇ 10 2Q cm ⁇ 3
  • the heavy miscellaneous N-type layer has a thickness of 5-20 nm, and the impurity concentration is greater than 2 ⁇ 10. 19 cm - 3 .
  • the N, P type impurity isolation layer acts as a high barrier layer, which can prevent impurity diffusion and impurity recombination (Auger recombination) of the high impurity layer without affecting the series resistance of the entire device.
  • the P-type miscellaneous isolation The impurity concentration of the layer is 8x10 17 ⁇ 5xl0 18 cm - 3 , and the impurity concentration of the N type impurity isolation layer is 8x10 17 ⁇ 5 x lO 18 cm 3 .
  • the material of the metal atom layer may be a metal atom formed by thermal cracking of a MO source during MOCVD growth, such as a metal atom such as Ga, In, Al, Sb, etc., which functions to assist tunneling by metal conductivity.
  • a metal atom such as Ga, In, Al, Sb, etc.
  • the metal atomic layer has a thickness of 1 to 2 atomic layers, the crystal lattice is in a strain state, and there is no lattice mismatch problem, and the same can effectively reduce the shading effect, does not affect the brightness of the device, and can also effectively reduce Series resistance, improve photoelectric conversion efficiency.
  • a multi-junction LED structure includes at least a first LED epitaxial structure, a tunneling junction, and a second LED epitaxial structure, the tunneling junction comprising: a P-type impurity isolation layer Heavy miscellaneous P-type layer; metal atomic layer; heavy miscellaneous N-type layer; N-type miscellaneous isolation layer.
  • the present invention provides a method for preparing a multi-junction LED, comprising the steps of: forming a first LED device structure; forming a tunneling junction above the first LED device structure, which comprises a P-type impurity isolation layer, Heavy miscellaneous P-type layer, metal atomic layer, heavily miscellaneous N-type layer, N-type impurity isolation layer; a second LE D device junction is formed above the tunneling junction. So far, a double junction LED structure has been formed, and the multi-junction LED device structure can be further epitaxially grown according to this method. Formal or flip-chip growth can be performed according to chip process requirements.
  • Each of the LED device substructures generally includes an n-type semiconductor layer, an active layer, and a p-type semiconductor, but may also include functional layers such as an etch stop layer, an ohmic contact layer, and a transparent conductive layer.
  • FIG. 1 is a schematic structural view of a multi-junction LED according to an embodiment of the present invention.
  • 2 is an enlarged schematic view showing a region of a tunnel junction of the multi-junction LED structure shown in FIG. 1.
  • FIG. 3 is a schematic diagram of a multi-junction LED chip including a tunneling junction with a high peak current density.
  • 105 a P-type doped isolation layer.
  • FIG. 1 shows a multi-junction LED structure including at least a first LED structure LE DI and a second LED structure LED II, through a tunnel between a second LED structure and a second LED structure, in accordance with an embodiment of the present invention.
  • Wear knot 005 to connect. 2 shows an enlarged schematic view of a region of a tunnel junction 005, which in turn includes: an N-type doped isolation layer 10 1.
  • the outer side of the N heavy miscellaneous layer as a high barrier layer, can prevent the impurity diffusion and impurity recombination of high miscellaneous layers (Auger recombination), the metal atomic layer 103 is located in the middle of the P, N heavy miscellaneous layer, auxiliary Tunneling.
  • the n-type miscellaneous (111) crystal plane off angle is selected to be 2.
  • the GaAs substrate is used as the growth substrate 001, the thickness is about 350 ⁇ m, and the impurity concentration is between lxl0 18 cm -3 ⁇ 4xl0 18 cm -3 , and the N-type layer 002 of the LED I is grown on the substrate.
  • Layer 003 and P-type layer 004 constitute a first LED epitaxial structure.
  • the N-type layer 003 may include an n-type GaAs ohmic contact layer, an N-type AllnP Clading layer, and a non-tacky AlGalnP as a spatial isolation layer; and the active layer 003 may use AlInGa As/AlGaAs having a peak wavelength of 810 nm as a quantum well and The multi-quantum well structure composed of the barrier has a total period of 12 cycles and a total thickness of 400-500 nm; the P-type layer 004 may include a P-type AllnP Clading layer and a non-disintegrating AlGalnP as a spatial isolation layer.
  • a tunneling junction 005 is formed over the p-type layer 004.
  • C is used as the N-type impurity barrier layer 10, and its impurity concentration is 2xl0 18 cm -3 , its thickness is 120 nm, and the band gap is 2.1.
  • AlGaAs: Te as an ultra-thin heavily miscellaneous N-type layer 102, the thickness of which is 15 nm, the impurity concentration can be 5x10 19 cm -3 , the band gap is 1.7 eV; then all the MOCVD sources are used, 11 2 purge growth chamber, smashing trimethylgallium source, epitaxially growing a 1-2 atom layer of Ga metal atom layer 103 at an extremely low growth rate as an auxiliary tunneling layer; then growing AlGaAs: C as an ultrathin
  • the peculiar P-type layer 104 has a thickness of 15 nm, a miscellaneous concentration of 2.5 x 10 2 ° cm -3 , and a band gap of 1.7.
  • AlGalnP Si is grown as a P-type barrier layer 105 with a viscous concentration of 8x10 17 cm -3 , a thickness of 120 nm and a band gap of 2.1 eV.
  • the LED II is symmetrically grown above the tunneling junction 004.
  • the N-type layer 006, the active layer 007 and the P-type layer 008 constitute a second LED epitaxial structure.
  • the N-type layer 006 may include an N-type AllnP Clading layer and an undissolved AlGalnP as a spatial isolation layer; AlInGaAs/AlGaAs with a peak wavelength of 810 nm is used as a multiple quantum well structure composed of a quantum well and a barrier, respectively, for 12 cycles with a total thickness of 400 to 500 nm; the P-type layer 008 may include a P-type GaAs ohmic contact layer.
  • the optical mask 009, the front electrode 010, and the back electrode 011 are vapor-deposited to form a desired double junction 810 nm LED light-emitting chip, as shown in FIG. 3.
  • the chip size and electrode pattern can be changed according to specific needs.
  • the core particles with and without the metal atomic layer have a Vf value of 1 to 1.5% and a brightness difference of 2 to 3 ⁇ 3 ⁇ 4 at a test current of 350 mA.
  • the n-type miscellaneous (111) crystal plane declination is selected to be 2.
  • the N-type layer 002, the active layer 003, and the P-type layer 004 of the LED I are sequentially grown on the substrate to constitute a first LED epitaxial structure.
  • the N-type layer 003 may comprise: an n-type GaAs ohmic contact layer, wherein the thickness of the i-type is 200 nm, the impurity concentration is lxl0 18 cm -3 ; the N-type AlGaAs cladding layer has a thickness of about 500 nm, and the impurity concentration is 2 ⁇ 5xl0 im -3 ; Undissolved AlGaAs as a spatial isolation layer; Active layer 003 can use InGaAs/AlGaAs with an emission wavelength of 940nm as a multiple quantum well structure composed of a quantum well and a barrier, respectively, for a total of 6 cycles, the total thickness is Between 200 and 250 nm; P-type layer 004 may comprise a non-tacky AlGaAs as
  • a tunnel junction 005 is formed over the P-type layer 004 of the LED I.
  • AlGalnP: C is used as the N-type impurity isolation layer 101, and its impurity concentration is 2x10 im - 3, its thickness is 120 nm, and the band gap is 2.1 eV.
  • AlGaAs: Te is grown as an ultrathin heavily doped N-type layer 102 having a thickness of 15 nm, a miscellaneous 5x10 19 cm 3 and a band gap of 1.7 eV.
  • the miscellaneous barrier layer 105 has a viscous concentration of 5xl0 17 cm -3 , a thickness of 120 nm and a band gap of 2.1 eV.
  • the N-type layer 002 may comprise an n-type GaAs ohmic contact layer having a thickness of 20 0 nm, a heterogeneous concentration of lxl0 18 cm -3 , an N-type AlGaAs cladding layer having a thickness of about 500 nm, and a poor concentration of 2 ⁇ 5xl0 18 cm - 3, undissolved AlGaAs as a spatial isolation layer; active layer 003 uses InGaAs/AlGaAs with an emission wavelength of 940 nm as a multiple quantum well structure composed of a quantum well and a barrier, respectively, for a total of 6 cycles, the total thickness is P-type layer 004 may comprise a non-tacky AlGaAs as a P-type region spatial
  • the chip process is further processed.
  • the optical mask 009, the front electrode 010 and the back electrode 011 are vapor-deposited to form the required double junction 940 nm LED light-emitting chip, and the chip size and electrode pattern can be changed according to customer needs.

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Abstract

本发明公开了一种用于多结LED的隧穿结、多结LED及其制备方法，所述隧穿结包括：P型掺杂隔离层；重掺杂P型层；金属原子层；重掺杂N型层；N型掺杂隔离层。其中，所述N、P型掺杂隔离层作为高势垒层，能阻止高掺杂层的杂质扩散和杂质复合（俄歇复合），所述金属原子层作为辅助隧穿层，具有1~2原子层厚度，晶格处于应变状态，不存在晶格失配问题，同时能够有效减小遮光效应，不影响器件亮度，也可以有效减小串联电阻，提高光电转化效率。

Description

一种用于多结 LED的隧穿结、 多结 LED及其制备方法 技术领域
[0001] 本发明涉及一种用于多结 LED的隧穿结、 多结 LED及其制备方法， 属半导体材 料技术领域。
背景技术
[0002] 研究表明脸部与虹膜识别在移动设备上的应用将逐渐普及， 预计到 2020年搭载 红外 LED识别器件的移动设备将达到 20亿部。 届吋红外 LED脸部与虹膜识别器件 产值将达到 2.5亿美元， 成为 IR LED最具潜力的应用之一。 商业化的虹膜识别系 统主要采用 700~900nm的近红外 LED, 利用其可拍摄出景深与立体影像的特征， 辅助相机系统获取虹膜特征影像。
[0003] 此系统对于 IR LED的亮度要求较高， 常用的解决方案是多结 LED串联， 即在外 延生长过程中利用隧穿结将各个子器件串联起来， 其关键技术是高峰值电流密 度的隧穿结的外延生长， 通常引入隧穿结峰值电流的概念来描述其特性。 子电 池间的隧穿结应是超薄高惨的"零压降 "欧姆连接： 1、 p/n结双侧惨杂浓度足够高 ， 使半导体进入简并状态， 一般的其惨杂浓度达到 10 i m - 3 ; 2、 p/n结界面杂质 浓度分布应尽可能陡峭， 以避免杂质相互扩散引起杂质补偿； 3、 隧穿结 p区和 n 区的厚度应尽可能的薄 （小于 15 nm) 。 为获得尽可能高的隧穿峰值电流， 隧穿 结材料的选择、 惨杂源的选择、 惨杂浓度及材料生长工艺等都是必须考虑的。 此外， 在后续生长过程中应避免有序惨杂剂的记忆效应和惨杂杂质的扩散等作 用影响 p/n结质量， 进而恶化器件性能。
[0004] 隧穿电流计算公式为：
Figure imgf000003_0001
[0005] 在杂质全部电离的情况下， 等于 n和 p区的惨杂浓度。
[0006] 从上面公式可以看出： 与隧穿结峰值电流关系最大的是惨杂浓度， 还与材料的 带隙有关， 惨杂浓度越高， 峰值电流越大， 隧穿结材料的带隙越低， 峰值电流 越大。 例如： 带隙较低的 GalnAs做隧穿结， 4寸片 /p∞i>lkA/Cm 2。
[0007] 在多结 LED实际应用中， 随着大尺寸高亮度产品的需求 （例如车灯、 舞台灯、 虹膜识别等产品） ， 器件的注入电流越来越大， 对隧穿结的峰值电流密度的要 求也越来越高 （/p∞i>100 A/Cm 2) 。 由于低带隙隧穿结存在的吸光现象， 严重 影响器件的发光亮度。 因此通过降低隧穿结半导体材料的带隙来提高峰值电流 密度的方法行不通。
技术问题
问题的解决方案
技术解决方案
[0008] 针对现有技术中存在的上述问题， 本发明旨在提供提一种用于多结 LED的隧穿 结、 多结 LED及其制备方法。
[0009] 根据本发明的第一个方面， 一种多结 LED用高峰值电流密度的隧穿结， 依次包 括： P型惨杂隔离层； 重惨杂 P型层； 金属原子层； 重惨杂 N型层； N型惨杂隔离 层。
[0010] 优选地， 所述重惨杂 P型层具有大于隧穿结上下两侧 LED带隙的第一带隙， 所 述重惨杂 N型层具有大于隧穿结上下两侧 LED带隙的第二带隙； 所述 P型惨杂隔 离层具有大于第一带隙的第三带隙； 所述 N型惨杂隔离层具有大于第二带隙的第 四带隙。
[0011] 所述重惨杂 N、 P型层的厚度和惨杂是有效调控 PN结区耗尽层厚度的关键参数 ， 是隧穿结隧穿效应和高峰值电流密度的保障。 优选地， 所述重惨杂 P型层的厚 度为 5~20 nm， 惨杂浓度大于 1x10 2Qcm -3， 所述重惨杂 N型层的厚度为 5~20 nm， 惨杂浓度大于 2x10 19cm - 3。
[0012] 所述 N、 P型惨杂隔离层作为高势垒层， 能阻止高惨杂层的杂质扩散和杂质复 合 （俄歇复合） ， 又不会影响整个器件的串联电阻。 优选地， 所述 P型惨杂隔离 层的惨杂浓度为 8x10 17~5xl0 18cm - 3， 所述 N型惨杂隔离层的惨杂浓度为 8x10 17~5 xlO 18cm 3。
[0013] 所述金属原子层的材料可以是在 MOCVD生长过程中 MO源热裂解形成的金属 原子， 例如 Ga、 In、 Al、 Sb等金属原子， 其作用是利用金属导电性辅助隧穿。 优选的， 所述金属原子层具有 1~2原子层厚度， 其晶格处于应变状态， 不存在晶 格失配问题， 同吋能够有效减小遮光效应， 不影响器件亮度， 也可以有效减小 串联电阻， 提高光电转化效率。
[0014] 根据本发明的第二个方面， 一种多结 LED结构， 至少包括第一 LED外延结构、 隧穿结和第二 LED外延结构， 所述隧穿结包含： P型惨杂隔离层； 重惨杂 P型层 ； 金属原子层； 重惨杂 N型层； N型惨杂隔离层。
[0015] 本发明同吋提供了一种多结 LED的制备方法， 包括步骤： 形成第一 LED器件结 构； 在第一 LED器件结构的上方形成隧穿结， 其包含 P型惨杂隔离层， 重惨杂 P 型层， 金属原子层， 重惨杂 N型层， N型惨杂隔离层； 在隧穿结上方形成第二 LE D器件结。 至此就形成了双结 LED结构， 可以依据此方法继续外延生长多结 LED 器件结构。 可以依据芯片工艺要求进行正装或者倒装生长。 各 LED器件子结构一 般包括 n型半导体层、 有源层和 p型半导体， 但也可以包含刻蚀截止层、 欧姆接 触层、 透明导电层等功能层。
发明的有益效果
有益效果
[0016] 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明书中 变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。
对附图的简要说明
附图说明
[0017] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0018] 图 1为根据本发明实施的一种多结 LED的结构示意图。 [0019] 图 2为图 1所示多结 LED结构之隧穿结的区域放大示意图。
[0020] 图 3为包含高峰值电流密度的隧穿结的多结 LED芯片示意图。
[0021] 图中各标号表示：
[0022] 001： 生长衬底；
[0023] 002： LED I的 N型层；
[0024] 003： LED I的有源层；
[0025] 004: LED I的 P型层；
[0026] 005： 隧穿结；
[0027] 006： LED II的 N型层；
[0028] 007： LED II的有源层；
[0029] 008: LED II的 P型层；
[0030] 009: 光学掩膜；
[0031] 010: 正面电极
[0032] 011： 背面电极
[0033] 101： N型惨杂隔离层
[0034] 102： 超薄重惨杂 N型层；
[0035] 103： 1~2层金属原子层；
[0036] 104: 超薄重掺杂 P型层；
[0037] 105： P型掺杂隔离层。
本发明的实施方式
[0038] 现在将描述本发明的细节， 包含本发明的示范性方面和实施例。 参看图示和以 下描述， 相同的参考编号用于识别相同或功能类似的元件， 且意在以高度简化 的图解方式说明示范性实施列的主要特征。 另外， 所述图示无意描绘实际实施 例的每个特征或所描绘元件的相对尺寸， 且所述图示未按比例绘制。
[0039] 图 1显示了根据本发明实施的一种多结 LED结构， 其至少包括第一 LED结构 LE D I和第二 LED结构 LED II， 在第二 LED结构和第二 LED结构之间通过隧穿结 005 连接。 图 2显示了隧穿结 005的区域放大示意图， 其依次包括： N型掺杂隔离层 10 1、 重惨杂 N型层 102、 金属原子层 103、 重惨杂 P型层 104和 P型惨杂隔离层 105。 其中 N、 P型惨杂隔离层分别位于！5、 N重惨杂层的外侧， 作为高势垒层， 能阻止 高惨杂层的杂质扩散和杂质复合 （俄歇复合） ， 金属原子层 103位于 P、 N重惨杂 层的中间， 辅助隧穿。
[0040] 下面以 AlGalnP系发光二极管为例， 结合制作方法对上述多结 LED结构进行详 细说明。
[0041] 实施例一
[0042] 首先， 在 MOCVD系统中， 选用 n型惨杂的向 (111)晶面偏角为 2。的 GaAs衬底作 为生长衬底 001， 厚度在 350微米左右， 惨杂浓度在 lxl0 18cm - 3 ~ 4xl0 18cm - 3之间 ， 在此衬底上生长 LED I的 N型层 002、 有源层 003、 P型层 004， 构成第一 LED外 延结构。 其中， N型层 003可以包含 n型 GaAs欧姆接触层、 N型 AllnP Clading层、 不惨杂 AlGalnP作为空间隔离层； 有源层 003可以采用峰值波长为 810nm的 AlInGa As/AlGaAs分别作为量子阱和势垒构成的多量子阱结构， 共 12个周期， 总厚度为 400-500 nm之间； P型层 004可包括 P型 AllnP Clading层、 不惨杂 AlGalnP作为空 间隔离层。
[0043] 接着， 在 LED I
的 P型层 004上方形成隧穿结 005。 首先， 生长 AlGalnP: C作为 N型惨杂隔离层 10 1， 其惨杂浓度为 2xl0 18cm - 3， 其厚度为 120 nm， 带隙为 2.1
eV; 之后生长 AlGaAs: Te作为超薄重惨杂 N型层 102， 其厚度为 15 nm， 惨杂浓 度可为 5x10 19cm -3， 带隙为 1.7 eV; 然后所有关掉所有 MOCVD源， 用11 2 purge 生长室， 打幵三甲基镓源， 在极低的生长速率下外延生长 1-2原子层的 Ga金属原 子层 103， 作为辅助隧穿层； 之后生长 AlGaAs: C作为超薄重惨杂 P型层 104， 其 厚度为 15 nm， 惨杂浓度可为 2.5x10 2°cm -3， 带隙为 1.7
eV; 最后生长 AlGalnP: Si作为 P型惨杂隔离层 105， 其惨杂浓度为 8x10 17cm -3， 其厚度为 120 nm， 带隙为 2.1 eV。
[0044] 然后， 在隧穿结 004的上方对称生长 LED II
的 N型层 006、 有源层 007和 P型层 008， 构成第二 LED外延结构。 其中， N型层 006 可以包含 N型 AllnP Clading层、 不惨杂 AlGalnP作为空间隔离层； 有源层 007采用 峰值波长为 810nm的 AlInGaAs/AlGaAs分别作为量子阱和势垒构成的多量子阱结 构， 共 12周期， 总厚度为 400~500 nm之间； P型层 008可包括 P型 GaAs欧姆接触层
、 P型 AllnP Clading层、 不惨杂 AlGalnP作为空间隔离层。
[0045] 外延生长完毕后再通过芯片工艺制程， 实现光学掩膜 009、 正面电极 010和背面 电极 011蒸镀， 形成所需要的双结 810nm LED发光芯片， 如图 3所示。 芯片尺寸 和电极图形可以根据具体需要进行变化。
[0046] 以 30mil芯片为例： 在其它结构相同的情况下， 包含和不包含金属原子层的芯 粒， 在 350mA测试电流下， Vf值相差 1~1.5%， 亮度相差 2~3<¾。
[0047] 实施例二
[0048] 在 MOCVD系统中， 选用 n型惨杂的向（111)晶面偏角为 2。的 GaAs衬底 001， 厚度 在 350微米左右， 惨杂浓度在 1x10 18cm 3~4xl0 18cm 3
之间。 依次在此衬底上生长 LED I的 N型层 002、 有源层 003、 P型层 004， 构成第 一 LED外延结构。 其中， N型层 003可以包含： n型 GaAs欧姆接触层， i厚度为 200 nm， 惨杂浓度为 lxl0 18cm - 3； N型 AlGaAs覆盖层， 其厚度为 500nm左右， 惨杂浓 度为为 2~5xl0 i m -3 ; 不惨杂 AlGaAs作为空间隔离层； 有源层 003可以采用发光 波长为 940nm的 InGaAs/AlGaAs分别作为量子阱和势垒构成的多量子阱结构， 共 6 周期， 总厚度为 200~250nm之间； P型层 004可以包含不惨杂 AlGaAs作为 P型区域 的空间隔离层和 P- AlGaAs覆盖层， P- AlGaAs覆盖层的厚度为 400nm， 惨杂浓度 为 4x10 17~lxl0 18cm 3。
[0049] 接着， 在 LED I的 P型层 004上方形成隧穿结 005。 首先生和 AlGalnP: C作为 N 型惨杂隔离层 101， 其惨杂浓度为 2x10 i m - 3， 其厚度为 120nm， 带隙为 2.1 eV。 之后生长 AlGaAs: Te作为超薄重惨杂 N型层 102， 其厚度为 15 nm， 惨杂 5x10 19 cm 3 , 带隙为 1.7 eV。 然后所有关掉所有 MOCVD源， 用11 ^113¾6生长室， 打幵 三甲基镓源， 在极低的生长速率下外延生长 1-2个原子层的 In金属原子层， 作为 辅助隧穿层 103 ; 之后生长 AlGaAs:C作为超薄重惨杂 P型层 104， 其厚度为 15 nm ， 惨杂浓度为 2.5x10 ¾m - 3， 带隙为 1.7 eV; 最后生长 AlGalnP: Si作为 P型惨杂 隔离层 105， 其惨杂浓度为 5xl0 17cm - 3， 其厚度为 120nm， 带隙为 2.1 eV。
[0050] 之后对称生长 006 LED II的 LED I的 N型层 002、 有源层 003、 P型层 004， 构成 第一 LED外延结构。 其中， N型层 002可以包含 n型 GaAs欧姆接触层， 其厚度为 20 0 nm， 惨杂浓度为 lxl0 18cm - 3， N型 AlGaAs覆盖层， 其厚度为 500 nm左右， 惨杂 浓度为 2~5xl0 18cm - 3， 不惨杂 AlGaAs作为空间隔离层； 有源层 003采用发光波长 为 940nm的 InGaAs/AlGaAs分别作为量子阱和势垒构成的多量子阱结构， 共 6周期 ， 总厚度为 200~250 nm之间； P型层 004可以包含不惨杂 AlGaAs作为 P型区域的空 间隔离层， P型 AlGaAs覆盖层， 其中 P型 AlGaAs覆盖层的厚度为 400 nm， 惨杂浓 度为 4xl0 17~lxl0 18cm - 3， P型 GaAs欧姆接触层， 厚度为 200nm， 惨杂浓度为 5x10 18cm - 3。
外延生长完毕后再通过芯片工艺制程。 实现光学掩膜 009、 正面电极 010和背面 电极 011蒸镀， 形成所需要的双结 940nm LED发光芯片， 芯片尺寸和电极图形可 以根据客户需要进行变化。

Claims

权利要求书
一种用于多结 LED的隧穿结， 包括：
P型惨杂隔离层；
重惨杂 P型层；
金属原子层；
重惨杂 N型层；
N型惨杂隔离层。
根据权利要求 1的一种用于多结 LED的隧穿结， 其特征在于： 所述重 惨杂 P型层具有大于隧穿结上下两侧 LED带隙的第一带隙， 所述重惨 杂 N型层具有大于隧穿结上下两侧 LED带隙的第二带隙； 所述 P型惨 杂隔离层具有大于第一带隙的第三带隙； 所述 N型惨杂隔离层具有大 于第二带隙的第四带隙。
根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述重惨杂 P型层的厚度为 5~20nm， 惨杂浓度大于 1x10 2ocm 具有大 于隧穿结上下两侧 LED带隙的第一带隙。
根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述重惨杂 N型层的厚度为 5~20nm， 惨杂浓度大于 2x10 ¾m -3， 具有大 于隧穿结上下两侧 LED带隙的第二带隙。
根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述 P型惨杂隔离层的惨杂浓度为 8x10 i7~5xl0 i m -3， 并且具有大于第 一带隙的第三带隙。
根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述 N型惨杂隔离层的惨杂浓度为 8x10 i7~5xl0 i m -3， 并且具有大于第 二带隙的第四带隙。
根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述N、 P型惨杂隔离层作为高势垒层， 阻止所述重惨杂层的杂质扩散 和杂质复合。
根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述金属原子层的材料是在 MOCVD生长过程中 MO源热裂解形成的金 属原子。
[权利要求 9] 根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述金属原子层利用金属自由电子辅助隧穿。
[权利要求 10] 根据权利要求 1所述的一种用于多结 LED的隧穿结， 其特征在于： 所 述金属原子层具有 1~2层原子的厚度， 其晶格处于应变状态。
[权利要求 11] 一种多结 LED结构， 至少包括第一 LED外延结构和第二 LED外延结构
， 其特征在于： 在所述第一 LED外延结构与第二 LED外延结构之间具 有权利要求 1-11所述的任意一种隧穿结。
[权利要求 12] —种多结 LED的制备方法， 包括步骤：
形成第一 LED器件结构；
在所述第一 LED器件结构的上方形成隧穿结， 其包含 P型惨杂隔离层 ， 重惨杂 P型层， 金属原子层， 重惨杂 N型层， N型惨杂隔离层； 在所述隧穿结上方形成第二 LED器件结构。
[权利要求 13] 根据权利要求 12所述的一种多结 LED的制备方法， 其特征在于： 所述 金属原子层的材料是在 MOCVD生长过程中 MO源热裂解形成的金属 原子。
PCT/CN2018/081671 2017-07-25 2018-04-03 一种用于多结 led 的隧穿结、多结 led 及其制备方法 WO2019019691A1 (zh)

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