WO2019015162A1 - 一种防污基板及其制备方法 - Google Patents

一种防污基板及其制备方法 Download PDF

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Publication number
WO2019015162A1
WO2019015162A1 PCT/CN2017/108668 CN2017108668W WO2019015162A1 WO 2019015162 A1 WO2019015162 A1 WO 2019015162A1 CN 2017108668 W CN2017108668 W CN 2017108668W WO 2019015162 A1 WO2019015162 A1 WO 2019015162A1
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substrate
template
boss
antifouling
etching
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PCT/CN2017/108668
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English (en)
French (fr)
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邱基华
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潮州三环（集团）股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

Definitions

  • the invention relates to an antifouling material, in particular to an antifouling substrate and a preparation method thereof.
  • the surface of the antifouling material generally has a hydrophobic surface
  • the hydrophobic surface generally refers to a surface having a contact angle of the solid surface with water of more than 120°. Since the contact area of the hydrophobic surface with the water droplets is very small, the water droplets are easily rolled off from the surface. Therefore, the hydrophobic surface not only has self-cleaning function, but also has functions of anti-current conduction, anti-corrosion, waterproof, anti-fog, anti-virus, anti-snow, anti-frost, anti-adhesion, anti-pollution, etc., and thus in construction, clothing textile, liquid transportation, Biomedicine, daily necessities and packaging, transportation tools and microanalysis have broad application prospects.
  • a superhydrophobic coating is mostly prepared on the surface of the sample, but the sample thus prepared has a problem of poor surface abrasion resistance, and it is difficult to maintain the original morphology of the sample surface after repeated rubbing.
  • a convex array is usually implanted on the surface of the substrate by a specific process, and the convex array forms an interface bond with the substrate. After repeated rubbing, the convex array is easily removed from the substrate. The surface is peeled off, which tends to cause a problem of poor wear resistance of the surface of the sample.
  • the object of the present invention is to provide an antifouling substrate with anti-adhesion, anti-pollution and wear resistance and a preparation method thereof, which overcome the deficiencies of the prior art.
  • the present invention provides an antifouling substrate, comprising:
  • the surface of the substrate has at least one functional region; at least a portion of the functional region has a coating; the functional region has a plurality of bosses, and the average height of the boss is 10 to 2000 nm, and the average of the bosses
  • the upper surface area is 78 to 1.964 ⁇ 10 5 nm 2 , and the average spacing between adjacent bosses is 1 to 5000 nm; the coating is made of a hydrophobic material.
  • the average upper surface area of the bosses refers to the average of the upper surface areas of each of the bosses; the average spacing between adjacent bosses refers to the average of the shortest distances between adjacent bosses.
  • the arrangement of the plurality of bosses can increase the wear resistance of the sample surface.
  • the height of the boss, the upper surface area, the spacing between adjacent bosses, and the coating prepared by the hydrophobic material affect the antifouling hydrophobicity of the material.
  • the antifouling substrate of the invention has better antifouling performance and solves the problem of poor wear resistance of the sample surface.
  • the shape of the boss can be any shape, and can be a cylinder, a truncated cone or a square, and is not a strict cylinder, a truncated cone or a square, such as a curved surface whose side is not completely smooth. If the diameter of the boss is too small and the height is too high, the mechanical strength will become low and it will be easily damaged, resulting in poor wear resistance. If the diameter of the boss is too large and the height is too low, the anti-fouling effect of the boss structure on the surface of the substrate is not obvious. When the average height of the boss is 10 to 2000 nm and the average upper surface area is 78 to 1.964 ⁇ 10 5 nm 2 , the wear resistance and the antifouling property of the substrate are better.
  • the average height of the bosses is from 80 to 1000 nm.
  • the height of the boss is greater than 1000 nm, if the height of the boss is continuously increased, the anti-fouling effect is not significantly improved, and the processing efficiency of the boss is lowered, and the cost is increased; when the height of the boss is less than 80 nm, the processing is highly uniform. It is difficult to ensure that the antifouling effect is easily deteriorated. Therefore, when the average height of the boss is 80 to 1000 nm, the processing efficiency is high, the processing cost is low, and the antifouling effect and the abrasion resistance are better.
  • the average pitch between adjacent bosses is preferably from 1 to 5000 nm.
  • the average spacing between adjacent bosses is 5 to 2500 nm.
  • the surface contact angle of the material is greater than 130°, and the antifouling effect is better.
  • the average spacing between adjacent protrusions is greater than 2500 nm, the antifouling performance tends to decrease. Therefore, when the average pitch between adjacent bosses is 5 to 2500 nm, the antifouling effect is better.
  • the coating has a thickness of from 2 to 200 nm.
  • the thicker the coating the better the antifouling performance of the prepared material, but the coating will have a certain filling on the depressed part.
  • the thicker the coating the smaller the effect of increasing the hydrophobic antifouling.
  • the boss structure reduces the height of the boss and reduces the contact angle more.
  • the thickness of the coating is preferably 2 to 200 nm.
  • the thickness of the coating is from 5 to 100 nm. Since the surface is basically covered by the hydrophobic coating, the thickness of the coating is greater than 100 nm. As the thickness of the coating continues to increase, the effect of the hydrophobic material on the contact angle is limited, and the effect of increasing the contact angle is no longer significant, so the thickness of the coating is 5 to 100nm antifouling performance is best.
  • the material of the substrate is a ceramic material; the material of the coating is a fluorine-containing compound.
  • the material of the substrate comprises at least one of silicon dioxide, zirconium dioxide, silicon carbide, cerium oxide, calcium oxide, cerium oxide, silicon nitride and zirconium carbide;
  • the fluorine-containing compound is fluorosilane, At least one of a perfluoropolyether, a perfluoroalkylsulfonate, and a fluorocarbon resin.
  • the material of the substrate is yttria, calcium oxide or yttria-doped zirconia or zirconia.
  • the fluorine-containing compound is perfluorodecyltriethoxysilane.
  • the coating material is perfluorodecyltriethoxysilane, the antifouling effect is optimal.
  • the invention also provides a preparation method of an antifouling substrate, comprising the following steps:
  • a hydrophobic material is applied to the substrate having the boss obtained in the step (6) to obtain the antifouling substrate.
  • the method for preparing the antifouling substrate of the present invention is specifically: first preparing a template layer on the surface of the substrate, The template layer is patterned by photolithography, and then the template layer is etched by plasma etching, reactive ion etching, etc. to form a first template boss, and the first step can be controlled by controlling the parameters of the exposure process.
  • the size of the template boss; the second etching of the first template boss is performed, the size of the template boss is reduced, and the second template boss is obtained, and the second etching can be controlled by controlling the parameters of the second etching.
  • the size of the template boss; then a protective film is applied in the groove around the second template boss, and the surface of the boss has no protective film.
  • the second template boss without the protective film After being etched and continuing to etch, the substrate corresponding to the position of the second template pad is etched to form a groove, and the depth of the groove can be controlled by setting the third etching parameter. After the etching is completed, the substrate is washed away.
  • the substrate surface protective film, the substrate having the protective film is a boss, and the substrate corresponding to the position of the second template boss is etched to form a groove, thereby obtaining a substrate having a boss, the boss is integrated with the substrate, and finally has Coating on the substrate table hydrophobic material, to obtain an antifouling substrate.
  • the limit of the spacing between the bosses which can be achieved by the bumps of the substrate obtained by photolithography is 7-8 nm, and the preparation of the pitch of a small size (tens of nanometers) between the bosses requires expensive equipment.
  • the antifouling substrate obtained by the method for preparing the antifouling substrate of the present invention can obtain an antifouling substrate with a pitch between the bosses as low as 1 nm, and greatly reduces the manufacturing cost of the bosses with small pitches. Instead of using a special light source, it can be achieved with ordinary UV exposure.
  • the antifouling substrate having the bosses with large size spacing is less susceptible to interference of light interference, and the antifouling substrate prepared by the method has regular or irregularity.
  • the size of the boss is precisely controllable, and the base and the boss are integrated, and the boss is not easily detached from the substrate, which greatly improves the wear resistance of the anti-fouling substrate.
  • the preparation of the template layer may be carried out by evaporation.
  • the template layer has a thickness of 5 to 2000 nm.
  • the thickness of the template layer is determined by the required etching depth of the substrate, but the thickness is less than 5 nm, which may cause the template layer to be completely etched in step (4) or step (5).
  • the template layer has a thickness of 20 to 2000 nm.
  • the material of the template layer is at least one of a solid inorganic oxide, a solid nitride, a solid carbide, and a solid metal.
  • the material of the template layer is at least one of silicon dioxide, zirconium dioxide, silicon carbide, hafnium oxide, calcium oxide, tantalum oxide, silicon nitride, zirconium carbide, copper, tungsten, and aluminum.
  • the exposure process is a deep ultraviolet exposure process; the reticle of the deep ultraviolet exposure process is a mask, and the light source is deep ultraviolet light.
  • the exposure processing is a raster exposure processing; the grating exposure processing mask is a grating, and the light source is ultraviolet light.
  • the exposure treatment may be performed by a conventional ultraviolet light source, deep ultraviolet exposure processing or raster exposure processing.
  • the deep ultraviolet wavelength is about one quarter of the ordinary ultraviolet light, that is, about 100 nm. It can be used for photolithography, and the photoresist is patterned by deep ultraviolet light and a mask to form a regular or irregular shape. Periodic pattern, and the size of the boss is precisely controllable. By using a grating as a mask, the substrate coated with the photoresist can be directly exposed by ultraviolet light, that is, light of about 400 nm, without requiring deep ultraviolet light, which can save production cost.
  • the grating When the grating is exposed as a reticle, it needs to be exposed twice, because the grating is a spacer stripe structure, which consists of a hollow light-transmitting stripe and an opaque stripe, and the grating needs to be rotated by 90 degrees for the second exposure. Form the desired boss pattern.
  • step (7) after applying the hydrophobic material to the substrate having the boss, further comprising the step of heat-treating the boss coated with the hydrophobic material, the heat treatment condition being: 50-250 ° C, 5 ⁇ 10 -3 to 1 ⁇ 10 -1 Pa.
  • the purpose of heat treatment of the boss coated with the hydrophobic material is to: (1) improve the adhesion of the hydrophobic coating to the substrate; (2) control the thickness of the hydrophobic coating; (3) control the penetration depth of the hydrophobic coating; 4) increase the contact angle; (5) improve the uniformity of the hydrophobic coating; (6) remove the free hydrophobic material.
  • the atmosphere of the heat treatment may be an air atmosphere, or may be an inert gas atmosphere such as nitrogen, argon or helium.
  • the thicker the hydrophobic coating the higher the temperature required for heat treatment or the longer the time; the higher the degree of vacuum, the lower the air content, and the heat treatment in the air atmosphere; conversely, the low vacuum requires heat treatment under an inert gas. .
  • the first etching is plasma etching or reactive ion etching; in the step (5), the second etching is plasma etching or reactive ion etching; (6) The third etching is plasma etching or reactive ion etching; in the step (7), the method of applying the hydrophobic material is at least one of CVD, PVD and evaporation.
  • the process parameters of the plasma etching are: gas flow rate is 100-400 sccm, chamber pressure is 12-25 Pa, and processing time is 10-120 min.
  • the process parameters of the reactive ion etching are: a gas mixture of BCl 3 or SF 6 and Ar, gas flow rates of 30-400 sccm and 10-100 sccm, respectively, etching time 30-200 s; can be based on the size of the boss Select the appropriate etching conditions for your needs.
  • the invention has the beneficial effects that the present invention provides an antifouling substrate and a preparation method thereof, and the antifouling substrate prepared by the invention has strong antifouling property and wear resistance, and the substrate has various options.
  • the antifouling substrate obtained by the method for preparing the antifouling substrate of the present invention can obtain an antifouling substrate with a pitch between the bosses as low as 1 nm, and greatly reduces the preparation cost of the bosses with small size spacing, without using Special light source can be achieved with ordinary UV exposure.
  • the antifouling substrate substrate and the boss prepared by the method are integrated, and the boss is not easily detached from the substrate, thereby greatly improving the wear resistance of the antifouling substrate.
  • FIG. 1 is a flow chart of one embodiment of a method of preparing an antifouling substrate of the present invention.
  • FIG. 1 is a flow chart of an embodiment of a method for preparing an antifouling substrate according to the present invention. Specifically, the method for preparing an antifouling substrate of the present invention includes the following steps:
  • a heat treatment is applied to the substrate coated with the hydrophobic material to obtain the antifouling substrate.
  • the base material of the antifouling substrate is zirconia
  • the coating is perfluorodecyltriethoxysilane
  • the average height of the stud is 120 nm, each The average upper surface area of the bosses was 1.767 ⁇ 10 4 nm 2 and the average spacing between adjacent bosses was 150 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the process parameters of the plasma etching are: a gas flow rate of 100 sccm, a chamber pressure of 12 Pa, and a processing time of 60 min. And then cleaning the etched substrate template to obtain a substrate having a boss;
  • the process parameters of the plasma etching are: a gas flow rate of 100 sccm, a chamber pressure of 12 Pa, and a processing time of 20 min. a substrate having a second template boss;
  • the plasma etching process parameters are: a gas flow rate of 100 sccm, a chamber pressure of 12 Pa, a treatment time of 50 min, and then cleaning the etched substrate to obtain a substrate having a boss;
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with perfluorodecyltriethoxysilane;
  • the substrate coated with the hydrophobic material is subjected to heat treatment under the following conditions of 200 ° C, 2 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 18 nm.
  • the template in this embodiment is silica.
  • the base material of the antifouling substrate is calcium oxide doped zirconia
  • the coating is fluorosilane
  • the average height of the boss is 120 nm
  • each convex The average upper surface area of the stage was 4.0 ⁇ 10 4 nm 2
  • the average spacing between adjacent bosses was 50 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the mask is a square array with a period of 150 nm, and the deep ultraviolet exposure is 10 s;
  • the reactive ion etching process parameter is: the gas is a mixed gas of BCl 3 and Ar, and the gas flow rate is respectively 70sccm and 30sccm, etching time is 100s; then the etched substrate template is cleaned to obtain a substrate having a boss;
  • the process parameter of the reactive ion etching is: the gas is a mixed gas of BCl 3 and Ar, and the gas flow rate is 70 sccm respectively. And 30 sccm, etching time 60 s; obtaining a substrate having a second template boss;
  • the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, gas flow rates of 70 sccm and 30 sccm, etching time of 100 s, and then cleaning the etched substrate to have a boss Substrate
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with a fluorosilane;
  • the substrate coated with the hydrophobic material is subjected to heat treatment at a process condition of 150 ° C, 2 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 18 nm.
  • the template in this embodiment is zirconium dioxide.
  • the base material of the antifouling substrate is yttria-doped zirconia
  • the coating is perfluoropolyether
  • the average height of the lands is 10 nm, each The average upper surface area of the bosses was 3.142 ⁇ 10 4 nm 2 , and the average spacing between adjacent bosses was 2000 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the mask is a square array with a period of 1000 nm, and ultraviolet exposure for 10 s;
  • the process parameter of the reactive ion etching is: the process parameter of the reactive ion etching is: gas is a mixed gas of SF 6 and Ar, a gas flow rate of 120 sccm and 50 sccm, respectively, and an etching time of 50 s; and then cleaning the etched base template to obtain a substrate having a boss;
  • the process parameter of the reactive ion etching is: the gas is a mixed gas of BCl 3 and Ar, and the gas flow rate is 70 sccm respectively. And 30sccm, etching time 200s, to obtain a substrate having a second template boss;
  • the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, a gas flow rate of 70 sccm and 30 sccm, an etching time of 50 s, and then cleaning the etched substrate to have a boss Substrate
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with a perfluoropolyether;
  • a heat treatment is applied to the substrate coated with the hydrophobic material under the conditions of 100 ° C, 4 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 2 nm.
  • the template in this embodiment is zirconium carbide.
  • the base material of the antifouling substrate is calcium oxide doped zirconium dioxide, and the coating is perfluorodecyltriethoxysilane, and the average of the bosses
  • the height is 1000 nm, the average upper surface area of each of the bosses is 3.142 ⁇ 10 4 nm 2 , and the average pitch between adjacent bosses is 5 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the process parameter for performing reactive ion etching on the template layer on the exposed substrate obtained by the step (3) is: the process parameter of the reactive ion etching is: the gas is a mixed gas of SF 6 and Ar The gas flow rate is 100 sccm and 10 sccm, respectively, and the etching time is 100 s; then the etched base template is cleaned to obtain a substrate having a boss;
  • the process parameter of the reactive ion etching is: the gas is a mixed gas of SF 6 and Ar, and the gas flow rate is 100 sccm respectively. And 10sccm, etching time 100s, to obtain a substrate having a second template boss;
  • the process parameters of the reactive ion etching are: the gas is a mixed gas of SF 6 and Ar, the gas flow rate is 100 sccm and 10 sccm, respectively, and the etching time is 200 s; then the etched substrate is cleaned to have a boss Substrate
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with perfluorodecyltriethoxysilane;
  • a heat treatment is applied to the substrate coated with the hydrophobic material under the conditions of 100 ° C, 4 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 100 nm.
  • the template described in this embodiment is ruthenium oxide.
  • the base material of the antifouling substrate is zirconium dioxide
  • the coating layer is perfluorodecyltriethoxysilane
  • the average height of the stud is 2000 nm
  • each The average upper surface area of the bumps is 1.964 ⁇ 10 5 nm 2
  • the average pitch between adjacent bosses is 5000 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the mask is a circular array with a period of 150 nm, and the deep ultraviolet exposure is for 10 s;
  • the process parameters of the plasma etching are: a gas flow rate of 240 sccm, a chamber pressure of 20 Pa, and a processing time of 10 min. And then cleaning the etched substrate template to obtain a substrate having a boss;
  • the process parameters of the plasma etching are: a gas flow rate of 240 sccm, a chamber pressure of 20 Pa, and a processing time of 120 min. a substrate having a second template boss;
  • the plasma etching process parameters are: gas flow rate is 240sccm, chamber pressure is 20Pa, processing time is 120min; then the etched substrate is cleaned to obtain a substrate having a boss;
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with perfluorodecyltriethoxysilane;
  • the substrate coated with the hydrophobic material is subjected to heat treatment under the conditions of 100 ° C, 4 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 5 nm.
  • the template described in this embodiment is calcium oxide.
  • the base material of the antifouling substrate is silicon nitride
  • the coating is fluorosilane
  • the average height of the boss is 60 nm
  • the average upper surface area of each boss At 78 nm 2
  • the average spacing between adjacent studs is 1 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the process parameters of the plasma etching are: a gas flow rate of 300 sccm, a chamber pressure of 22 Pa, and a processing time of 100 min. And then cleaning the etched substrate template to obtain a substrate having a boss;
  • the process parameters of the plasma etching are: a gas flow rate of 300 sccm, a chamber pressure of 22 Pa, and a processing time of 60 min. a substrate having a second template boss;
  • the plasma etching process parameters are: a gas flow rate of 300 sccm, a chamber pressure of 22 Pa, a treatment time of 20 min, and then cleaning the etched substrate to obtain a substrate having a boss;
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with a fluorosilane;
  • a heat treatment is applied to the substrate coated with the hydrophobic material under the conditions of 100 ° C, 4 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 40 nm.
  • the template described in this embodiment is ruthenium oxide.
  • the base material of the antifouling substrate is yttria-doped zirconia
  • the coating is a perfluoropolyether
  • the average height of the boss is 60 nm, each The average upper surface area of the bosses was 1.267 x 10 5 nm 2 and the average spacing between adjacent studs was 2500 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the reactive ion etching process parameter is: the gas is a mixed gas of BCl 3 and Ar, and the gas flow rate is respectively
  • the etching time is 30 s for 130 sccm and 30 sccm; then the etched base template is cleaned to obtain a substrate having a boss;
  • step (4) performing reactive ion etching on the first template boss on the substrate obtained in the step (4), wherein the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, and the gas flow rate is 130 sccm respectively. And 30sccm, etching time 30s; obtaining a substrate having a second template boss;
  • the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, a gas flow rate of 130 sccm and 30 sccm, an etching time of 60 s, and then cleaning the etched substrate to have a boss Substrate
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with a perfluoropolyether;
  • a heat treatment is applied to the substrate coated with the hydrophobic material under the conditions of 200 ° C, 5 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 200 nm.
  • the template in this embodiment is silicon nitride.
  • the base material of the antifouling substrate is silicon carbide
  • the coating is fluorocarbon resin
  • the average height of the boss is 120 nm
  • the average upper surface area of each boss It is 7.069 ⁇ 10 4 nm 2 and the average spacing between adjacent bosses is 100 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the reactive ion etching process parameter is: the gas is a mixed gas of BCl 3 and Ar, and the gas flow rate is respectively
  • the etching time is 100 s for 100 sccm and 50 sccm; then the etched base template is cleaned to obtain a substrate having a boss;
  • step (4) performing reactive ion etching on the first template boss on the substrate obtained in the step (4), wherein the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, and the gas flow rate is 130 sccm respectively. And 30sccm, etching time 40s; obtaining a substrate having a second template boss;
  • the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, a gas flow rate of 130 sccm and 30 sccm, an etching time of 120 s, and then cleaning the etched substrate to have a boss Substrate
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with a perfluoropolyether;
  • the substrate coated with the hydrophobic material is subjected to heat treatment at a process condition of 150 ° C, 5 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 18 nm.
  • the template in this embodiment is silicon nitride.
  • the base material of the antifouling substrate is yttria-doped zirconia
  • the coating is a perfluoropolyether
  • the average height of the boss is 60 nm, each The average upper surface area of the bosses was 1.267 x 10 5 nm 2 and the average spacing between adjacent studs was 2500 nm.
  • the surface of the template obtained in the step (1) is coated with a layer of photoresist, coated with a thickness of 200 nm, and then baked at 100 ° C for 1 min;
  • the reactive ion etching process parameter is: the gas is a mixed gas of BCl 3 and Ar, and the gas flow rate is respectively
  • the etching time is 30 s for 130 sccm and 30 sccm; then the etched base template is cleaned to obtain a substrate having a boss;
  • step (4) performing reactive ion etching on the first template boss on the substrate obtained in the step (4), wherein the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, and the gas flow rate is 130 sccm respectively. And 30sccm, etching time 30s; obtaining a substrate having a second template boss;
  • the process parameters of the reactive ion etching are: a gas mixture of BCl 3 and Ar, a gas flow rate of 130 sccm and 30 sccm, an etching time of 60 s, and then cleaning the etched substrate to have a boss Substrate
  • the substrate having the boss obtained in the step (6) is subjected to a chemical vapor deposition method, and is hydrophobized with a perfluoropolyether;
  • a heat treatment is applied to the substrate coated with the hydrophobic material under the conditions of 200 ° C, 5 ⁇ 10 -3 Pa, and a nitrogen atmosphere to obtain an antifouling substrate having a coating thickness of 200 nm.
  • the template in this embodiment is copper.
  • the antifouling substrate of Comparative Example 1 differs from Example 1 only in that the average pitch between adjacent projections is different, and the average spacing between adjacent projections of the antifouling substrate is 5500 nm.
  • the substrate of the present comparative example is a bump formed by photolithography etching, and the bumps do not belong to the bulk material of the substrate, are connected to the substrate through the interface, and are then hydrophobized with a perfluorodecyltriethoxysilane pair. The treatment was carried out to obtain a comparative substrate.
  • the antifouling substrates of Examples 1 to 9 and Comparative Examples 1 and 2 were subjected to abrasion resistance tests, respectively.
  • the abrasion resistance test is carried out by using a friction tester, and the test time is the same and the same The test was carried out under the same conditions of the number of rubbing.
  • the specific load was 1 kg, the number of rubbing was 5000 times, the stroke was 3 cm, the friction head was 0000# steel wool, and the friction head was 1 cm*1 cm.
  • the boss structure of the surface of the substrate of Comparative Example 2 was subjected to large-area damage and peeled off from the surface of the substrate; the protrusions of the anti-fouling substrate of Examples 1 to 9 and Comparative Example 1 did not peel off from the surface of the substrate,
  • the antifouling substrate of the boss structure prepared by the method of the antifouling substrate of the present invention is more excellent in abrasion resistance.
  • Example 10 The antifouling substrates of Examples 1 to 9, Comparative Examples 1, 2, and Examples 1 to 9 and Comparative Examples 1 and 2 subjected to the rubbing test described in Example 10 were subjected to antifouling performance tests.
  • the antifouling performance test is tested by the contact angle of water droplets. The test results are shown in Table 1.

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Abstract

一种防污基板，包括：基底；所述基底的表面至少具有一个功能区域；所述功能区域至少一部分具有涂层；所述功能区域上具有多个凸台，所述凸台的平均高度为10～2000nm，凸台的平均上表面积为78～1.964×10 5nm 2，相邻凸台之间的平均间距为1～5000nm；所述涂层采用疏水材料制成。一种防污基板及其制备方法，制备的防污基板具有较强的防污性和耐磨性，且基底有多种选择。所述防污基板的制备方法获得的防污基板，能够制得凸台之间的间距低至1nm的防污基板，且大大缩小了小尺寸间距的凸台的制备成本，防污基板基底和凸台为一体，凸台不易从基底上脱落，提高了防污基板的耐磨性。

Description

一种防污基板及其制备方法 技术领域
本发明涉及一种防污材料，具体涉及一种防污基板及其制备方法。
背景技术
防污材料的表面一般具有疏水表面，疏水表面一般是指固体表面与水的接触角大于120°的表面。由于疏水表面与水滴的接触面积非常小，水滴极易从表面滚落。因此，疏水表面不仅具有自清洁功能，而且还具有防电流传导、防腐蚀、防水、防雾、防毒、防雪、防霜冻、防黏附、防污染等功能，因而在建筑、服装纺织、液体输送、生物医学、日用品与包装、交通运输工具以及微量分析等领域都具有广泛的应用前景。
为了使样品具有防污功能，大多是在样品的表面制备超疏水涂层，但是这样制备的样品存在表面耐磨性差的问题，经过反复摩擦难以维持样品表面原本形貌。为了使样品表面具有耐磨性，在传统的制备工艺中，通常通过特定的工艺在基底表面植入凸起阵列，凸起阵列与基底形成界面粘接，经过反复摩擦，凸起阵列容易从基底表面剥离，从而容易导致样品表面的耐磨性较差的问题。
发明内容
本发明的目的在于克服现有技术存在的不足之处而提供一种具有防粘附、防污染且耐磨的防污基板及其制备方法。
为实现上述目的，本发明采取的技术方案为：本发明提供了一种防污基板，包括：
基底；所述基底的表面至少具有一个功能区域；所述功能区域至少一部分具有涂层；所述功能区域上具有多个凸台，所述凸台的平均高度为10～2000nm，凸台的平均上表面积为78～1.964×105nm2，相邻凸台之间的平均间距为1～5000nm；所述涂层采用疏水材料制成。
凸台的平均上表面积是指每个凸台的上表面积的平均值；相邻凸台之间的平均间距是指相邻凸台之间的最短距离的平均值。
多个凸台的设置可以增加样品表面的耐磨性，凸台的高度、上表面积、相邻凸台之间的间距和疏水材料制备的涂层影响着材料的防污疏水性。本发明所述防污基板上具有较好防污性能的同时还解决了样品表面耐磨性差的问题。
凸台的形状可以为任意形状，可以为圆柱、圆台型或者方形，并非是严格的圆柱、圆台或方形，如侧面不是完全光滑的弧面。如果凸台直径太小，高度太高，其机械强度将变低，容易遭到破坏，导致耐磨性越差。如果凸台直径太大，高度太低，凸台结构对基板表面产生的防污效果不明显。当凸台的平均高度为10～2000nm，平均上表面积为78～1.964×105nm2时，基板的耐磨性和防污性能较佳。
优选地，凸台的平均高度为80～1000nm。凸台的高度大于1000nm时，如果继续提高凸台高度，对防污效果提升不明显，且会导致凸台的加工效率下降，成本上升；当凸台高度小于80nm时，加工过程中高度一致性较难保证，防污效果容易恶化。因此当凸台的平均高度为80～1000nm时，加工效率较高、加工成本较低、防污效果和耐磨性较佳。
相邻凸台之间的平均间距为小于1nm时，基板的表面的凸台结构将不明显，基板的防污效果也会变差；当相邻凸台之间的平均间距大于5000nm时，材料的表面接触角较小，使基板表面的防污性能较差。因此，相邻凸台之间的平均间距优选为1～5000nm。
更优选地，相邻凸台之间的平均间距为5～2500nm。当相邻凸台之间的平均间距大于5nm时，材料的表面接触角大于130°，防污效果较好，当相邻凸台之间的平均间距大于2500nm时，防污性能呈现下降的趋势；因此，相邻凸台之间的平均间距为5～2500nm时，防污效果更佳。
优选地，所述涂层的厚度为2～200nm。涂层的厚度越厚，制备而成的材料的防污性能越好，但是涂层将对凹陷的部位有一定的填充，涂层越厚其对疏水防污的增加效果就越来越小，相反当它的厚度大到一定程度时，它的增大影响 了凸台结构，让凸台的高度下降，会更大地减少接触角，涂层的厚度为2～200nm较佳。
更优选地，涂层的厚度为5～100nm。由于表面基本被疏水涂层覆盖，涂层厚度大于100nm，随着涂层厚度的继续增大，疏水材料对提升接触角效果有限，对接触角的增大效果不再明显，故涂层的厚度在5～100nm防污性能最佳。
优选地，所述基底的材料为陶瓷材料；所述涂层的材料为含氟化合物。
优选地，所述基底的材料包含二氧化硅、二氧化锆、碳化硅、氧化钇、氧化钙、氧化铈、氮化硅和碳化锆中的至少一种；所述含氟化合物为氟硅烷、全氟聚醚、全氟烷基磺酸盐和氟碳树脂中的至少一种。
更优选地，所述基底的材料为氧化钇、氧化钙或氧化铈掺杂的氧化锆或氧化锆。
优选地，所述含氟化合物为全氟癸基三乙氧基硅烷。当涂层材料为全氟癸基三乙氧基硅烷时，防污效果最佳。
本发明还提供了一种防污基板的制备方法，包括以下步骤：
(1)、在基底表面制备一层模板层；
(2)、对步骤(1)所得模板层的表面涂覆一层光刻胶；
(3)、对涂覆有光刻胶的基底进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行第一次刻蚀，然后对刻蚀后的基底进行清洗，得具有第一模板凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行第二次刻蚀，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层保护膜，对第二模板凸台和与第二模板凸台位置对应的基底进行第三次刻蚀，然后清洗第三次刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底涂覆疏水材料，得所述防污基板。
本发明所述防污基板的制备方法具体为：首先在基底表面制备一层模板层， 对模板层采用光刻法进行图案化处理，然后再采用等离子刻蚀、反应离子刻蚀等方法对模板层进行刻蚀，形成第一模板凸台，通过控制曝光处理的参数，可以控制第一模板凸台的尺寸；再对第一模板凸台进行第二次刻蚀，缩小模板凸台的大小，得到第二模板凸台，通过控制第二次刻蚀的参数，可以控制得到的第二模板凸台的大小；然后在第二模板凸台周围的凹槽内涂覆一层保护膜，凸台表面没有保护膜，进行第三次刻蚀的时候，没有保护膜的第二模板凸台被刻蚀，继续刻蚀，与第二模板凸台位置对应的基底被刻蚀，形成凹槽，通过第三次刻蚀参数的设置，可以控制凹槽的深度，刻蚀完成后，洗去基底表面保护膜，有保护膜的基底即为凸台，第二模板凸台对应位置的基底被刻蚀形成凹槽，这样得到了具有凸台的基底，凸台与基底为一体，最后在具有凸台的基底上涂覆疏水材料，得到防污基板。
目前，采用光刻法得到的基板的凸台能够达到的凸台之间的间距的极限是7～8nm，且制备得到凸台之间很小尺寸的间距(几十纳米)需要采用昂贵的设备，而采用本发明所述防污基板的制备方法获得的防污基板，能够制得凸台之间的间距低至1nm的防污基板，且大大缩小了小尺寸间距的凸台的制备成本，不用采用特殊光源，采用普通的紫外曝光就可以达到。相比具有大尺寸间距的凸台的防污基板，具有小尺寸间距的凸台的防污基板更不易受光线干涉反射的影响，且采用此方法制备的防污基板具有规整或不规则的、具有周期性的图案，凸台的大小精确可控，且基底和凸台为一体，凸台不容易从基底上脱落，大大提高了防污基板的耐磨性。
步骤(1)中，所述模板层的制备可以采用蒸镀的方法形成。
优选地，步骤(1)中，所述模板层的厚度为5～2000nm。
模板层的厚度由基板所需的刻蚀深度决定，但厚度小于5nm，那么可能造成在步骤(4)或步骤(5)中该模板层被全部刻蚀。
更优选地，所述模板层的厚度为20～2000nm。
优选地，所述模板层的材料为固体无机氧化物、固体氮化物、固体碳化物和固体金属中的至少一种。
更优选地，所述模板层的材料为二氧化硅、二氧化锆、碳化硅、氧化钇、氧化钙、氧化铈、氮化硅、碳化锆、铜、钨和铝中的至少一种。优选地，步骤(3)中，所述曝光处理为深紫外曝光处理；所述深紫外曝光处理的光罩为掩模板，光源为深紫外光。
优选地，步骤(3)中，所述曝光处理为光栅曝光处理；所述光栅曝光处理的光罩为光栅，光源为紫外光。
所述曝光处理可以采用普通紫外光源，深紫外曝光处理或光栅曝光处理。
深紫外的波长约为普通紫外光的四分之一，也就是100nm左右，可以被用来进行光刻，采用深紫外光和掩模板将光刻胶图案化，形成规整或不规则的、具有周期性的图案，且凸台的大小精确可控。采用光栅作为光罩，可以直接用紫外光，也就是400nm左右的光，对涂覆有光刻胶的基底直接进行曝光，而不需要深紫外光，这样能节省生产成本。
光栅作为光罩曝光时，需要进行两次曝光，因为光栅是间隔条纹结构，由镂空透光条纹和不透光条纹构成一个周期，第二次曝光时需将光栅要旋转九十度，这样才能形成所需要的凸台图案。
优选地，步骤(7)中，在对具有凸台的基底涂覆疏水材料之后，还包括对涂覆了疏水材料的凸台进行热处理的步骤，所述热处理的条件为：50～250℃，5×10-3～1×10-1Pa。
对涂覆了疏水材料的凸台进行热处理的目的是：(1)提高疏水涂层与基底的结合力；(2)控制疏水涂层的厚度；(3)控制疏水涂层的渗透深度；(4)提高接触角；(5)提高疏水涂层均匀性；(6)去除游离的疏水材料。热处理的氛围可以为空气氛围，也可以为氮气、氩气、氦气等惰性气体氛围。一般来说，疏水涂层越厚，热处理需要的温度更高或者时间更长；真空度越高，空气含量低，可在空气氛围下热处理；反之，低真空度时需要在惰性气体下进行热处理。
优选地，步骤(4)中，所述第一次刻蚀为等离子刻蚀或反应离子刻蚀；步骤(5)中，所述第二次刻蚀为等离子刻蚀或反应离子刻蚀；步骤(6)中，所 述第三次刻蚀为等离子刻蚀或反应离子刻蚀；步骤(7)中，涂覆疏水材料采用的方法为CVD、PVD和蒸镀中的至少一种。
优选地，所述等离子刻蚀的工艺参数为：气体流量为100～400sccm，腔室内压力为12～25Pa，处理时间为10～120min。所述反应离子刻蚀的工艺参数为：气体为BCl3或SF6和Ar的混合气体，气体流量分别为30～400sccm和10～100sccm，刻蚀时间30～200s；可以根据对凸台尺寸的需求选择合适的刻蚀条件。
本发明的有益效果在于：本发明提供了一种防污基板及其制备方法，本发明制备的防污基板具有较强的防污性和耐磨性，且基底有多种选择。采用本发明所述防污基板的制备方法获得的防污基板，能够制得凸台之间的间距低至1nm的防污基板，且大大缩小了小尺寸间距的凸台的制备成本，不用采用特殊光源，采用普通的紫外曝光就可以达到。采用此方法制备的防污基板基底和凸台为一体，凸台不容易从基底上脱落，大大提高了防污基板的耐磨性。
附图说明
图1为本发明所述防污基板的制备方法的一个实施例的流程图。
具体实施方式
附图1为本发明所述防污基板的制备方法的一个实施例的流程图，具体地，本发明所述防污基板的制备方法包括以下步骤：
(1)、在基底表面制备一层模板层；
(2)、对步骤(1)所得模板层的表面涂覆一层光刻胶；
(3)、对涂覆有光刻胶的基底进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行第一次刻蚀，然后对刻蚀后的基底进行清洗，得具有第一模板凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行第二次刻蚀，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层保护膜，对第二模板凸台和与第二模板凸台位置对应的基底进行第三次刻蚀，然后清洗第三次刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底涂覆疏水材料；
(8)、对涂覆有疏水材料的基底进行热处理，得所述防污基板。
为更好的说明本发明的目的、技术方案和优点，下面将结合具体实施例对本发明作进一步说明。
实施例1
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氧化锆，涂层为全氟癸基三乙氧基硅烷，所述凸台的平均高度为120nm，每个凸台的平均上表面积为1.767×104nm2，相邻凸台之间的平均间距为150nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用光栅进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为100sccm，腔室内压力为12Pa，处理时间为60min；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为100sccm，腔室内压力为12Pa，处理时间为20min，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为100sccm，腔室内压力为12Pa，处理时间为50min，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟癸基三乙氧基硅烷对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为：200℃，2×10-3Pa，氮气气氛，得涂层的厚度为18nm的防污基板。
本实施例所述模板为二氧化硅。
实施例2
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氧化钙掺杂的二氧化锆，涂层为氟硅烷，所述凸台的平均高度为120nm，每个凸台的平均上表面积为4.0×104nm2，相邻凸台之间的平均间距为50nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用深紫外进行曝光处理，光罩为周期150nm的方形阵列，深紫外曝光10s；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为70sccm和30sccm，刻蚀时间100s；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为70sccm和30sccm，刻蚀时间60s；得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为70sccm和30sccm，刻蚀时间100s，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用氟硅烷对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为150℃，2×10-3Pa，氮气气氛，得涂层的厚度为18nm的防污基板。
本实施例所述模板为二氧化锆。
实施例3
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氧化铈掺的二氧化锆，涂层为全氟聚醚，所述凸台的平均高度为10nm，每个凸台的平均上表面积为3.142×104nm2，相邻凸台之间的平均间距为2000nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用紫外曝光处理，光罩为周期1000nm的方形阵列，紫外曝光10s；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：所述反应离子刻蚀的工艺参数为：气体为SF6和Ar的混合气体，气体流量分别为120sccm和50sccm，刻蚀时间50s；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为70sccm和30sccm，刻蚀时间200s，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为70sccm和30sccm，刻蚀时间50s，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟聚醚对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为100℃，4×10-3Pa，氮气气氛，得涂层的厚度为2nm的防污基板。
本实施例所述模板为碳化锆。
实施例4
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氧化钙掺杂的二氧化锆，涂层为全氟癸基三乙氧基硅烷，所述凸台的平均高度为1000nm，每个凸台的平均上表面积为3.142×104nm2，相邻凸台之间的平均间距为5nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用光栅进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行反应离子刻蚀的工艺参数为：所述反应离子刻蚀的工艺参数为：气体为SF6和Ar的混合气体，气体流量分别为100sccm和10sccm，刻蚀时间100s；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为SF6和Ar的混合气体，气体流量分别为100sccm和10sccm，刻蚀时间100s，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为SF6和Ar的混合气体，气体流量分别为100sccm和10sccm，刻蚀时间200s；然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟癸基三乙氧基硅烷对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为100℃，4×10-3Pa，氮气气氛，得涂层的厚度为100nm的防污基板。
本实施例所述模板为氧化钇。
实施例5
本发明所述防污基板的一种实施例，所述防污基板的基底材料为二氧化锆， 涂层为全氟癸基三乙氧基硅烷，所述凸台的平均高度为2000nm，每个凸台的平均上表面积为1.964×105nm2，相邻凸台之间的平均间距为5000nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用深紫外曝光处理，光罩为周期150nm的圆形阵列，深紫外曝光10s；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为240sccm，腔室内压力为20Pa，处理时间为10min；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为240sccm，腔室内压力为20Pa，处理时间为120min，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为240sccm，腔室内压力为20Pa，处理时间为120min；然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟癸基三乙氧基硅烷对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为100℃，4×10-3Pa，氮气气氛，得涂层的厚度为5nm的防污基板。
本实施例所述模板为氧化钙。
实施例6
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氮化硅，涂层为氟硅烷，所述凸台的平均高度为60nm，每个凸台的平均上表面积为78nm2，相邻凸台之间的平均间距为1nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用光栅进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为300sccm，腔室内压力为22Pa，处理时间为100min；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为300sccm，腔室内压力为22Pa，处理时间为60min，得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行等离子刻蚀，所述等离子刻蚀的工艺参数为：气体流量为300sccm，腔室内压力为22Pa，处理时间为20min，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用氟硅烷对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为100℃，4×10-3Pa，氮气气氛，得涂层的厚度为40nm的防污基板。
本实施例所述模板为氧化铈。
实施例7
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氧化钇掺的二氧化锆，涂层为全氟聚醚，所述凸台的平均高度为60nm，每个凸台的平均上表面积为1.267×105nm2，相邻凸台之间的平均间距为2500nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用光栅进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间30s；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间30s；得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间60s，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟聚醚对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为200℃，5×10-3Pa，氮气气氛，得涂层的厚度为200nm的防污基板。
本实施例所述模板为氮化硅。
实施例8
本发明所述防污基板的一种实施例，所述防污基板的基底材料为碳化硅，涂层为氟碳树脂，所述凸台的平均高度为120nm，每个凸台的平均上表面积为7.069×104nm2，相邻凸台之间的平均间距为100nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用光栅进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为100sccm和50sccm，刻蚀时间100s；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间40s；得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间120s，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟聚醚对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为150℃，5×10-3Pa，氮气气氛，得涂层的厚度为18nm的防污基板。
本实施例所述模板为氮化硅。
实施例9
本发明所述防污基板的一种实施例，所述防污基板的基底材料为氧化钇掺的二氧化锆，涂层为全氟聚醚，所述凸台的平均高度为60nm，每个凸台的平均上表面积为1.267×105nm2，相邻凸台之间的平均间距为2500nm。
本实施例所述防污基板的制备方法，包括以下步骤：
(1)、对基底用清洗剂清洗，然后用超声波清洗5min，再用去离子水清洗2min，然后在氧化锆基底表面制备一层模板；
(2)、对步骤(1)所得模板的表面涂覆一层光刻胶，涂覆厚度200nm，然后在100℃下烘1min；
(3)、对涂覆有光刻胶的基底使用光栅进行曝光处理；
(4)、对步骤(3)所得的曝光处理后的基底上的模板层进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间30s；然后对刻蚀后的基底模板进行清洗，得具有凸台的基底；
(5)、对步骤(4)所得基底上的第一模板凸台进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间30s；得具有第二模板凸台的基底；
(6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层光刻胶，对第二模板凸台和与第二模板凸台位置对应的基底进行反应离子刻蚀，所述反应离子刻蚀的工艺参数为：气体为BCl3和Ar的混合气体，气体流量分别为130sccm和30sccm，刻蚀时间60s，然后清洗刻蚀后的基底，得具有凸台的基底；
(7)、对步骤(6)所得的具有凸台的基底采用化学气相沉积法，用全氟聚醚对其进行疏水化处理；
(8)、对涂覆有疏水材料的基底进行热处理，所述热处理的工艺条件为200℃，5×10-3Pa，氮气气氛，得涂层的厚度为200nm的防污基板。
本实施例所述模板为铜。
对比例1
对比例1所述防污基板与实施例1的区别之处仅在于相邻凸台之间的平均间距不同，对比例所述防污基板相邻凸台之间的平均间距为5500nm。
对比例2
本对比例所述基板为通过光刻刻蚀法制得凸台，这些凸台不属于基底的本体材料，与基底通过界面连接在一起，然后用全氟癸基三乙氧基硅烷对进行疏水化处理，得对比例基板。
实施例10
将实施例1～9和对比例1、2所述防污基板分别进行耐磨性测试。
耐磨性测试是利用摩擦试验机进行测试，在测试的时间相同以及相同的摩 擦次数相同的条件下进行测试，具体的载荷1kg，摩擦次数为5000次，行程3cm，摩擦头使用0000#钢丝绒，摩擦头1cm*1cm。经测试，所述对比例2基板表面的凸台结构受到大面积破坏且从基底表面剥离；实施例1～9和对比例1所述防污基板的凸台未出现从基底表面剥离的现象，说明采用本发明所述防污基板所述方法制备的凸台结构的防污基板的耐磨性能更加优异。
实施例10
将实施例1～9、对比例1、2，以及经过实施例10所述摩擦测试后的实施例1～9和对比例1、2所述防污基板分别进行防污性能测试。防污性能测试是通过水滴接触角来测试，测试结果如表1所示。
表1 实施例1～9、对比例1、2和经过摩擦测试后的实施例1～9、对比例1、2的接触角测试结果
组别 接触角(度) 摩擦测试后的接触角(度)
实施例1 148.6 143.2
实施例2 149.3 144.2
实施例3 130.2 128.5
实施例4 146.5 142.3
实施例5 145.4 141.4
实施例6 134.7 129.2
实施例7 128.2 124.9
实施例8 147.3 144.7
实施例9 130.1 125.2
对比例1 120.3 113.2
对比例2 129.3 102.4
从表1可以看出，与对比例相比，实施例1～9所述防污基板的接触角较大，说明实施例1～9的防污性能较好；经过摩擦测试后，对比例1、2的接触角出现了大幅度的下降，而实施例1～9下降幅度较小，且具有较大的接触角，说明经多次摩擦后的实施例1～9仍具有较佳地防污性能。
最后所应当说明的是，以上实施例仅用以说明本发明的技术方案而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而 不脱离本发明技术方案的实质和范围。

Claims (10)

  1. 一种防污基板，其特征在于，包括：
    基底；所述基底的表面至少具有一个功能区域；所述功能区域至少一部分具有涂层；所述功能区域上具有多个凸台，所述凸台的平均高度为10～2000nm，凸台的平均上表面积为78～1.964×105nm2，相邻凸台之间的平均间距为1～5000nm；所述涂层采用疏水材料制成。
  2. 如权利要求1所述的防污基板，其特征在于，所述涂层的厚度为2～200nm；优选地，所述涂层的厚度为5～100nm。
  3. 如权利要求1所述的防污基板，其特征在于，所述基底的材料包含二氧化硅、二氧化锆、碳化硅、氧化钇、氧化钙、氧化铈、氮化硅和碳化锆中的至少一种；所述涂层的材料为氟硅烷、全氟聚醚、全氟烷基磺酸盐和氟碳树脂中的至少一种；优选地，所述基底的材料为氧化钇、氧化钙或氧化铈掺杂的氧化锆或氧化锆。
  4. 一种防污基板的制备方法，其特征在于，包括以下步骤：
    (1)、在基底表面制备一层模板层；
    (2)、对步骤(1)所得模板层的表面涂覆一层光刻胶；
    (3)、对涂覆有光刻胶的基底进行曝光处理；
    (4)、对步骤(3)所得的曝光处理后的基底上的模板层模板进行第一次刻蚀，然后对刻蚀后的基底进行清洗，得具有第一模板凸台的基底；
    (5)、对步骤(4)所得基底上的第一模板凸台进行第二次刻蚀，得具有第二模板凸台的基底；
    (6)、对步骤(5)所得基底上第二模板凸台周围的凹槽内涂覆一层保护膜，对第二模板凸台和与第二模板凸台位置对应的基底进行第三次刻蚀，然后清洗第三次刻蚀后的基底，得具有凸台的基底；
    (7)、对步骤(6)所得的具有凸台的基底涂覆疏水材料，得所述防污基板。
  5. 如权利要求4所述防污基板的制备方法，其特征在于，所述模板层的材料为固体无机氧化物、固体氮化物、固体碳化物和固体金属中的至少一种；优 选地，所述模板层的材料为二氧化硅、二氧化锆、碳化硅、氧化钇、氧化钙、氧化铈、氮化硅、碳化锆、铜、钨和铝中的至少一种。
  6. 如权利要求4所述防污基板的制备方法，其特征在于，步骤(3)中，所述曝光处理为深紫外曝光处理；所述深紫外曝光处理的光罩为掩模板，光源为深紫外光。
  7. 如权利要求4所述防污基板的制备方法，其特征在于，步骤(3)中，所述曝光处理为光栅曝光处理；所述光栅曝光处理的光罩为光栅，光源为紫外光。
  8. 如权利要求4所述防污基板的制备方法，其特征在于，步骤(6)中，所述保护膜为光刻胶。
  9. 如权利要求4所述防污基板的制备方法，其特征在于，步骤(7)中，在对具有凸台的基底涂覆疏水材料之后，还包括对涂覆了疏水材料的凸台进行热处理的步骤，所述热处理的条件为：50～250℃，5×10-3～1×10-1Pa。
  10. 如权利要求4所述防污基板的制备方法，其特征在于，步骤(4)中，所述第一次刻蚀为等离子刻蚀或反应离子刻蚀；步骤(5)中，所述第二次刻蚀为等离子刻蚀或反应离子刻蚀；步骤(6)中，所述第三次刻蚀为等离子刻蚀或反应离子刻蚀；步骤(7)中，涂覆疏水材料采用的方法为CVD、PVD和蒸镀中的至少一种。
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