WO2019001441A1 - 信息处理的方法、装置和通信设备 - Google Patents

信息处理的方法、装置和通信设备 Download PDF

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WO2019001441A1
WO2019001441A1 PCT/CN2018/092974 CN2018092974W WO2019001441A1 WO 2019001441 A1 WO2019001441 A1 WO 2019001441A1 CN 2018092974 W CN2018092974 W CN 2018092974W WO 2019001441 A1 WO2019001441 A1 WO 2019001441A1
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matrix
rows
base
columns
column
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PCT/CN2018/092974
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English (en)
French (fr)
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金杰
马祖连科伊万•列昂尼多维奇
帕特尤斯基亚历山大
张朝龙
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华为技术有限公司
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Priority to EP18823969.3A priority Critical patent/EP3629481B1/en
Publication of WO2019001441A1 publication Critical patent/WO2019001441A1/zh
Priority to US16/719,529 priority patent/US11088706B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing

Definitions

  • Embodiments of the present invention relate to the field of communications, and in particular, to a method for information processing and a communication device.
  • Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
  • the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
  • LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
  • an LDPC matrix with special structured features can be used.
  • the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
  • QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
  • the LDPC matrix can be designed to be applied to channel coding.
  • QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
  • the LDPC matrix can be designed to be applied to channel coding.
  • Embodiments of the present invention provide a method, a communication device, and a system for information processing, which can support encoding and decoding of information bit sequences of various lengths.
  • an encoding method and an encoder are provided that encode an input sequence using a low density parity check LDPC matrix.
  • a decoding method and decoder are provided that decode an input sequence using a low density parity check LDPC matrix.
  • the LDPC matrix is obtained based on the spreading factor Z and the base matrix.
  • the base matrix of the base map 30a may include one of the matrices shown by the matrices 30b-10, 30b-20, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70, and 30b-80.
  • Columns 0 to 4 and columns 0 to 26, or the matrix includes matrixes 30b-10, 30b-20, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and The 0th to 4th rows in one of the matrices shown in 30b-80 and the partial columns in the 0th to 26th columns, or the base matrix may be the 0th to the one of the matrices shown in the matrix 30b-10 to 30b-80.
  • the row/column transformed matrix of 4 rows and 0th to 26th columns may be matrix 30b-10, 30b-20, 30b-30, 30b-40, 30b-50, 30b-60, 30b-
  • the base matrix of the base map 30a may further include one of the matrices shown in the matrix 30b-10, 30b-20, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70, and 30b-80.
  • Lines 0 to (m-1), and columns 0 to (n-1), or the matrix may be matrix 30b-10, 30b-20, 30b-30, 30b-40, 30b-
  • the 0th row to the (m-1)th row in one of the matrices 50, 30b-60, 30b-70, and 30b-80, and the row/column after the 0th column to the (n-1)th column are transformed
  • the matrix 5 ⁇ m ⁇ 46, 27 ⁇ n ⁇ 68.
  • the LDPC code requires different spreading factors Z.
  • a base matrix corresponding thereto is adopted based on different spreading factors Z.
  • Z a ⁇ 2 j , 0 ⁇ j ⁇ 7, a ⁇ ⁇ 2, 3, 5, 7, 9, 11, 13, 15 ⁇ .
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-10, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-10 A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-10, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-20, or the base matrix includes the 0th to 4th rows and the 0th to the 0th of the matrix 30b-20 Part of the 26 columns. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-20, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-30, or the base matrix may include the 0th to 4th rows and the 0th to 26th of the matrix 30b-30.
  • the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-30, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-40, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-40 A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-40, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-50, or the base matrix may include the 0th to 4th rows and the 0th to 26th of the matrix 30b-50 A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-50, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-60, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-60. A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-60, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-70, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-70. A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-70, and the 0th column to the (n-1)th column.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-80, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-80. A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-80, and the 0th column to the (n-1)th column.
  • the base matrix may be a matrix after the row/column transformation of the corresponding matrix.
  • the LDPC matrix may be obtained based on the spreading factor Z and the matrix Hs compensated for each of the foregoing base matrices, or based on the spreading factor Z and the matrix after compensating the foregoing base matrices.
  • the matrix after the row/column transformation of Hs is obtained.
  • the offset value may be increased or decreased for an offset value greater than or equal to 0 in one or more of the columns.
  • the base map and the base matrix of the LDPC matrix in each of the foregoing implementation manners can satisfy the performance requirements of the code blocks of various block lengths.
  • the method further includes: determining the expansion factor Z.
  • the value of the spreading factor Z is determined according to the length K of the input sequence, and in the supported set of spreading factors, the smallest Z 0 is found as the magnitude of the spreading factor Z, and Kb ⁇ Z 0 ⁇ K is satisfied.
  • Kb can be the number of columns of information bits in the base matrix of the LDPC code.
  • Kb 22.
  • the value of Kb may also vary according to the value of K, but does not exceed the number of information bit columns in the base matrix of the LDPC code.
  • the spreading factor Z may be determined by the encoder or the decoder according to the length K of the input sequence, or may be determined by other devices and provided as an input parameter to the encoder or the decoder.
  • the LDPC matrix may be obtained according to the obtained spreading factor Z and the base matrix corresponding to the spreading factor Z.
  • the LDPC matrix is obtained based on parameters of the spreading factor Z and the LDPC matrix.
  • the parameters of the LDPC matrix may include: a row number, a column in which the non-zero element is located, and a non-zero element offset value, as shown in Table 3-10, Table 3-20, Table 3-30, Table 3-40, Table 3-50, Table 3-60, Table 3-70, and Table 3-80 are saved. It can also include line weights.
  • the offset values in the positions of the non-zero elements and the non-zero element offset values are one-to-one correspondence.
  • the encoder thus encodes the input sequence according to the spreading factor Z and the parameters of the LDPC matrix.
  • the parameters saved according to Table 3-10 correspond to the matrix 30b-10
  • the parameters saved according to Table 3-20 correspond to the matrix 30b-20
  • the parameters saved according to Table 3-30 correspond to the matrix 30b-30, according to Table 3-
  • the saved parameters correspond to the matrix 30b-40
  • the parameters saved according to Table 3-50 correspond to the matrix 30b-50
  • the parameters saved according to Table 3-60 correspond to the matrix 30b-60
  • the parameters saved according to Table 3-70 are
  • the matrices 30b-70 correspond to the parameters stored in accordance with Table 3-80 corresponding to the matrices 30b-80.
  • encoding the input sequence using the LDPC matrix may include:
  • the row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.
  • decoding the input sequence using the LDPC matrix includes:
  • the input sequence is decoded by using an LDPC matrix corresponding to the spreading factor Z; or the LDPC matrix corresponding to the spreading factor Z is subjected to row/column transformation, and the input sequence is encoded using the matrix after the row/column transformation to the input.
  • the sequence is encoded.
  • the row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.
  • the LDPC matrix may be saved, the input sequence is encoded using the LDPC matrix, or transformed (row/column transform) or extended based on the LDPC matrix to obtain an LDPC matrix usable for encoding.
  • parameters may be saved, and an LDPC matrix for encoding or decoding may be obtained according to the parameters, so that the input sequence may be encoded or decoded based on the LDPC matrix.
  • the parameter includes at least one of: a base map, a base matrix, a transform matrix based on a base/column transformation of a base map or a base matrix, an extended matrix based on a base map or a base matrix, and an offset value of a non-zero element in the base matrix; Or any parameter related to obtaining an LDPC matrix.
  • the base matrix of the LDPC matrix can be stored in a memory.
  • the base map of the LDPC matrix is stored in a memory, and offset values of non-zero elements in the base matrix of the LDPC matrix may be stored in the memory.
  • the parameters of the LDPC matrix are stored in the memory in the manner shown in Tables 3-10 through 23-80.
  • At least one of the base map and the base matrix used for LDPC encoding or decoding is at least one of a base map and a base matrix of the foregoing LDPC matrix, or Column exchange, or row exchange and column exchange.
  • a communication device can include corresponding modules for performing the above method design.
  • the module can be software and/or hardware.
  • a communication device provided by the third aspect includes a processor and a transceiver component that can be used to implement the functions of various portions of the encoding or decoding method described above.
  • the transceiver component if the communication device is a terminal, a base station or other network device, the transceiver component thereof may be a transceiver. If the communication device is a baseband chip or a baseband single board, the transceiver component may be a baseband chip or a baseband single board. Input/output circuits for receiving/transmitting input/output signals.
  • the communication device can optionally also include a memory for storing data and/or instructions.
  • the processor may include the encoder and the determining unit as described in the first aspect above.
  • the determining unit is operative to determine a spreading factor Z required to encode the input sequence.
  • the encoder is configured to encode the input sequence using an LDPC matrix corresponding to the spreading factor Z.
  • the processor may include the decoder and the obtaining unit as described in the second aspect above.
  • the obtaining unit is configured to acquire a soft value and an expansion factor Z of the LDPC code.
  • the decoder is configured to decode the soft value of the LDPC code based on the base matrix H B corresponding to the spreading factor Z to obtain an information bit sequence.
  • a communication device in a fourth aspect, includes one or more processors.
  • one or more of the processors may implement the functions of the encoder of the first aspect, and in another possible design, the encoder of the first aspect may be the processor In part, the processor can implement other functions in addition to the functions of the encoder described in the first aspect.
  • one or more of the processors may implement the functions of the decoder of the second aspect, and in another possible design, the decoder of the second aspect may be Part of the processor.
  • the communication device may further include a transceiver and an antenna.
  • the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
  • a demodulator for demodulation operation e.g., a demodulator for demodulation operation
  • a deinterleaver for deinterleaving e.g., a device for de-rate matching
  • the functionality of these devices can be implemented by one or more processors.
  • the functionality of these devices can be implemented by one or more processors.
  • an embodiment of the present invention provides a communication system, where the system includes the communication device described in the foregoing third aspect.
  • an embodiment of the present invention provides a communication system, where the system includes one or more communication devices according to the fourth aspect.
  • an embodiment of the present invention provides a computer storage medium having stored thereon a program, and when executed, causes a computer to perform the method described in the above aspect.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • the method, device, communication device and communication system of the information processing according to the embodiments of the present invention can adapt to the flexible code length code rate requirement of the system in coding performance and error leveling.
  • 1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code
  • FIG. 2 is a schematic structural diagram of a base diagram of an LDPC code
  • FIG. 3a is a schematic diagram of a LDPC code base diagram according to an embodiment of the present invention.
  • FIG. 3b-1 is a schematic diagram of a base matrix according to an embodiment of the present invention.
  • 3b-2 is a schematic diagram of another base matrix according to an embodiment of the present invention.
  • 3b-3 is a schematic diagram of another base matrix according to an embodiment of the present invention.
  • 3b-4 is a schematic diagram of another base matrix according to an embodiment of the present invention.
  • FIG. 3b is a schematic diagram of another base matrix according to an embodiment of the present disclosure.
  • 3b-6 is a schematic diagram of another base matrix according to an embodiment of the present invention.
  • 3b-7 is a schematic diagram of another base matrix according to an embodiment of the present invention.
  • 3b-8 is a schematic diagram of another base matrix according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of an information processing method according to another embodiment of the present invention.
  • FIG. 6 is a flowchart of an information processing method according to another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an information processing apparatus according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a communication system according to another embodiment of the present invention.
  • the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
  • a terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
  • the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
  • a base station is called an evolved Node B (eNB or eNodeB).
  • eNB evolved Node B
  • NR transmission reception point
  • gNB next generation node B
  • Base stations in other various evolved networks may also adopt other names. The invention is not limited to this.
  • the LDPC code can usually be represented by a parity check matrix H.
  • the parity check matrix H of the LDPC code can be obtained by a base graph and a shift value.
  • the base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns.
  • the value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix.
  • An element with a value of 1, sometimes referred to as a non-zero element indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement.
  • each matrix element represents an all-zero matrix or a cyclic permutation matrix.
  • the row number and column number of the base map and the matrix are numbered from 0, for convenience of explanation, for example, the 0th column is represented as the base map and the first column of the matrix, the first The columns are represented as the base and the second column of the matrix, the 0th row represents the base map and the first row of the matrix, the first row is represented as the base map and the second row of the matrix, and so on.
  • the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 on the basis of the line number and column number shown in this article, for example, if the line number or column number is from 1 Starting with the number, the first column represents the base column and the first column of the matrix, the second column represents the base map and the second column of the matrix, the first row represents the first row representing the base map and the matrix, and the second row represents the base map. And the second line of the matrix, and so on.
  • the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P i,j , P i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1
  • the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P i,j , which can be obtained by cyclically shifting the unit matrix of Z*Z by P i, j times to the right.
  • each element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and each element having a value of 1 is replaced by a cyclic permutation matrix of Z*Z corresponding to its offset value,
  • Z is a positive integer, which can also be called a lifting factor, which can be determined according to the code block size supported by the system and the size of the information data.
  • the system usually defines a base matrix of m rows and n columns, sometimes called PCM (parity check matrix).
  • PCM parity check matrix
  • each element corresponds to the position of each element in the base map.
  • the zero elements in the base map are in the same position in the base matrix, and can be represented by -1 or null "null".
  • the non-zero elements of the j-th column with a value of 1 are invariant in the base matrix, and may be expressed as P i,j , P i,j may be offset values defined relative to a predetermined or specific spreading factor Z.
  • the base matrix is sometimes referred to as an offset matrix of the base matrix.
  • a base matrix corresponding to the base map 10a is shown.
  • the LDPC code used in the wireless communication system is a QC-LDPC code, and the check bit portion has a double diagonal structure or a raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission.
  • a QC-LDPC shift network QSN
  • Banyan network a Banyan network
  • Benes network is generally used to implement cyclic shift of information.
  • the matrix size of the base map is m rows and n columns, and may include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by a non-zero element
  • the number of rows refers to the number of non-zero elements included in a row
  • the weight of the column refers to the number of non-zero elements included in a column.
  • Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
  • the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
  • the sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 may be located before the sub-matrix B', as shown in FIG. 20a; the sub-matrix B may further include one or more columns of columns having a column weight of 1 (referred to as a single column of re-columns).
  • a single column of re-columns referred to as a single column of re-columns
  • a matrix that is typically generated based on sub-matrices A and B can be referred to as a core matrix and can be used to support high code rate encoding.
  • Submatrix C is an all-zero matrix with a size of m A ⁇ m D .
  • the sub-matrix E is an identity matrix having a size of m D ⁇ m D .
  • the submatrix D has a size of m D ⁇ (n A + m A ) and can generally be used to generate a low bit rate check bit.
  • the structure of the two sub-matrices A, B and D is one of the factors influencing the coding performance of the LDPC code.
  • the matrix of the sub-matrices A and B may be encoded to obtain the parity bit corresponding to the sub-matrix B, and then The entire matrix is encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B' of the double-diagonal structure and a single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column can be obtained.
  • H core the core matrix part composed of sub-matrices A and B
  • the last row and the last column are removed from the H core , that is, the single-column re-column and the row where the non-zero elements of the column are located are obtained, and the obtained matrix portion is H core-dual
  • H core-dual ⁇ [S P e ] T 0, where S is an input sequence, represented by a vector of information bits, P e is a vector of check bits, and [S P e ] T represents The matrix consists of input sequences S and P e transposed.
  • H core-dual H core-dual check bit corresponding to the input sequence S includes all information bits; then according to obtain H core-dual check bit corresponding to an input sequence and calculates S Obtaining the parity bits corresponding to the single column re-column in the sub-matrix B, in this case, all the parity bits corresponding to the sub-matrix B can be obtained; and then according to the input sequence S and the parity bits corresponding to the sub-matrix B, the sub-matrix D is partially encoded.
  • the check bits corresponding to the sub-matrix E thus obtaining all information bits and all check bits, these bits constitute the encoded sequence, that is, an LDPC code sequence.
  • the LDPC code encoding may also include shortening and puncturing operations. Both truncated bits and punctured bits are not transmitted.
  • the truncation is generally truncated from the last bit of the information bit, and can be truncated in different ways.
  • the truncated number of bits s 0 can be set to the last s 0 bits in the input sequence S to obtain the input sequence S', such as set to 0 or null, or some other value, and then through the LDPC matrix pair
  • the input sequence S' is encoded.
  • the last (s 0 mod Z) bits in the input sequence S may be set to the known bits to obtain the input sequence S', such as set to 0 or null, or some other value.
  • the input sequence S' is encoded using the LDPC matrix H', or the last in the submatrix A
  • the column does not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.
  • the punching may be a punching bit built in the input sequence or a punching bit.
  • the last bit of the parity bit is usually punctured.
  • the puncturing may be performed according to the preset puncturing order of the system.
  • a possible implementation manner is that the input sequence is first encoded, and then the last p bits in the parity bit are selected according to the number of bits p to be punctured, or p bits are selected according to the system's preset puncturing order. p bits are not sent.
  • the p columns of the matrix corresponding to the punctured bits and the p rows of the non-zero elements in the columns may also be determined, and the rows and columns do not participate in the coding, and the corresponding school is not generated. Check the bit.
  • the coding mode is only an example here, and other coding methods known to those skilled in the art may be used based on the present disclosure to provide a base map and/or a base matrix, which is not limited in this application.
  • the decoding involved in the present application may be a plurality of coding modes, for example, a min-sum (MS) decoding method or a belief propagation decoding method.
  • MS decoding method is sometimes also referred to as a Flood MS decoding method.
  • the input sequence is initialized and iteratively processed, the hard decision detection is performed after the iteration, and the hard decision result is verified. If the decoding result conforms to the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. .
  • the decoding mode is only an example.
  • the base map and/or the base matrix provided by the present application, other decoding methods known to those skilled in the art may be used.
  • the decoding method is not limited in this application.
  • the LDPC code can usually be obtained by designing a base map or a base matrix. For example, a density evolution method may be applied to the base map or the base matrix to determine an upper performance limit of the LDPC code, and an error leveling layer of the LDPC code is determined according to the offset value in the base matrix. By designing the base or base matrix, coding or decoding performance can be improved, and error leveling can be reduced.
  • the code length in the wireless communication system is flexible, for example, it can be 2560 bits, 38400 bits, etc.
  • FIG. 3a is an example of a base diagram 30a of an LDPC code
  • FIG. 3b-1 to FIG. 3b-8 are base matrixes of the base diagram 30a.
  • Figure 3a shows an example of a base map 30a of an LDPC code, in which the uppermost row 0 to 67 (i.e., columns 0 to 67) represents the column number, and the leftmost column 0 to 45 (i.e., 0 to 45 rows) represents the row.
  • the number, that is, the matrix size of the base map 30a is 46 rows and 68 columns.
  • portions of sub-matrix A and sub-matrix B can be viewed as the core matrix portion of the base map of the LDPC code, which can be used for high bit rate encoding.
  • a matrix of 5 rows and 27 columns is constructed, and a matrix of 5 rows and 27 columns as shown in the base diagram 10a can be used as a core matrix portion of the base map.
  • the sub-matrix A may include one or more columns of built-in punctured bit columns.
  • the column may include two columns of built-in punctured bit columns.
  • the core matrix can support a code rate of 0.88.
  • the sub-matrix B may include one column and three columns of re-columns, that is, the 0th column of the sub-matrix B (the 22nd column of the core matrix) has a column weight of 3, and the first to third columns of the sub-matrix B (the core matrix) Columns 23 to 25), the 0th to 3rd behaviors are double-diagonal structures, and the sub-matrix B also includes 1 column of single column weights (the 26th column of the core matrix).
  • the sub-matrix B may correspond to a parity bit having a size of m A rows and m A columns, and elements of the 0th row to the 4th row and the 22nd column to the 26th column in the base map 30a. .
  • sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates.
  • the sub-matrix C is an all-zero matrix
  • the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed.
  • the main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.
  • the sub-matrix D may include the m D rows in the 5th line to the 41st line of the base map 30a.
  • the two rows are orthogonal to each other. If there are only one non-zero element in the same column except for a partial column in the adjacent two rows in the base map, the adjacent two rows are quasi-orthogonal. For example, for two adjacent rows, except for the column other than the built-in punctured bit column, which has only one non-zero element, the adjacent two rows can be considered to be quasi-orthogonal.
  • Lines 5 to 41 of the base map 30a may include a multi-row quasi-orthogonal structure and at least two rows of orthogonal structures.
  • the fifth row to the 41st line in the base map 30a includes at least 15 rows conforming to the quasi-orthogonal structure, and in any of the adjacent two rows of the 15 rows, except for the built-in punch bit column, in the same column There is at most one non-zero element.
  • Lines 5 to 41 of the base map 30a may further include 10 to 26 lines conforming to the orthogonal structure, that is, among the lines, any one of the adjacent two lines has at most one non-zero element, that is, built-in There is also at most one non-zero element in the hole bit column.
  • the sub-matrix D in the LDPC code base map has a size of 15 rows and 27 columns, and may be composed of a matrix of the 5th to 19th rows and the 0th column to the 26th column of the base map 30a, corresponding to the LDPC code.
  • the sub-matrix E is an element matrix of 15 rows and 15 columns
  • the sub-matrix C is an all-zero matrix of 5 rows and 15 columns;
  • the size of the sub-matrix D in the LDPC code base map is 19 rows and 27 columns, which may be composed of a matrix of the 5th to 23rd rows and the 0th column to the 26th column of the base map 30a, corresponding to the LDPC code.
  • the sub-matrix E is an identity matrix of 19 rows and 19 columns
  • the sub-matrix C is an all-zero matrix of 5 rows and 19 columns.
  • row/column swapping may be performed on the base map and/or base matrix, that is, row swapping, or column swapping, or row swapping and column swapping.
  • the row/column swap operation does not change the row weight and the column weight, and the number of non-zero elements does not change. Therefore, the base and/or base matrix after row/column swap has limited impact on system performance. That is to say, as a whole, the impact on system performance is acceptable, within tolerance, for example, performance may fall within the allowable range for certain scenarios or within certain ranges, but in some scenarios or certain ranges Within the performance, the performance has improved, and overall it has little effect on performance.
  • the 34th row and the 36th row of the base map 30a can be exchanged, and the 44th column and the 45th column can be exchanged.
  • the sub-matrix D includes m D rows in the matrix F.
  • the m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, and no row is performed.
  • the column swap for example, performs row swapping of the 27th and 29th rows of the matrix F, the submatrix D includes the m D rows in the matrix F, and the submatrix E is still a diagonal structure. It can be understood that if the base map or the base matrix includes the sub-matrix D, when the columns of the core matrix are exchanged, the columns in the corresponding sub-matrix D also need to be exchanged.
  • the matrices 30b-10 to 30b-80 shown in Figures 3b-1 to 3b-8 are the design of a plurality of base matrices of the base map 30a, respectively.
  • the non-zero elements of the i-th row and the j-th column in the base map 30a are invariant positions in the matrices of the matrices 30b-10 to 30b-80, and the values are offset values V i,j , and the zero elements are in the offset matrix.
  • the sub-matrix D in the group matrix which may include corresponding parts D m row matrix of any of which line 5 to line 45, and can choose different values of the bit rate according to D m.
  • the base map is a matrix after row/column transformation with respect to the base map 30a
  • the base matrix is also a matrix after row/column transformation corresponding to any one of the matrices 30b-10 to 30b-80.
  • the base matrix of the LDPC code may include rows 0 to 4 and columns 0 to 26 of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-8.
  • the matrix composed of the 0th to 4th rows and the 0th to 26th columns of the matrix shown in FIGS. 3b-1 to 3b-8 can be used as the core portion of the base matrix.
  • the structure of the other part of the base matrix of the LDPC code for example, the matrix C, D, E is not limited, for example, any of the structures shown in FIG. 3b-1 to FIG. 3b-8 may be used.
  • Other matrix designs can be used.
  • the base matrix of the LDPC code may include the 0th to (m-1)th rows of any of the matrices 30b-10 to 30b-80 shown in FIG. 3b-1 to FIG. 3b-8. And a matrix composed of columns 0 to (n-1), wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer.
  • the structure of other parts of the base matrix of the LDPC code is not limited.
  • any of the structures shown in FIG. 3b-1 to FIG. 3b-8 may be employed, and other matrix designs may be employed.
  • the base matrix of the LDPC code may include the 0th to 4th rows and the 0th to 26th of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-8.
  • the core portions (rows 0 to 4 and columns 0 to 26) of the matrix shown in Figures 3b-1 through 3b-8 can be shortened and/or punctured.
  • the base matrix of the LDPC code may not include columns corresponding to truncated and/or punctured bits.
  • the other portions of the base matrix of the LDPC code are not limited.
  • the structure shown in FIG. 3b-1 to FIG. 3b-8 may be referred to, and other configurations may be employed.
  • the base matrix of the LDPC code may include the 0th to (m-1)th rows of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-8. And a matrix composed of partial columns in the 0th to (n-1)th columns, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer.
  • the 0th to (m-1)th rows and the 0th to (n-1)th columns of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-8 may be truncated ( Shortening) and/or puncturing.
  • the base matrix of the LDPC code may not include columns corresponding to truncated and/or punctured bits.
  • the other portions of the base matrix of the LDPC code are not limited.
  • the structure shown in FIG. 3b-1 to FIG. 3b-8 may be referred to, and other configurations may be employed.
  • the truncating operation may be truncating the information bits.
  • the base matrix of the LDPC code may not include FIG. 3b-1.
  • the base matrix of the LDPC code may include columns 0 to 20 and columns 22 to 26 of any matrix of 30b-10 to 30b-80.
  • the code rate is 7/8.
  • the puncturing may be puncturing the parity bit.
  • one of the columns shown in FIG. 3b-1 to FIG. 3b-8 is used as an example, and one or more columns in the 22nd to 26th columns are punched.
  • the base matrix of the LDPC code may not include one or more columns that are perforated in the matrix shown in FIGS. 3b-1 to 3b-8.
  • the base matrix of the LDPC code may include columns 0 to 25 of any matrix of 30b-10 to 30b-80.
  • Different spreading factors Z are designed for the LDPC code to support information bit sequences of different lengths.
  • different base factors can be used for different spreading factors to achieve better performance.
  • the expansion factor Z a ⁇ 2 j , 0 ⁇ j ⁇ 7, a ⁇ ⁇ 2, 3, 5, 7, 9, 11, 13, 15 ⁇ .
  • Table 1 is a set of extension factors that may be supported ⁇ 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ , wherein each cell represents, in addition to the top row and the leftmost column, respectively
  • the set of spreading factors supported by the base map may be all the spreading factors in Table 1, it may also be a part of the spreading factor, for example, it may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ , that is, Z is greater than or equal to 24.
  • one or more of ⁇ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22 ⁇ The union of 24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384 ⁇ . It should be noted that this is only an example.
  • the set of spreading factors supported by the base map can be divided into different subsets according to the value of a.
  • the set of spreading factors supported by the base map can be divided according to different values of a to determine the corresponding base matrix:
  • the base matrix may include the 0th to 4th rows and the 0th to 26th of the matrix 30b-10.
  • the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-10, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-10 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, where n is an integer. .
  • the base matrix may include the 0th to 4th rows and the 0th to 26th of the matrix 30b-20.
  • the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-20, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-20 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, where n is an integer. .
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-30, Alternatively, the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-30, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is An integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-30 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is an integer.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-40, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-40, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; Alternatively, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-40 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68 , n is an integer.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-50, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-50, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; Alternatively, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-50 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, and 27 ⁇ n ⁇ 68 , n is an integer.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-60, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-60, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; Alternatively, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-60 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, and 27 ⁇ n ⁇ 68 , n is an integer.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-70, or the base matrix
  • the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-70 are included, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; or
  • the base matrix includes the 0th to (m-1)th rows of the matrix 30b-70 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68,n Is an integer.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-80, or the base matrix
  • the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-80 are included, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; or
  • the base matrix includes the 0th to (m-1)th rows of the matrix 30b-80 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68,n Is an integer.
  • the offset value Offset s may be increased or decreased for the offset value of one or more columns of non-zero elements in the matrix , but has little effect on system performance.
  • the compensation values of the non-zero elements in different columns may be the same or different.
  • one or more columns of the matrix may be compensated.
  • the compensation values of different columns may be the same or different, and the application is not limited.
  • a small impact on system performance means that the impact on system performance is acceptable and within tolerance. For example, performance may be degraded within certain limits for certain scenarios or within certain ranges, but performance may improve over certain scenarios or within certain ranges, and overall has little impact on performance.
  • the compensation value Offset s for each offset value greater than or equal to 0 in the sth column of any of the matrices 30b-10 to 30b-80 can obtain the compensation matrix Hs of the matrix, where Offset s is greater than Or an integer equal to 0, 0 ⁇ s ⁇ 23.
  • the offset values Offsets of one or more columns may be the same or different.
  • the decoding performance curves of the LDPC codes encoded based on the matrices 30b-10 to 30b-80 on the AWGN channel, QPSK modulation, and 50 iterations.
  • the curves are smooth, indicating that the matrix has superior performance over different block lengths.
  • the base map of 10a in Figure 1 is a matrix of 5 rows and 27 columns, and the parameters involved can be represented by Tables 2-10.
  • the size of the base matrix shown in Fig. 1 is a matrix of 5 rows and 27 columns, and the parameters involved can be expressed by Table 2-11.
  • matrix 30b-10 in Figure 3b-1 can be represented by Tables 3-10.
  • matrix 30b-20 in Figure 3b-2 can be represented by Tables 3-20.
  • matrix 30b-30 in Figure 3b-3 can be represented by Tables 3-30.
  • the matrix 30b-40 of Figures 3b-4 can be represented by Tables 3-40.
  • the matrix 30b-50 of Figures 3b-5 can be represented by Tables 3-50.
  • the matrix 30b-60 of Figures 3b-6 can be represented by Table 3-60.
  • the matrix 30b-70 of Figures 3b-7 can be represented by Table 3-70.
  • the matrix 30b-80 of Figures 3b-8 can be represented by Table 3-80.
  • FIG. 1 to FIG. 3a, FIG. 3b-1 to FIG. 3b-8, and Table 2-10, Table 2-11, and Tables 3-10 to 3-80 are for understanding understanding of the design of the base map and the matrix, Its manifestation is not limited to the representations of Figures 1 to 3a, 3b-1 to 3b-8 or Tables 2-10, 2-11 and 3-10 to 3-80 above. Other possible variations may also be included.
  • the parameter "row weight" in Tables 2-10, 2-11, and 3-10 to 3-80 above may also be omitted. You can know how many non-zero elements are in the row through a column with a non-zero element, so the row weight is known.
  • the parameter values in the “column of non-zero elements” in Table 2-10, Table 2-11, and Tables 3-10 to 3-80 may also not be from small to large. The order is as long as the parameter value is indexed to the column in which the non-zero element is located.
  • the parameter values in "non-zero element offset values" of Table 2-10, Table 2-11, Tables 3-10 to 3-80 are not necessarily arranged in the order of the columns, as long as “non-zero elements are biased"
  • the parameter value in the "shift value” can be in one-to-one correspondence with the parameter value in the "column where the non-zero element is located".
  • Figure 5 shows the design of the process of processing data.
  • the process of processing the data may be implemented by a communication device, which may be a base station, terminal or other entity, such as a communication chip, an encoder/decoder, or the like.
  • Section 501 the input sequence is obtained.
  • the encoded input sequence can be a sequence of information bits.
  • the information bit sequence is sometimes also referred to as a code block, and may be, for example, an output sequence after code block division of the transport block.
  • the decoded input sequence may be a soft sequence of LDPC codes.
  • the input sequence is encoded/decoded based on an LDPC matrix;
  • the base matrix of the LDPC matrix may be any of the base matrices in the foregoing examples.
  • the LDPC matrix can be derived based on the spreading factor Z and the base matrix.
  • related parameters of the LDPC matrix may be saved, and the parameters include one or more of the following:
  • the base matrix may be obtained based on the parameters; for example, the parameters may include one or more of the following: row number, row weight, The position of the non-zero element, the offset value in the base matrix, the non-zero element offset value and the corresponding position, the compensation value, the spreading factor, the base map, the code rate, and the like.
  • any of the base matrix enumerated in each of the above implementation modes passes through at least one column of compensated compensation matrix Hs;
  • the input sequence is encoded/decoded based on the low density parity check LDPC matrix, which may be performed in one or more of the following manners in the encoding/decoding process:
  • the compensation matrix of the base matrix is encoded/decoded, or encoded/decoded based on the matrix of the matrix matrix obtained by the compensation matrix Hs.
  • it may further include an extended matrix encoding/decoding based on an extension matrix of the base matrix or the compensation matrix Hs, or truncating or playing based on a base matrix or a compensation matrix.
  • the base matrix or the compensation matrix Hs encoding/decoding optionally, it may further include an extended matrix encoding/decoding based on an extension matrix of the base matrix or the compensation matrix Hs, or truncating based on a base matrix or a compensation matrix or Matrix coding/decoding after puncturing;
  • Figure 6 shows a design for the process of obtaining processed data, which can be used in section 502 of Figure 5.
  • the spreading factor Z can be determined based on the length K of the input sequence. For example, it may be that in the set of supported extension factors, the smallest Z 0 is found as the size of the expansion factor Z, and Kb ⁇ Z 0 ⁇ K is satisfied. In one possible design, Kb can be the number of columns of information bits in the base matrix of the LDPC code.
  • the set of spreading factors supported by the base map 30a is ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60 , 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ .
  • a specific information length K may also be used, for example, for 104 ⁇ K ⁇ 512, Z may be selected according to a system-defined rule, and K is other lengths according to any of the foregoing implementation manners. For example, the minimum Z 0 of Kb ⁇ Z 0 ⁇ K is satisfied, where Kb is 22 or is determined according to the threshold.
  • the spreading factor Z may be determined by the communication device according to the length K of the input sequence, or may be obtained by the communication device from other entities such as a processor.
  • an LDPC matrix is obtained based on the spreading factor and the base matrix.
  • the base matrix is any of the base matrices exemplified in the foregoing embodiments, or a compensation matrix obtained by compensating at least one of any of the base matrices exemplified above, or with respect to any of the base matrices exemplified above or
  • the row order is transformed, or the column order is transformed, or the base matrix in which the row order and the column order are transformed, and the base map includes at least the sub-matrix A and the sub-matrix B.
  • the sub-matrix C, the sub-matrix D, and the sub-matrix E are further included in the descriptions of the foregoing embodiments, and details are not described herein again.
  • the corresponding base matrix is determined according to the spreading factor Z, and the base matrix is replaced according to the spreading factor Z to obtain an LDPC matrix.
  • the correspondence between the spreading factor and the base matrix may be stored, and the expansion factor Z obtained in part 601 is used to determine the corresponding base matrix.
  • the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-7, or the base matrix includes the 0th to 4th rows in the matrix 30b-7 and the a partial column of 0 to 26 columns; further, or the base matrix further includes a matrix 0 to m-1 row and a 0th to n-1th column, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68 n is an integer, or the base matrix includes the 0th to m-1th rows and the 0th to the n-1th columns of the matrix 30b-7, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is Integer.
  • the base matrix is replaced according to the spreading factor Z to obtain an LDPC matrix.
  • the i-th row and the j-th column element P i,j in the base matrix can satisfy the following relationship:
  • V i,j may be an offset value of an element of the i-th row and the j-th column in the base matrix of the set of the expansion factor Z, or an i-th row of the base matrix of the largest spreading factor in the set of the expansion factor Z The offset value of the non-zero element of the column.
  • the element P i,j of the i-th row and the j-th column in the base matrix is satisfied.
  • V i,j is the offset value of the non-zero element of the ith row j column of PCM 7 and matrix 30b-70.
  • the input sequence is encoded/decoded based on the LDPC matrix.
  • the encoded input sequence can be a sequence of information bits.
  • the decoded input sequence may be a soft value sequence of the LDPC code, as described in the related description in FIG.
  • the LDPC matrix H obtained by extending the Z-base matrix can be used.
  • a cyclic permutation matrix h i,j of Z*Z size is determined, where h i,j is a cyclic permutation matrix obtained by cyclically shifting the unit matrix by P i,j times Substituting h i,j for the non-zero element P i,j , replacing the zero-element in the base matrix H B with the all-zero matrix of the Z*Z size, thereby obtaining the parity check matrix H;
  • the base matrix of the LDPC code may be stored in a memory, and the communication device acquires an LDPC matrix corresponding to the spreading factor Z, thereby encoding/decoding the input sequence.
  • the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively, row by row or column by column.
  • the offset values of the non-zero elements in each base matrix are saved, and then the LDPC matrix is obtained according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.
  • the offset values of non-zero elements in each base matrix may also be saved as parameters of the LDPC matrix according to Table 2-10, 2-11,3-10 to 3-80.
  • Table 2-10 the “row weight” column in 2-11,3-10 to 3-80 is optional, that is, the “row weight” column can be optionally saved or not saved.
  • the parameter values in the "column of non-zero elements" in 2-11,3-10 to 3-80 may not be from small to large.
  • the parameter value in the "non-zero element offset value" in 2-11,3-10 to 3-80 are not necessarily arranged in the order of the columns, as long as “non-zero element offset”
  • the value of the parameter in the value corresponds to the parameter value in the column of "non-zero element”
  • the communication device can know that the non-zero element offset value is a non-zero element of which row corresponds to which column.
  • relevant parameters of the LDPC matrix may be saved by referring to the related description in FIG. 5.
  • FIG. 1 to FIG. 3 to FIG. 3a, 3b-1 to 3b-8, or Table 2-10, 2-11,3-10 may not be saved. All rows of the matrix shown in 3-80 can hold the parameters indicated by the corresponding rows in the table according to the rows included in the base matrix. For example, a matrix composed of rows and columns included in the base matrix of the LDPC matrix described in the above embodiments, or related parameters involved in the matrix formed by the rows and columns may be saved.
  • the base matrix includes the 0th to 4th rows and the 0th to 26th columns in any of the matrixes 30b-10 to 30b-80
  • the 0th to 4th rows and the 0th to 26th columns may be saved.
  • the matrix, and/or the related parameters of the matrix constructed by the 0th to 4th rows and the 0th to 26th columns can be referred to the parameters shown in Tables 3-10 to 3-80, and the above description.
  • the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in any of the matrixes 30b-10 to 30b-80, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, where n is an integer
  • the matrix formed by the 0th to (m-1)th rows and the 0th to (n-1)th columns may be saved, and/or the 0th to (m-1)th may be saved.
  • the relevant parameters of the matrix and the matrix formed by the 0th to (n-1)th columns reference may be made to the parameters shown in Tables 3-10 to 3-80 and the descriptions of the above sections.
  • the offset value greater than or equal to 0 indicated by the position s in at least one column of the non-zero element in any of the tables in Tables 3-10 to 3-80 may be increased or decreased. Compensation value Offset s .
  • the 22nd to 25th columns can be obtained through the input sequence and the 0th to 3rd rows and the 0th to 25th columns of the base matrix, that is, the H core-dual part.
  • Check bit then according to the input sequence and the check bit corresponding to H core-dual , the 26th column, that is, the check bit corresponding to the single column re-column; and then according to the input sequence and the check bits corresponding to the 22nd to 26th columns
  • the partial coding corresponding to the sub-matrix D obtains the parity bits corresponding to the E-part E, thereby completing the encoding.
  • the LDPC code is obtained by using the above method.
  • the communication device may perform one or more operations of performing rate matching on the LDPC code, interleaving the rate matched LDPC code according to the interleaving scheme, and modulating the interleaved LDPC code according to the modulation scheme.
  • Bit sequence X transmit bit sequence X.
  • Decoding is the inverse of encoding.
  • the base matrix used in the decoding process has the same characteristics as the base matrix used in the encoding process.
  • the communication device may perform one or more operations of: receiving a signal including LDPC-based coding, demodulating, deinterleaving, and de-rate matching the signal to obtain a soft value of the LDPC code.
  • the sequence decodes the soft value sequence of the LDPC code.
  • the preservation referred to in this application may be stored in one or more memories.
  • the one or more memories may be separate settings, or may be integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal.
  • the one or more memories may be separately provided in a part, and the part may be integrated in a decoder, a processor, a chip, a communication device, or a terminal.
  • the type of the memory may be any form of storage medium, and the present application does not limited.
  • the embodiment of the present invention further provides a corresponding communication device, the communication device comprising a corresponding module for executing each part of Fig. 5 or Fig. 6.
  • the module can be software, hardware, or a combination of software and hardware.
  • a module can include a memory, an electronic device, an electronic component, a logic circuit, etc., or any combination of the above.
  • FIG. 7 is a schematic structural diagram of a communication device 700.
  • the device 700 can be used to implement the method described in the foregoing method embodiments. For details, refer to the description in the foregoing method embodiments.
  • the communication device 700 can be a chip, a base station, a terminal, or other network device.
  • the communication device 700 includes one or more processors 701.
  • the processor 701 can be a general purpose processor or a dedicated processor or the like. For example, it can be a baseband processor, or a central processing unit.
  • the baseband processor can be used to process communication protocols and communication data
  • the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.
  • one or more of the modules of FIG. 6 may be implemented by one or more processors, or by one or more processors and memories.
  • the communication device 700 includes one or more of the processors 701, and the one or more processors 701 can implement the above-described encoding/decoding functions, for example, the communication device can be an encoder. Or decoder. In another possible design, the processor 701 can implement other functions in addition to the encoding/decoding functions.
  • the communication device 700 encodes/decodes an input sequence based on an LDPC matrix;
  • the base matrix of the LDPC matrix may be any of the base matrix in the foregoing example or may be changed in a row order with respect to any of the base matrices exemplified above, Or a column matrix in which the column order is transformed, or a matrix matrix in which both the row order and the column order are transformed, or a base matrix based on the truncation or puncturing of any of the base matrix exemplified above, or based on any of the foregoing basic matrix extensions After the matrix.
  • the base matrix of the LDPC matrix may be any of the base matrix in the foregoing example or may be changed in a row order with respect to any of the base matrices exemplified above, Or a column matrix in which the column order is transformed, or a matrix matrix in which both the row order and the column order are transformed, or a base matrix based on the truncation or puncturing of any of the
  • the processor 701 can include instructions 703 (sometimes referred to as code or programs) that can be executed on the processor such that the communication device 700 performs the above-described implementation The method described in the example.
  • communication device 700 can also include circuitry that can implement the encoding/decoding functions of the previous embodiments.
  • the communication device 700 may include one or more memories 702 on which instructions 704 are stored, the instructions being executable on the processor such that the communication device 700 performs the method described in the above method embodiments.
  • data may also be stored in the memory.
  • Instructions and/or data can also be stored in the optional processor.
  • the processor and the memory may be provided separately or integrated.
  • the “storage” described in the above embodiments may be in the storage memory 702, or may be stored in a memory or a storage device of other peripherals.
  • one or more of the stores 702 may store parameters related to the LDPC matrix enumerated above, eg, base matrix related parameters, such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, extensions The factor, the base matrix or the base matrix is extended to the matrix and so on.
  • base matrix related parameters such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, extensions
  • the factor, the base matrix or the base matrix is extended to the matrix and so on.
  • the communication device 700 may further include a transceiver 705 and an antenna 706.
  • the processor 701 may be referred to as a processing unit that controls a communication device (terminal or base station).
  • the transceiver 505 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiver function of the communication device through the antenna 506.
  • the communication device 700 may further comprise a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a device for rate matching, or for Modulation of the modulator, etc.
  • a device for generating a transport block CRC a device for code block splitting and CRC check
  • an interleaver for interleaving a device for rate matching, or for Modulation of the modulator, etc.
  • the functionality of these devices can be implemented by one or more processors 701.
  • the communication device 700 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, or a code block cascading and CRC calibration. Tested devices and so on. The functionality of these devices can be implemented by one or more processors 701.
  • FIG. 8 shows a schematic diagram of a communication system 800 that includes a communication device 80 and a communication device 81, wherein the information data is received and transmitted between the communication device 80 and the communication device 81.
  • the communication devices 80 and 81 may be the communication device 700, or the communication devices 80 and 81 respectively include a communication device 700 for receiving and/or transmitting information data.
  • communication device 80 can be a terminal, and corresponding communication device 81 can be a base station; in another example, communication device 80 is a base station and corresponding communication device 81 can be a terminal.
  • processing units for performing these techniques at a communication device may be implemented in one or more general purpose processors, digital signal processors (DSPs), digital Signal processing device (DSPD), application specific integrated circuit (ASIC), programmable logic device (PLD), field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or In any combination.
  • DSPs digital signal processors
  • DSPD digital Signal processing device
  • ASIC application specific integrated circuit
  • PLD programmable logic device
  • FPGA field programmable gate array
  • a general purpose processor may be a microprocessor.
  • the general purpose processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.
  • the steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two.
  • the memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art.
  • the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory.
  • the memory can also be integrated into the processor.
  • the processor and the memory may be disposed in an ASIC, and the ASIC may be disposed in the UE. Alternatively, the processor and memory may also be located in different components in the UE.
  • the present invention can be implemented in hardware, firmware implementation, or a combination thereof.
  • a software program it may be implemented in whole or in part in the form of a computer program product comprising one or more computer instructions.
  • the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the functions described above may also be stored in or transmitted as one or more instructions or code on a computer readable medium.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.
  • encoding/decoding refers to encoding, or decoding, or encoding and decoding.

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Abstract

本申请公开了编码方法，装置、通信设备和通信系统。该方法包括：使用低密度奇偶校验LDPC矩阵对输入比特序列进行编码；其中，所述LDPC矩阵是基于扩展因子Z和基矩阵得到的，所述基矩阵包括图3b-1至图3b-8所示矩阵之一中的第0至4行以及第0至26列，或者，所述基矩阵包括图3b-1至图3b-8所示矩阵之一中的第0至4行以及第0至26列中的部分列。本申请的编码方法、装置、通信设备和通信系统，能够满足信道编码需求。

Description

信息处理的方法、装置和通信设备 技术领域
本发明实施例涉及通信领域，尤其涉及信息处理的方法、和通信装置。
背景技术
低密度奇偶校验(low density parity check，LDPC)码是一类具有稀疏校验矩阵的线性分组编码，具有结构灵活，译码复杂度低的特点。由于它采用部分并行的迭代译码算法，从而比传统的Turbo码具有更高的吞吐率。LDPC码可用于通信系统的纠错码，从而提高信道传输的可靠性和功率利用率。LDPC码还可以广泛应用于空间通信、光纤通信、个人通信系统、ADSL和磁记录设备等。目前在第五代移动通信中已考虑采用LDPC码作为信道编码方式之一。
实际使用过程中，可以采用具有特殊结构化特征的LDPC矩阵。该具有特殊结构化特征的LDPC矩阵H可以由准循环(quasi cycle，QC)结构的LDPC基矩阵扩展得到。QC-LDPC适合并行度高的硬件，提供的吞吐率更高。可以通过对LDPC矩阵进行设计使之应用于信道编码。
QC-LDPC适合并行度高的硬件，提供的吞吐率更高。可以通过对LDPC矩阵进行设计使之应用于信道编码。
发明内容
本发明实施例提供了一种信息处理的方法、通信装置和系统，可以支持多种长度的信息比特序列的编码和译码。
第一方面，提供了一种编码方法及编码器，所述编码器使用低密度奇偶校验LDPC矩阵对输入序列进行编码。
第二方面，提供了一种译码方法及译码器，所述译码器使用低密度奇偶校验LDPC矩阵对输入序列进行译码。
在上述第一方面或第二方面的第一种实现方式中：所述LDPC矩阵是基于扩展因子Z和基矩阵得到的。
基于上述实现方式，基图30a的基矩阵可以包括矩阵30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80所示矩阵之一中的第0～4行以及第0至26列，或者，所述基矩阵包括矩阵30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80所示矩阵之一中的第0～4行以及第0至26列中的部分列，或，基矩阵可以是矩阵30b-10至30b-80所示矩阵之一中的第0～4行以及第0至26列的行/列变换后的矩阵，或，基矩阵可以是矩阵30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80所示矩阵之一中的第0至4行以及第0至26列中的部分列的行/列变换后的矩阵。
进一步，基图30a的基矩阵还可以包括矩阵30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80所示矩阵之一中的第0行至第(m-1)行，以及第0列至第(n-1)列，或，基矩阵可以是矩阵30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80 所示矩阵之一中的第0行至第(m-1)行，以及第0列至第(n-1)列的行/列变换后的矩阵，5≤m≤46,27≤n≤68。
为了支持不同块长，LDPC码需要不同的扩展因子Z，基于前述实现方式，在一种可能的实现方式中，基于不同的扩展因子Z采用与之对应的基矩阵。例如，Z＝a×2 j，0≤j＜7，a∈{2,3,5,7,9,11,13,15}。
若a＝2，基矩阵可以包括矩阵30b-10中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-10中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-10的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝3，基矩阵可以包括矩阵30b-20中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-20 1中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-20的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝5，基矩阵可以包括矩阵30b-30中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-30中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-30的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝7，基矩阵可以包括矩阵30b-40中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-40中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-40的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝9，基矩阵可以包括矩阵30b-50中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-50中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-50的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝11，基矩阵可以包括矩阵30b-60中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-60中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-60的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝13，基矩阵可以包括矩阵30b-70中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-70中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-70的第0行至第(m-1)行，以及第0列至第(n-1)列。
若a＝15，基矩阵可以包括矩阵30b-80中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-80中的第0至4行以及第0至26列中的部分列。进一步地，基矩阵还包括矩阵30b-80的第0行至第(m-1)行，以及第0列至第(n-1)列。
基矩阵可以是相应地矩阵的行/列变换后的矩阵。
进一步地，可选地，基于上述实现方式，LDPC矩阵可以基于扩展因子Z和对前述各基矩阵进行补偿后的矩阵Hs得到，或者是基于扩展因子Z和对前述各基矩阵进行补偿后的矩阵Hs的行/列变换后的矩阵得到。对前述各基矩阵补偿，可以是对其中一列或多列中大于或等于0的偏移值增加或减少补偿值。
上述各实现方式中的LDPC矩阵的基图和基矩阵可以满足多种块长的码块的性能需求。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，还包括：确定扩展因子Z。例如，根据输入序列的长度K来确定扩展因子Z的取值，可以是在支持的扩展因子集合中，找到最小的Z 0作为扩展因子Z的大小，且满足Kb·Z 0≥K。一种可能的设计中，Kb可以为LDPC码的基矩阵中信息比特的列数。例如，对于基图30a，Kb＝22。 又一种可能的设计中，Kb的取值也可以根据K的取值变化，但不超过LDPC码的基矩阵中信息比特列数。例如，K大于第一门限时，Kb＝22；K小于或者等于第一门限时，Kb＝21。或者，K大于第一门限时，Kb＝22；K小于或者等于第一门限，且K大于第二门限时，Kb＝21；K小于或者等于第二门限时，Kb＝20。
其中，扩展因子Z可以由编码器或译码器根据输入序列的长度K来确定，也可以是由其他器件确定后作为输入参数提供给编码器或译码器。
可选地，可以根据获取到的扩展因子Z和该扩展因子Z对应的基矩阵得到LDPC矩阵。
在上述第一方面或第二方面的第二种实现方式中：所述LDPC矩阵是基于扩展因子Z和LDPC矩阵的参数得到的。
LDPC矩阵的参数可以包括:行号、非零元素所在的列，非零元素偏移值，如表3-10、表3-20、表3-30、表3-40、表3-50、表3-60、表3-70以及表3-80的方式保存。还可以包括行重。其中非零元素所在的列中各位置和非零元素偏移值中各偏移值是一一对应的。
从而编码器根据扩展因子Z和LDPC矩阵的参数对输入序列进行编码。其中根据表3-10保存的参数与矩阵30b-10对应，根据表3-20保存的参数与矩阵30b-20对应，根据表3-30保存的参数与矩阵30b-30对应，根据表3-40保存的参数与矩阵30b-40对应，根据表3-50保存的参数与矩阵30b-50对应，根据表3-60保存的参数与矩阵30b-60对应，根据表3-70保存的参数与矩阵30b-70对应，根据表3-80保存的参数与矩阵30b-80对应。
对于发送端的通信设备，使用LDPC矩阵对所述输入序列进行编码可以包括：
使用扩展因子Z对应的LDPC矩阵对所述输入序列进行编码；或者扩展因子Z对应的LDPC矩阵经过了行/列变换，使用行/列变换后的矩阵对输入序列进行编码后的矩阵对所述输入序列进行编码。本申请中行/列变换是指行变换、列变换、或者行变换和列变换。
对于接收端的通信设备，使用LDPC矩阵对输入序列进行译码包括：
使用扩展因子Z对应的LDPC矩阵对输入序列进行译码；或者扩展因子Z对应的LDPC矩阵经过了行/列变换，使用行/列变换后的矩阵对输入序列进行编码后的矩阵对所述输入序列进行编码。本申请中行/列变换是指行变换、列变换、或者行变换和列变换。
在一种可能的实现方式中，可以保存LDPC矩阵，使用该LDPC矩阵对输入序列进行编码，或者基于该LDPC矩阵进行变换(行/列变换)或扩展获得可用于编码的LDPC矩阵。
在另一种可能的实现方式中，可以保存参数，依据所述参数可以获得用于编码或者译码的LDPC矩阵，从而可以基于LDPC矩阵对输入序列进行编码或者译码。所述参数包括以下至少之一：基图、基矩阵、基于基图或基矩阵行/列变换后的变换矩阵、基于基图或基矩阵的扩展矩阵、基矩阵中非零元素的偏移值、或者与获得LDPC矩阵相关的任何参数。
在又一种可能的实现方式中，LDPC矩阵的基矩阵可以保存在存储器中。
在又一种可能的实现方式中，LDPC矩阵的基图保存在存储器中，LDPC矩阵的基矩阵中非零元素的偏移值可以保存在存储器中。
在又一种可能的实现方式中，LDPC矩阵的参数按照表3-10至表23-80所示的方式保存在存储器中。
基于上述各可能的实现方式，在一种可能的设计中，用于LDPC编码或者译码的基图和基矩阵中至少一个是上述LDPC矩阵的基图和基矩阵中至少一个经过行交换、或者列交换、 或者行交换和列交换后得到的。
第三方面，提供一种通信装置可以包含用于执行上述方法设计中相对应的模块。所述模块可以是软件和/或是硬件。
在一个可能的设计中，第三方面提供的通信装置，包括处理器和收发组件，该处理器和收发组件可用于实现上述编码或者译码方法中各部分的功能。在该设计中，如果该通信装置是终端、基站或者其他网络设备，其收发组件可以是收发机，如果该通信装置是基带芯片或基带单板，其收发组件可以是基带芯片或基带单板的输入/输出电路，用于实现输入/输出信号的接收/发送。所述通信装置可选的还可以包括存储器，用于存储数据和/或指令。
在一种实现方式中，所述处理器可以包括如上述第一方面所述的编码器以及确定单元。所述确定单元用于确定对输入序列编码所需的扩展因子Z。所述编码器用于使用所述扩展因子Z对应的LDPC矩阵对所述输入序列进行编码。
在另一种实现方式中，所述处理器可以包括如上述第二方面所述的译码器以及获取单元。所述获取单元用于获取LDPC码的软值和扩展因子Z。所述译码器用于基于扩展因子Z对应的基矩阵H B对LDPC码的软值译码得到信息比特序列。
第四方面，提供了一种通信装置，包括一个或多个处理器。
在一种可能的设计中，一个或多个所述处理器可实现第一方面所述编码器的功能，在另一种可能的设计中，第一方面所述编码器可以是所述处理器的一部分，处理器除了实现第一方面所述编码器的功能，还可以实现其他功能。
在一种可能的设计中，一个或多个所述处理器可实现第二方面所述译码器的功能，在另一种可能的设计中，第二方面所述译码器可以是所述处理器的一部分。
可选地，所述通信装置还可以包括收发器以及天线。
可选的，所述通信装置还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、或者用于调制处理的调制器等。
可选的，所述通信装置还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器实现这些器件的功能。
在一种可能的设计中，可以通过一个或多个处理器实现这些器件的功能。
第五方面，本发明实施例提供了一种通信系统，该系统包括上述第三方面所述的通信装置。
第六方面，本发明实施例提供了一种通信系统，该系统包括一个或多个第四方面所述的通信装置。
再一方面，本发明实施例提供了一种计算机存储介质，其上存储有程序，当其运行时，使得计算机执行上述方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本发明实施例的信息处理的方法、装置、通信设备和通信系统，在编码性能和错误平层上能够适应系统灵活多变的码长码率需要。
附图说明
图1为一LDPC码的基图、基矩阵及其循环置换矩阵的示意图；
图2为一LDPC码的基图的结构示意图；
图3a为本发明一实施例提供的LDPC码基图的示意图；
图3b-1为本发明实施例提供的一基矩阵的示意图；
图3b-2为本发明实施例提供的另一基矩阵的示意图；
图3b-3为本发明实施例提供的另一基矩阵的示意图；
图3b-4为本发明实施例提供的另一基矩阵的示意图；
图3b-5为本发明实施例提供的另一基矩阵的示意图；
图3b-6为本发明实施例提供的另一基矩阵的示意图；
图3b-7为本发明实施例提供的另一基矩阵的示意图；
图3b-8为本发明实施例提供的另一基矩阵的示意图；
图4为本发明实施例提供的性能示意图；
图5为本发明另一实施例提供的信息处理方法的流程图；
图6为本发明另一实施例提供的信息处理方法的流程图；
图7为本发明另一实施例提供的信息处理装置的结构示意图；
图8为本发明另一实施例提供的通信系统的示意图。
具体实施方式
为便于理解下面对本申请中涉及到的一些名词做些说明。
本申请中，名词“网络”和“系统”经常交替使用，“装置”和“设备”也经常交替使用，但本领域的技术人员可以理解其含义。“通信装置”可以是芯片(如基带芯片，或者数据信号处理芯片，或者通用芯片等等)，终端，基站，或者其他网络设备。终端是一种具有通信功能的设备，可以包括具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。为描述方便，本申请中简称为终端。基站(base station，BS)，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。在不同的无线接入系统中基站的叫法可能有所不同，例如在而在通用移动通讯系统(Universal Mobile Telecommunications System，UMTS)网络中基站称为节点B(NodeB),而在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在新空口(new radio,NR)网络中的基站称为收发点(transmission reception point，TRP)或者下一代节点B(generation nodeB，gNB)，或者其他各种演进网络中的基站也可能采用其他叫法。本发明并不限于此。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
LDPC码通常可以用奇偶校验矩阵H来表示。LDPC码的奇偶校验矩阵H可以通过基图(base graph)和偏移(shift)值得到。基图通常可以包括m*n个矩阵元素(entry)，可以用m行n列的矩阵形式表示，矩阵元素的值为0或1，其中值为0的元素，有时候也称之为零元素，表示该元素可以被Z*Z的全零矩阵(zero matrix)替换，值为1的元素，有时候也称 之为非零元素，表示该元素可以被Z*Z的循环置换矩阵(circulant permutation matrix)替换。也就是说，每个矩阵元素代表的是一个全零矩阵或者一个循环置换矩阵。如图1中10a所示为一个示例性的m＝5，n＝27具有QC结构的LDPC码的基图中的各元素。需要说明的是，在本文中，基图和矩阵的行号和列号均是从0开始编号的，仅仅是为了方便说明，例如第0列表示为基图和矩阵的第一列，第1列表示为基图和矩阵的第二列、第0行表示基图和矩阵的第一行，第1行表示为基图和矩阵的第二行，以此类推。
可以理解的是，行号和列号也可以从1开始编号，则相应的行号和列号在本文所示的行号和列号基础上加1，例如，如果行号或者列号从1开始编号，则第1列表示基图和矩阵的第一列，第2列表示基图和矩阵的第二列，第1行表示表示基图和矩阵的第一行，第2行表示基图和矩阵的第二行，以此类推。
若基图中第i行第j列的元素值为1，其偏移值为P i,j，P i,j为大于或者等于0的整数，则表示第i行第j列的值为1的元素可以被P i,j对应的Z*Z的循环置换矩阵替换，该循环置换矩阵可通过将Z*Z的单位矩阵进行P i,j次向右循环移位得到。可见，将基图中每个值为0的元素用Z*Z的全零矩阵替换，每个值为1的元素采用其偏移值对应的Z*Z的循环置换矩阵进行替换，则可以得到LDPC码的奇偶校验矩阵。Z为正整数，也可以称之为扩展(lifting)因子，可以根据系统支持的码块大小和信息数据的大小确定的。可见奇偶校验矩阵H的大小为(m*Z)*(n*Z)。例如，扩展因子Z＝4，则每个零元素被一个4*4大小的全0矩阵11a替换，若P 2,3＝2，则第2行第3列的非0元素被4*4的循环置换矩阵11d替换，该矩阵是由4*4的单位矩阵11b经过2次向右循环移位得到的，若P 2,4＝0，则第2行第4列的非0元素被单位矩阵11b替换。需要说明的是，此处仅仅只是举例说明，并不以此为限制。
由于P i,j可以是基于扩展因子Z得到的，对于同一个位置上值为1的元素，采用不同的扩展因子Z可能存在不同的P i,j。为了简化实现，通常系统也会定义一个m行n列的基矩阵(base matrix)，有时候也称之为PCM(parity check matrix)。在基矩阵中每个元素和基图中每个元素的位置一一对应，基图中的零元素在基矩阵中位置不变，可以采用-1或者空值“null”表示，基图中第i行第j列值为1的非零元素在基矩阵中位置不变，可表示为P i,j，P i,j可以是相对于一个预定或者特定的扩展因子Z定义的偏移值。在本申请实施例中，有时也将基矩阵称为基图矩阵的偏移矩阵。
如图1中10b所示为基图10a对应的一个基矩阵。
通常LDPC码的基图或基矩阵中还可以包括p列内置打孔(built-in puncture)比特列，p可以为0～2的整数，这些列参与编码，但是其编码对应的系统比特不被发送，则LDPC码基矩阵的码率满足R＝(n-m)/(n-p)。以基图10a为例，如果有2列内置打孔比特列，则码率为(27-5)/(27-2)＝0.88，近似于8/9。
无线通信系统中采用的LDPC码为QC-LDPC码，其校验位部分具有双对角结构或者raptor-like结构，可以简化编码，支持增量冗余混合重传。QC-LDPC码的译码器中中通常采用QC-LDPC移位网络(QC-LDPC shift network，QSN)，Banyan网络或者Benes网络实现信息的循环移位。
具有raptor-like结构的QC-LDPC码的，其基图的矩阵大小为m行n列，可以包括5个子矩阵A、B、C、D和E，其中，矩阵的权重是由非零元素的个数决定的，行的权重(行重)是指一行中包括的非零元素的个数，列的权重(列重)是指一列中包括的非零元素的个数。如图2中200所示，其中：
子矩阵A为m A行n A列的矩阵，其大小可以为m A*n A，其中每列对应LDPC码中的Z个系统比特，系统比特有时候也称为信息比特。
子矩阵B为为m A行m A列的方阵，其大小可以为m A*m A，每列对应于LDPC码中的Z个校验比特。子矩阵B包括双对角结构的子矩阵B’和一列权重为3的矩阵列(简称为3列重列)，其中列重为3的矩阵列可以位于子矩阵B’之前，如图2中20a所示；子矩阵B还可以包括一列或多列列重为1的矩阵列(简称为单列重列)，例如，一种可能的实现方式如图2中20b或20c所示。
通常基于子矩阵A和B生成的矩阵可以称为核心矩阵，可以用来支持高码率的编码。
子矩阵C为全零矩阵，其大小为m A×m D。
子矩阵E为单位矩阵，其大小为m D×m D。
子矩阵D大小为m D×(n A+m A)，通常可用来生成低码率的校验位。
由于子矩阵C和E的结构相对确定，子矩阵A、B和D两部分的结构是LDPC码的编译码性能的影响因素之一。
采用raptor-like结构的LDPC矩阵进行编码时，一种可能的实现方式为，可以先对子矩阵A和B部分的矩阵，也就是核心矩阵进行编码，得到子矩阵B对应的校验比特，再对整个矩阵进行编码，得到子矩阵E部分对应的校验比特。由于子矩阵B可以包括双对角结构的子矩阵B’和一单列重列，在编码中可以先获得双对角结构对应的校验比特，再获得单列重列对应的校验比特。
下面给出一种编码的示例方式。假设子矩阵A和B构成的核心矩阵部分为H core，H core中去掉最后一行和最后一列，也就是去掉单列重列以及该列非零元素所在的行，得到的矩阵部分为H core-dual，H core-dual中的校验位部分表示为H e＝[H e1H e2],H e1为3列重列，H e2为双对角结构。根据LDPC码矩阵定义，H core-dual·[S P e] T＝0，其中，S为输入序列，由信息比特构成的向量表示，P e为校验比特构成的向量，[S P e] T表示由输入序列S和P e构成的矩阵转置。因此可以先根据输入序列S和H core-dual计算出H core-dual对应的校验比特，输入序列S中包括所有信息比特；再根据得到H core-dual对应的校验比特和输入序列S计算得到子矩阵B中单列重列对应的校验比特，此时可以得到子矩阵B对应的所有校验比特；再根据输入序列S以及子矩阵B对应的校验比特，利用子矩阵D部分编码得到子矩阵E对应的校验比特，从而得到所有信息比特和所有校验比特，这些比特构成编码后的序列，也就是一个LDPC码序列。
可选地，LDPC码编码还可能包含截短(shortening)和打孔(puncturing)操作。被截短的比特和被打孔的比特均不发送。
其中，截短一般是从信息比特的最后一位开始向前截短，可以采用不同的方式进行截短。例如，被截短的比特数s 0，可以将输入序列S中最后s 0个比特设置为已知比特得到输入序列S’，如设置为0或者null，或者其他一些值，然后通过LDPC矩阵对输入序列S’进行编码，又例如，也可以可以将输入序列S中最后(s 0mod Z)个比特设置为已知比特得到输入序列S’， 如设置为0或者null，或者其他一些值，将子矩阵A中最后
Figure PCTCN2018092974-appb-000001
列删除得到LDPC矩阵H’，使用LDPC矩阵H‘对输入序列S’进行编码，或者子矩阵A中最后
Figure PCTCN2018092974-appb-000002
列不参与对输入序列S’的编码。在完成编码后，被截短的比特不发送。
其中，打孔可以是对输入序列中内置打孔比特，或者校验比特进行打孔。对校验比特打孔时通常也是从校验比特的最后一位进行打孔的，当然，也可以按照系统预设的打孔顺序进行打孔。一种可能的实现方式为，先对输入序列进行编码，然后根据需要被打孔的比特数p，选择校验比特中最后p个比特或者根据系统预设的打孔顺序选择p个比特，这p个比特不发送。又一种可能的实现方式中，也可以确定出被打孔比特对应的矩阵的p列以及这些列中非零元素所在的p行，这些行、列不参与编码，也就不产生相应的校验比特。
需要说明的是，这里对编码方式只是举例，基于本申请提供基图和/或基矩阵还可以采用本领域技术人员所知的其他编码方式，本申请并不限定。本申请中涉及的译码，可以是采用多种编码方式，例如可以采用，min-sum(MS)译码方式，也可以采用belief propagation译码方式。MS译码方法有时也称为Flood MS译码方法。例如，对输入序列初始化，并进行迭代处理，在迭代后进行硬判决检测，并对硬判决结果进行校验，如果译码结果符合校验方程，则译码成功，终止迭代，并输出判决结果。如果不符合校验方程，则在最大迭代次数内再次进行迭代处理，若达到最大迭代次数，仍校验失败，则译码失败。可以理解的是，本领域的技术人员可以理解MS译码的原理，在此不再详述。
需要说明的是，对于译码方式只是举例说明，对于基于本申请提供基图和/或基矩阵还可以采用本领域技术人员所知的其他译码方式，本申请对译码方式并不限定。
通常可以通过对基图或者基矩阵的设计来获得LDPC码。例如，可以对基图或者基矩阵采用密度进化的方法可以确定出LDPC码的性能上限，并且根据基矩阵中的偏移值确定出LDPC码的错误平层。通过对基图或者基矩阵的设计，可以改善编码或者译码性能，以及降低错误平层。无线通信系统中码长灵活多变，例如，可以是2560比特，38400比特等，图3a为一个LDPC码的基图30a示例，图3b-1至图3b-8是基图30a的各基矩阵示例，可满足多种块长的性能需求。为方便说明及理解，附图中3a和3b-1至3b-8中在最上侧以及最左侧，分别示出了列号和行号。
图3a所示为一个LDPC码的基图30a示例，其中，图中最上面一行0至67(即0至67列)表示列编号，最左面一列0～45(即0至45行)表示行编号，也就是基图30a的矩阵大小为46行68列。
在一种实现方式中，子矩阵A和子矩阵B的部分可以看做LDPC码的基图的核心矩阵部分，可用于高码率编码。构成了一个5行27列的矩阵，如基图10a所示的5行27列的矩阵可以作为基图的核心矩阵部分。
在一种实现方式中，子矩阵A中可以包括一列或多列内置打孔比特列，例如：可以包括2列内置打孔比特列，则打孔后，核心矩阵可以支持的码率为0.88。
其中，子矩阵B中可以包括1列3列重列，即子矩阵B的第0列(核心矩阵的第22列)列重为3，子矩阵B的第1至3列(核心矩阵的第23至25列)，第0至3行为双对角结构，子矩阵B还包括1列单列重的列(核心矩阵的第26列)。
在一种实现方式中，子矩阵A可以对应系统比特，有时也称为信息比特，其大小为m A行22列，其中，m A＝5，在基图30a中由第0行至第4行以及第0列至第21列的元素构成；
在一种实现方式中，子矩阵B可以对应校验比特，其大小为m A行m A列，在基图30a中由第0行至第4行以及第22列至第26列的元素构成。
为了获得灵活的码率，可以基于核心矩阵添加相应大小的子矩阵C、子矩阵D和子矩阵E，来获得不同的码率。由于子矩阵C为全零矩阵，子矩阵为单位矩阵，其大小主要是根据码率来确定，结构相对固定。影响到编译码性能的主要在于核心矩阵和子矩阵D部分。在核心矩阵的基础上添加行列，形成相应的C、D和E部分可以得到不同码率。
子矩阵D的列数m D为子矩阵A和B的列数之和，其行数主要与码率相关。以基图30a为例，子矩阵D的列数为27列。若LDPC码支持的码率为R m，则其基图或者基矩阵的大小为m行n列，其中，n＝n A/R m+p，m＝n-n A＝n A/R m+p-n A。若最低码率R m＝1/3，内置打孔列数p＝2，以基图30a为例，则n＝68，m＝46，子矩阵D的行数m D最大可以为m-m A＝46-5＝41，从而0≤m D≤41。
以基图30a为例，其中子矩阵D可以包括基图30a中第5行至第41行中的m D行。
在本申请中，若基图中相邻两行的同一列最多只有1个非零元素，则这两行彼此正交。若基图中相邻两行除了部分列以外的其他列中，同一列最多只有1个非零元素，则该相邻两行是准正交的。例如，对于相邻两行，除了内置打孔比特列以外的其他列只有一个非零元素，则可以认为该相邻两行是准正交的。
基图30a中第5行至第41行可以包括多行准正交结构和至少两行正交结构。例如，基图30a中第5行至第41行至少包括15行符合准正交结构的行，这15行中任意相邻2行中除了内置打孔比特列以外的其余列中，同一列中最多只有一个非零元素。基图30a中第5行至第41行还可以包括10至26行符合正交结构的行，也就是这些行中，任意相邻2行中同一列最多只有一个非零元素，也就是内置打孔比特列中也最多只有一个非零元素。
若m D＝15，LDPC码基图中子矩阵D大小为15行27列，可以是由基图30a的第5行至第19行，第0列至第26列的矩阵构成，对应LDPC码支持的码率为22/40＝0.55，也就是在该码率下，LDPC码的基图对应于基图30a的第0行至第19行，第0列至第41列构成的矩阵部分，其中子矩阵E为15行15列的单位矩阵，子矩阵C为5行15列的全0矩阵；
若m D＝19，LDPC码基图中子矩阵D大小为19行27列，可以是由基图30a的第5行至第23行，第0列至第26列的矩阵构成，对应LDPC码支持的码率为22/44＝1/2，也就是在该码率下，LDPC码的基图对应于基图30a的第0行至第23行，第0列至第45列构成的矩阵部分，其中子矩阵E为19行19列的单位矩阵，子矩阵C为5行19列的全0矩阵。
以此类推，不一一阐述。
在一种设计中，可以对基图和/或基矩阵做行/列交换，也就是说，进行行交换，或者列交换，或者行交换和列交换。所述行/列交换操作，并不改变行重和列重，非零元素的个数也没有发生改变。因此，行/列交换后的基图和/或基矩阵对系统性能影响有限。也就是说从整体讲，对系统性能的影响可接受，在容忍范围内，例如，可能对某些场景或者在某些范围内，性能在允许范围内下降，但是在某些场景或者某些范围内，性能有所改善，整体上看对性能影响不大。
例如，可将基图30a的第34行和第36行进行交换，并且将第44列和第45列进行交换。又例如，子矩阵D包括矩阵F中m D行，这m D行可以不进行行交换，也可以将其中一行或多行之间进行行交换，子矩阵E仍为对角结构，不做行、列交换，例如，将矩阵F的第27行和第29行进行行交换，子矩阵D包括矩阵F中m D行，子矩阵E仍为对角结构。可以理解的是，若基图或基矩阵包括子矩阵D，那么对核心矩阵的列进行交换时，相应的子矩阵D中列也需要进行交换。
如图3b-1至图3b-8所示矩阵30b-10至30b-80分别为基图30a的多个基矩阵的设计。其中，基图30a中第i行第j列的非零元素在矩阵30b-10至30b-80各矩阵中的位置不变，值为偏移值V i,j，零元素在偏移矩阵中以-1或者null表示。其中，子矩阵D在基矩阵中相应的部分可以包括其中任一基矩阵的第5行至第45行中的m D行，可以根据码率的不同选择m D的值。可以理解的是，如果基图是相对于基图30a进行过行/列变换后的矩阵，则基矩阵也是相应地矩阵30b-10至30b-80中任一个经过行/列变换后的矩阵。
在一种可能的设计中，LDPC码的基矩阵可以包括图3b-1至图3b-8所示的任一矩阵30b-10至30b-80的第0至4行以及第0至26列，此时，图3b-1至图3b-8所示矩阵的第0至4行以及第0至26列构成的矩阵可以作为基矩阵的核心部分。在本设计中，对于LDPC码的基矩阵的其他部分，例如矩阵C,D,E部分的结构并不限定，例如可以采用图3b-1至图3b-8所示的任一种结构，也可以采用其他的矩阵设计。
在另一种可能的设计中，LDPC码的基矩阵可以包括：图3b-1至图3b-8所示的任一矩阵30b-10至30b-80中的第0至(m-1)行以及第0至(n-1)列构成的矩阵，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
在本设计中，对于LDPC码的基矩阵的其他部分的结构并不限定，例如可以采用图3b-1至图3b-8所示的任一种结构，也可以采用其他的矩阵设计。
在又一种可能的设计中，LDPC码的基矩阵可以包括：图3b-1至图3b-8所示的任一矩阵30b-10至30b-80的第0至4行以及第0至26列中的部分列。例如，可以对图3b-1至图3b-8所示矩阵的核心部分(第0至4行以及第0至26列)截短(shortening)和/或打孔(puncturing)。在一种实现方式中，LDPC码的基矩阵可以不包括被截短和/或打孔的比特对应的列。
在本设计中，对于LDPC码的基矩阵的其他部分并不限定，例如可以参照图3b-1至图3b-8所示的结构，也可以采用其他的结构。
在又一种可能的设计中，LDPC码的基矩阵可以包括：图3b-1至图3b-8所示的任一矩阵30b-10至30b-80中的第0至(m-1)行以及第0至(n-1)列中的部分列构成的矩阵，其中5≤m≤46,m为整数，27≤n≤68,n为整数。例如，可以对图3b-1至图3b-8所示的任一矩阵30b-10至30b-80中的第0至(m-1)行以及第0至(n-1)列截短(shortening)和/或打孔(puncturing)。在一种实现方式中，LDPC码的基矩阵可以不包括被截短和/或打孔的比特对应的列。在本设计中，对于LDPC码的基矩阵的其他部分并不限定，例如可以参照图3b-1至图3b-8所示的结构，也可以采用其他的结构。
在一种实现方式中，所述截短操作，可以是对信息比特截短。例如，以图3b-1至图3b-8所示的任一矩阵为例，对0至21列中的1列或者多列截短，那么LDPC码的基矩阵可以不包括图3b-1至图3b-8所示矩阵中被截短的1列或者多列。比如，若第21列被截短，那么LDPC 码的基矩阵可以包括：30b-10至30b-80任一矩阵的第0至20列和第22至26列。对于第0至4行，以及第0至20列和第22至26列来讲，这时码率为7/8。
在另一种实现方式中，所述打孔可以是对校验比特打孔。例如，以图3b-1至图3b-8所示的任一矩阵为例，对第22至第26列中的1列或者多列打孔。那么LDPC码的基矩阵可以不包括图3b-1至图3b-8所示矩阵中被打孔的1列或者多列。比如，若第26列被打孔，那么LDPC码的基矩阵可以包括：30b-10至30b-80任一矩阵的第0至25列。
为LDPC码设计了不同的扩展因子Z，以支持不同的长度的信息比特序列。在一种可能的设计中，可以对不同扩展因子使用不同的基矩阵取得较好的性能。例如，扩展因子Z＝a×2 j，0≤j＜7，a∈{2,3,5,7,9,11,13,15}。表一为一种可能支持的扩展因子集合{2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}，其中除了最上面一行和最左面一列以外，每一格表示相应地a和j的取值对应的Z的值，例如，a＝2这一列，且j＝1这一行，Z＝4，又例如，a＝11且j＝3，Z＝88。以此类推，不再赘述。
表1
Z a＝2 a＝3 a＝5 a＝7 a＝9 a＝11 a＝13 a＝15
j＝0 2 3 5 7 9 11 13 15
j＝1 4 6 10 14 18 22 26 30
j＝2 8 12 20 28 36 44 52 60
j＝3 16 24 40 56 72 88 104 120
j＝4 32 48 80 112 144 176 208 240
j＝5 64 96 160 224 288 352    
j＝6 128 192 320          
j＝7 256 384            
由于基图支持的扩展因子集合可以是表1中的所有扩展因子，也可以是一部分扩展因子，例如，可以为{24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}，也就是Z大于或者等于24。又例如，可以为{2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22}中的一个或多个与{24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}的并集。需要说明的是此处仅为举例。可以根据a的取值将基图支持的扩展因子集合划分成不同的子集。例如，a＝2，扩展因子Z的子集可以包括{2,4,8,16,32,64,128,256}中的一个或多个，又例如，a＝3，扩展因子Z的子集可以包括{3,6,12,24,48,96,192,384}中的一个或多个，以此类推。
可以对基图支持的扩展因子集合根据a的不同取值划分，从而确定出相应的基矩阵：
若a＝2，或者扩展因子Z取值为{2,4,8,16,32,64,128,256}中的一个时，基矩阵可以包括矩阵30b-10中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-10中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-10的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。。
若a＝3，或者扩展因子Z取值为{3,6,12,24,48,96,192,384}中的一个时，基矩阵可以包括矩阵30b-20中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-20中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-20的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。。
若a＝5，或者扩展因子Z取值为{5,10,20,40,80,160,320}中的一个时，基矩阵可以包括矩阵30b-30中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-30中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-30的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
若a＝7，或者扩展因子Z取值为{7,14,28,56,112,224}中的一个时，基矩阵可以包括矩阵30b-40中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-40中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-40的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
若a＝9，或者扩展因子Z取值为{9,18,36,72,144,288}中的一个时，基矩阵可以包括矩阵30b-50中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-50中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-50的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
若a＝11，或者扩展因子Z取值为{11,22,44,88,176,352}中的一个时，基矩阵可以包括矩阵30b-60中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-60中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-60的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
若a＝13，或者扩展因子Z取值为{13,26,52,104,208}中的一个时，基矩阵可以包括矩阵30b-70中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-70中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-70的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
若a＝15，或者扩展因子Z取值为{15,30,60,120,240}中的一个时，基矩阵可以包括矩阵30b-80中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-80中的第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数；或者，基矩阵包括矩阵30b-80的第0至(m-1)行以及第0至(n-1)列中的部分列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。
可选地，对于一个LDPC码给定的基矩阵而言，可以对矩阵中一列或者多列非零元素的偏移值增加或减少补偿值Offset s，而对系统性能影响不大。不同列中非零元素的补偿值可以相同也可以不同，例如，对矩阵的一列或多列进行补偿，不同列的补偿值可以相同，也可以不同，本申请并不限定。
对系统性能影响不大是指对系统性能的影响可接受，在容忍范围内。例如，可能对某些场景或者在某些范围内，性能在允许范围内下降，但是在某些场景或者某些范围内，性能有所改善，整体上看对性能影响不大。
例如对矩阵30b-10至30b-80中任一矩阵中第s列中大于或等于0的各偏移值分别增加或减少补偿值Offset s可以得到该矩阵的补偿矩阵Hs，其中Offset s为大于或等于0的整数，0≤s＜23。一列或多列的补偿值Offsets可以相同，也可以不同。
图4所示的性能图中，为基于矩阵30b-10至30b-80编码的LDPC码在AWGN信道，QPSK调制，50次迭代的译码性能曲线。横坐标表示信息比特序列的长度，单位为比特，纵坐标是达到对应BLER＝0.01需要的符号信噪比(Es/N0)，其中120≤K≤8192,码率分别为1/3,2/5,1/2,2/3,3/4,5/6,8/9。各曲线平滑，说明矩阵在不同块长上都具有较优的性能。
附图1至图3a、图3b-1至图3b-8对LDPC码涉及的基图以及基矩阵的结构进行了展示。为了充分说明本发明实施方式中对于基图和/或基矩阵的设计，可以通过下表2-10至表2-11进一步说明。
在一种设计中，图1中的10a所述基图为5行27列的而矩阵，其涉及的参数可以用表2-10来表示。
表2-10
Figure PCTCN2018092974-appb-000003
在一种设计中，图1中10b所示基矩阵的尺寸为5行27列的矩阵，其涉及的参数可以用表2-11来表示。
表2-11
Figure PCTCN2018092974-appb-000005
在一种设计中，图3b-1中的矩阵30b-10，可以用表3-10来表示。
表3-10
Figure PCTCN2018092974-appb-000006
Figure PCTCN2018092974-appb-000007
在一种设计中，图3b-2中的矩阵30b-20，可以用表3-20来表示。
表3-20
Figure PCTCN2018092974-appb-000008
Figure PCTCN2018092974-appb-000009
Figure PCTCN2018092974-appb-000010
在一种设计中，图3b-3中的矩阵30b-30，可以用表3-30来表示。
表3-30
Figure PCTCN2018092974-appb-000011
Figure PCTCN2018092974-appb-000012
在一种设计中，图3b-4中的矩阵30b-40，可以用表3-40来表示。
表3-40
Figure PCTCN2018092974-appb-000013
Figure PCTCN2018092974-appb-000014
在一种设计中，图3b-5中的矩阵30b-50，可以用表3-50来表示。
表3-50
Figure PCTCN2018092974-appb-000015
Figure PCTCN2018092974-appb-000016
Figure PCTCN2018092974-appb-000017
在一种设计中，图3b-6中的矩阵30b-60，可以用表3-60来表示。
表3-60
Figure PCTCN2018092974-appb-000018
Figure PCTCN2018092974-appb-000019
在一种设计中，图3b-7中的矩阵30b-70，可以用表3-70来表示。
表3-70
Figure PCTCN2018092974-appb-000020
Figure PCTCN2018092974-appb-000021
Figure PCTCN2018092974-appb-000022
在一种设计中，图3b-8中的矩阵30b-80，可以用表3-80来表示。
表3-80
Figure PCTCN2018092974-appb-000023
Figure PCTCN2018092974-appb-000024
可以理解，上述图1至图3a、图3b-1至图3b-8以及表2-10,表2-11，表3-10至3-80是为了帮助理解对于基图和矩阵的设计，其表现形式并不仅仅局限于图1至图3a、图3b-1至图3b-8或者上述表2-10,表2-11，表3-10至3-80的表现形式。还可以包括其他可能的变形。
在一种实现方式中，上述表2-10,表2-11，表3-10至3-80中的“行重”这一参数也可以省略。可以通过一行非零元素所在的列，获知这一行有多少个非零元素，因此行重也就获知了。
在一种实现方式中，对于上述表2-10,表2-11，表3-10至3-80中的“非零元素所在的列”中的参数值，也可以不按照由小到大的顺序排列，只要参数值索引到非零元素所在的列就行。此外，对于表2-10,表2-11，表3-10至3-80的“非零元素偏移值”中的参数值，也不一定按照列的顺序排列，只要“非零元素偏移值”中的参数值，与“非零元素所在的列”中的参数值一一对应就可以。
图5给出了处理数据过程的设计。处理数据的过程可以通信装置来实现，所述通信装置 可以是基站、终端或者其他实体等，例如通信芯片，编码器/译码器等等。
501部分，获取输入序列。
在一种实现方式中，编码的输入序列可以是信息比特序列。信息比特序列有时也称为码块(code block)，例如，可以是对传输块进行码块划分后的输出序列。在一种实现方式中，译码的输入序列可以是LDPC码的软值序列。
502部分，基于LDPC矩阵对所述输入序列进行编码/译码；该LDPC矩阵的基矩阵可以为前述示例中的任一基矩阵。
在一种实现方式中，LDPC矩阵可以是基于扩展因子Z和基矩阵得到的。
在一种实现方式中，可以保存LDPC矩阵的相关参数，这些参数包括以下一个或多个：
a)用于获得上述各实现方式中列举的任一基矩阵中的参数，基于所述参数可以获得所述基矩阵；例如，所述参数可以包括以下一个或多个：行号、行重、非零元素的位置、基矩阵中的偏移值，非零元素偏移值及对应的位置，补偿值，扩展因子，基图，码率等。
b)上述各实现方式中列举的任一基矩阵；
c)上述各实现方式中列举的任一基矩阵经过至少一列补偿后的补偿矩阵Hs；
d)基于所述基矩阵或其补偿矩阵Hs扩展后的矩阵；
e)基于上述各实现方式中列举的任一基矩阵或者补偿矩阵Hs经过行/列变换后的基矩阵。
f)基于所述行/列变换后的基矩阵或者补偿矩阵Hs扩展后的矩阵。
g)基于上述各实现方式中列举的任一基矩阵或者补偿矩阵Hs的进行截短或者打孔后的矩阵。
在一种可能的实现方式中，基于低密度奇偶校验LDPC矩阵对输入序列进行编码/译码，可以是在编码/译码过程中，按照以下方式的一种或者多种进行：
i.基于上述a)获得基矩阵，基于获得的基矩阵编码/译码；或者基于获得的基矩阵进行行/列交换，基于行/列变换后的基矩阵编码/译码，或者基于获得的基矩阵的补偿矩阵进行编码/译码，或者基于获得的基矩阵的补偿矩阵Hs进性行/列变换后的矩阵进行编码/译码。这里基于基矩阵或者补偿矩阵Hs编码/译码，可选的，还可以包括基于基矩阵的扩展矩阵或者补偿矩阵Hs的扩展矩阵编码/译码，或者基于基矩阵或者补偿矩阵进行截短或者打孔后的矩阵编码/译码；
ii.基于b)、c)d)或者e)保存的基矩阵(保存基矩阵H或者Hs、或者保存的基于基矩阵H或者Hs行/列变换后的基矩阵)编码/译码，或者基于所述保存的基矩阵进行行/列变换，基于行/列变换后的基矩阵编码/译码。这里，基于基矩阵或者补偿矩阵Hs编码/译码，可选的，还可以包括基于基矩阵的扩展矩阵或者补偿矩阵Hs的扩展矩阵编码/译码,或者基于基矩阵或者补偿矩阵进行截短或者打孔后的矩阵编码/译码；
iii.基于d),f)或者g)进行编码/译码。
503部分，输出编码/译码后的比特序列。
图6给出了获得处理数据过程的一种设计，其可用于附图5中的502部分。
601部分，获取扩展因子Z。
一种实现方式中，扩展因子Z可以根据输入序列的长度K确定。例如，可以是在支持的扩展因子集合中，找到最小的Z 0作为扩展因子Z的大小，且满足Kb·Z 0≥K。一种可能的设 计中，Kb可以为LDPC码的基矩阵中信息比特的列数。对于基图30a，其中信息比特的列数Kb max＝22，假设基图30a支持的扩展因子集合为{24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}。
若输入序列的长度K＝529比特，则Z为26，若输入序列的长度K＝5000比特，则Z为240。需要说明的是，此处仅为举例，并不以此为限制。
又例如，Kb的取值也可以根据K的取值变化，但不超过LDPC码的基矩阵中信息比特列数。如，K大于第一门限时，Kb＝22；K小于或者等于第一门限时，Kb＝21。或者，K大于第一门限时，Kb＝22；K小于或者等于第一门限，且K大于第二门限时，Kb＝21；K小于或者等于第二门限时，Kb＝20。需要说明的是，此处仅为举例说明，并不以此为限制。
此外，基于上述任一实现方式的基础上，还可以对特定的信息长度K，例如，对于104≤K≤512，Z可以根据系统定义的规则选取，K为其他长度仍根据上述任一实现方式选取，如，满足Kb·Z 0≥K的最小的Z 0，其中Kb取值为22或者是根据门限值确定。
一种设计中，104≤K≤512时，Z的选取如表4-1所示，其他长度根据上述任一实现方式选取：
表4-1
K的取值范围 扩展因子Z
104-119 6
120-127 8
128-135 6
136-183 8
184-199 10
200-271 12
272-279 16
280-287 13
288-303 16
304-311 18
312-327 16
328-335 20
336-375 18
376-383 20
384-399 18
400-415 20
416-431 22
432-447 20
448-463 22
464-479 24
480-487 28
488-503 26
504-511 24
其中，扩展因子Z可以由通信装置根据输入序列的长度K来确定，也可以是由通信装置从其他实体(如处理器)获得。
602部分，基于扩展因子和基矩阵获得LDPC矩阵。
基矩阵是前述各实施方式中例举的任一基矩阵，或者，相对于前述例举的任一基矩阵中至少一列进行补偿得到的补偿矩阵，或者相对于前述例举的任一基矩阵或补偿矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵，其基图至少包括子矩阵A和子矩阵B。可选的还可以包括子矩阵C、子矩阵D和子矩阵E，各部分可以参考前述各实施例中的描述，此处不再赘述。
在一种可能的实现方式中，根据扩展因子Z确定对应的基矩阵，并且根据扩展因子Z对该基矩阵进行置换得到LDPC矩阵。
在一种实现方式中，可以存储扩展因子与基矩阵的对应关系，601部分获得的扩展因子Z，确定对应的基矩阵。
例如，Z为26，a＝13，基矩阵可以包括矩阵30b-7中的第0至4行以及第0至26列，或者，基矩阵包括矩阵30b-7中的第0至4行以及第0至26列中的部分列，；进一步地，或者基矩阵还包括矩阵0至m-1行以及第0至n-1列，其中5≤m≤46,m为整数，27≤n≤68,n为整数，或者，基矩阵包括矩阵30b-7的第0至m-1行以及第0至n-1列，其中5≤m≤46,m为整数，27≤n≤68,n为整数。根据扩展因子Z对该基矩阵进行置换得到LDPC矩阵。
需要说明的是，这里仅仅是以Z＝26,a＝13,图3b-7所示的矩阵为例说明。此处仅为举例，本发明不限于此。可以理解，扩展因子不同，则基矩阵也有所不同。
一种可能的实现方式中，扩展因子与基矩阵的对应关系可以如表5所示，根据表5确定扩展因子对应的基矩阵索引。一种可能的设计，PCM1可以是如图3b-1所示的矩阵30b-10；PCM2可以是如图3b-2所示的矩阵30b-20；PCM3可以是如图3b-3所示的矩阵30b-30；PCM4可以是如图3b-4所示的矩阵30b-40；PCM5可以是如图3b-5所示的矩阵30b-50；PCM6可以是如图3b-6所示的矩阵30b-60；PCM7可以是如图3b-7所示的矩阵30b-70；PCM8可以是如图3b-8所示的矩阵30b-80。此处仅为举例，并不以此为限制。
表5
Figure PCTCN2018092974-appb-000025
Figure PCTCN2018092974-appb-000026
进一步地，在一种可能的设计中，对于扩展因子Z，其基矩阵中第i行第j列元素P i,j可以满足下述关系：
Figure PCTCN2018092974-appb-000027
其中，V i,j可以是扩展因子Z所在集合的基矩阵中第i行第j列的元素的偏移值，或者是扩展因子Z所在集合中最大扩展因子的基矩阵的第i行第j列的非零元素的偏移值。
例如，以Z为13为例，其基矩阵中第i行第j列的元素P i,j满足
Figure PCTCN2018092974-appb-000028
其中，V i,j是PCM7，矩阵30b-70中第i行第j列的非零元素的偏移值。对于Z＝13而言，需要将矩阵30b-70中第i行第j列的非零元素的偏移值V i,j对Z＝13取模。
需要说明的是，此处仅为举例，本发明不限于此。
603部分，基于LDPC矩阵对输入序列进行编码/译码。
在一种实现方式中，编码的输入序列可以是信息比特序列。在又一种实现方式中，译码的输入序列可以是LDPC码的软值序列，可以参照图5中的相关描述。
对输入序列进行编码/译码时，可以根据Z对基矩阵进行扩展得到的LDPC矩阵H。对基矩阵中每一非零元素P i,j，确定Z*Z大小的循环置换矩阵h i,j，其中h i,j为单位矩阵经过P i,j次循环移位得到的循环置换矩阵，将h i,j替换非零元素P i,j，将Z*Z大小的全零矩阵替换基矩阵H B中的零元素，从而得到奇偶校验矩阵H；
在一种可能的实现方式中，LDPC码的基矩阵可以是保存在存储器中，通信装置获取扩展因子Z对应的LDPC矩阵，从而对输入序列进行编码/译码。
在一种可能的实现方式中，由于LDPC码的基矩阵有多个，按照矩阵结构保存会占用较大的存储空间，也可以将LDPC码的基图保存在存储器中，分别逐行或者逐列保存各基矩阵中非零元素的偏移值，然后根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。
在一种可能的实现方式中，也可以按照表2-10,2-11,3-10至3-80的方式保存各基矩阵中非零元素的偏移值，作为LDPC矩阵的参数，其中表2-10,2-11,3-10至3-80中“行重”一列可选，也就是“行重”这列可以可选的保存或者不保存。通过一行非零元素所在的列，获知这一行有多少个非零元素，因此行重也就获知了。在一种可能的实现方式中，对于上述表2-10,2-11,3-10至3-80中的“非零元素所在的列”中的参数值，也可以不按照由小到大的顺序排列，只要参数值索引到非零元素所在的列就行。此外，对于表2-10,2-11,3-10至3-80中的“非零元素偏移值”中的参数值，也不一定按照列的顺序排列，只要“非零元素偏移值”中的参数值，与“非零元素所在的列”中的参数值一一对应，通信装置可获知非零元素偏移值是对应哪行哪一列的非零元素就性。例如：
在一种可能的实现方式中，可以参照图5中的相关描述，对LDPC矩阵的相关参数保存。
在一种可能的实现方式中，保存LDPC矩阵的相关的参数时，也可以不保存图1至图3a,3b-1至3b-8，或者表2-10,2-11,3-10至3-80中所示矩阵的所有行，可以根据基矩阵中包括的行保存表格中相应的行所指示的参数。例如，可以保存上述实施例中所描述的LDPC矩阵的基矩阵所包括的行和列所构成的矩阵，或者所述行和列所构成的矩阵所涉及的相关参数。
例如，如果基矩阵包括30b-10至30b-80任一矩阵中的第0至4行以及第0至26列，则，可以保存所述第0至4行以及第0至26列所构成的矩阵，和/或保存第0至4行以及第0至26列所构成的矩阵的相关参数，可以参照表3-10至3-80中所示的参数，以及上述部分描述。
如果基矩阵包括30b-10至30b-80任一矩阵中第0至(m-1)行以及第0至(n-1)列，其中5≤m≤46,m为整数，27≤n≤68,n为整数，则，可以保存所述第0至(m-1)行以及第0至(n-1)列所构成的矩阵，和/或者保存所述第0至(m-1)行以及第0至(n-1)列所构成的矩阵的相关参数，可以参照表3-10至3-80中所示的参数以及上述部分的描述。
在一种可能的实现方式中，可以对表3-10至3-80任一表中至少一个“非零元素所在的列”中位置s指示的大于或等于0的各偏移值增加或减少补偿值Offset s。
需要说明的是，此处均只是举例，并不以此为限制。
以图1为例，确定出基矩阵H B后，可以先通过输入序列和基矩阵的第0至3行以及第0至第25列，也就是H core-dual部分得到第22至25列对应的校验比特；再根据输入序列和H core-dual对应的校验比特得到第26列，也就是单列重列对应的校验比特；然后根据输入序列以及第22至26列对应的校验比特和子矩阵D对应的部分编码得到子矩阵E部分对应的校验比特，从而完成编码。LDPC码的编码过程可以参考前述实现方式描述，此处不再赘述。
可选地，在通信系统中，可采用上述方法编码后得到LDPC码。获得LDPC码后，通信装置，还可以进行以下一个或多个操作：对LDPC码进行速率匹配；根据交织方案对速率匹配后的LDPC码进行交织；根据调制方案对交织后的LDPC码进行调制得到比特序列X；发送比特序列X。
译码是编码的逆过程，译码过程使用的基矩阵与编码过程使用的的基矩阵具有相同的特征。LDPC码的编码过程可以参考前述实现方式描述，此处不再赘述。在一种实现方式中，在译码之前，通信装置还可以进行以下一个或多个操作：接收包含基于LDPC编码的信号，对信号进行解调，解交织以及解速率匹配得到LDPC码的软值序列，对LDPC码的软值序列进行译码。
本申请中涉及的保存，可以是指的保存在一个或者多个存储器中。所述一个或者多个存储器，可以是单独的设置，也可以是集成在编码器或者译码器，处理器、芯片、通信装置、或者终端。所述一个或者多个存储器，也可以是一部分单独设置，一部分集成在译码器、处理器、芯片、通信装置、或者终端中，存储器的类型可以是任意形式的存储介质，本申请并不对此限定。
相应于图5，图6的给出的数据处理过程的设计，本发明实施例还提供了相应的通信装 置，所述通信装置包括用于执行图5或图6中每个部分相应的模块。所述模块可以是软件，也可以是硬件，或者是软件和硬件结合。例如模块可以包括存储器，电子设备，电子部件，逻辑电路等，或上述任一组合。图7给出了一种通信装置700的结构示意图，装置700可用于实现上述方法实施例中描述的方法，可以参见上述方法实施例中的说明。所述通信装置700可以是芯片，基站，终端或者其他网络设备。
所述通信装置700包括一个或多个处理器701。所述处理器701可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理，中央处理器可以用于对通信装置(如，基站、终端、或芯片等)进行控制，执行软件程序，处理软件程序的数据。
在一种可能的涉及中，如5，图6中的一个或者多个模块可能由一个或者多个处理器来实现，或者一个或者多个处理器和存储器来实现。
在一种可能的设计中，所述通信装置700包括一个或多个所述处理器701，所述一个或多个处理器701可实现上述编码/译码的功能，例如通信装置可以是编码器或者译码器。在另一种可能的设计中，处理器701除了实现编码/译码功能，还可以实现其他功能。
所述通信装置700基于LDPC矩阵对输入序列进行编码/译码；该LDPC矩阵的基矩阵可以为前述示例中的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换，或者行顺序和列顺序均发生变换的基矩阵，或者是基于前述例举的任一基矩阵截短或者打孔的基矩阵，或者是基于前述例举任一基矩阵扩展后的矩阵。关于编码或者/译码的处理可以参见图5和图6相关部分的描述，在此不再赘述。
可选的，在一种设计中，处理器701可以包括指令703(有时也可以称为代码或程序)，所述指令可以在所述处理器上被运行，使得所述通信装置700执行上述实施例中描述的方法。在又一种可能的设计中，通信装置700也可以包括电路，所述电路可以实现前述实施例中的编码/译码功能。
可选的，在一种设计中，所述通信装置700中可以包括一个或多个存储器702，其上存有指令704，所述指令可在所述处理器上被运行，使得所述通信装置700执行上述方法实施例中描述的方法。
可选的，所述存储器中还可以存储有数据。可选的处理器中也可以存储指令和/或数据。所述处理器和存储器可以单独设置，也可以集成在一起。
可选的，上述实施例中所述的“保存”可以是保存存储器702中，也可以是保存在其他的外设的存储器或者存储设备中。
例如，一个或多个存储702可以存储与上述列举的LDPC矩阵相关的参数，例如，基矩阵相关的参数，例如偏移值，基图，基于基图扩展到矩阵、基矩阵中的各行，扩展因子，基矩阵或者基于基矩阵扩展到矩阵等等。具体可以参见上述图5部分的相关描述。
可选的，所述通信装置700还可以包括收发器705以及天线706。所述处理器701可以称为处理单元，对通信装置(终端或者基站)进行控制。所述收发器505可以称为收发单元、收发机、收发电路、或者收发器等，用于通过天线506实现通信装置的收发功能.
可选的，所述通信装置700还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、用于速率匹配的器件、或者用于调制处理的调制器等。 可以通过一个或多个处理器701实现这些器件的功能。
可选的，所述通信装置700还可以包括，用于解调操作的解调器、用于解交织的解交织器、用于解速率匹配的器件、或者用于码块级联和CRC校验的器件等等。可以通过一个或多个处理器701实现这些器件的功能。
图8给出了一种通信系统800的示意图，通信系统800中包括通信设备80和通信设备81，其中，信息数据在通信设备80和通信设备81之间接收和发送。通信设备80和81可以是所述通信装装置700，或者通信设备备80和81分别包括通信装置700，对信息数据进行接收和/或发送。在一个例子中，通信设备80可以为终端，相应的通信设备81可以为基站；在另一个例子中，通信设备80为基站，相应的通信设备81可以为终端。
本领域技术任何还可以了解到本发明实施例列出的各种说明性逻辑块(illustrative logical block)和步骤(step)可以通过电子硬件、电脑软件，或两者的结合进行实现。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用，可以使用各种方法实现所述的功能，但这种实现不应被理解为超出本发明实施例保护的范围。
本申请所描述的技术可通过各种方式来实现。例如，这些技术可以用硬件、软件或者硬件结合的方式来实现。对于硬件实现，用于在通信装置(例如，基站，终端、网络实体、或芯片)处执行这些技术的处理单元，可以实现在一个或多个通用处理器、数字信号处理器(DSP)、数字信号处理器件(DSPD)、专用集成电路(ASIC)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合中。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。
本发明实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的指令、或者这两者的结合。存储器可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介。例如，存储器可以与处理器连接，以使得处理器可以从存储器中读取信息，并可以向存储器存写信息。可选地，存储器还可以集成到处理器中。处理器和存储器可以设置于ASIC中，ASIC可以设置于UE中。可选地，处理器和存储器也可以设置于UE中的不同的部件中。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式实现，所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本发明实施例所述的流程或功能。当使用软件程序实现时，也可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。 存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定义中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
需要说明的是，本申请中的“/”表示和/或，例如“编码/译码(编码和/或译码)，是指的编码、或者译码、或者编码和译码。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种编码方法，其特征在于，所述方法包括：
    使用低密度奇偶校验LDPC矩阵对输入序列进行编码；
    所述LDPC矩阵是基于扩展因子Z和基矩阵得到的，所述基矩阵包括以下所示矩阵：30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列，或者，所述基矩阵包括以下所示矩阵：30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列中的部分列。
  2. 一种译码方法，其特征在于，所述方法包括：
    使用低密度奇偶校验LDPC矩阵对输入序列进行译码；
    所述LDPC矩阵是基于扩展因子Z和基矩阵得到的，所述基矩阵包括以下所示矩阵：30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列，或者，所述基矩阵包括以下所示矩阵：30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列中的部分列。
  3. 根据权利要求1或2所述的方法，其特征在于，所述基矩阵还包括以下所示矩阵30b-10、30b-20、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，所述扩展因子Z＝a×2 j，0≤j＜7，a∈{2,3,5,7,9,11,13,15}，其中，
    a＝2，所述基矩阵包括矩阵30b-10中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-10中的第0至4行以及第0至26列中的部分列；或者，
    a＝3，所述基矩阵包括矩阵30b-20中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-20中的第0～4行以及第0至26列中的部分列；或者，
    a＝5，所述基矩阵包括矩阵30b-30中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-30中的第0～4行以及第0至26列中的部分列；或者，
    a＝7，所述基矩阵包括矩阵30b-40中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-40中的第0～4行以及第0至26列中的部分列；或者，
    a＝9，所述基矩阵包括矩阵30b-50中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-50中的第0～4行以及第0至26列中的部分列；或者，
    a＝11，所述基矩阵包括矩阵30b-60中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-60中的第0～4行以及第0至26列中的部分列；或者，
    a＝13，所述基矩阵包括矩阵30b-70中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-70中的第0至4行以及第0至26列中的部分列；或者，
    a＝15，所述基矩阵包括矩阵30b-80中的第0至4行以及第0至26列，或者，所述基矩阵包括矩阵30b-80中的第0至4行以及第0至26列中的部分列。
  5. 根据权利要求1至4任一项所述的方法所述的方法，其特征在于，
    a＝2，所述基矩阵还包括矩阵30b-10的第0行至第(m-1)行，以及第0列至第(n-1)列，其 中5≤m≤46,27≤n≤68；或者，
    a＝3，所述基矩阵还包括矩阵30b-20 1的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68；或者，
    a＝5，所述基矩阵还包括矩阵30b-30的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68；或者，
    a＝7，所述基矩阵还包括矩阵30b-40的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68；或者，
    a＝9，所述基矩阵还包括矩阵30b-50的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68；或者，
    a＝11，所述基矩阵还包括矩阵30b-60的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68；或者，
    a＝13，所述基矩阵还包括矩阵30b-70的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68；或者，
    a＝15，所述基矩阵还包括矩阵30b-80的第0行至第(m-1)行，以及第0列至第(n-1)列，其中5≤m≤46,27≤n≤68。
  6. 根据权利要求1至5任一项所述的方法，其特征在于，所述LDPC矩阵是基于所述扩展因子Z，和对所述基矩阵进行补偿后的矩阵Hs得到的，其中，所述矩阵Hs是对所述基矩阵中至少一列s中大于或等于0的各偏移值增加或减少补偿值Offset s得到的，其中，所述补偿值Offset s为大于或等于0的整数，0≤s＜23。
  7. 根据权利要求1至6任一项所述的方法，其特征在于，所述LDPC矩阵是基于所述扩展因子Z，和所述基矩阵或者基矩阵的补偿矩阵Hs经过行交换、或者列交换、或者行交换和列交换后的矩阵得到的。
  8. 一种编码方法，其特征在于，所述方法包括：
    根据扩展因子Z和低密度奇偶校验LDPC矩阵的参数对输入序列进行编码；
    其中，所述LDPC矩阵的参数包括表3-10、表3-20、表3-30、表3-40、表3-50、表3-60、表3-70以及表3-80之一中行号为0至4对应的参数。
  9. 一种译码方法，其特征在于，所述方法包括：
    根据扩展因子Z和低密度奇偶校验LDPC矩阵的参数对输入序列进行译码；
    其中，所述LDPC矩阵的参数包括表3-10、表3-20、表3-30、表3-40、表3-50、表3-60、表3-70以及表3-80之一中行号为0至4对应的参数。
  10. 根据权利要求8或9所述的方法，其特征在于，所述LDPC矩阵的参数还包括所述0至4之一中行号为5-45中的m D行对应的参数，其中0≤m D≤41。
  11. 根据权利要求8至10任一项所述的方法，其特征在于，所述扩展因子Z＝a×2 j，0≤j＜7，a∈{2,3,5,7,9,11,13,15}，其中，
    a＝2，所述LDPC矩阵的参数包括表3-10中行号为0至4行所对应的参数；或者，
    a＝3，所述LDPC矩阵的参数包括表3-20中行号为0至4行所对应的参数；或者，
    a＝5，所述LDPC矩阵的参数包括表3-30中行号为0至4行所对应的参数；或者，
    a＝7，所述LDPC矩阵的参数包括表3-40中行号为0至4行所对应的参数；或者，
    a＝9，所述LDPC矩阵的参数包括表3-50中行号为0至4行所对应的参数；或者，
    a＝11，所述LDPC矩阵的参数包括表3-60中行号为0至4行所对应的参数；或者，
    a＝13，所述LDPC矩阵的参数包括表3-70中行号为0至4行所对应的参数；或者，
    a＝15，所述LDPC矩阵的参数包括表3-80中行号为0至4行所对应的参数。
  12. 根据权利要求11所述的方法，其特征在于，
    a＝2，所述LDPC矩阵的参数包括表3-10的行号为5至45中的m D行所对应的参数；或者，
    a＝3，所述LDPC矩阵的参数包括表3-20的行号为5至45中的m D行所对应的参数；或者，
    a＝5，所述LDPC矩阵的参数包括表3-30的行号为5至45中的m D行所对应的参数；或者，
    a＝7，所述LDPC矩阵的参数包括表3-40的行号为5至45中的m D行所对应的参数；或者，
    a＝9，所述LDPC矩阵的参数包括表3-50的行号为5至45中的m D行所对应的参数；或者，
    a＝11，所述LDPC矩阵的参数包括表3-60的行号为5至45中的m D行所对应的参数；或者，
    a＝13，所述LDPC矩阵的参数包括表3-70的行号为5至45中的m D行所对应的参数；或者，
    a＝15，所述LDPC矩阵的参数包括表3-80的行号为5至45中的m D行所对应的参数。
  13. 根据权利要求8至12任一项所述的方法，其特征在于，所述根据扩展因子Z和低密度奇偶校验LDPC矩阵的参数对输入序列进行编码，包括：
    根据扩展因子Z和对所述LDPC矩阵的参数进行补偿后的参数对输入序列进行编码；
    所述对所述LDPC矩阵的参数进行补偿，包括：
    对所述LDPC矩阵的参数中至少一个列位置s上的大于或等于0的各偏移值增加或减少补偿值Offset s得到的，其中，所述补偿值Offset s为大于或等于0的整数，0≤s＜23。
  14. 一种装置，用于执行如权利要求1至13项任一项所述的方法。
  15. 一种通信装置，其特征在于，所述通信装置包括处理器、存储器以及存储在存储器上并可在处理器上运行的指令，当所述指令被运行时，使得所述通信装置执行如权利要求1至13项任一项所述的方法。
  16. 一种终端，其特征在于，包括如权利要求14所述的装置或权利要求15所述的通信装置。
  17. 一种基站，其特征在于，包括如权利要求14所述的装置或权利要求15所述的通信装置。
  18. 一种通信系统，其特征在于包括如权利要求16所述的终端以及如权利要求17所述的基站。
  19. 一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1至13任一项所述的方法。
  20. 一种计算机程序产品，当其在计算机上运行时，使得计算机执行权利要求1至13任一项所述的方法。
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ZTE; ZTE MICROELECTRONICS: "Compact LDPC design for eMBB", 3GPP TSG-RAN WG1 AH NR MEETING R1-1701473, no. R1-1701473, 20 January 2017 (2017-01-20), XP051222469 *

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CN109150193B (zh) 2020-11-27
EP3629481A1 (en) 2020-04-01
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