WO2018218466A1 - 信息处理的方法和通信装置 - Google Patents

信息处理的方法和通信装置 Download PDF

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WO2018218466A1
WO2018218466A1 PCT/CN2017/086458 CN2017086458W WO2018218466A1 WO 2018218466 A1 WO2018218466 A1 WO 2018218466A1 CN 2017086458 W CN2017086458 W CN 2017086458W WO 2018218466 A1 WO2018218466 A1 WO 2018218466A1
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twenty
bit sequence
matrix
columns
column
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PCT/CN2017/086458
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English (en)
French (fr)
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郑晨
魏岳军
马亮
刘晓健
曾歆
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华为技术有限公司
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Priority to PCT/CN2017/086458 priority Critical patent/WO2018218466A1/zh
Priority to PCT/CN2017/086500 priority patent/WO2018218471A1/zh
Priority to EP17911561.3A priority patent/EP3641172B1/en
Priority to CN201780090597.5A priority patent/CN110612679B/zh
Publication of WO2018218466A1 publication Critical patent/WO2018218466A1/zh
Priority to US16/691,281 priority patent/US11463108B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • Embodiments of the present invention relate to the field of communications, and in particular, to a method and a communication device for information processing.
  • Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
  • the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
  • LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
  • an LDPC matrix with special structured features can be used.
  • the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
  • the length of information bit sequences to be encoded ranges from tens to hundreds, and the code rate required by the communication system is also flexible. When the code rate is high, it is often necessary to perform puncturing on the encoded bit sequence, and puncturing the bit sequence may affect the performance of the LDPC code.
  • Embodiments of the present invention provide a method, a communication device, and a system for information processing, which meet the performance requirements of an LDPC code at a high code rate.
  • a method of information processing comprising:
  • the input sequence is encoded using a low density parity check LDPC matrix to obtain a bit sequence D, the base matrix of the LDPC matrix being represented as a matrix of m rows and n columns, each column corresponding to a set of Z consecutive bits in the bit sequence D, Both n and Z are integers greater than 0;
  • bit sequence V is obtained by replacing two sets of bits corresponding to at least two columns of the check column in the bit sequence D, wherein the at least two columns of the check column a z-th column to an n-th column of the base matrix, wherein the j-th group of Z consecutive bits in the bit sequence V is the first group of Z consecutive bits in the bit sequence D, and j is an integer And 0 ⁇ j ⁇ n.
  • a method of information processing comprising:
  • the base matrix of the LDPC matrix is represented as a matrix of m rows and n columns, and each column corresponds to a set of Z consecutive soft value bits in the soft value sequence D', and n and Z are integers greater than 0;
  • the jth group of Z consecutive soft value bits in the soft value sequence V is Z consecutive (s) soft value bits of the P(j) group in the soft value sequence D', j is an integer, and 0 ⁇ j ⁇ n;
  • the soft value sequence V' is obtained by replacing two sets of bits corresponding to at least two columns of the check columns of the soft value sequence D', and the at least two columns of check columns are the nm of the base matrix. Column to at least 2 columns in column n-1.
  • the at least two columns of check columns are at least two columns of ⁇ P(a+i)
  • 0 ⁇ i ⁇ 6 ⁇ ⁇ 22,23,24,25,26,27 ⁇ .
  • the bit sequence V is obtained by replacing at least two sets of Z consecutive bits in ⁇ P(a+i)
  • the soft value sequence V' is obtained by replacing at least two sets of Z consecutive bits in ⁇ P(a+i)
  • 0 ⁇ i ⁇ 6 ⁇ includes any one of the values in Tables 1 to 8.
  • the output bit sequence is obtained starting from the 2*Z bit of the bit sequence V.
  • the base matrix of the LDPC matrix may be stored in a memory.
  • the base map of the LDPC matrix is stored in the memory, and the offset value of the non-zero element in the base matrix of the LDPC matrix may be Saved in memory.
  • a communication apparatus can include a module for performing any of the possible implementations of the first aspect of the method design described above.
  • the module can be software and/or hardware.
  • the communication device provided by the third aspect comprises the coding unit and the processing unit as described in the first aspect above.
  • the encoding unit is configured to encode the input sequence using a low density parity check LDPC matrix to obtain a bit sequence D, and the processing unit obtains an output bit sequence based on the bit sequence V.
  • the communication device further includes a transceiver, and the transceiver is configured to send a signal corresponding to the encoded information data.
  • a communication apparatus can include a module for performing any of the possible implementations of the second aspect of the method design described above.
  • the module can be software and/or hardware.
  • the communication device provided by the fourth aspect includes the decoding unit and the processing unit according to the second aspect described above.
  • the processing unit is operative to acquire a soft value sequence V' based on a low density parity check LDPC matrix encoded signal.
  • the decoding unit decodes the soft value sequence D' using the LDPC matrix.
  • the communication device also includes a transceiver for receiving a signal comprising an LDPC based code.
  • a communication device in a fifth aspect, includes one or more processors.
  • one or more of the processors may implement the first aspect information processing method or the third aspect communication device. In another possible design, the processor implements the first aspect information.
  • the functions of the processing method can also implement other functions.
  • one or more of the processors may implement the functions of the second aspect information processing method, and in another possible design, the processor not only implements the functions of the second aspect information processing method, but also Other functions can be implemented.
  • the communication device may further include a transceiver and an antenna.
  • the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
  • a demodulator for demodulation operation e.g., a demodulator for demodulation operation
  • a deinterleaver for deinterleaving e.g., a device for de-rate matching
  • the functionality of these devices can be implemented by one or more processors.
  • the functionality of these devices can be implemented by one or more processors.
  • an embodiment of the present invention provides a communication system, including the communication device according to the above third aspect, and the communication device according to the fourth aspect.
  • an embodiment of the present invention provides a communication system, where the system includes one or more communication devices according to the fifth aspect.
  • an embodiment of the present invention provides a computer storage medium having stored thereon a program, and when executed, causes a computer to perform the method described in the above aspect.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • the information processing method, device, communication device and communication system of the embodiments of the present invention can meet the performance requirements of the LDPC code at a high code rate.
  • 1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code
  • FIG. 2 is a schematic structural diagram of a base diagram of an LDPC code
  • FIG. 3 is a schematic diagram of an LDPC code base matrix according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a communication system according to another embodiment of the present invention.
  • FIG. 5 is a flowchart of an information processing method according to another embodiment of the present invention.
  • FIG. 6 is a flowchart of an information processing method according to another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an information processing apparatus according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of performance provided by another embodiment of the present invention.
  • the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
  • a terminal is a communication-enabled device that can include a handheld device with wireless communication capabilities, an in-vehicle device, and wearable Wear equipment, computing equipment, or other processing equipment connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
  • the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
  • a base station is called an evolved Node B (eNB or eNodeB).
  • eNB evolved Node B
  • NR transmission reception point
  • gNB next generation node B
  • Base stations in other various evolved networks may also adopt other names. The invention is not limited to this.
  • the LDPC code can usually be represented by a parity check matrix H.
  • the parity check matrix H of the LDPC code can be obtained by a base graph and a shift value.
  • the base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns.
  • the value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix.
  • An element with a value of 1, sometimes referred to as a non-zero element indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement.
  • each matrix element represents an all-zero matrix or a cyclic permutation matrix.
  • the row number and column number of the base map and the base matrix are numbered from 0, just for the convenience of understanding. It can be understood that the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 based on the line number and column number shown in this article.
  • the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P i,j , P i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1
  • the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P i,j , which can be obtained by cyclically shifting the unit matrix of Z*Z by P i, j times to the right.
  • each element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and each element having a value of 1 is replaced by a cyclic permutation matrix of Z*Z corresponding to its offset value,
  • Z is a positive integer, which can also be called a lifting factor, which can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z).
  • the system usually defines a base matrix of m rows and n columns. Each element in the base matrix corresponds to the position of each element in the base map. The zero elements in the base map are based on The position in the matrix is unchanged, and is represented by -1. The non-zero elements with the value of the i-th row and the j-th column in the base map are in the same position in the base matrix, and can be expressed as P i,j , P i,j is greater than or A positive integer equal to 0.
  • the base matrix is sometimes referred to as an offset matrix of the base matrix. If the input sequence is encoded based on the base matrix of m rows and n columns, each column in the base matrix may correspond to Z consecutive bits in the encoded bit sequence.
  • a base matrix corresponding to the base map 10a is shown.
  • the LDPC code used in the wireless communication system has a matrix size of m rows and n columns, and may include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by the number of non-zero elements.
  • the weight of a row refers to the number of non-zero elements included in a row
  • the weight of a column refers to the number of non-zero elements included in a column.
  • Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
  • the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
  • the sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 is located before the sub-matrix B', as shown in FIG.
  • the sub-matrix B may further include a matrix column having a column weight of 1 (referred to as a single column re-column), and the single-column re-column may be located in the first column or the last column of the sub-matrix B, and the non-zero elements in the sub-matrix B
  • the last line causes the row of the last row of the submatrix B to have a weight of 1, as shown by 20b or 20c in FIG.
  • the matrix generated based on the sub-matrices A and B is usually a core matrix and can be used to support high code rate encoding.
  • the sub-matrix C is an all-zero matrix having a size of m A ⁇ (n - (m A + n A )).
  • the sub-matrix E is an identity matrix having a size of (mm A ) ⁇ (mm A ).
  • the submatrix D has a size of (mm A ) ⁇ (n A + m A ) and is generally used to generate a low bit rate check bit.
  • FIG. 3 is an example of a base map 30a of an LDPC code and a corresponding base matrix 30b, wherein the matrix is 46 rows and 68 columns, wherein the sub-matrix A is the 0th row to the 5th row and the 0th column to the 21st column.
  • the matrix portion, the sub-matrix B is a matrix portion composed of the 0th row to the 5th row and the 22nd column to the 26th column.
  • Submatrix A and submatrix B form the core matrix portion of the base matrix.
  • sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates.
  • the sub-matrix C is an all-zero matrix
  • the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed.
  • the main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.
  • the number of columns of the sub-matrix D is the sum of the number of columns of the sub-matrices A and B, and the number of rows thereof is mainly related to the code rate.
  • the code rate supported by the LDPC code is R m
  • the size of the base map or the base matrix Is m*n, where n n A /R m +p
  • the minimum code rate R m 1/3
  • the communication system 400 includes a communication device 40 and a communication device 41, and control information or data information is received and transmitted between the communication device 40 and the communication device 41 as a sequence of information.
  • the information sequence transmitted by the communication device 40 is subjected to a channel block CRC and a code block to obtain a channel coded input sequence C.
  • the input sequence C is subjected to channel coding to obtain a bit sequence D, and the bit sequence D is subjected to rate matching processing to obtain an output bit sequence. E, further processed by interleaving, modulation, etc. and transmitted.
  • the reception of the information sequence by the communication device 41 is the inverse of the above transmission process.
  • communication device 40 can be a terminal, and corresponding communication device 41 can be a base station; in another example, communication device 40 is a base station, and corresponding communication device 41 can be a terminal.
  • FIG. 5 is a flowchart of an information processing method according to an embodiment of the present invention. The method includes:
  • the base map of the LDPC matrix may be a matrix of m rows and n columns in the foregoing example, such as the base map 30a. Each column corresponds to a set of Z consecutive bits in the bit sequence D, and n and Z are integers greater than zero.
  • the bit sequence V is obtained by replacing two sets of bits corresponding to at least two columns of the check columns in the bit sequence D.
  • the check column may be the n-thth column to the n-1th column in the base matrix, for example, for the base map 30a, it may be the 22nd column to the 67th column.
  • the check bit can also be punched, and the bit corresponding to the column to be punched needs to be replaced for punching.
  • At least two sets of bits in the bit sequence D corresponding to at least two columns from the nth to mth columns to the n-1th column of the base matrix may be replaced, each set of bits including Z consecutive bits.
  • the base matrix column number is numbered from 0.
  • the at least two columns of check columns are at least two columns from the nmth column to the n-1th column of the base matrix, and the base matrix column number starts from 0. It can be understood that if the base matrix column number Starting from 1, the at least two columns of check columns are correspondingly at least two columns from the n-m+1th column to the nth column of the base matrix. In this document, the row number of the matrix is not specifically described. The column number and the column number are all starting from 0. If the row number and column number of the matrix are numbered from 1, the corresponding increment is 1.
  • the jth group of Z consecutive bits in the bit sequence V is the Pth (j)th group of consecutive bits in the bit sequence D, j is an integer, and 0 ⁇ j ⁇ n.
  • the starting group number of the six columns in the bit sequence V is a, then ⁇ P(a+i)
  • 0 ⁇ i ⁇ 6 ⁇ ⁇ 22,23,24,25, 26,27 ⁇ .
  • bit sequence V which may be at least 2 of ⁇ P(a+i)
  • a group of Z consecutive bits are substituted to obtain a bit sequence V.
  • the sub-matrix B is usually a double-diagonal structure, that is, the check columns of these columns have a double-diagonal structure. Since the punching is generally performed from the back to the front, the s column that needs to be punched can be replaced with the last s column of the six columns, s is an integer greater than 0, and other columns can be adjusted as needed.
  • each column in the table represents the corresponding value of each element in ⁇ P(a+i)
  • the columns in the double diagonal structure can be replaced.
  • Each column in each table represents a corresponding value of each element in ⁇ P(a+i)
  • the bits The two sets of bits corresponding to the built-in punched column in the sequence D may be replaced with the last two groups in the bit sequence V, so a possible replacement order is as shown in Table 9, from left to right, from top to bottom, and is a bit.
  • Each group of bits in the sequence V corresponds to a representation of the P(j) group bits in the bit sequence D.
  • the 0th group of bits in the bit sequence V is the second group of bits in the bit sequence D
  • the first group of bits is in the bit sequence D.
  • the third group of bits, and so on, will not be repeated.
  • the 65th group of bits is the 67th group of bits in the bit sequence D
  • the 0th group and the 1st group of bits in the bit sequence D are placed in the bit sequence.
  • 0 ⁇ i ⁇ 6 ⁇ may be any possible combination of values in any one of Tables 1 to 8.
  • the 0th bit of the bit sequence V can be used as the starting position to obtain the output bit sequence E when the initial transmission is performed. In this manner, when retransmitting It is still possible to obtain 2 sets of bits corresponding to the built-in punched column.
  • the two sets of bits corresponding to the built-in punctured column in the bit sequence D are not replaced, and the possible replacement order is as shown in Table 10, from left to right, from top to bottom, and is a bit sequence.
  • Each group of bits in V corresponds to the P(j) group of bits in the bit sequence D.
  • the 0th bit in the bit sequence V is the 0th bit in the bit sequence D
  • the first set of bits is the bit in the bit sequence D. 1 set of bits, and so on, not repeated.
  • the 67th group of bits is the 67th group of bits in the bit sequence D.
  • 0 ⁇ i ⁇ 6 ⁇ may be any possible combination of values in any one of Tables 1 to 8.
  • the 2*Z bit of the bit sequence V can be used as the starting position during the initial transmission to obtain the output bit sequence E, that is, the 0th group is skipped.
  • the bit and the first group of bits in this way, it is still possible to obtain two sets of bits corresponding to the built-in punched column when retransmitting.
  • the two sets of bits corresponding to the built-in punctured column in the bit sequence D are directly discarded, so the order of replacement is as shown in Table 11, from left to right, from top to bottom, in the bit sequence V.
  • Each group of bits corresponds to a representation of the P(j) group bits in the bit sequence D.
  • the 0th group of bits in the bit sequence V is the second group of bits in the bit sequence D
  • the first group of bits is the third group in the bit sequence D. Bits, and so on, are not repeated.
  • the 65th group of bits is the 67th group of bits in the bit sequence D.
  • 0 ⁇ i ⁇ 6 ⁇ may be any possible combination of values in any one of Tables 1 to 8.
  • the 0th bit of the bit sequence V can be used as the starting position to obtain the output bit sequence E during the initial transmission, because the two groups corresponding to the built-in punched column are obtained. If the bit is discarded, the output bit sequence does not include the 2 sets of bits corresponding to the built-in punctured column, that is, the 0th bit and the 1st set of bits in the bit sequence D, whether it is initial transmission or retransmission.
  • FIG. 8 is a schematic diagram showing the performance comparison before and after the replacement of the LDPC matrix of the base map 30a at a code rate of 0.93, wherein the "original order" is the LDPC matrix of the base map 30a without the punching.
  • the performance curve of the different Es/N0 when performing the replacement can be seen that the BLER is 1 and cannot work normally.
  • the "post-switching sequence” is the LDPC matrix of the base map 30a. According to the information processing method provided by the embodiment of the present invention, the performance curve of the punctured check column after replacement at different Es/N0 can be seen. Under Es/N0, the BLER drops and the performance is better.
  • FIG. 6 is a diagram showing an information processing method according to another embodiment of the present invention, where the method includes:
  • the communication device 41 functions as a communication device at the receiving end, and acquires an LDPC matrix-coded signal transmitted by the communication device 40.
  • the communication device 40 transmits the output bit sequence obtained in the foregoing embodiments to the communication device 41.
  • the output bit sequence in the above embodiment is a rate-matched output bit sequence, and the communication device 40 can rate the output.
  • the matched output bit sequence is subjected to interleaving modulation or the like to transmit a transmission signal corresponding to the output bit sequence, and the communication device 41 receives the output signal and demodulates and deinterleaves to obtain a soft value corresponding to the output bit sequence.
  • the sequence, that is, one bit in the output bit sequence corresponds to a soft channel bit in the soft value sequence.
  • the locations where these soft-valued bits are stored in the soft-message buffer of the communication device 41 correspond one-to-one with the locations of the encoded blocks in the circular buffer in the communication device 40, and the size of the soft-message buffer is the same as the size of the encoded block in the circular buffer. , can be N CB .
  • the output bit transmitted by the communication device 40 is 1, and after the channel transmission, the communication device 41 obtains its corresponding soft value bit of 1.45. If the position of the output bit in the coding block is the 5th bit, the soft at the communication device 41 The 5th soft value bit in the message buffer is 1.45. It should be noted that the description herein is merely an example, and the embodiment of the present invention is not limited thereto. If the output bit sequence acquired by the communication device 40 includes n output bits, the communication device 41 can acquire n corresponding soft value bits. If the communication device 41 receives the soft value bits of the same location twice, the two soft values are combined, for example, the soft value bit received during the first transmission is 1.45, and the softness received during the second transmission. The value bit is 0.5, which is 1.95 after the combination. It should be noted that the examples are merely examples and are not limited thereto.
  • the signal acquired by the communication device 41 on 601 is subjected to demodulation or the like to obtain a soft value sequence V'.
  • One bit in the bit sequence V corresponds to a soft channel bit in the soft value sequence V'.
  • the base matrix of the LDPC matrix is represented as a matrix of m rows and n columns, and each column corresponds to a set of Z consecutive soft value bits in the soft value sequence D', and n and Z are integers greater than 0;
  • the zth consecutive soft value bits of the jth group in the soft value sequence V' are Z consecutive soft value bits of the P(j) group in the soft value sequence D', j is an integer, and 0 ⁇ j ⁇ n;
  • the soft value sequence V' is obtained by replacing two sets of bits corresponding to at least two columns of the check columns of the soft value sequence D', and the at least two columns of check columns are the nm of the base matrix. Column to at least 2 columns in column n-1.
  • the position of the check column of the replacement has the features corresponding to the foregoing embodiments.
  • the soft value sequence V' and the soft value sequence D' are described in the communication device 41, and the bit sequence V and the bit sequence D are in the communication device 40.
  • FIG. 7 is a schematic structural diagram of a communication device 700.
  • the communication device 700 can be used to implement the method described in the foregoing method embodiments. For details, refer to the description in the foregoing method embodiments.
  • the communication device 700 can be a chip, a base station, a terminal, or other network device.
  • the communication device 700 includes one or more processors 701.
  • the processor 701 can be a general purpose processor or a dedicated processor or the like. For example, it can be a baseband processor, or a central processing unit.
  • the baseband processor can be used to process communication protocols and communication data
  • the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.
  • the communication device 700 includes one or more of the processors 701, and the one or more processors 701 can implement the method in the method embodiment shown in FIG. 5, in another In a possible design, the processor 701 can implement other functions in addition to the method in the method embodiment shown in FIG. 5.
  • the communication device 700 encodes the input sequence using a low density parity check LDPC matrix to obtain a bit sequence D, the base matrix of the LDPC matrix is represented as a matrix of m rows and n columns, and each column corresponds to a group of the bit sequence D Z consecutive bits, n and Z are integers greater than 0; obtaining an output bit sequence based on the bit sequence V, wherein the bit sequence V is 2 sets of bits corresponding to at least 2 columns of check columns in the bit sequence D And performing the permutation, wherein the at least two columns of check columns are at least two columns from the nmth column to the n-1th column of the base matrix, and the jth group of Z consecutive bits in the bit sequence V is The P (j) group of Z consecutive bits in the bit sequence D, j is an integer, and 0 ⁇ j ⁇ n.
  • one or more of the processors 701 may implement the method in the method embodiment shown in FIG. 6. In another possible design, the processor 701 implements the method shown in FIG. Other functions can also be implemented by the method in the embodiment.
  • the communication device 700 can be configured to acquire a soft value sequence V′ based on a low density parity check LDPC matrix encoded signal; use the LDPC matrix to decode the soft value sequence D′; wherein the base matrix representation of the LDPC matrix a matrix of m rows and n columns, each column corresponding to a set of Z consecutive soft value bits in the soft value sequence D', n and Z are integers greater than 0; wherein the soft value sequence V is the jth The Z consecutive soft value bits are Z consecutive (s) soft value bits of the P(j) group in the soft value sequence D', j is an integer, and 0 ⁇ j ⁇ n; wherein the soft value sequence V ' is that the two sets of bits corresponding to at least two columns of the check columns in the soft value sequence D' are replaced, and the at least two columns of check columns are in the nth to nth columns of the base matrix. At least 2 columns.
  • the processor 701 can also include instructions 703 that can be executed on the processor such that the communication device 700 performs the methods described in the above method embodiments.
  • the communication device 700 can also include circuitry that can implement the methods of the foregoing method embodiments.
  • the communication device 700 can include one or more memories 702 having instructions 704 stored thereon, the instructions being executable on the processor, such that the communication device 700 performs the above method embodiments.
  • data may also be stored in the memory. Instructions and/or data can also be stored in the optional processor.
  • the processor and the memory may be provided separately or integrated.
  • the one or more memories 702 may store parameters related to the base matrix, such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, spreading factors, and the like.
  • the one or more memories 702 may store a base matrix or extend to a matrix based on a base matrix.
  • the communication device 700 may further include a transceiver 705 and an antenna 706.
  • the processor 701 may be referred to as a processing unit that controls a communication device (terminal or base station).
  • the transceiver 705 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiver function of the communication device through the antenna 706.
  • the communication device 700 may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
  • a device for generating a transport block CRC a device for generating a transport block CRC
  • a device for code block splitting and CRC check a device for code block splitting and CRC check
  • an interleaver for interleaving a modulator for modulation processing, and the like.
  • the functionality of these devices can be implemented by one or more processors 701.
  • the communication device 700 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
  • a demodulator for demodulation operation e.g., a demodulator for demodulation operation
  • a deinterleaver for deinterleaving e.g., a device for de-rate matching
  • the functionality of these devices can be implemented by one or more processors 701.
  • a general purpose processor may be a microprocessor.
  • the general purpose processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.
  • the steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two.
  • the memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art.
  • the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory.
  • the memory can also be integrated into the processor.
  • the processor and the memory may be disposed in an ASIC, and the ASIC may be disposed in the UE. Alternatively, the processor and memory may also be located in different components in the UE.
  • the present invention can be implemented in hardware, firmware implementation, or a combination thereof.
  • a software program all can be Or partially implemented in the form of a computer program product comprising one or more computer instructions.
  • the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the functions described above may also be stored in or transmitted as one or more instructions or code on a computer readable medium.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

Abstract

一种信息处理的方法，装置、通信设备和通信系统。该方法包括：使用低密度奇偶校验LDPC矩阵对输入序列进行编码得到比特序列D（501），所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述比特序列D中一组Z个连续比特，n和Z均为大于0的整数；基于比特序列V获取输出比特序列，其中，所述比特序列V是对所述比特序列D中至少2列校验列对应的2组比特进行置换得到的（502）。所述信息处理的方法，装置、通信设备和通信系统，能够支持高码率的LDPC码性能需求。

Description

信息处理的方法和通信装置 技术领域
本发明实施例涉及通信领域，尤其涉及信息处理的方法和通信装置。
背景技术
低密度奇偶校验(low density parity check，LDPC)码是一类具有稀疏校验矩阵的线性分组编码，具有结构灵活，译码复杂度低的特点。由于它采用部分并行的迭代译码算法，从而比传统的Turbo码具有更高的吞吐率。LDPC码可用于通信系统的纠错码，从而提高信道传输的可靠性和功率利用率。LDPC码还可以广泛应用于空间通信、光纤通信、个人通信系统、ADSL和磁记录设备等。目前在第五代移动通信中已考虑采用LDPC码作为信道编码方式之一。
实际使用过程中，可以采用具有特殊结构化特征的LDPC矩阵。该具有特殊结构化特征的LDPC矩阵H可以由准循环(quasi cycle，QC)结构的LDPC基矩阵扩展得到。
通常情况下，待编码的信息比特序列长度从几十到上百不等，通信系统要求的码率也灵活多变。当码率较高时，往往需要对编码后的比特序列进行打孔处理，而对比特序列打孔会影响到LDPC码的性能。
发明内容
本发明实施例提供了一种信息处理的方法、通信装置和系统，符合高码率下LDPC码的性能要求。
第一方面，提供了一种信息处理的方法，所述方法包括：
使用低密度奇偶校验LDPC矩阵对输入序列进行编码得到比特序列D，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述比特序列D中一组Z个连续比特,n和Z均为大于0的整数；
基于比特序列V获取输出比特序列，其中，所述比特序列V是对所述比特序列D中至少2列校验列对应的2组比特进行置换得到的，其中，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列，所述比特序列V中第j组Z个连续比特为所述比特序列D中第组Z个连续比特，j为整数，且0≤j＜n。
第二方面，提供了一种信息处理的方法，所述方法包括：
基于低密度奇偶校验LDPC矩阵编码的信号获取软值序列V’；
使用所述LDPC矩阵对软值序列D’进行译码；
其中，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述软值序列D’中一组Z个连续的软值比特,n和Z均为大于0的整数；
其中，所述软值序列V中第j组Z个连续的软值比特为所述软值序列D’中第P(j)组Z个连续的软值比特，j为整数，且0≤j＜n；
其中，所述软值序列V’是所述软值序列D’中至少2列校验列对应的2组比特经过置换得到的，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列。
在上述第一方面或第二方面的第一种实现方式中：所述至少2列校验列为所述基矩阵的{P(a+i)|0≤i＜6}中至少2列，其中{P(a+i)|0≤i＜6}＝{22,23,24,25,26,27}。
所述比特序列V是对所述比特序列D中{P(a+i)|0≤i＜6}中至少2组Z个连续比特进行置换得到的。或者，所述软值序列V’是对所述软值序列D’中{P(a+i)|0≤i＜6}中至少2组Z个连续比特进行置换得到的。
在又一种可能的实现方式中，P(a+5)＝26，P(a+4)＝24或者P(a+4)＝25；或者，
P(a+5)＝25，P(a+4)＝24或者P(a+4)＝26；或者，
P(a+5)＝24，P(a+4)＝23或者P(a+4)＝25或者P(a+4)＝26；或者，
P(a+5)＝23，P(a+4)＝24。
基于上述实现方式，a＝20或者a＝22。
可选地，所述{P(a+i)|0≤i＜6}包括表1～表8中任一组取值。
基于上述实现方式，在又一种可能的实现方式中，
a＝20，以所述比特序列V的第0比特作为起始位置获取输出比特序列；或者，
a＝20，以所述比特序列V的第0比特作为起始位置获取输出比特序列，且所述输出比特序列不包括所述比特序列D中第0组和第1组比特；或者，
a＝22，以所述比特序列V的第2*Z比特作起始位置获取输出比特序列。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，LDPC矩阵的基矩阵可以保存在存储器中。
基于上述各方面，或者各方面任一种可能的实现方式，在又一种可能的实现方式中，LDPC矩阵的基图保存在存储器中，LDPC矩阵的基矩阵中非零元素的偏移值可以保存在存储器中。
第三方面，提供一种通信装置可以包含用于执行上述方法设计中第一方面任一种可能的实现方式相对应的模块。所述模块可以是软件和/或是硬件。
在一个可能的设计中，第三方面提供的通信装置，包括如上述第一方面所述的编码单元以及处理单元。所述编码单元用于使用低密度奇偶校验LDPC矩阵对输入序列进行编码得到比特序列D，所述处理单元基于比特序列V获取输出比特序列。
可选地，所述通信装置还包括收发器，所述收发器用于发送对应于所编码后的信息数据的信号。
第四方面，提供一种通信装置可以包含用于执行上述方法设计中第二方面任一种可能的实现方式相对应的模块。所述模块可以是软件和/或是硬件。
在一种可能的设计中，第四方面提供的通信装置，包括如上述第二方面所述的译码单元以及处理单元。所述处理单元用于基于低密度奇偶校验LDPC矩阵编码的信号获取软值序列V’。所述译码单元，使用所述LDPC矩阵对软值序列D’进行译码。
所述通信装置还包括收发器，所述收发器用于接收包含基于LDPC编码的信号。
第五方面，提供了一种通信装置，包括一个或多个处理器。
在一种可能的设计中，一个或多个所述处理器可实现第一方面信息处理方法或者第三方面通信装置的功能，在另一种可能的设计中，处理器除了实现第一方面信息处理方法的功能，还可以实现其他功能。
在一种可能的设计中，一个或多个所述处理器可实现第二方面信息处理方法的功能，在另一种可能的设计中，处理器除了实现第二方面信息处理方法的功能，还可以实现其他功能。
可选地，所述通信装置还可以包括收发器以及天线。
可选的，所述通信装置还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、或者用于调制处理的调制器等。
可选的，所述通信装置还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器实现这些器件的功能。
在一种可能的设计中，可以通过一个或多个处理器实现这些器件的功能。
第六方面，本发明实施例提供了一种通信系统，该系统包括上述第三方面所述的通信装置和上述第四方面所述的通信装置。
第七方面，本发明实施例提供了一种通信系统，该系统包括一个或多个第五方面所述的通信装置。
再一方面，本发明实施例提供了一种计算机存储介质，其上存储有程序，当其运行时，使得计算机执行上述方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本发明实施例的信息处理的方法、装置、通信设备和通信系统，可以满足高码率下LDPC码的性能要求。
附图说明
图1为一LDPC码的基图、基矩阵及其循环置换矩阵的示意图；
图2为一LDPC码的基图的结构示意图；
图3为本发明一实施例提供的LDPC码基矩阵的示意图；
图4为本发明另一实施例提供的通信系统的示意图；
图5为本发明另一实施例提供的信息处理方法的流程图；
图6为本发明另一实施例提供的信息处理方法的流程图；
图7为本发明另一实施例提供的信息处理装置的结构示意图；
图8为本发明另一实施例提供的性能示意图。
具体实施方式
为便于理解下面对本申请中涉及到的一些名词做些说明。
本申请中，名词“网络”和“系统”经常交替使用，“装置”和“设备”也经常交替使用，但本领域的技术人员可以理解其含义。“通信装置”可以是芯片(如基带芯片，或者数据信号处理芯片，或者通用芯片等等)，终端，基站，或者其他网络设备。终端是一种具有通信功能的设备，可以包括具有无线通信功能的手持设备、车载设备、可穿 戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。为描述方便，本申请中简称为终端。基站(base station，BS)，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。在不同的无线接入系统中基站的叫法可能有所不同，例如在而在通用移动通讯系统(Universal Mobile Telecommunications System，UMTS)网络中基站称为节点B(NodeB),而在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在新空口(new radio,NR)网络中的基站称为收发点(transmission reception point，TRP)或者下一代节点B(generation nodeB，gNB)，或者其他各种演进网络中的基站也可能采用其他叫法。本发明并不限于此。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
LDPC码通常可以用奇偶校验矩阵H来表示。LDPC码的奇偶校验矩阵H可以通过基图(base graph)和偏移(shift)值得到。基图通常可以包括m*n个矩阵元素(entry)，可以用m行n列的矩阵形式表示，矩阵元素的值为0或1，其中值为0的元素，有时候也称之为零元素，表示该元素可以被Z*Z的全零矩阵(zero matrix)替换，值为1的元素，有时候也称之为非零元素，表示该元素可以被Z*Z的循环置换矩阵(circulant permutation matrix)替换。也就是说，每个矩阵元素代表的是一个全零矩阵或者一个循环置换矩阵。如图1中10a所示为一个示例性的m＝4，n＝20具有QC结构的LDPC码的基图中的各元素。需要说明的是，在本文中，基图和基矩阵的行号和列号均是从0开始编号的，仅仅是为了方便理解。可以理解的是，行号和列号也可以从1开始编号，则相应的行号和列号在本文所示的行号和列号基础上加1。
若基图中第i行第j列的元素值为1，其偏移值为Pi,j，Pi,j为大于或者等于0的整数，则表示第i行第j列的值为1的元素可以被Pi,j对应的Z*Z的循环置换矩阵替换，该循环置换矩阵可通过将Z*Z的单位矩阵进行Pi,j次向右循环移位得到。可见，将基图中每个值为0的元素用Z*Z的全零矩阵替换，每个值为1的元素采用其偏移值对应的Z*Z的循环置换矩阵进行替换，则可以得到LDPC码的奇偶校验矩阵。Z为正整数，也可以称之为扩展(lifting)因子，可以根据系统支持的码块大小和信息数据的大小确定的。可见奇偶校验矩阵H的大小为(m*Z)*(n*Z)。例如，扩展因子Z＝4，则每个零元素被一个4*4大小的全0矩阵11a替换，若P2,3＝2，则第2行第3列的非0元素被4*4的循环置换矩阵11d替换，该矩阵是由4*4的单位矩阵11b经过2次向右循环移位得到的，若P2,4＝0，则第2行第3列的非0元素被单位矩阵11b替换。需要说明的是，此处仅仅只是举例说明，并不以此为限制。
由于Pi,j可以是基于扩展因子Z得到的，对于同一个位置上值为1的元素，采用不同的扩展因子Z可能存在不同的Pi,j。为了简化实现，通常系统也会定义一个m行n列的基矩阵(base matrix)，在基矩阵中每个元素和基图中每个元素的位置一一对应，基图中的零元素在基矩阵中位置不变，采用-1表示，基图中第i行第j列值为1的非零元素在基矩阵中位置不变，可表示为Pi,j，Pi,j为大于或者等于0的正整数。在本申请实施例中，有时也将基 矩阵称为基图矩阵的偏移矩阵。若基于m行n列的基矩阵对输入序列进行编码，则基矩阵中每一列都可以对应编码后的比特序列中的Z个连续比特。
如图1中10b所示为基图10a对应的一个基矩阵。
通常LDPC码的基图或基矩阵中还可以包括p列内置打孔(built-in puncture)比特列，p可以为0～2的整数，这些列参与编码，但是其编码对应的系统比特不被发送，则LDPC码基矩阵的码率满足R＝(n-m)/(n-p)。对于一个4行20列(4*20)的基矩阵来讲，如果有2列内置打孔比特列，则码率为(20-4)/(20-2)＝8/9。
无线通信系统中采用的LDPC码，其基图的矩阵大小为m行n列，可以包括5个子矩阵A、B、C、D和E，其中，矩阵的权重是由非零元素的个数决定的，行的权重(行重)是指一行中包括的非零元素的个数，列的权重(列重)是指一列中包括的非零元素的个数。如图2中200所示，其中：
子矩阵A为mA行nA列的矩阵，其大小可以为mA*nA，其中每列对应LDPC码中的Z个系统比特，系统比特有时候也称为信息比特。
子矩阵B为为mA行mA列的方阵，其大小可以为mA*mA，每列对应于LDPC码中的Z个校验比特。子矩阵B包括双对角结构的子矩阵B’和一列权重为3的矩阵列(简称为3列重列)，其中列重为3的矩阵列位于子矩阵B’之前，如图2中20a所示；子矩阵B还可以包括一列重为1的矩阵列(简称为单列重列)，单列重列可以位于子矩阵B的首列或者最后一列，并且其中的非零元素在子矩阵B的最后一行，使得子矩阵B的最后一行的行重为1，如图2中20b或20c所示。
通常基于子矩阵A和B生成的矩阵为核心矩阵，可以用来支持高码率的编码。
子矩阵C为全零矩阵，其大小为mA×(n-(mA+nA))。
子矩阵E为单位矩阵，其大小为(m-mA)×(m-mA)。
子矩阵D大小为(m-mA)×(nA+mA)，通常可用来生成低码率的校验位。
图3所示为一个LDPC码的基图30a以及相应的基矩阵30b示例，其中该矩阵为46行68列，其中子矩阵A为第0行至第5行以及第0列至第21列构成的矩阵部分，子矩阵B为第0行至第5行以及第22列至第26列构成的矩阵部分。子矩阵A和子矩阵B构成了基矩阵的核心矩阵部分。
为了获得灵活的码率，可以基于核心矩阵添加相应大小的子矩阵C、子矩阵D和子矩阵E，来获得不同的码率。由于子矩阵C为全零矩阵，子矩阵为单位矩阵，其大小主要是根据码率来确定，结构相对固定。影响到编译码性能的主要在于核心矩阵和子矩阵D部分。在核心矩阵的基础上添加行列，形成相应的C、D和E部分可以得到不同码率。
子矩阵D的列数为子矩阵A和B的列数之和，其行数主要与码率相关。以基图30a为例，则相应的子矩阵D的列数mD为(nA+mA)＝27列，若LDPC码支持的码率为Rm，则其基图或者基矩阵的大小为m*n，其中，n＝nA/Rm+p，m＝n-nA＝nA/Rm+p-nA。若最低码率Rm＝1/3，内置打孔列数p＝2，以基图30a为例，则n＝68，m＝46，子矩阵D的行数mD最大可以为m-mA＝46-5＝41，也就是0≤mD≤41。
其中，基矩阵中可以包括2列内置打孔比特列，则打孔后，核心矩阵可以支持的码率为22/(27-2)＝0.88。如果需要获得更高的码率，则还需要对校验位进行打孔，也就是对子矩阵B、C、E中的列进行打孔。例如，以基图30a的第0行至第6行以及第0列至第27列构成的矩阵为例。基于该矩阵得到LDPC矩阵对输入序列进行编码后得到比特序列D，对内置打孔列对应的比特打孔，以及对第22列至第27列中任意两列对应的比特打孔，则比特序列D被打孔后的码率为22/24＝0.916。需要说明的是，此处仅为举例，还可以对更多校验列进行打孔，以获得更高的码率，此处不再赘述。
如图4所示，通信系统400包括通信设备40和通信设备41，控制信息或者数据信息作为信息序列在通信设备40和通信设备41之间接收和发送。以通信设备40发送信息序列为例，信息序列经过传输块CRC以及码块分割得到信道编码的输入序列C，输入序列C经过信道编码得到比特序列D，比特序列D经过速率匹配处理得到输出比特序列E，进一步经过交织、调制等处理并发送。通信设备41接收信息序列是上述发送过程的逆过程。其中速率匹配过程中，将根据码率确定对比特序列D的打孔以及选择，从而得到输出比特序列。为了保证高码率下打孔的性能，需要对比特序列D中校验位所在的列对应的比特顺序进行调整置换。在一个例子中，通信设备40可以为终端，相应的通信设备41可以为基站；在另一个例子中，通信设备40为基站，相应的通信设备41可以为终端。
图5为本发明一实施例提供的信息处理方法的流程图。该方法包括：
501：使用LDPC矩阵对输入序列进行编码得到比特序列D。
其中，LDPC矩阵的基图可以是前述示例中m行n列的矩阵，如基图30a。每一列对应所述比特序列D中一组Z个连续比特,n和Z均为大于0的整数。
502：基于比特序列V获取输出比特序列。
其中，所述比特序列V是对所述比特序列D中至少2列校验列对应的2组比特进行置换得到的。
根据前述示例可知，校验列可以是基矩阵中第n-m列至第n-1列，例如，对于基图30a，可以是第22列至第67列。
在对内置打孔列进行打孔后，为了进一步获取更高的码率，还可以对校验位打孔，需要打孔的列对应的比特需要进行置换以便进行打孔处理。
可以对所述基矩阵的第n-m列至第n-1列中至少2列对应的比特序列D中的至少两组比特进行置换，每组比特包括Z个连续比特。其中基矩阵列号从0开始编号。
其中，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列，所述基矩阵列号从0开始，可以理解的是，如果基矩阵列号从1开始，则相应地所述至少2列校验列为所述基矩阵的第n-m+1列至第n列中至少2列，在本文中，不做特别说明，矩阵的行号和列号均是从0开始，如果矩阵的行号和列号从1开始编号，则相应增加1即可。
对于基图30a，为了获得0.916码率的比特序列，可以对第22列至第27列这6列校验列中的2列进行打孔。
由于经过置换，所述比特序列V中第j组Z个连续比特为所述比特序列D中第P(j)组Z个连续比特，j为整数，且0≤j＜n。
在一种可能的实现方式中，这6列在比特序列V中的起始组号为a，则{P(a+i)|0≤i＜6}＝{22,23,24,25,26,27}。
对比特序列D中至少2列校验列对应的至少2组比特进行置换得到比特序列V，可以是对所述比特序列D中{P(a+i)|0≤i＜6}中至少2组Z个连续比特进行置换得到比特序列V。
根据前述示例说明，子矩阵B通常为双对角结构，也就是这几列的校验列存在双对角结构。由于打孔一般从后向前打孔，因此可以将需要打孔的s列置换到这6列中最后s列，s为大于0的整数，其他列可以根据需要调整顺序。
在一种可能的实现方式中，可以采用间隔打孔，例如将比特序列D中第24列和第26列置换到比特序列V中这6列中的最后2列，也就是P(a+5)＝26，P(a+4)＝24，如表1所示为{P(a+i)|0≤i＜6}各组可能的取值；或者P(a+5)＝24，P(a+4)＝26，如表2所示，为{P(a+i)|0≤i＜6}各组可能的取值。其中，表中每一列表示{P(a+i)|0≤i＜6}中各元素相应的取值，每一行是一组可能的取值组合。
表1
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 23 25 27 24 26
22 23 27 25 24 26
22 27 23 25 24 26
22 27 25 23 24 26
22 25 27 23 24 26
22 25 23 27 24 26
23 22 25 27 24 26
23 22 27 25 24 26
23 25 22 27 24 26
23 25 27 22 24 26
23 27 25 22 24 26
23 27 22 25 24 26
27 22 23 25 24 26
27 22 25 23 24 26
27 23 22 25 24 26
27 23 25 22 24 26
27 25 22 23 24 26
27 25 23 22 24 26
25 22 23 27 24 26
25 22 27 23 24 26
25 23 22 27 24 26
25 23 27 22 24 26
25 27 22 23 24 26
25 27 23 22 24 26
表2
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 23 25 27 26 24
22 23 27 25 26 24
22 27 23 25 26 24
22 27 25 23 26 24
22 25 27 23 26 24
22 25 23 27 26 24
23 22 25 27 26 24
23 22 27 25 26 24
23 25 22 27 26 24
23 25 27 22 26 24
23 27 25 22 26 24
23 27 22 25 26 24
27 22 23 25 26 24
27 22 25 23 26 24
27 23 22 25 26 24
27 23 25 22 26 24
27 25 22 23 26 24
27 25 23 22 26 24
25 22 23 27 26 24
25 22 27 23 26 24
25 23 22 27 26 24
25 23 27 22 26 24
25 27 22 23 26 24
25 27 23 22 26 24
在又一种可能的实现方式中，可以对双对角结构的中的列进行置换。例如，可以将比特序列D中第25列和第26列置换到比特序列V中这6列中的最后2列，也就是P(a+5)＝26，P(a+4)＝25，如表3所示为{P(a+i)|0≤i＜6}各种可能的取值；或者P(a+5)＝25，P(a+4)＝26，如表4所示，为{P(a+i)|0≤i＜6}各种可能的取值。又例如，也可以将比特序列D中第24列和第25列置换到比特序列V中这6列中的最后2列，也就是P(a+5)＝25，P(a+4)＝24，如表5所示为{P(a+i)|0≤i＜6}各种可能的取值；或者P(a+5)＝24，P(a+4)＝25，如表6所示，为{P(a+i)|0≤i＜6}各种可能的取值。又例如，也可以将比特序列D中第23列和第24列置换到比特序列V中这6列中的最后2列，也就是P(a+5)＝24，P(a+4)＝23，如表7所示为{P(a+i)|0≤i＜6}各种可能的取值；或者P(a+5)＝23，P(a+4)＝24，如表8所示，为{P(a+i)|0≤i＜6}各种可能的取值。
其中，各表中每一列表示{P(a+i)|0≤i＜6}中各元素相应的取值，每一行是一组可能的取值组合。
表3
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 23 24 27 25 26
22 23 27 24 25 26
22 24 23 27 25 26
22 24 27 23 25 26
22 27 23 24 25 26
22 27 24 23 25 26
23 22 24 27 25 26
23 22 27 24 25 26
23 24 22 27 25 26
23 24 27 22 25 26
23 27 22 24 25 26
23 27 24 22 25 26
24 22 23 27 25 26
24 22 27 23 25 26
24 23 22 27 25 26
24 23 27 22 25 26
24 27 22 23 25 26
24 27 23 22 25 26
27 22 23 24 25 26
27 22 24 23 25 26
27 23 22 24 25 26
27 23 24 22 25 26
27 24 22 23 25 26
27 24 23 22 25 26
表4
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 23 24 27 26 25
22 23 27 24 26 25
22 24 23 27 26 25
22 24 27 23 26 25
22 27 23 24 26 25
22 27 24 23 26 25
23 22 24 27 26 25
23 22 27 24 26 25
23 24 22 27 26 25
23 24 27 22 26 25
23 27 22 24 26 25
23 27 24 22 26 25
24 22 23 27 26 25
24 22 27 23 26 25
24 23 22 27 26 25
24 23 27 22 26 25
24 27 22 23 26 25
24 27 23 22 26 25
27 22 23 24 26 25
27 22 24 23 26 25
27 23 22 24 26 25
27 23 24 22 26 25
27 24 22 23 26 25
27 24 23 22 26 25
表5
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 23 26 27 24 25
22 23 27 26 24 25
22 26 23 27 24 25
22 26 27 23 24 25
22 27 23 26 24 25
22 27 26 23 24 25
23 22 26 27 24 25
23 22 27 26 24 25
23 26 22 27 24 25
23 26 27 22 24 25
23 27 22 26 24 25
23 27 26 22 24 25
26 22 23 27 24 25
26 22 27 23 24 25
26 23 22 27 24 25
26 23 27 22 24 25
26 27 22 23 24 25
26 27 23 22 24 25
27 22 23 26 24 25
27 22 26 23 24 25
27 23 22 26 24 25
27 23 26 22 24 25
27 26 22 23 24 25
27 26 23 22 24 25
表6
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 23 26 27 25 24
22 23 27 26 25 24
22 26 23 27 25 24
22 26 27 23 25 24
22 27 23 26 25 24
22 27 26 23 25 24
23 22 26 27 25 24
23 22 27 26 25 24
23 26 22 27 25 24
23 26 27 22 25 24
23 27 22 26 25 24
23 27 26 22 25 24
26 22 23 27 25 24
26 22 27 23 25 24
26 23 22 27 25 24
26 23 27 22 25 24
26 27 22 23 25 24
26 27 23 22 25 24
27 22 23 26 25 24
27 22 26 23 25 24
27 23 22 26 25 24
27 23 26 22 25 24
27 26 22 23 25 24
27 26 23 22 25 24
表7
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 25 26 27 23 24
22 25 27 26 23 24
22 26 25 27 23 24
22 26 27 25 23 24
22 27 25 26 23 24
22 27 26 25 23 24
25 22 26 27 23 24
25 22 27 26 23 24
25 26 22 27 23 24
25 26 27 22 23 24
25 27 22 26 23 24
25 27 26 22 23 24
26 22 25 27 23 24
26 22 27 25 23 24
26 25 22 27 23 24
26 25 27 22 23 24
26 27 22 25 23 24
26 27 25 22 23 24
27 22 25 26 23 24
27 22 26 25 23 24
27 25 22 26 23 24
27 25 26 22 23 24
27 26 22 25 23 24
27 26 25 22 23 24
表8
P(a) P(a+1) P(a+2) P(a+3) P(a+4) P(a+5)
22 25 26 27 24 23
22 25 27 26 24 23
22 26 25 27 24 23
22 26 27 25 24 23
22 27 25 26 24 23
22 27 26 25 24 23
25 22 26 27 24 23
25 22 27 26 24 23
25 26 22 27 24 23
25 26 27 22 24 23
25 27 22 26 24 23
25 27 26 22 24 23
26 22 25 27 24 23
26 22 27 25 24 23
26 25 22 27 24 23
26 25 27 22 24 23
26 27 22 25 24 23
26 27 25 22 24 23
27 22 25 26 24 23
27 22 26 25 24 23
27 25 22 26 24 23
27 25 26 22 24 23
27 26 22 25 24 23
27 26 25 22 24 23
由于内置打孔列通常为2列，如第0列和第1列。在一种可能的实现方式中，比特 序列D中内置打孔列对应的2组比特可能会置换到比特序列V中的最后2组，因此一种可能的置换顺序如表9所示，从左至右从上至下顺序，为比特序列V中各组比特对应于比特序列D中P(j)组比特的示意，例如，比特序列V中第0组比特为比特序列D中第2组比特，第1组比特为比特序列D中第3组比特，以此类推，不一一赘述。第20组比特为比特序列中P(a)，也就是a＝20，第65组比特为比特序列D中第67组比特，比特序列D中第0组和第1组比特被放在比特序列V中第66组和第67组的位置。其中，{P(a+i)|0≤i＜6}可以是表1至表8中任一组可能的取值组合。
表9
Figure PCTCN2017086458-appb-000001
在上述实现方式中，如果采用表9所示的置换顺序，在进行初传时可以将比特序列V的第0比特作为起始位置从而获取输出比特序列E，在这种方式下，重传时仍有可能获取到内置打孔列对应的2组比特。
在又一种可能的实现方式中，比特序列D中内置打孔列对应的2组比特不做置换，可能的置换顺序如表10所示，从左至右从上至下顺序，为比特序列V中各组比特对应于比特序列D中P(j)组比特的示意，例如，比特序列V中第0组比特为比特序列D中第0组比特，第1组比特为比特序列D中第1组比特，以此类推，不一一赘述。第22组比特为比特序列中P(a)，也就是a＝22，第67组比特为比特序列D中第67组比特。其中，{P(a+i)|0≤i＜6}可以是表1至表8中任一组可能的取值组合。
表10
Figure PCTCN2017086458-appb-000002
在上述实现方式中，如果采用表10所示的置换顺序，在进行初传时可以将比特序列V的第2*Z比特作为起始位置从而获取输出比特序列E，也就是跳过第0组比特和第1组比特，在这种方式下，重传时仍有可能获取到内置打孔列对应的2组比特。
在又一种可能的实现方式中，比特序列D中内置打孔列对应的2组比特直接丢弃，因此置换顺序如表11所示，从左至右从上至下顺序，为比特序列V中各组比特对应于比特序列D中P(j)组比特的示意，例如，比特序列V中第0组比特为比特序列D中第2组比特，第1组比特为比特序列D中第3组比特，以此类推，不一一赘述。第20组比特为比特序列中P(a)，也就是a＝20，第65组比特为比特序列D中第67组比特。其中，{P(a+i)|0≤i＜6}可以是表1至表8中任一组可能的取值组合。
表11
Figure PCTCN2017086458-appb-000003
Figure PCTCN2017086458-appb-000004
在上述实现方式中，如果采用表11所示的置换顺序，在进行初传时可以将比特序列V的第0比特作为起始位置从而获取输出比特序列E，由于内置打孔列对应的2组比特被丢弃，则无论是初传还是重传，输出比特序列都不包括内置打孔列对应的2组比特，也就是比特序列D中的第0组和第1组比特。
本发明实施例提供的信息处理方法，为了获得较高的码率，对校验位进行打孔，由于对编码后的比特序列处理考虑打孔校验列，从而对这些列对应的比特组进行了置换，使得每一行被打孔的元素减少，因而可以满足高码率下LDPC码的性能需求。图8所示为基图30a的LDPC矩阵在码率为0.93时，输入序列长度为512时置换前后的性能对比示意图，其中，“原始顺序”为基图30a的LDPC矩阵没有对打孔的校验列进行置换时在不同Es/N0下的性能曲线，可以看到其BLER为1，无法正常工作。而“交换后顺序”为基图30a的LDPC矩阵根据本发明实施例提供的信息处理方法，对打孔的校验列进行置换后在不同Es/N0下的的性能曲线，可以看到同样的Es/N0下，BLER下降，性能较好。
图6给出了本发明另一实施例提供的信息处理方法，所述方法包括:
601：获取基于低密度奇偶校验LDPC矩阵编码的信号；
通信系统400中，通信设备41作为接收端的通信设备，获取通信设备40发送的基于LDPC矩阵编码的信号。
602：基于所述信号获取软值序列V；
通信设备40向通信设备41发送如前述各实施例中得到的输出比特序列，可以理解的是，上述实施例中的输出比特序列是速率匹配后的输出比特序列，所述通信设备40可以对速率匹配后的输出比特序列进行交织调制等处理，从而发送对应于所述输出比特序列的发送信号，通信设备41接收所述输出信号并经解调、解交织后，得到输出比特序列对应的软值序列，也就是输出比特序列中一个比特对应软值序列中一个软值比特(soft channel bit)。这些软值比特在通信设备41的软信息缓存中保存的位置和通信设备40中循环缓存中的编码块的位置一一对应，软信息缓存的大小与循环缓存中的编码块的大小也是相同的，都可以是NCB。
例如，通信设备40发送的输出比特为1，经过信道传输，通信设备41得到其相应的软值比特为1.45，如果输出比特在编码块中的位置为第5比特，则在通信设备41的软信息缓存中第5软值比特为1.45。需要说明的是此处只是举例说明，本发明实施例并不限于此。如果通信设备40获取的输出比特序列中包括n个输出比特，则通信设备41可以获取到n个对应的软值比特。如果通信设备41两次接收到同一位置的软值比特，则将两次的软值进行合并，例如，第一次传输时接收到的软值比特为1.45，第二次传输时接收到的软值比特为0.5，则合并后为1.95。需要说明的是，此处仅为举例，并不以此为限制。
通信设备41对601获取到的信号经过解调等处理后得到软值序列V’。比特序列V中一个比特对应软值序列V’中一个软值比特(soft channel bit)。
603：使用所述LDPC矩阵对软值序列D’进行译码；
其中，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述软值序列D’中一组Z个连续的软值比特,n和Z均为大于0的整数；
其中，所述软值序列V’中第j组Z个连续的软值比特为所述软值序列D’中第P(j)组Z个连续的软值比特，j为整数，且0≤j＜n；
其中，所述软值序列V’是所述软值序列D’中至少2列校验列对应的2组比特经过置换得到的，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列。
可见置换的校验列的位置具备和前述各实施例相应的特征，可以参见前述各实施例所述，此处不在赘述。只是在通信设备41中描述是软值序列V’和软值序列D’，通信设备40中则是比特序列V和比特序列D。
图7给出了一种通信装置700的结构示意图，通信装置700可用于实现上述方法实施例中描述的方法，可以参见上述方法实施例中的说明。所述通信装置700可以是芯片，基站，终端或者其他网络设备。
所述通信装置700包括一个或多个处理器701。所述处理器701可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理，中央处理器可以用于对通信装置(如，基站、终端、或芯片等)进行控制，执行软件程序，处理软件程序的数据。
在一种可能的设计中，所述通信装置700包括一个或多个所述处理器701，所述一个或多个处理器701可实现图5所示方法实施例中的方法，在另一种可能的设计中，处理器701除了实现图5所示方法实施例中的方法，还可以实现其他功能。
所述通信装置700使用低密度奇偶校验LDPC矩阵对输入序列进行编码得到比特序列D，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述比特序列D中一组Z个连续比特,n和Z均为大于0的整数；基于比特序列V获取输出比特序列，其中，所述比特序列V是对所述比特序列D中至少2列校验列对应的2组比特进行置换得到的，其中，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列，所述比特序列V中第j组Z个连续比特为所述比特序列D中第P(j)组Z个连续比特，j为整数，且0≤j＜n。
在一种可能的设计中，一个或多个所述处理器701可实现图6所示的方法实施例中的方法，在另一种可能的设计中，处理器701除了实现图6所示方法实施例中的方法，还可以实现其他功能。
所述通信装置700可用于基于低密度奇偶校验LDPC矩阵编码的信号获取软值序列V’；使用所述LDPC矩阵对软值序列D’进行译码；其中，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述软值序列D’中一组Z个连续的软值比特,n和Z均为大于0的整数；其中，所述软值序列V中第j组Z个连续的软值比特为所述软值序列D’中第P(j)组Z个连续的软值比特，j为整数，且0≤j＜n；其中，所述软值序列V’是所述软值序列D’中至少2列校验列对应的2组比特经过置换得到的，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列。
可选的一种设计中，处理器701也可以包括指令703，所述指令可以在所述处理器上被运行，使得所述通信装置700执行上述方法实施例中描述的方法。
在又一种可能的设计中，通信装置700也可以包括电路，所述电路可以实现前述方法实施例中方法。
可选的，所述通信装置700中可以包括一个或多个存储器702，其上存有指令704，所述指令可在所述处理器上被运行，使得所述通信装置700执行上述方法实施例中描述的方法。可选的，所述存储器中还可以存储有数据。可选的处理器中也可以存储指令和/或数据。所述处理器和存储器可以单独设置，也可以集成在一起。可选的，一个或多个存储器702可以存储与基矩阵相关的参数，例如偏移值，基图，基于基图扩展到矩阵、基矩阵中的各行，扩展因子等等。可选的，所述一个或者多个存储器702可以存储基矩阵或者基于基矩阵扩展到矩阵。
可选的，所述通信装置700还可以包括收发器705以及天线706。所述处理器701可以称为处理单元，对通信装置(终端或者基站)进行控制。所述收发器705可以称为收发单元、收发机、收发电路、或者收发器等，用于通过天线706实现通信装置的收发功能.
可选的，所述通信装置700还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、或者用于调制处理的调制器等。可以通过一个或多个处理器701实现这些器件的功能。
可选的，所述通信装置700还可以包括，用于解调操作的解调器、用于解交织的解交织器、或者用于解速率匹配的器件等等。可以通过一个或多个处理器701实现这些器件的功能。
本领域技术任何还可以了解到本发明实施例列出的各种说明性逻辑块(illustrative logical block)和步骤(step)可以通过电子硬件、电脑软件，或两者的结合进行实现。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用，可以使用各种方法实现所述的功能，但这种实现不应被理解为超出本发明实施例保护的范围。
本发明实施例中所描述的各种说明性的逻辑单元和电路可以通过通用处理器，数字信号处理器，专用集成电路(ASIC)，现场可编程门阵列(FPGA)或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合的设计来实现或操作所描述的功能。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。
本发明实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的指令、或者这两者的结合。存储器可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介。示例性地，存储器可以与处理器连接，以使得处理器可以从存储器中读取信息，并可以向存储器存写信息。可选地，存储器还可以集成到处理器中。处理器和存储器可以设置于ASIC中，ASIC可以设置于UE中。可选地，处理器和存储器也可以设置于UE中的不同的部件中。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件程序实现时，可以全部 或部分地以计算机程序产品的形式实现，所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本发明实施例所述的流程或功能。当使用软件程序实现时，也可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定义中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (21)

  1. 一种信息处理的方法，其特征在于，所述方法包括：
    使用低密度奇偶校验LDPC矩阵对输入序列进行编码得到比特序列D，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述比特序列D中一组Z个连续比特,n和Z均为大于0的整数；
    基于比特序列V获取输出比特序列，其中，所述比特序列V是对所述比特序列D中至少2列校验列对应的2组比特进行置换得到的，其中，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列，所述比特序列V中第j组Z个连续比特为所述比特序列D中第P(j)组Z个连续比特，j为整数，且0≤j＜n。
  2. 根据权利要求1所述的方法，其特征在于，所述至少2列校验列为所述基矩阵的{P(a+i)|0≤i＜6}中至少2列，其中{P(a+i)|0≤i＜6}＝{22,23,24,25,26,27}；
    所述对所述比特序列D中至少2列校验列对应的2组比特进行置换得到比特序列V，包括：
    对所述比特序列D中{P(a+i)|0≤i＜6}中至少2组Z个连续比特进行置换得到比特序列V。
  3. 根据权利要求1或2所述的方法，其特征在于，
    P(a+5)＝26，P(a+4)＝24或者P(a+4)＝25；或者，
    P(a+5)＝25，P(a+4)＝24或者P(a+4)＝26；或者，
    P(a+5)＝24，P(a+4)＝23或者P(a+4)＝25或者P(a+4)＝26；或者，
    P(a+5)＝23，P(a+4)＝24。
  4. 根据权利要求2或3所述的方法，其特征在于，a＝20或者a＝22。
  5. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表1中任一组取值。
  6. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表2中任一组取值。
  7. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表3中任一组取值。
  8. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表4中任一组取值。
  9. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表5中任一组取值。
  10. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表6中任一组取值。
  11. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表7中任一组取值。
  12. 根据权利要求2至4任一项所述的方法，其特征在于，所述{P(a+i)|0≤i＜6}包括表8中任一组取值。
  13. 根据权利要求1至12任一项所述的方法，其特征在于，所述基于所述比特序列 V获取输出比特序列包括：
    a＝20，以所述比特序列V的第0比特作为起始位置获取输出比特序列；或者，
    a＝20，以所述比特序列V的第0比特作为起始位置获取输出比特序列，且所述输出比特序列不包括所述比特序列D中第0组和第1组比特；或者，
    a＝22，以所述比特序列V的第2*Z比特作起始位置获取输出比特序列。
  14. 一种信息处理的方法，其特征在于，所述方法包括：
    基于低密度奇偶校验LDPC矩阵编码的信号获取软值序列V’；
    使用所述LDPC矩阵对软值序列D’进行译码；
    其中，所述LDPC矩阵的基矩阵表示为m行n列的矩阵，每一列对应所述软值序列D’中一组Z个连续的软值比特,n和Z均为大于0的整数；
    其中，所述软值序列V中第j组Z个连续的软值比特为所述软值序列D’中第P(j)组Z个连续的软值比特，j为整数，且0≤j＜n；
    其中，所述软值序列V’是所述软值序列D’中至少2列校验列对应的2组比特经过置换得到的，所述至少2列校验列为所述基矩阵的第n-m列至第n-1列中至少2列。
  15. 一种装置，用于执行如权利要求1至14项任一项所述的方法。
  16. 一种通信装置，其特征在于，所述通信装置包括处理器、存储器以及存储在存储器上并可在处理器上运行的指令，当所述指令被运行时，使得所述通信装置执行如权利要求1至14项任一项所述的方法。
  17. 一种终端，其特征在于，包括如权利要求15所述的装置或权利要求16所述的通信装置。
  18. 一种基站，其特征在于，包括如权利要求15所述的装置或权利要求16所述的通信装置。
  19. 一种通信系统，其特征在于包括如权利要求17所述的终端以及如权利要求18所述的基站。
  20. 一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1至14任一项所述的方法。
  21. 一种计算机程序产品，当其在计算机上运行时，使得计算机执行权利要求1至14任一项所述的方法。
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