WO2019029690A1 - 通信方法和装置 - Google Patents

通信方法和装置 Download PDF

Info

Publication number
WO2019029690A1
WO2019029690A1 PCT/CN2018/099904 CN2018099904W WO2019029690A1 WO 2019029690 A1 WO2019029690 A1 WO 2019029690A1 CN 2018099904 W CN2018099904 W CN 2018099904W WO 2019029690 A1 WO2019029690 A1 WO 2019029690A1
Authority
WO
WIPO (PCT)
Prior art keywords
code rate
coding matrix
matrix type
mcs index
sequence
Prior art date
Application number
PCT/CN2018/099904
Other languages
English (en)
French (fr)
Inventor
马亮
曾歆
郑晨
刘晓健
魏岳军
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710807911.9A external-priority patent/CN109391367B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18842878.3A priority Critical patent/EP3657707B1/en
Publication of WO2019029690A1 publication Critical patent/WO2019029690A1/zh
Priority to US16/787,958 priority patent/US11368241B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the embodiments of the present application relate to the field of communications, and in particular, to a communication method and apparatus.
  • Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
  • the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
  • LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
  • an LDPC matrix with special structured features can be used.
  • the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
  • QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
  • the LDPC matrix can be designed to be applied to channel coding.
  • QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
  • the LDPC matrix can be designed to be applied to channel coding.
  • the embodiment of the present application provides a communication method and apparatus, which can reasonably select an encoding matrix type for encoding.
  • a communication method including: determining an encoding matrix type according to at least a length of a first sequence, encoding a first sequence based on an encoding matrix corresponding to the encoding matrix type, and further, when the length of the first sequence When less than or equal to the first threshold, the coding matrix type may be determined according to the MCS index.
  • the first sequence is obtained by dividing a second sequence by a code block, and the length of the second sequence is related to the MCS index.
  • the coding matrix type is determined by inputting the length of the sequence of the encoder and the MCS index, and the coding matrix type is reasonably selected, which can reduce the decoding delay and improve the decoding performance under the premise of ensuring the normal operation of the system.
  • the coding matrix type corresponding to the MCS index is determined by using the correspondence between the MCS index and the coding matrix type.
  • the coding matrix type and the MCS index are bound, which can increase the robustness of the system.
  • the coding matrix type may be configured according to the granularity of N PRB for all or part of the MCS index.
  • the MCS index corresponds to M N PRBs
  • M is a positive integer
  • the coding matrix type is determined according to the N PRB and MCS indexes.
  • it may be that for all MCS indexes, under each MCS index, the N PRB whose value is less than or equal to the second threshold corresponds to the second coding matrix type, and the other possible manner may be for the part.
  • the MCS index may be configured to configure the coding matrix type according to the granularity of the N PRB according to the MCS index that the difference between the at least two code rates of the M code rates is greater than the third threshold, and may specifically be a value that is less than or equal to the second threshold.
  • the PRB corresponds to the second coding matrix type.
  • the code rate corresponding to the MCS index is determined by using the correspondence between the MCS index and the code rate; and the coding matrix type is determined according to the code rate and the code rate threshold.
  • the code rate and the code rate threshold may be floating point numbers or fractions.
  • the code rate index corresponding to the MCS index may be determined by using a correspondence between the MCS index and the code rate index; and the code rate corresponding to the code rate index is searched according to the code rate index; according to the code rate and the code rate
  • the threshold determines the type of encoding matrix.
  • the determining the coding matrix type according to the code rate and the code rate threshold may be: comparing the code rate with the code rate threshold to determine the coding matrix type, for example, when the code rate is greater than the code rate threshold, determining the first coding matrix type; Alternatively, when the code rate is less than or equal to the code rate threshold, it is determined that the second coding matrix type is obtained. In the above manner, it is also possible to avoid calculating the code rate each time the coding matrix type is determined, and indirectly binding the MCS index to the coding matrix type, which can increase the robustness of the system.
  • the size of the coding matrix corresponding to the first coding matrix type is larger than the size of the coding matrix corresponding to the second coding matrix type.
  • the coding matrix type is determined according to an MCS index by means of a look-up table.
  • the coding matrix type in the above method includes a base map.
  • a communication method is also provided, which is applicable to a decoding process, and the decoding process corresponds to the communication method described in the first aspect, and the coding matrix type is determined in the same manner as the communication method in the first aspect. Further determining the coding matrix.
  • a communication apparatus can include a corresponding module for performing the communication method design of the first aspect or the second aspect described above.
  • the module can be software and/or hardware.
  • a communication device provided by the third aspect includes a processor and a transceiver component that can be used to implement the functions of various portions of the encoding or decoding method described above.
  • the transceiver component if the communication device is a terminal, a base station or other network device, the transceiver component thereof may be a transceiver. If the communication device is a baseband chip or a baseband single board, the transceiver component may be a baseband chip or a baseband single board. Input/output circuits for receiving/transmitting input/output signals.
  • the communication device can optionally also include a memory for storing data and/or instructions.
  • the above communication device may be a chip, a terminal or a base station.
  • an embodiment of the present application provides a communication system, where the system includes the communication device described in the foregoing third aspect.
  • an embodiment of the present application provides a computer storage medium having a program stored thereon that, when executed, causes a computer to perform the method described in the above aspect.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • 1 is a schematic diagram of a base diagram of an LDPC code
  • FIG. 2 is a schematic diagram of a communication method according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a base diagram of an LDPC code
  • FIG. 4 is a schematic structural diagram of a communication apparatus according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a communication apparatus according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a communication system according to an embodiment of the present application.
  • the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
  • a terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
  • the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
  • a base station is called an evolved Node B (eNB or eNodeB).
  • eNB evolved Node B
  • NR transmission reception point
  • gNB next generation node B
  • Base stations in other various evolved networks may also adopt other names. This application is not limited to this.
  • a sequence is a bit string consisting of bits "0" and/or "1".
  • the length of the sequence refers to the number of bits included in the sequence. For example, sequence 00 includes 2 bits and has a length of 2; sequence 111 includes 3 bits of length 3; sequence "0100" includes 4 bits and has a length of 4.
  • a transport block (transport blocB, TB) and a code block (code blocB, CB) can all be regarded as a sequence.
  • the code block is obtained by dividing the transport block or the processed transport block, and is an encoded object. Therefore, in the present application, the code block length refers to the number of bits included in the code block, and the code block length may also be referred to as code block size (CBS); the transport block length refers to the transport block. The number of bits included, the transport block length may also be referred to as a transport block size (TBS). It will be appreciated that as technology advances, transport blocks or code blocks may have different terminology names.
  • the processed transport block may also be understood as a transport block, and the process may be to add a check bit on the basis of the initial transport block, for example, adding a cyclic redundancy check (CRC) bit.
  • CRC cyclic redundancy check
  • the code rate mentioned refers to the code rate adopted by the sequence to be encoded.
  • LDPC codes can usually be represented by a parity check matrice (sometimes referred to as a base matrix).
  • the parity check matrix of the LDPC code can be pre-configured, pre-configured, or pre-stored.
  • the parity check matrix of the LDPC code can also be represented by a base graph (abbreviated as BG) and a shift value V i,j .
  • the base graph (BG for short) and the shift value V i,j may be agreed upon by the protocol, pre-configured, or pre-stored.
  • the parity check matrix and the base map may each be represented by a matrix of m rows and n columns, where m, n are positive integers.
  • the size of the parity checker and the size of the base map may be represented by the number of rows and columns of the matrix, or by the number of matrix elements included.
  • the size of the parity check matrix may correspond to the size of the base map.
  • the number of rows and the number of columns of the parity check matrix are the same as the number of rows and columns of the base map, and can also be understood as the number of rows and columns of the parity check matrix, respectively. There is a correspondence between the number of rows/columns of the base map.
  • the base map can usually include m*n matrix elements.
  • the value of the matrix element is 0 or 1.
  • the element with a value of 0 can also be represented as null.
  • the base map can be used to indicate the location of the offset value, and the non-zero elements in the base map correspond to the offset values.
  • An example of a base map of 5 rows and 27 columns is shown as 10a in Fig.
  • the row index (row number) and column index (column number) of the base and base matrices are numbered from 0. It can be understood that the row number and column number can also be numbered from 1 or other values. Start numbering, as long as you can index to the corresponding row and column.
  • the required BG size can vary depending on system requirements.
  • the BG can be classified based on the BG size.
  • the type of BG may be specified, pre-defined, pre-configured, or pre-stored by the protocol, each type BG being different in size (ie, the number of rows and/or the number of columns of the matrix is different).
  • Table 1 gives a distributed locations respectively corresponding to non-zero elements BG1 and BG2 H BG of the possible forms.
  • a base map can be regarded as a kind of coding matrix, and the base map can be understood as a representation of the type of the coding matrix.
  • the coding matrix type may also include the type of the parity check matrix.
  • an encoding matrix type represents a structure of an encoding matrix, where the structure of the encoding matrix includes the size of the encoding matrix, zero elements in the encoding matrix, and/or non- The positional distribution of zero elements in the coding matrix.
  • Each coding matrix type may correspond to at least one coding matrix, and the structure of at least one coding matrix corresponding to each coding matrix type is the same, except that the specific values of the non-zero elements are not exactly the same (that is, partially identical or different)
  • BG1 can correspond to 8 coding matrices.
  • there may be other differences between the different coding matrix types which is not limited by the embodiment of the present application.
  • At least two coding matrix types may be included, and the following two coding matrix types: a first coding matrix type and a second coding matrix type are exemplified.
  • the size of the coding matrix corresponding to the first coding matrix type is larger than the size of the coding matrix corresponding to the second coding matrix type. Due to the size of the coding matrix, the design supports a different range of coding block lengths and coding rate.
  • BG1 may correspond to a first coding matrix type
  • BG2 may correspond to a second coding matrix type.
  • the first coding matrix type is BG1, which supports a minimum coding rate of 1/3, a maximum of at least 0.89, a supported block length of at least 40 bits, and a minimum supported block length of at least 512 bits.
  • the block length is 8448 bits.
  • the supported code rate is at least 1/5
  • the maximum is at least 0.67
  • the supported block length is up to 40 bits
  • the maximum can be up to 2560 bits.
  • a reasonable coding matrix type selection method is to select a matrix with a smaller Kb value (for example, a second coding matrix type) when the code length and the code rate are the same and both coding matrix types are supported.
  • the embodiment of the present application provides a communication method, which is implemented by a communication device.
  • the communication device may be a terminal or A chip that can be used for a terminal.
  • the communication device can be a base station or a chip that can be used for a base station.
  • the communication method can include:
  • the first sequence can be understood as the sequence of the input encoder to be encoded, which can be expressed as c 0 , c 1 , c 2 , c 3 , . . . , c K-1 .
  • the first sequence may be a code block after code block division of the transport block, and the length of the input sequence is also a code block size (CBS).
  • the transport block can also be referred to as a second sequence.
  • code block segmentation refers to a process of inputting a transmission block to be processed and outputting the sequence to be encoded, and the sequence to be encoded may be referred to as a code block. That is to say, code block segmentation can be understood as the process from the transport block to the code block.
  • the code block segmentation may be different. For example, it may be determined whether the transport block is divided into one or more code blocks according to whether the transport block size is greater than the split threshold. It can be understood that even if the transport block size is smaller than the split threshold, the transport block is reserved as one code block, which can be regarded as undergoing the code block split operation.
  • the transport block may or may not be processed before the partitioning, wherein the processing of the transport block before the splitting may be to add a check bit on the basis of the initial transport block, for example, adding a CRC bit;
  • the obtained code block may be processed or not processed before being input to the encoder, and the processing of the code block may be, for example, adding a check bit, for example, adding a CRC, or the processing of the code block may further include
  • the padding bit is added, which is not limited in this embodiment of the present application.
  • the length of the first sequence may be the length of the code block after the check bit is added, or may be the length of the code block before the check bit is added. There is no limit to this.
  • the size of the segmentation threshold may be a preset fixed value, and the segmentation threshold may be determined directly or indirectly according to a modulation and coding scheme (MCS) index.
  • MCS modulation and coding scheme
  • the determining the segmentation threshold according to the MCS index may be: searching for the segmentation threshold corresponding to the MCS index according to the correspondence between the MCS index and the segmentation threshold; and determining the segmentation threshold according to the MCS index indirectly: obtaining the corresponding code according to the MCS index After the rate is determined, the segmentation threshold is determined according to the code rate.
  • the method for determining the segmentation threshold and the value of the segmentation threshold are not limited in this embodiment of the present application. It can be understood that the MCS index may be an MCS index value or an MCS index interval.
  • the coding matrix type may be determined to be the first coding matrix type.
  • the coding matrix type may be determined according to the MCS index. That is, when the coding matrix type is determined according to the MCS index, the length of the first sequence is less than or equal to the first threshold.
  • a correspondence between an MCS index and an encoding matrix type may be established.
  • the type of the coding matrix is determined based on the MCS index and the correspondence.
  • the correspondence between the MCS index and the coding matrix type can be established through protocol, pre-configuration, pre-storage, or signaling.
  • the MCS index and the coding matrix type may be a direct correspondence or an indirect correspondence.
  • a correspondence list of the MCS index and the coding matrix type is stored, and the corresponding coding matrix type is determined by looking up the table.
  • the coding matrix type determined in the above manner may be referred to as the coding matrix type of the first sequence.
  • the first threshold is a preset value, and may be, for example, 2560 or 3840. It can be understood that, for different manners of defining the length of the first sequence, the first threshold may have different settings. For example, if the length of the first sequence does not include the length of the code block of the check bit, the first threshold is considered. The sequence length of the check bit is deducted, for example, may be 3816, 3824, 2536, 2544, etc., or if the length of the first sequence is not including the code block length of the check bit, the value of the first threshold may not be considered.
  • the length of the first sequence or the first threshold may be processed and then compared, for example, comparing the length of the first sequence with the second preset value and comparing with the first threshold. Or comparing the length of the first sequence with the value after the first threshold is subtracted from the second preset value.
  • the network device may determine the MCS index according to a channel quality indicator (CQI) fed back by the terminal (for example, the terminal feedback CQI in the scheduling process).
  • CQI channel quality indicator
  • the network device can derive the transport block size based on the determined MCS index, ie the length of the second sequence.
  • the corresponding TBS index can be obtained according to the MCS index, so that the size of the transport block can be obtained by combining the TBS index and the N PRB , where N PRB represents a hybrid automatic repeat request (HARQ).
  • N PRB represents a hybrid automatic repeat request
  • the number of resource blocks herein may be the number of resource blocks actually allocated, or the number of normalized resource blocks.
  • the TBS is related to the MCS index.
  • the embodiment of the present application does not limit how to obtain the TBS according to the MCS index.
  • Table 2 gives an example of the correspondence between MCS index (I MCS ), TBS index (I TBS ), and modulation mode (Q m ).
  • Table 3 shows a TBS index (I TBS ) and N PRB.
  • the transport block size can be obtained based on Table 2 and Table 3. It can be understood that the deformation is also made based on Table 2 or Table 3, or the corresponding correspondence is expressed in other forms or contents different from Table 2 or Table 3 to obtain the size of the transport block. This embodiment of the present application does not limit this.
  • the modulation mode column in Table 2 is optional.
  • the correspondence between the MCS index and the code rate may be established, and the code rate is determined based on the correspondence between the MCS index and the code rate, and then the TBS is determined according to the code rate and the N PRB .
  • the correspondence between the MCS index and the code rate can be established by using a protocol, a pre-configuration, a pre-storage, or a signaling indication.
  • the MCS index can also be referred to as the MCS level.
  • a network device (such as a base station, etc.) can transmit the determined MCS index to the terminal, so that the terminal can determine the coding matrix type using the received MCS index.
  • the first sequence may be encoded based on an encoding matrix corresponding to the determined coding matrix type.
  • the coding matrix may be determined according to the value of the spreading factor, and the value of the spreading factor may be determined by the code block length obtained after the code block is divided.
  • the decoding delays of different coding matrix types are different, and the decoding performance also has some differences.
  • the coding block length and code rate supported by different coding matrix types are also used. Different, even if the code rate and the block length are both supported, the decoding delay and the performance are different.
  • the foregoing communication method provided by the embodiment of the present application determines the type of the coding matrix by inputting the length of the sequence of the encoder and the MCS index. Selecting the coding matrix type can reduce the decoding delay and improve the decoding performance under the premise of ensuring the normal operation of the system.
  • the coding matrix type may be determined according to the MCS index in one of the following manners:
  • Mode (1) determining a coding matrix type corresponding to the MCS index by using a correspondence between an MCS index and an encoding matrix type.
  • the correspondence between the MCS index and the coding matrix type may be stored in a memory of the communication device, wherein each coding matrix type is represented by a different value.
  • the correspondence between the MCS index and the coding matrix type can be, for example, as shown in Table 4, wherein the coding matrix type corresponding to the value "2" in Table 4 can be referred to as the second coding matrix type, and the coding matrix type corresponding to the value "1". It can be called the first coding matrix type.
  • the correspondence between the MCS index and the coding matrix type may be expressed in other forms or contents different from the table 4, which is not limited in this embodiment of the present application.
  • the modulation scheme and TBS index column in Table 4 are optional.
  • the correspondence between the MCS index and the coding matrix type in the embodiment of the present application may be the correspondence between the MCS index value and the coding matrix type, or may be the correspondence between the MCS index interval and the coding matrix type. The application embodiment does not limit this.
  • the complete information of the correspondence between the MCS index and the coding matrix type in Table 4 can be saved in the memory, and in order to further save memory usage, only part of the information can be saved, for example, only the value stored in Table 3 is saved.
  • 1) other information such as the MCS index involved in the corresponding coding matrix type, and the coding matrix type corresponding to the other unsaved MCS index is the second coding matrix type.
  • the correspondence relationship as shown in Table 4 can also be simplified to the form of Table 5, and the other coding matrix types "2" corresponding to the MCS indexes not listed in Table 5 are used.
  • the foregoing correspondence may be that the correspondence between the MCS index and the coding matrix type may be obtained by considering a corresponding code rate of each MCS index. For example, if the coded code rate of all the TBSs corresponding to the MCS index is less than the code rate threshold, the MCS index may correspond to the second coding matrix type, for example, BG2; if for some MCS index, the corresponding all TBSs are encoded. If the code rate is greater than the code rate threshold, the MCS index corresponds to the first coding matrix type, for example, BG1; if for a certain MCS index, the coded code rate of the corresponding TBS is partially greater than the code rate threshold, and a part is less than the code rate threshold. Or the corresponding coded code rate is only slightly larger than the code rate threshold, and the coding matrix type corresponding to the MCS index may be set to the first coding matrix type or the second coding matrix type according to the actual situation.
  • the application examples are not limited.
  • the code rate is related to many parameters, including the number of RBs allocated by the system, the number of information symbols carried in each RB, the modulation order, etc.
  • the calculated code rate may be different.
  • the method of calculating the code rate and comparing with the code rate threshold before selecting the coding matrix type each time not only makes the calculation process cumbersome, but also reduces the robustness of the system due to the inconsistent understanding between the transmitting end and the receiving end and the different precision.
  • binding the coding matrix type and the MCS index may increase the robustness of the system. Because the MCS index of the sender and the receiver can be aligned by control signaling. At the same time, the expected coding rate under each MCS index is very close, and the coding matrix type under the corresponding MCS index can be determined through pre-configuration.
  • the above code rate threshold may be a predefined value, for example, 2/3.
  • a certain margin may be left on the predefined value, for example, 2/3 is raised to 0.7.
  • one MCS index may correspond to M N PRBs , and in order to implement the coding matrix type configuration more flexibly, the coding matrix type may be configured according to the granularity of N PRB for all or part of the MCS index. The coding matrix type can then be determined from the N PRB and MCS indices. Where M is a positive integer.
  • each MCS index value is less than or equal to the second threshold value matrix N PRB corresponding to a second type of coding, e.g. BG2, the second threshold value is greater than N PRB corresponding value
  • the first encoding matrix type such as BG1.
  • an MCS index whose difference between at least two code rates of the M code rates is greater than a third threshold may be configured according to the granularity of the N PRB .
  • the N PRB whose value is less than or equal to the second threshold corresponds to the second coding matrix type, for example, BG2
  • the N PRB whose value is greater than the second threshold corresponds to the first coding matrix type, for example, BG1.
  • the predefined value is, for example, 2/3.
  • the correspondence between the MCS index and the code rate may be saved in a memory of the communication device, and the correspondence between the MCS index and the code rate may be, for example, as shown in Table 7. It is to be understood that the correspondence between the MCS index and the code rate may be expressed in other forms or contents different from those in Table 7. This embodiment of the present application does not limit this.
  • the modulation scheme and TBS index column in Table 7 are optional. It can be understood that the correspondence between the MCS index and the code rate in the embodiment of the present application may be the correspondence between the MCS index value and the code rate, and may also be the correspondence between the MCS index interval and the code rate. There is no limit to this.
  • an Rj represents a code rate.
  • the code rate is a floating point number, and the corresponding precision can be defined.
  • the definition precision is 4 digits after the decimal point is rounded off.
  • the code rate can also be defined as a score.
  • the denominator is defined as 2 t .
  • the molecular value Rj corresponding to the code rate is recorded, and Rj ⁇ 2 t .
  • the maximum bit width of the code rate defined by the score is defined in the hardware implementation process.
  • comparing the code rate with the code rate threshold to determine a coding matrix type, such as determining that the first coding matrix type is obtained when the code rate is greater than the code rate threshold; or, when the code is When the rate is less than or equal to the code rate threshold, it is determined that the second coding matrix type is obtained.
  • the code rate threshold may adopt a corresponding representation.
  • the code rate threshold is also represented by a floating point number.
  • the code rate threshold can also be expressed as a fraction of the same bit width, so that only the molecular value of the code rate can be compared with the molecular value of the code rate threshold.
  • the code rate threshold or code rate can be converted and compared.
  • Method (3) determining a code rate index corresponding to the MCS index by using a correspondence between the MCS index and the code rate index; searching a code rate corresponding to the code rate index according to the code rate index; and determining an encoding matrix according to the code rate and the code rate threshold Types of.
  • the correspondence between the MCS index and the code rate index may be saved in a memory of the communication device, and the correspondence between the MCS index and the code rate index may be, for example, as shown in Table 8. It is to be understood that the correspondence between the MCS index and the code rate index may be expressed in other forms or contents different from the table 8, which is not limited in this embodiment of the present application.
  • the modulation scheme and TBS index column in Table 8 are optional.
  • the correspondence between the MCS index and the code rate index in the embodiment of the present application may be the correspondence between the MCS index value and the code rate index, or may be the correspondence between the MCS index interval and the code rate index.
  • the application embodiment does not limit this.
  • the code rate index may further search for the corresponding code rate, and further determine the coding matrix type according to the found code rate and the code rate threshold: comparing the code rate with the code rate threshold to determine the coding matrix type, such as when the code When the rate is greater than the code rate threshold, determining the first coding matrix type; or, when the code rate is less than or equal to the code rate threshold, determining to obtain the second coding matrix type.
  • the code rate threshold may be made to the related description in the mode (2), and details are not described herein again.
  • the first coding matrix type and the second coding matrix type are used for exemplification, and there may be more types of coding matrix, which is not limited in this embodiment of the present application.
  • the preservation involved in the above embodiments of the present application may be stored in one or more memories.
  • the one or more memories may be separate settings, or may be integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal.
  • the one or more memories may be separately configured in a part, and the part may be integrated in a decoder, a processor, a chip, a communication device, or a terminal.
  • the type of the memory may be any type of storage medium. Not limited to this.
  • multiple coding modes may be adopted based on the coding matrix, which will be described below.
  • the encoding matrix can be viewed as obtaining a check matrix containing an offset value by extending the base map.
  • the LDPC code used in the wireless communication system assumes that the matrix size of the base map is m*n, and may include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by the number of non-zero elements.
  • the weight of a row refers to the number of non-zero elements included in a row
  • the weight of a column refers to the number of non-zero elements included in a column.
  • Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
  • the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
  • the sub-matrix B includes a sub-matrix B of a double-diagonal structure and a matrix of columns with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 may be located before the B-matrix of the sub-matrix, as shown in FIG. 30a; the sub-matrix B may further include one or more columns of columns having a column weight of 1 (referred to as a single column of re-columns). For example, one possible implementation is as shown by 30b or 30c in FIG.
  • the matrix generated based on the sub-matrices A and B is usually a core matrix and can be used to support high code rate encoding.
  • Submatrix C is an all-zero matrix with a size of m A ⁇ m D .
  • the sub-matrix E is an identity matrix having a size of m D ⁇ m D .
  • the submatrix D has a size of m D ⁇ (n A + m A ) and can generally be used to generate a low bit rate check bit.
  • the structure of the two sub-matrices A, B and D is one of the factors influencing the coding performance of the LDPC code.
  • the matrix of the sub-matrices A and B may be encoded to obtain the parity bit corresponding to the sub-matrix B, and then The entire matrix is encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B of the double-diagonal structure and the single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column are obtained.
  • sequence to be encoded of the determined coding matrix may be encoded in the following manner.
  • the input sequence c (first sequence) to be encoded is represented as c 0 , c 1 , c 2 , c 3 , ..., c K-1
  • the output sequence d obtained by the encoder after the input sequence is encoded denoted as d 0 , d 1 , d 2 , ..., d N-1 , K, N are integers greater than 0, and K, N may be integer multiples of the spreading factor Z c .
  • BG1 66Zc
  • K 22Zc
  • BG2 50Zc
  • K 10Zc
  • the encoding process can be as follows:
  • the base matrix index i LS is obtained , and the expansion factor Zc can be determined according to the length K of the input sequence;
  • the correspondence between the expansion factor Zc and the index of the parity check matrix can be expressed as:
  • Set index(i LS ) Set of lifting sizes 1 ⁇ 2,4,8,16,32,64,128,256 ⁇ 2 ⁇ 3,6,12,24,48,96,192,384 ⁇ 3 ⁇ 5,10,20,40,80,160,320 ⁇ 4 ⁇ 7,14,28,56,112,224 ⁇ 5 ⁇ 9,18,36,72,144,288 ⁇ 6 ⁇ 11,22,44,88,176,352 ⁇ 7 ⁇ 13,26,52,104,208 ⁇ 8 ⁇ 15,30,60,120,240 ⁇
  • the assignment can be made as follows:
  • ⁇ NULL> represents a padding bit, which may take a value of 0, or other predetermined value. Alternatively, padding bits may not be sent.
  • H represents a parity check matrix (coding matrix),
  • the parity check matrix can be specified by protocol, pre-configured, or pre-stored.
  • the H is obtained by an index of the base matrix.
  • the parity check matrix may be stored in a plurality of manners, for example, a matrix may be stored, or a parameter related to the storage matrix may be used, for example, an offset value is stored, which is not limited in this embodiment of the present application.
  • the communication device may save the parity check matrix without saving the generator matrix that may be needed for encoding.
  • the generator matrix G satisfies:
  • the generator matrix can be obtained by the check matrix H transform.
  • the row and column transform can be used to change the right side into a diagonal matrix form, which is expressed as:
  • the check matrix H may be any one of the check matrix or the base matrix described in the above embodiments, or an LDPC matrix.
  • encoding when encoding, for the double diagonal portion of the parity check matrix, encoding may be performed by any of the above methods, or may be performed by a method for storing a multi-row superposition matrix.
  • the matrices are stored for compilation.
  • the embodiment of the present application further provides a communication method, where the code rate is determined according to an MCS index, and the first is determined according to a relationship between a code rate and a first code rate threshold and/or a second code rate threshold.
  • a coding matrix type of the sequence encoding the first sequence based on an encoding matrix corresponding to the coding matrix type.
  • the manner of determining the first sequence according to the relationship between the code rate and the first code rate threshold and/or the second code rate threshold may include at least one of the following:
  • the coding matrix type of the first sequence may be determined to be the second coding matrix type. It should be noted that, for the case where the code rate is smaller than the second coding threshold, the second coding matrix is used.
  • the maximum coded block length supported is less than or equal to the first threshold.
  • the length of the first sequence may be made less than or equal to the first threshold by a certain operation, which may be performed in the code block splitting operation.
  • the code rate is smaller than the first code rate threshold and greater than the second code rate threshold, if the length of the first sequence is greater than the first threshold, it may be determined that the coding matrix type of the first sequence is the first coding matrix type, if The length of a sequence is less than or equal to the first threshold, and the coding matrix type of the first sequence may be determined to be the second coding matrix type.
  • the coding matrix type may also be determined by mode B or C.
  • the coding matrix type may also be determined by mode C. This embodiment of the present application does not limit this.
  • the coding matrix type of the first sequence is also determined according to the MCS index, wherein, in summary, when the length of the first sequence is less than or equal to the first threshold, the code rate is smaller than In the case of the first code rate threshold, the coding matrix type of the first sequence is determined to be the second coding matrix type.
  • the value of the first code rate threshold and the second code rate threshold are not limited.
  • the first code rate threshold may be 2/3
  • the second code rate threshold may be 1/4.
  • the manner of determining the code rate according to the MCS index may be understood as the code rate obtained according to the MCS index query.
  • the final The code rate may be higher than the code rate obtained from the MCS index query.
  • determining the code rate according to the MCS index may include: obtaining a first code rate according to the MCS index query, and supporting the first code rate and the actual transmission.
  • the larger of the lowest code rate is finally determined as the code rate determined according to the MCS index, which may be simply referred to as the final code rate, which is the code rate that is finally actually encoded for the first sequence.
  • the code rate obtained from the MCS index query is 1/3, and since the system has a limited buffer, the lowest code rate that can be supported by the actual transmission is 1/2, and 1/2 is determined as the final code rate.
  • the encoding matrix type can be determined by using the final code rate in the manner of the foregoing embodiment.
  • determining the coding matrix type of the first sequence according to the code rate may also determine the coding matrix type according to the code rate and the code rate set, where the code rate set and the coding matrix type exist directly Or an indirect correspondence, the set of code rates may be predefined or configured by the system.
  • One or more code rates are included in the above set of code rates. For example, suppose there are two code rate sets, the first code rate set is (1/3, 1/2), the second code rate set is (1/4, 1/5), and the first code rate set corresponds to the first code set.
  • the matrix type, the second code rate set corresponds to the second coding matrix type.
  • the determined code rate 1/4, 1/4 corresponds to the second code rate set, then the coding matrix type of the code rate 1/4 can be determined.
  • the second encoding matrix type is the first code rate set and the code rate set, where the code rate set and the coding matrix type exist directly Or an indirect correspondence, the set of code rates may be predefined or configured by the system.
  • One or more code rates are included in the above set
  • the LDPC code is obtained by using the above method.
  • the communication device may perform one or more operations of performing rate matching on the LDPC code, interleaving the rate matched LDPC code according to the interleaving scheme, and modulating the interleaved LDPC code according to the modulation scheme.
  • Bit sequence X transmit bit sequence X.
  • Decoding is the inverse of encoding.
  • the base matrix used in the decoding process has the same characteristics as the base matrix used in the encoding process.
  • the communication device may perform one or more operations of: receiving a signal including LDPC-based coding, demodulating, deinterleaving, and de-rate matching the signal to obtain a soft value of the LDPC code.
  • the sequence decodes the soft value sequence of the LDPC code.
  • the above process exemplifies the coding scheme implemented on the transmitting side.
  • the corresponding method is used for decoding on the receiving side.
  • the same method as the transmitting side may be used to determine the coding matrix type. Further determining the coding matrix to complete the decoding.
  • the above decoding can be implemented by a communication device and implemented on the receiving side.
  • the embodiment of the present application further provides a corresponding communication device, and the communication device includes a corresponding module for executing each part in FIG. 2.
  • the module can be software, hardware, or a combination of software and hardware.
  • an embodiment of the present application provides a communication device 400, which may include:
  • the determining module 401 is configured to determine the coding matrix type according to at least the length of the first sequence, and further, when the length of the first sequence is greater than the first threshold, the coding matrix type may be determined as the first coding matrix type, when the first sequence When the length is less than or equal to the first threshold, the coding matrix type may be determined according to the MCS index.
  • the determining module 401 determines the code rate according to the MCS index, and further determines the coding matrix type according to the code rate and the length of the first sequence.
  • the encoding module 402 is configured to encode the first sequence based on an encoding matrix corresponding to the coding matrix type determined by the determining module 401.
  • modules in FIG. 4 may refer to corresponding descriptions in the method embodiments, and details are not described herein again.
  • one or more of the modules in FIG. 4 may be implemented by one or more processors, or one or more processors and memories.
  • FIG. 5 also provides a communication device 500 that can include one or more processors 501.
  • the one or more processors may implement the method illustrated in FIG. 2 and the methods described in the various other embodiments described above.
  • the processor 501 can be a general purpose processor or a dedicated processor or the like.
  • it can be a baseband processor, or a central processing unit.
  • the baseband processor can be used to process communication protocols and communication data
  • the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.
  • the communication device may include a transceiver module for implementing input (reception) and output (transmission) of signals.
  • the communication device can be a chip, and the transceiver unit can be an input and/or output circuit of the chip, or a communication interface.
  • the chip can be used for a terminal or base station or other network device.
  • the communication device may be a terminal or a base station or other network device, and the transceiver unit may be a transceiver, a radio frequency chip, or the like.
  • the communication device 500 includes one or more of the processors 501, and the one or more processors 501 can implement the functions of the encoding described above, for example, the communication device can be an encoder. In another possible design, the processor 501 can implement other functions in addition to the encoding function.
  • the processor 501 can be used to implement the respective functions of the determining module 401 and the encoding module 402 in the foregoing embodiments.
  • the communication device 500 includes means for determining an encoding matrix type based on a length of a sequence to be encoded, and a component encoding a sequence to be encoded based on an encoding matrix corresponding to the encoding matrix type (means).
  • functions can be implemented by one or a processor, and can be specifically referred to the description of the method part of the above method.
  • the communication device 500 can include means for determining a code rate based on the MCS index, for determining a component of the coding matrix type based on the code rate and the length of the first sequence, and for determining the coding matrix based on the coding matrix A component of the coding matrix corresponding to the type to encode the first sequence to be encoded.
  • these functions may be implemented by one or a processor, and may be specifically referred to the description of the method section of the above method.
  • the communication device 500 can also include circuitry that can implement the functions of the foregoing method embodiments.
  • the communication device 500 includes circuitry for determining an encoding matrix type based on a length of a sequence to be encoded, and circuitry for encoding a sequence to be encoded based on an encoding matrix corresponding to the encoding matrix type.
  • the communication device 500 may include circuitry for determining a code rate based on the MCS index, a circuit for determining an encoding matrix type based on a code rate and a length of the first sequence, and for treating the encoding matrix based on the encoding matrix type A circuit that encodes the first sequence to encode.
  • the processor 501 can include instructions 503 (sometimes referred to as code or programs) that can be executed on the processor such that the communication device 500 performs the above-described implementation The method described in the example.
  • instructions 503 sometimes referred to as code or programs
  • the communication device 500 may include one or more memories 502 on which instructions 504 are stored, the instructions being executable on the processor such that the communication device 500 performs the method described in the above method embodiments.
  • the memory can hold the necessary instructions or data.
  • various parameters mentioned in the above method embodiments, and corresponding relationships may be stored.
  • data may also be stored in the memory.
  • Instructions and/or data can also be stored in the optional processor.
  • the processor and the memory may be provided separately or integrated.
  • the “save”, “storage”, or “pre-storage” described in the above embodiments may be in the storage memory 502, or may be stored in a memory or a storage device of other peripherals.
  • the communication device 500 may further include a transceiver 505 and an antenna 506.
  • the processor 501 can be referred to as a processing unit to control the communication device.
  • the transceiver 505 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiving function of the communication device through the antenna 506.
  • the transceiver 505 can be configured to receive the MCS index from the base station.
  • the communication device 500 may further comprise a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a device for rate matching, or for Modulation of the modulator, etc.
  • the functionality of these devices may be implemented by one or more processors 501.
  • the communication device 500 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, or a code block cascading and CRC calibration. Tested devices and so on. The functionality of these devices may be implemented by one or more processors 501.
  • the embodiment of the present application further provides a communication device, which may include a circuit, and the circuit may implement the corresponding functions of the determining module 401 and the encoding module 402 in the foregoing embodiments.
  • FIG. 6 shows a schematic diagram of a communication system 600 that includes a communication device 60 and a communication device 61 in which information data is received and transmitted between the communication device 60 and the communication device 61.
  • the communication devices 60 and 61 may be the communication device 500 or 400, or the communication device devices 60 and 61 respectively include the communication device 500 or 400 for receiving and/or transmitting information data.
  • communication device 60 can be a terminal, and corresponding communication device 61 can be a base station; in another example, communication device 60 is a base station and corresponding communication device 61 can be a terminal.
  • processing units for performing these techniques at a communication device may be implemented in one or more general purpose processors, digital signal processors (DSPs), digital Signal processing device (DSPD), application specific integrated circuit (ASIC), programmable logic device (PLD), field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or In any combination.
  • DSPs digital signal processors
  • DSPD digital Signal processing device
  • ASIC application specific integrated circuit
  • PLD programmable logic device
  • FPGA field programmable gate array
  • a general purpose processor may be a microprocessor.
  • the general purpose processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.
  • the steps of the method or algorithm described in the embodiments of the present application may be directly embedded in hardware, instructions executed by the processor, or a combination of the two.
  • the memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art.
  • the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory.
  • the memory can also be integrated into the processor.
  • the processor and the memory can be disposed in the ASIC, and the ASIC can be disposed in the terminal. Alternatively, the processor and memory may also be located in different components in the terminal.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)) or the like. Combinations of the above should also be included within the scope of the computer readable media.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

本申请实施例公开了一种通信方法和装置，其中方法包括：根据调制编码方式MCS索引确定第一序列的编码矩阵类型，其中，所述第一序列是由第二序列经过码块分割后得到的,所述第二序列的长度与所述MCS索引相关，所述第一序列的长度小于或等于第一阈值；基于所述编码矩阵类型对应的编码矩阵对所述第一序列进行编码。上述方案，可以合理选择编码矩阵类型以用于编码。

Description

通信方法和装置
本申请要求于2017年8月11日提交中国专利局、申请号为201710687631.9、申请名称为“通信方法和装置”的中国专利申请的优先权，2017年9月8日提交中国专利局、申请号为201710807911.9的申请名称为“通信方法和装置”的中国专利申请优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，尤其涉及通信方法和装置。
背景技术
低密度奇偶校验(low density parity check，LDPC)码是一类具有稀疏校验矩阵的线性分组编码，具有结构灵活，译码复杂度低的特点。由于它采用部分并行的迭代译码算法，从而比传统的Turbo码具有更高的吞吐率。LDPC码可用于通信系统的纠错码，从而提高信道传输的可靠性和功率利用率。LDPC码还可以广泛应用于空间通信、光纤通信、个人通信系统、ADSL和磁记录设备等。目前在第五代移动通信中已考虑采用LDPC码作为信道编码方式之一。
实际使用过程中，可以采用具有特殊结构化特征的LDPC矩阵。该具有特殊结构化特征的LDPC矩阵H可以由准循环(quasi cycle，QC)结构的LDPC基矩阵扩展得到。QC-LDPC适合并行度高的硬件，提供的吞吐率更高。可以通过对LDPC矩阵进行设计使之应用于信道编码。
QC-LDPC适合并行度高的硬件，提供的吞吐率更高。可以通过对LDPC矩阵进行设计使之应用于信道编码。
发明内容
本申请实施例提供了一种通信方法和装置，可以合理选择编码矩阵类型以用于编码。
第一方面，提供一种通信方法，包括：至少根据第一序列的长度确定编码矩阵类型，基于所述编码矩阵类型对应的编码矩阵对第一序列进行编码，进一步的，当第一序列的长度小于或者等于第一阈值时，可以根据MCS索引确定编码矩阵类型。其中，该第一序列是由第二序列经过码块分割后得到的,该第二序列的长度与所述MCS索引相关。
上述方法，通过输入编码器的序列的长度和MCS索引确定编码矩阵类型，合理选择编码矩阵类型，可在保证系统正常工作的前提下，降低译码时延，提高译码性能。
一种可能的设计中，当第一序列的长度小于或者等于第一阈值时，利用MCS索引与编码矩阵类型的对应关系，确定与所述MCS索引对应的编码矩阵类型。该方案中，将编码矩阵类型和MCS索引绑定，可以增加系统的鲁棒性。
进一步的，基于以上方式，为了更加灵活的实现编码矩阵类型的配置，对于全部或者部分MCS索引可以按照N PRB的粒度配置编码矩阵类型。比如，MCS索引对应M个N PRB，M为正整数，根据N PRB和MCS索引确定所述编码矩阵类型。一种可能 的方式中，可以是针对全部的MCS索引，每种MCS索引下，数值小于或等于第二阈值的N PRB对应第二编码矩阵类型，另一种可能的方式中，可以是针对部分MCS索引，比如可以将M个码率中至少两个码率之间的差值大于第三阈值的MCS索引按照N PRB的粒度配置编码矩阵类型，具体可以是数值小于或等于第二阈值的N PRB对应第二编码矩阵类型。
另一种可能的设计中，利用MCS索引与码率的对应关系，确定与MCS索引对应的码率；根据码率与码率阈值确定所述编码矩阵类型。其中，码率和码率阈值可以为浮点数或者分数。当码率为分数时，在MCS索引与码率的对应关系中记录与码率对应的分子值。
又一种可能的设计中，可以利用MCS索引与码率索引的对应关系，确定与MCS索引对应的码率索引；根据码率索引查找与码率索引对应的码率；根据码率与码率阈值确定编码矩阵类型。
以上根据码率与码率阈值确定编码矩阵类型可以是：将码率与码率阈值进行比较确定编码矩阵类型，比如当所述码率大于该码率阈值时，确定得到第一编码矩阵类型；或者，当所述码率小于或者等于所述码率阈值时，确定得到第二编码矩阵类型。通过上述方式，也可以避免每次确定编码矩阵类型时计算码率，而是间接的将MCS索引与编码矩阵类型绑定，可以增加系统的鲁棒性。
上述方法中，第一编码矩阵类型对应的编码矩阵的尺寸大于第二编码矩阵类型对应的编码矩阵的尺寸。
上述方法中所提到的各个对应关系，可以以表格的形式保存。
上述方法中，通过查表方式，根据MCS索引确定所述编码矩阵类型。
上述方法中的编码矩阵类型包括基图。
第二方面，还提供一种通信方法，该方法适用于译码过程，译码过程与第一方面所述的通信方法相对应，采用与第一方面中的通信方法相同的方式确定编码矩阵类型，进一步确定编码矩阵。
第三方面，提供一种通信装置可以包含用于执行上述第一方面或者第二方面的通信方法设计中相对应的模块。所述模块可以是软件和/或是硬件。
在一个可能的设计中，第三方面提供的通信装置，包括处理器和收发组件，该处理器和收发组件可用于实现上述编码或者译码方法中各部分的功能。在该设计中，如果该通信装置是终端、基站或者其他网络设备，其收发组件可以是收发机，如果该通信装置是基带芯片或基带单板，其收发组件可以是基带芯片或基带单板的输入/输出电路，用于实现输入/输出信号的接收/发送。所述通信装置可选的还可以包括存储器，用于存储数据和/或指令。
上述通信装置可以是芯片，终端或者基站。
第四方面，本申请实施例提供了一种通信系统，该系统包括上述第三方面所述的通信装置。
再一方面，本申请实施例提供了一种计算机存储介质，其上存储有程序，当其运行时，使得计算机执行上述方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
附图说明
图1为一LDPC码的基图示意图；
图2为本申请一实施例提供的通信方法示意图；
图3为一LDPC码的基图的结构示意图；
图4为本申请一实施例提供的通信装置结构示意图；
图5为本申请另一实施例提供的通信装置结构示意图；
图6为本申请一实施例提供的通信系统示意图。
具体实施方式
为便于理解下面对本申请中涉及到的一些名词做些说明。
本申请中，名词“网络”和“系统”经常交替使用，“装置”和“设备”也经常交替使用，但本领域的技术人员可以理解其含义。“通信装置”可以是芯片(如基带芯片，或者数据信号处理芯片，或者通用芯片等等)，终端，基站，或者其他网络设备。终端是一种具有通信功能的设备，可以包括具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。为描述方便，本申请中简称为终端。基站(base station，BS)，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。在不同的无线接入系统中基站的叫法可能有所不同，例如在而在通用移动通讯系统(Universal Mobile Telecommunications System，UMTS)网络中基站称为节点B(NodeB),而在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在新空口(new radio,NR)网络中的基站称为收发点(transmission reception point，TRP)或者下一代节点B(generation nodeB，gNB)，或者其他各种演进网络中的基站也可能采用其他叫法。本申请并不限于此。
以下对本申请中的一些术语或者概念做出说明。
序列是一种由比特“0”和/或“1”组成的比特串。序列的长度是指序列包括的比特的数目。例如：序列00包括2个比特，其长度为2；序列111包括3个比特，其长度为3；序列“0100”包括4个比特，其长度为4。
传输块(transport blocB,TB)以及码块(code blocB,CB)都可以视为一种序列。码块是通过对传输块或者经过处理的传输块分割后得到的，是编码的对象。因此，本申请中，码块长度指的是该码块所包括的比特的数目，码块长度也可以称为码块大小(code block size，CBS)；传输块长度指的是该传输块所包括的比特的数目，传输块长度也可以称为传输块大小(transport block size,TBS)。可以理解，随着技术的发展，传输块或者码块可能有不同的术语名称。本申请实施例中，经过处理的传输块也可以理解为传输块，该处理 可以是在初始的传输块基础上添加校验比特，例如添加循环冗余校验(cyclic redundancy check，CRC)比特，本申请实施例对此不做限定。
本申请实施例中，所提到的码率是指对待编码的序列采用的编码码率。
LDPC码通常可以用奇偶校验矩阵(parity check matrice)(有时也称为基矩阵)来表示。LDPC码的奇偶校验矩阵可以通过协议约定、预配置、或预存储。LDPC码的奇偶校验矩阵也可以通过基图(base graph，简称为BG)和偏移(shift)值V i,j表示。所述基图(base graph，简称为BG)和偏移(shift)值V i,j可以通过协议约定、预配置、或预存储。
在一种实现方式中，所述奇偶校验矩阵以及基图均可以用m行n列的矩阵形式表示,其中m,n为正整数。所述奇偶校验矩的尺寸以及基图的尺寸可以通过矩阵的行数和列数来表示，也可以通过所包含的矩阵元素的个数来表示。奇偶校验矩阵的尺寸可以与基图的尺寸相对应。所述尺寸相对应，可以理解为，奇偶校验矩阵的行数和列数与基图的行数和列数分别相同，也可以理解为，奇偶校验矩阵的行数和列数，分别与基图的行数/列数存在对应关系。
基图通常可以包括m*n个矩阵元素(entry)，矩阵元素的值为0或1，其中值为0的元素，也可以表示为null，有时候也称之为零元素，表示该元素可以被Z*Z的全零矩阵(zero matrix)替换，值为1的元素，有时候也称之为非零元素，所述非零元素可以被偏移值V i,j替换，其中i为行索引(行号),j为列索引(列号)。基图可用于指示偏移值的位置，基图中的非零元素与偏移值对应。如图1中10a所示为一个5行27列的基图的例子，也就是说m＝5，n＝27。在本文中，基图和基矩阵的行索引(行号)和列索引(列号)均是从0开始编号的，可以理解的是，行号和列号也可以从1开始编号或者其他值开始编号，只要能索引到相应的行和列即可。
根据系统需求不同，需求的BG尺寸大小可以不同。可以基于BG尺寸大小，对BG进行分类。例如，可以通过协议规定、预定义、预配置、或预存储BG的类型，每种类型BG的尺寸不同(也就是矩阵的行数和/或列数不同)。例如可以规定包含两种类型的BG，分别为BG1和BG2，也可以规定两种以上类型的BG，如BG1,BG2,BG3…。本申请对BG类型的个数并不进行限定。
在一种实现方式中，对于BG1，其对应的奇偶校验矩阵H BG1的尺寸为46行68列，行索引为i＝0,1,2,...,45，列索引为j＝0,1,2,...,67；对于BG2，其对应的奇偶校验矩阵H BG2的尺寸为为42行52列，行索引为i＝0,1,2,...,41，列索引为j＝0,1,2,...,51。
表1给出了分别对应于BG1和BG2的H BG的非零元素的位置分布的一种可能的形式。
表1:BG1和BG2的H BG
Figure PCTCN2018099904-appb-000001
Figure PCTCN2018099904-appb-000002
可以理解的是，由上可以看出，一种基图可以被看作是一类编码矩阵，那么可以将基图理解为是编码矩阵类型的一种表现方式。当然，编码矩阵类型也可以包括奇偶校验矩阵的类型。
需要说明的是，本申请实施例中，一种编码矩阵类型代表了一种编码矩阵的结构，此处所述的编码矩阵的结构包括编码矩阵的尺寸、编码矩阵中的零元素和/或非零元素的在编码矩阵中位置分布。每种编码矩阵类型可以对应至少一种编码矩阵，每种编码矩阵类型对应的至少一种编码矩阵的结构是相同的，只是非零元素的具体取值不完全同(即部分相同或均不相同)，比如BG1可以对应8种编码矩阵。当然,除了尺寸以及编码矩阵中的零元素和/或非零元素的在编码矩阵中位置分布,不同编码矩阵类型之间还可能存在其他差异,本申请实施例对此不做限定。
本申请实施例中，可以包括至少两种编码矩阵类型，下面以两种编码矩阵类型：第一编码矩阵类型和第二编码矩阵类型举例说明。
本申请实施例中，第一编码矩阵类型对应的编码矩阵的尺寸大于第二编码矩阵类型对应的编码矩阵的尺寸。由于编码矩阵尺寸的不同，其设计支持的编码块长和编码码率的范围不同。相应的，BG1可以对应第一编码矩阵类型，BG2可以对应第二编码矩阵类型。
以第一编码矩阵类型为BG1举例，其支持的编码码率最小为1/3，最高至少可达到0.89，支持的块长最小可到40bit，支持的最小块长至少可为512bit，支持的最大块长为8448bit；以第二编码矩阵类型为BG2为例，其支持的编码码率最小为1/5，最高至少可达0.67，支持的块长最小可到40bit，最大可到2560bit，可扩展支持到3840bit。由于编码矩阵尺寸的不同，采用相同的硬件架构实现时，其译码时延可吞吐率不同，这主要由矩阵的列数和行数的差值Kb决定。对于BG1，Kb＝68-46＝22；对于BG2， Kb＝52-42＝10。通常情况，在码长和码率相同的前提下，Kb值越小，矩阵的译码时延越低，吞吐率越高。一种合理的编码矩阵类型选择思路为，当码长和码率相同且两种编码矩阵类型均支持时，优先选择Kb值较小的矩阵(例如第二编码矩阵类型)。
为了提供一种合理的确定编码矩阵类型的方案，图2所示，本申请实施例提供了一种通信方法，该通信方法通过通信装置实现，当为上行传输时，该通信装置可以是终端或者可用于终端的芯片，当为下行传输时，该通信装置可以是基站或者可用于基站的芯片。该通信方法可以包括：
S201，基于第一序列的长度确定编码矩阵类型。
此处，该第一序列可以理解为是输入编码器的待编码的序列，可以表示为c 0,c 1,c 2,c 3,...,c K-1。例如，该第一序列可以是经过将传输块进行码块分割后的码块，该输入序列的长度也是码块大小(CBS)。此处，也可以将传输块称为第二序列。
需要说明的是,此处所描述的码块分割，是指输入为待处理的传输块，输出为待编码的序列的处理过程，该待编码的序列可以称为码块。也就是说码块分割可以理解为从传输块到码块的处理过程。
可以理解的是，根据系统的实际需求，码块分割可能有不同的方式，例如可以是：根据传输块大小是否大于分割阈值，决定将传输块分割成一个或多个码块。可以理解的，即使是传输块大小小于分割阈值，将传输块保留为一个码块，这也可以视为经历了码块分割操作。可以理解的是，传输块在分割前可以经过处理也可以不经过处理，其中，传输块在分割前的处理可以是在初始的传输块基础上添加校验比特，例如添加CRC比特；此外，分割得到的码块在输入编码器之前，可以是经过一定的处理，也可以不经过处理，对码块的处理例如可以是添加校验比特，例如添加CRC，或者,对码块的处理还可以包括添加填充比特,本申请实施例对此不做限定。
如果码块是经过添加校验比特处理的，此时第一序列的长度可以是添加了校验比特之后的码块长度，也可以是指添加校验比特之前的码块长度，本申请实施例对此不做限定。
在一种实现方式中，上述分割阈值的大小可以为预设的固定值，也可以直接或者间接地根据调制编码方式(modulation and coding scheme，MCS)索引确定分割阈值。其中，直接地根据MCS索引确定分割阈值可以是：根据MCS索引与分割阈值的对应关系，查找与MCS索引对应的分割阈值；间接地根据MCS索引确定分割阈值可以是：根据MCS索引得到对应的码率后，根据码率来确定分割阈值，本申请实施例对确定分割阈值的方式以及分割阈值的取值不做限定。可以理解，所述MCS索引可以是MCS索引值，也可以是MCS索引区间。
当第一序列的长度大于第一阈值时，可以将编码矩阵类型确定为第一编码矩阵类型。
当第一序列的长度小于或者等于第一阈值时，可以根据MCS索引确定编码矩阵类型。也就是说，在根据MCS索引确定编码矩阵类型时，第一序列的长度小于或者等于第一阈值。
在一种实现方式中，可以建立MCS索引与编码矩阵类型之间的对应关系。基于MCS索引以及所述对应关系确定编码矩阵的类型。
例如，可以通过协议约定、预配置，预存储或者信令等方式建立MCS索引与编码矩阵类型的对应关系。
MCS索引与编码矩阵类型之间可以是直接的对应关系，也可以是间接的对应关系。
例如，存储MCS索引与编码矩阵类型的对应关系列表，通过查表的方式确定对应的编码矩阵类型。
上述方式确定的编码矩阵类型可以称为第一序列的编码矩阵类型。
可以理解的是，上述第一阈值为预设的数值，例如可以是2560或者3840，本申请实施例对此不做限定。可以理解的是，对于不同的第一序列长度的定义方式，第一阈值可能会有不同的设置，例如如果第一序列的长度不包括校验比特的码块的长度，第一阈值会考虑到扣除校验比特的序列长度，例如可以是3816，3824，2536,2544等，或者，如果第一序列的长度是不包括校验比特的码块长度的，第一阈值的取值也可以没有考虑到扣除校验比特的序列长度而设置，可以对第一序列的长度或者第一阈值进行处理后再进行比较，例如将第一序列的长度加上第二预设值之后与第一阈值进行比较，或者是将第一序列的长度与第一阈值减去第二预设值之后的数值进行比较。
可选的，网络设备(如基站等)可以根据终端反馈的信道质量指示(channelquality indicator,CQI)(例如，在调度过程中，终端反馈CQI)确定MCS索引。网络设备可以基于确定的MCS索引得到传输块大小,即第二序列的长度。
一种可能的实现方式中，可以根据MCS索引得到对应的TBS索引，从而结合TBS索引以及N PRB可以得到传输块的大小，其中N PRB表示一个混合自动重传请求(hybrid automatic repeat request，HARQ)进程或者一次传输进程中分配的资源块(resource block，RB)的个数。其中，当N PRB表示一次传输进程中分配的资源块数目时，此处的资源块数目既可以是实际分配的资源块的个数，也可以是一个归一化的资源块个数。例如，新无线(new radio，NR)可以支持一个资源块中可以包含72，108或者144个资源单元(resource element，RE)，定义资源块数目N RE，定义归一化的RB Size为N Normalized＝144。在一种情况下，假如系统采用一个资源块包含144个RE的配置，某进程一共包括N RE＝288个RE，则该进程包括的归一化的资源块数目N PRB＝N RE/N Normalized＝2，正好就是实际分配的资源块的个数；在另一种情况中，假如系统采用一个资源块包括72个RE的配置，某进程一共包括N RE＝288个RE，则该进程包括的归一化的资源块数目N PRB＝N RE/N Normalized＝2，但是此时该进程实际包括288/72＝4个资源块，这里计算得到的N PRB＝2是按照N Normalized等于144归一化后计算得到的资源块个数。
由上可知，TBS是和MCS索引相关的，然而本申请实施例对于如何根据MCS索引确定得到TBS不做限定。
例如，表2给出了一种MCS索引(I MCS)、TBS索引(I TBS)以及调制方式(Q m)的对应关系举例，表3给出了一种TBS索引(I TBS)与N PRB的对应关系举例。基于表2和表3便可以得到传输块大小。可以理解的是，也基于表2或表3做些变形，或者以其他不同于表2或者表3的形式或者内容来表示相应的对应关系，获得传输块的大 小。本申请实施例对此不做限定。例如，表2中的调制方式一列是可选的。
表2
Figure PCTCN2018099904-appb-000003
Figure PCTCN2018099904-appb-000004
表3
Figure PCTCN2018099904-appb-000005
另一种可能的实现方式中，可以建立MCS索引与码率的对应关系，基于所述MCS索引与码率的对应关系，确定出码率，进而根据码率和N PRB确定TBS。例如可以通过协议约定、预配置、预存储或者信令指示等方式建立MCS索引与码率的对应关系。
MCS索引也可以称为MCS等级。
网络设备(如基站等)可以将确定的MCS索引发送给终端，从而终端可以利用接收到的MCS索引确定编码矩阵类型。
S202，基于所述编码矩阵类型对应的编码矩阵对第一序列进行编码。
当编码矩阵类型确定后，可以基于与该确定的编码矩阵类型对应的编码矩阵对第一序列进行编码。可选的，可以根据扩展因子的值确定编码矩阵，而扩展因子的值可 以由码块分割后得到的码块长度确定。
采用相同硬件架构支持相同码长和码率的码字时，采用不同编码矩阵类型的译码时延不同，译码性能也存在一些差异，此外，不同编码矩阵类型支持的编码块长和码率不同，即使是都支持的码率和块长，其译码时延和性能也不同，本申请实施例提供的上述通信方法，通过输入编码器的序列的长度和MCS索引确定编码矩阵类型，合理选择编码矩阵类型，可在保证系统正常工作的前提下，降低译码时延，提高译码性能。
可选的，当第一序列的长度小于或者等于第一阈值时，可以通过以下方式之一根据MCS索引确定编码矩阵类型：
方式(1)：利用MCS索引与编码矩阵类型的对应关系，确定与所述MCS索引对应的编码矩阵类型。可选的，可以在通信装置的存储器中保存MCS索引与编码矩阵类型的对应关系，其中，每种编码矩阵类型用不同的数值表示。MCS索引与编码矩阵类型的对应关系例如可以如表4所示，其中，表4中的数值“2”对应的编码矩阵类型可以称为第二编码矩阵类型，数值“1”对应的编码矩阵类型可以称为第一编码矩阵类型。可以理解的是，可以以其他不同于表4的形式或者内容来表示MCS索引与编码矩阵类型的对应关系，本申请实施例对此不做限定。此外，表4中的调制方式和TBS索引列是可选的。可以理解的是，本申请实施例所述的MCS索引与编码矩阵类型的对应关系，可以是MCS索引数值与编码矩阵类型的对应关系，也可以是MCS索引区间与编码矩阵类型的对应关系，本申请实施例对此不做限定。
表4
Figure PCTCN2018099904-appb-000006
Figure PCTCN2018099904-appb-000007
可以理解的是，可以将如表4的MCS索引与编码矩阵类型的对应关系完整信息均保存在存储器中，而为了进一步节约内存占用的话，可以只保存部分信息，例如只表3中保存数值“1”对应的编码矩阵类型所涉及的MCS索引等其他信息，而其他未保存的MCS索引对应的编码矩阵类型为第二编码矩阵类型。可选的，如表4的对应关系也可以简化为如表5的形式，其他未在表5中列出的MCS索引对应的编码矩阵类型“2”。
表5
Figure PCTCN2018099904-appb-000008
Figure PCTCN2018099904-appb-000009
本申请实施例对对应关系的存储方式或者表达形式不做限定。
可选的，上述对应关系可以是根据MCS索引与编码矩阵类型的对应关系可以是在考虑到各个MCS索引的对应的码率推算得到的。例如，如果MCS索引对应的所有TBS的编码后码率均小于码率阈值，则该MCS索引可以对应第二编码矩阵类型，例如BG2；如果对于某一MCS索引，其对应的所有TBS的编码后码率均大于码率阈值，则该MCS索引对应第一编码矩阵类型，例如BG1；如果对于某一MCS索引，其对应的TBS的编码后码率一部分大于码率阈值，一部分小于码率阈值，或者其对应的编码后码率的均值只是略大于码率阈值，则该MCS索引对应的编码矩阵类型根据实际情况，可能设置为第一编码矩阵类型，也可能设置为第二编码矩阵类型，本申请实施例不做限定。
码率和很多参数相关，包括系统分配的RB个数，每个RB内承载信息符号的个数，调制阶数等，当系统配置不同或者计算精度不同时，计算得到的码率可能不同，如果采用每次选择编码矩阵类型前计算码率并和码率阈值比较的方法，不仅计算过程繁琐，还可能由于发送端和接收端理解不一致，精度不同的原因，降低系统的鲁棒性。而本申请实施例中，将编码矩阵类型和MCS索引绑定，可以增加系统的鲁棒性。因为可以通过控制信令，令发送端和接收端的MCS索引对齐。同时，每个MCS索引下的预计编码码率都十分接近，可通过预先配置，确定对应MCS索引下的编码矩阵类型。
上述的码率阈值可以是预定义的数值，例如为2/3，可选的，实际计算时，可在该预定义的数值上留一定的余量，比如将2/3抬升为0.7。
进一步的，一个MCS索引可以对应M个N PRB，而为了更加灵活的实现编码矩阵类型的配置，对于全部或者部分MCS索引可以按照N PRB的粒度配置编码矩阵类型。那么可以根据N PRB和MCS索引确定所述编码矩阵类型。其中，M为正整数。
一种可能的方式中，可以是针对全部的MCS索引，每种MCS索引下，数值小于或等于第二阈值的N PRB对应第二编码矩阵类型，例如BG2，数值大于第二阈值的N PRB对应第一编码矩阵类型，例如BG1。
另一种可能的方式中，可以是针对部分MCS索引，比如可以将M个码率中至少两个码率之间的差值大于第三阈值的MCS索引按照N PRB的粒度配置编码矩阵类型，具体可以是数值小于或等于第二阈值的N PRB对应第二编码矩阵类型，例如BG2，数值大于第二阈值的N PRB对应第一编码矩阵类型，例如BG1。
以MCS索引为26为例，一种可能的按照N PRB的粒度配置编码矩阵类型的形式可以如表6所示：
表6
Figure PCTCN2018099904-appb-000010
方式(2)：利用MCS索引与码率的对应关系，确定与所述MCS索引对应的码率；根据所述码率与码率阈值确定所述编码矩阵类型，此处，码率阈值可以是预定义的数值，例如为2/3。
可选的，可以在通信装置的存储器中保存MCS索引与码率的对应关系，MCS索引与码率的对应关系例如可以如表7所示。可以理解的是，可以以其他不同于表7的形式或者内容来表示MCS索引与码率的对应关系，本申请实施例对此不做限定。此外，表7中的调制方式和TBS索引列是可选的。可以理解的是，本申请实施例所述的MCS索引与码率的对应关系，可以是MCS索引数值与码率的对应关系，也可以是MCS索引区间与码率的对应关系，本申请实施例对此不做限定。
表7
Figure PCTCN2018099904-appb-000011
Figure PCTCN2018099904-appb-000012
表7中，一个Rj表示一种码率，通常情况下，码率为一个浮点数，可以定义相应的精度，比如定义精度为小数点后4位四舍五入。
或者，码率也可以定义成一个分数，例如，定义分母为2 t，在MCS索引与码率的对应关系中记录与码率对应的分子值Rj，Rj<2 t，通过这种方式也就限定了该用分数定义的码率在硬件实现过程中的最大位宽为t。
在根据MCS索引确定码率后，将码率与码率阈值进行比较确定编码矩阵类型，比如当所述码率大于该码率阈值时，确定得到第一编码矩阵类型；或者，当所述码率小于或者等于所述码率阈值时，确定得到第二编码矩阵类型。
其中,可以理解的是，对应于不同的码率的表示形式，码率阈值可以采用相应的表示形式，例如，当码率为浮点数时，码率阈值也采用浮点数表示。当码率为分数时，码率阈值也可以采用相同位宽的分数表示，这样可以只用将码率的分子值与码率阈值的分子值比较。或者，如果码率阈值采用和码率不同的表示形式时，可以将码率阈值或者码率进行换算后再比较。
通过上述方式，也可以避免每次确定编码矩阵类型时计算码率，而是间接的将MCS索引与编码矩阵类型绑定，可以增加系统的鲁棒性，因为可以通过控制信令，令发送端和接收端的MCS索引对齐。
方式(3)：利用MCS索引与码率索引的对应关系，确定与MCS索引对应的码率索引；根据码率索引查找与码率索引对应的码率；根据码率与码率阈值确定编码矩阵类型。可选的，可以在通信装置的存储器中保存MCS索引与码率索引的对应关系，MCS索引与码率索引的对应关系例如可以如表8所示。可以理解的是，可以以其他不同于表8的形式或者内容来表示MCS索引与码率索引的对应关系，本申请实施例对此不做限定。此外，表8中的调制方式和TBS索引列是可选的。可以理解的是，本申请实施例所述的MCS索引与码率索引的对应关系，可以是MCS索引数值与码率索引的对应关系，也可以是MCS索引区间与码率索引的对应关系，本申请实施例对此不做限定。
表8
Figure PCTCN2018099904-appb-000013
Figure PCTCN2018099904-appb-000014
进一步的,可以通过码率索引进一步查找对应的码率,进一步根据查找到的码率与码率阈值确定编码矩阵类型：将码率与码率阈值进行比较确定编码矩阵类型，比如当所述码率大于该码率阈值时，确定得到第一编码矩阵类型；或者，当所述码率小于或者等于所述码率阈值时，确定得到第二编码矩阵类型。此处，关于码率以及码率阈值的表示形式可以参考方式(2)中的相关描述，此处不再赘述。
可以理解的是，上述方式(1)-(3)中，所涉及的对应关系可以通过表格的形式表示，也可以通过数组或者其他形式，本申请实施例对此不做限定。
此外，上述实施例中，是以第一编码矩阵类型和第二编码矩阵类型进行举例说明，可以有更多种编码矩阵类型，本申请实施例对此不做限定。当有更多编码矩阵类型的情况下，可以有多于一个的码率阈值，从而可以实现更多编码矩阵类型的选择。
本申请上述实施例中涉及的保存，可以是指的保存在一个或者多个存储器中。所述一个或者多个存储器，可以是单独的设置，也可以是集成在编码器或者译码器，处理器、芯片、通信装置、或者终端。所述一个或者多个存储器，也可以是一部分单独设置，一部分集成在译码器、处理器、芯片、通信装置、或者终端中，存储器的类型 可以是任意形式的存储介质，本申请实施例并不对此限定。
进一步的，本申请实施例中，可以基于编码矩阵可以采用多种编码方式，下面进行说明。
在一种实现方式中，可以将编码矩阵看作通过对基图扩展获得包含偏移值(Shift value)的校验矩阵。
无线通信系统中采用的LDPC码，假设其基图的矩阵大小为m*n，可以包括5个子矩阵A、B、C、D和E，其中，矩阵的权重是由非零元素的个数决定的，行的权重(行重)是指一行中包括的非零元素的个数，列的权重(列重)是指一列中包括的非零元素的个数。如图3中300所示，其中：
子矩阵A为m A行n A列的矩阵，其大小可以为m A*n A，其中每列对应LDPC码中的Z个系统比特，系统比特有时候也称为信息比特。
子矩阵B为为m A行m A列的方阵，其大小可以为m A*m A，每列对应于LDPC码中的Z个校验比特。子矩阵B包括双对角结构的子矩阵B括和一列权重为3的矩阵列(简称为3列重列)，其中列重为3的矩阵列可以位于子矩阵B矩之前，如图3中30a所示；子矩阵B还可以包括一列或多列列重为1的矩阵列(简称为单列重列)，例如，一种可能的实现方式如图3中30b或30c所示。
通常基于子矩阵A和B生成的矩阵为核心矩阵，可以用来支持高码率的编码。
子矩阵C为全零矩阵，其大小为m A×m D。
子矩阵E为单位矩阵，其大小为m D×m D。
子矩阵D大小为m D×(n A+m A)，通常可用来生成低码率的校验位。
可以理解的是，上述从数学定义的角度对基图进行表述，由于C为全零矩阵，E为单位矩阵，在一种可能的实现方式中，也可以由子矩阵A和B构成的矩阵，或者子矩阵A、B和D构成的矩阵来简化地表示编码或译码的矩阵的基图。
由于子矩阵C和E的结构相对确定，子矩阵A、B和D两部分的结构是LDPC码的编译码性能的影响因素之一。
采用raptor-like结构的LDPC矩阵进行编码时，一种可能的实现方式为，可以先对子矩阵A和B部分的矩阵，也就是核心矩阵进行编码，得到子矩阵B对应的校验比特，再对整个矩阵进行编码，得到子矩阵E部分对应的校验比特。由于子矩阵B可以包括双对角结构的子矩阵B以和一单列重列，在编码中可以先获得双对角结构对应的校验比特，再获得单列重列对应的校验比特。
在另一种实现方式中，可以通过以下方式给确定的编码矩阵对待编码的序列进行编码。
待编码的输入序列c(第一序列)表示为c 0,c 1,c 2,c 3,...,c K-1，输入序列经过编码器编码后得到的输出序列d，表示为d 0,d 1,d 2,...,d N-1,K，N为大于0的整数，K,N可以是扩展因子Z c的整数倍。例如对于BG1,N＝66Zc,K＝22Zc，对于BG2,N＝50Zc，K＝10Zc
编码过程可以如下：
(1)基于扩展因子Zc与奇偶校验矩阵的索引的对应关系，获得基矩阵索引i LS，而根据输入序列的长度K可以确定扩展因子Zc；
例如，所述扩展因子Zc与奇偶校验矩阵的索引的对应关系可以表示为：
Set index(i LS) Set of lifting sizes
1 {2,4,8,16,32,64,128,256}
2 {3,6,12,24,48,96,192,384}
3 {5,10,20,40,80,160,320}
4 {7,14,28,56,112,224}
5 {9,18,36,72,144,288}
6 {11,22,44,88,176,352}
7 {13,26,52,104,208}
8 {15,30,60,120,240}
(2)给编码后的比特序列d中的前K-2Z c个比特赋值。这里，需要跳过待编码比特段前2Z c个填充比特，而且需要考虑待编码的比特段中可能会包含填充比特。
一种实现方式中，可采用如下方式进行赋值：
for k＝2Z c to K-1
Figure PCTCN2018099904-appb-000015
Figure PCTCN2018099904-appb-000016
else
c k＝0；
Figure PCTCN2018099904-appb-000017
end if
end for
其中，k为索引值，且k为整数，＜NULL＞表示填充比特，其取值可以为0，或者是其他预定的值。可选的，填充比特可以不被发送。
(3)生成N+2Z c-K个校验比特
Figure PCTCN2018099904-appb-000018
使得校验比特满足以下公式：
Figure PCTCN2018099904-appb-000019
其中c＝[c 0,c 1,c 2,...,c K-1] T；0表示列向量，其中所有元素的值都为0.H表示奇偶校验矩阵(编码矩阵)，所述奇偶校验矩阵的可以通过协议规定，预先配置，或者预存储。通过所述基矩阵的索引可获得所述H。奇偶校验矩阵的存储方式可以有多种，比如可以存储矩阵，也可以是存储矩阵相关的参数，例如存储偏移值，本申请实施例对此不做限定。
(4)for k＝K to
Figure PCTCN2018099904-appb-000020
Figure PCTCN2018099904-appb-000021
end for
在又一种实现方式中，通信装置可以不保存奇偶校验矩阵，而保存可能需要的生成矩阵进行编码。假设待编码比特段为c＝c 0,c 1,c 2,c 3,...,c K-1，编码后比特段为d＝d 0,d 1,d 2,...,d N-1，则生成矩阵G满足：
d＝c·G
生成矩阵可以由校验矩阵H变换得到，对于校验矩阵H，通过行列变换，可将其右侧变为对角阵形式，表示为：
H＝[P I]  (2)
则，其对应生成矩阵G满足：
G＝[I P T]  (3)
其中校验矩阵H可以是上述实施例中所述的任一校验矩阵或者基矩阵，或LDPC矩阵。编码时，可利用存储的生成矩阵G，由待编码比特段为c＝c 0,c 1,c 2,c 3,...,c K-1直接计算编码后比特段d＝d 0,d 1,d 2,...,d N-1。
在又一种实现方式中，编码时，对于奇偶校验矩阵双对角部分，可以采用上述任一方式进行编码，也可以采用存储一个多行叠加矩阵的的方法进行编码。
在又一种实现方式中，可以对每一个扩展因子Z c，根据P i,j＝mod(V i,j,Z c)计算出其对应的偏移值矩阵，然后将每个扩展因子对应的矩阵均存储下来用于编译码。
下表以BG2为例，示例了一种可能的V i,j取值：
Figure PCTCN2018099904-appb-000022
Figure PCTCN2018099904-appb-000023
下表以BG1为例，示例了一种可能的V i,j取值：
Figure PCTCN2018099904-appb-000024
Figure PCTCN2018099904-appb-000025
可选的，本申请实施例还提供了一种通信方法，该方法中，根据MCS索引确定出码率，根据码率与第一码率阈值和/或第二码率阈值的关系确定第一序列的编码矩阵类型，基于所述编码矩阵类型对应的编码矩阵对第一序列进行编码。其中，根据MCS索引确定码率可以参见上述实施例中所描述的方式(2)和(3)，关于第一序列的描述也可以参见前述实施例，此处不再赘述。
而根据码率与第一码率阈值和/或第二码率阈值的关系确定第一序列的方式可以 包括以下至少一种：
A：在码率大于第一码率阈值时，可以确定第一序列的编码矩阵类型为第一编码矩阵类型。
B：在码率小于第二码率阈值时，可以确定第一序列的编码矩阵类型为第二编码矩阵类型，需要说明的是，对于码率小于第二编码阈值的情况，由于第二编码矩阵支持的最大编码块长小于或者等于第一阈值，在获得第一序列时，可以通过一定的操作使得第一序列的长度小于或者等于第一阈值，该操作通常可以在码块分割操作中进行。
C:对于码率小于第一码率阈值且大于第二码率阈值的情况，如果第一序列的长度大于第一阈值，可以确定第一序列的编码矩阵类型为第一编码矩阵类型，如果第一序列的长度小于或者等于第一阈值，可以确定第一序列的编码矩阵类型为第二编码矩阵类型。
需要说明的是，对于码率等于第二码率阈值的情况，也可以通过方式B或者C确定编码矩阵类型，对于码率等于第一码率阈值的情况，也可以通过方式C确定编码矩阵类型，本申请实施例对此不做限定。
可以理解的是，上述方式A-C中，同样是根据MCS索引确定出了第一序列的编码矩阵类型，其中，综上来看，在第一序列的长度小于或者等于第一阈值时，对于码率小于第一码率阈值的情况，均将第一序列的编码矩阵类型确定为第二编码矩阵类型。
其中，本申请实施例对第一码率阈值和第二码率阈值的取值不做限定，例如第一码率阈值可以为2/3,第二码率阈值可以为1/4。
可选地，对于上述各个实施例中，所例举的根据MCS索引确定码率的方式，可以理解为是根据MCS索引查询得到的码率，然而，如果系统中存在有限缓存的场景，则最终的码率可能高于根据MCS索引查询得到的码率。
那么对于系统中存在有限缓存的场景，本申请实施例一种可能的方式中，根据MCS索引确定码率可以包括：根据MCS索引查询得到第一码率，将第一码率和实际发送可支持的最低编码码率中的较大值最终确定为根据MCS索引确定的码率，可以简称为最终的码率，该最终的码率也就是最终实际对第一序列编码的码率。例如，根据MCS索引查询得到的码率为1/3，而由于系统存在有限缓存导致实际发送可支持的最低编码码率为1/2，则将1/2确定为最终的码率。进一步的，可以参照前述实施例的方式，利用该最终的码率来确定编码矩阵类型。
一种可能的设计中,上述各个实施例中,根据码率确定第一序列的编码矩阵类型也可以是根据码率与码率集合确定编码矩阵类型,其中该码率集合与编码矩阵类型存在直接或间接的对应关系,该码率集合可以是预定义的,也可以是系统配置的。上述码率集合中包括一个或多个码率。例如，假设有两个码率集合，第一码率集合是(1/3,1/2)第二码率集合是(1/4,1/5),第一码率集合对应第一编码矩阵类型，第二码率集合对应第二编码矩阵类型，当确定出的码率1/4,1/4对应的是第二码率集合，那么可以确定码率1/4的编码矩阵类型是第二编码矩阵类型。
可选地，在通信系统中，可采用上述方法编码后得到LDPC码。获得LDPC码后，通信装置，还可以进行以下一个或多个操作：对LDPC码进行速率匹配；根据交织方案对速率匹配后的LDPC码进行交织；根据调制方案对交织后的LDPC码进行调制得 到比特序列X；发送比特序列X。
译码是编码的逆过程，译码过程使用的基矩阵与编码过程使用的的基矩阵具有相同的特征。LDPC码的编码过程可以参考前述实现方式描述，此处不再赘述。在一种实现方式中，在译码之前，通信装置还可以进行以下一个或多个操作：接收包含基于LDPC编码的信号，对信号进行解调，解交织以及解速率匹配得到LDPC码的软值序列，对LDPC码的软值序列进行译码。
需要说明的是，上述过程示例性的说明了在发送侧的实现的编码方案，对应的，在接收侧会采用相应的方法进行译码，例如可以采用与发送侧相同的方法来确定编码矩阵类型，进一步确定编码矩阵，从而完成译码。上述的译码可以通过一个通信装置实现，在接收侧实施。
相应于图2的给出的通信方法，本申请实施例还提供了相应的通信装置，所述通信装置包括用于执行图2中每个部分相应的模块。所述模块可以是软件，也可以是硬件，或者是软件和硬件结合。
如图4所示，本申请一实施例提供了一种通信装置400，可以包括：
确定模块401，用于至少根据第一序列的长度确定编码矩阵类型，进一步的，当第一序列的长度大于第一阈值时，可以将编码矩阵类型确定为第一编码矩阵类型，当第一序列的长度小于或者等于第一阈值时，可以根据MCS索引确定编码矩阵类型。
或者说确定模块401根据MCS索引确定码率，进一步根据码率以及第一序列的长度确定编码矩阵类型。
编码模块402，用于基于与确定模块401确定的编码矩阵类型对应的编码矩阵对所述第一序列进行编码。
需要说明的是，图4所示的通信装置中的各个模块的相应处理过程和实现方式可以参考方法实施例中的相应描述，此处不再赘述。在一种可能的设计中，如图4中的一个或者多个模块可能由一个或者多个处理器来实现，或者一个或者多个处理器和存储器来实现。
图5还提供了一种通信装置500，所述通信装置500可以包括一个或多个处理器501。所述一个或多个处理器可以实现图2所示的方法以及上述其他各个实施例所述的方法。
所述处理器501可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理，中央处理器可以用于对通信装置(如，基站、终端、或芯片等)进行控制，执行软件程序，处理软件程序的数据。
所述通信装置可以包括收发模块，用以实现信号的输入(接收)和输出(发送)。例如，通信装置可以为芯片，所述收发单元可以是芯片的输入和/或输出电路，或者通信接口。所述芯片可以用于终端或基站或其他网络设备。又如，通信装置可以为终端或基站或其他网络设备，所述收发单元可以为收发器，射频芯片等。
在一种可能的设计中，所述通信装置500包括一个或多个所述处理器501，所述一个或多个处理器501可实现上述编码的功能，例如通信装置可以是编码器。在另一种可能的设计中，处理器501除了实现编码功能，还可以实现其他功能。
处理器501可以用于实现前述实施例中的确定模块401和编码模块402的相应功能。
在一种可能的设计中，通信装置500包括用于基于待编码的序列的长度确定编码矩阵类型的部件(means),以及基于所述编码矩阵类型对应的编码矩阵对待编码的序列进行编码的部件(means)。可以通过一个或者处理器来实现这些功能，具体可以参照上述方法实施例部分的描述。
在一种可能的设计中,通信装置500可以包括用于根据MCS索引确定码率的部件，用于根据码率以及第一序列的长度确定编码矩阵类型的部件，以及用于基于所述编码矩阵类型对应的编码矩阵对待编码的第一序列进行编码的部件。例如，可以通过一个或者处理器来实现这些功能，具体可以参照上述方法实施例部分的描述。
在又一种可能的设计中，通信装置500也可以包括电路，所述电路可以实现前述方法实施例中的功能。例如，通信装置500包括用于基于待编码的序列的长度确定编码矩阵类型的电路，以及用于基于所述编码矩阵类型对应的编码矩阵对待编码的序列进行编码的电路。或者，通信装置500可以包括用于根据MCS索引确定码率的电路，用于根据码率以及第一序列的长度确定编码矩阵类型的电路，以及用于基于所述编码矩阵类型对应的编码矩阵对待编码的第一序列进行编码的电路。
可选的，在一种设计中，处理器501可以包括指令503(有时也可以称为代码或程序)，所述指令可以在所述处理器上被运行，使得所述通信装置500执行上述实施例中描述的方法。
可选的，在一种设计中，所述通信装置500中可以包括一个或多个存储器502，其上存有指令504，所述指令可在所述处理器上被运行，使得所述通信装置500执行上述方法实施例中描述的方法。例如，所述存储器可以保存必要的指令或数据。例如，可以存储上述方法实施例中提及的各种参数，以及对应关系。
可选的，所述存储器中还可以存储有数据。可选的处理器中也可以存储指令和/或数据。所述处理器和存储器可以单独设置，也可以集成在一起。
可选的，上述实施例中所述的“保存”，“存储”，或“预存储”可以是保存存储器502中，也可以是保存在其他的外设的存储器或者存储设备中。
可选的，所述通信装置500还可以包括收发器505以及天线506。所述处理器501可以称为处理单元，对通信装置进行控制。所述收发器505可以称为收发单元、收发机、收发电路、或者收发器等，用于通过天线506实现通信装置的收发功能。其中，对于通信装置为终端而言，收发器505可以用于从基站处接收MCS索引。
可选的，所述通信装置500还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、用于速率匹配的器件、或者用于调制处理的调制器等。可以通过一个或多个处理器501实现这些器件的功能。
可选的，所述通信装置500还可以包括，用于解调操作的解调器、用于解交织的解交织器、用于解速率匹配的器件、或者用于码块级联和CRC校验的器件等等。可以通过一个或多个处理器501实现这些器件的功能。
在又一种可能的设计中，本申请实施例还提供一种通信装置，该通信装置可以包括电路，所述电路可以实现前述实施例中的确定模块401和编码模块402的相应功能。
图6给出了一种通信系统600的示意图，通信系统600中包括通信设备60和通信设备61，其中，信息数据在通信设备60和通信设备61之间接收和发送。通信设备60和61可以是所述通信装装置500或400，或者通信设备备60和61分别包括通信装置500或者400，对信息数据进行接收和/或发送。在一个例子中，通信设备60可以为终端，相应的通信设备61可以为基站；在另一个例子中，通信设备60为基站，相应的通信设备61可以为终端。
本领域技术人员还可以了解到本申请实施例列出的各种说明性逻辑块(illustrative logical block)和步骤(step)可以通过电子硬件、电脑软件，或两者的结合进行实现。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用，可以使用各种方法实现所述的功能，但这种实现不应被理解为超出本申请实施例保护的范围。
本申请所描述的技术可通过各种方式来实现。例如，这些技术可以用硬件、软件或者硬件结合的方式来实现。对于硬件实现，用于在通信装置(例如，基站，终端、网络实体、或芯片)处执行这些技术的处理单元，可以实现在一个或多个通用处理器、数字信号处理器(DSP)、数字信号处理器件(DSPD)、专用集成电路(ASIC)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合中。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。
本申请实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的指令、或者这两者的结合。存储器可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介。例如，存储器可以与处理器连接，以使得处理器可以从存储器中读取信息，并可以向存储器存写信息。可选地，存储器还可以集成到处理器中。处理器和存储器可以设置于ASIC中，ASIC可以设置于终端中。可选地，处理器和存储器也可以设置于终端中的不同的部件中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如， 软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。上面的组合也应当包括在计算机可读介质的保护范围之内。
本说明书中各个实施例之间相同或相似的部分可以互相参考。
以上所述的本申请实施方式并不构成对本申请保护范围的限定。

Claims (15)

  1. 一种通信方法，其特征在于，所述方法包括：
    根据调制编码方式MCS索引与码率的对应关系，确定与所述MCS索引对应的码率；
    根据与所述MCS索引对应的码率以及码率阈值确定编码矩阵类型；
    基于所述编码矩阵类型对应的编码矩阵对第一序列进行编码，其中，所述第一序列的长度小于或等于第一阈值。
  2. 根据权利要求1所述的方法，其特征在于，所述第一序列是由第二序列经过码块分割后得到的，所述第二序列的长度与所述MCS索引相关。
  3. 根据权利要求1或2所述的方法，其特征在于，所述根据与所述MCS索引对应的码率以及码率阈值确定所述编码矩阵类型，包括：
    当所述码率大于所述码率阈值时，确定所述编码矩阵类型为第一编码矩阵类型；或者，
    当所述码率小于或者等于所述码率阈值时，确定所述编码矩阵类型为第二编码矩阵类型；其中，所述第一编码矩阵类型对应的编码矩阵的尺寸大于所述第二编码矩阵类型对应的编码矩阵的尺寸。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，通过查表方式，根据所述MCS索引确定所述码率。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述编码矩阵类型包括:基图(Base graph)的类型，和/或奇偶校验矩阵的类型。
  6. 根据权利要求1-5任一项所述的方法，还包括：存储以下一项或多项：
    MCS索引与编码矩阵类型的对应关系；
    MCS索引与码率的对应关系；
    MCS索引、码率、以及编码矩阵类型的对应关系。
  7. 一种通信装置，其特征在于，包括：
    确定模块，用于根据调制编码方式MCS索引与码率的对应关系，确定与所述MCS索引对应的码率，以及根据与所述MCS索引对应的码率以及码率阈值确定编码矩阵类型；
    编码模块，用于基于所述编码矩阵类型对应的编码矩阵对第一序列进行编码，其中，所述第一序列的长度小于或等于第一阈值。
  8. 根据权利要求7所述的装置，其特征在于，所述第一序列是由第二序列经过码块分割后得到的，所述第二序列的长度与所述MCS索引相关。
  9. 根据权利要求7或8所述的装置，其特征在于，所述确定模块具体用于：当所述码率大于所述码率阈值时，确定所述编码矩阵类型为第一编码矩阵类型；或者，
    当所述码率小于或者等于所述码率阈值时，确定所述编码矩阵类型为第二编码矩阵类型；其中，所述第一编码矩阵类型对应的编码矩阵的尺寸大于所述第二编码矩阵类型对应的编码矩阵的尺寸。
  10. 根据权利要求7-9任一项所述的装置，其特征在于，所述确定模块用于通过查表方式，根据所述MCS索引确定所述码率。
  11. 根据权利要求7-10任一项所述的装置，其特征在于，所述编码矩阵类型包括:基图(Base graph)的类型，和/或奇偶校验矩阵的类型。
  12. 根据权利要求7-11任一项所述的装置，其特征在于，还包括存储器，用于存储以下一项或多项：
    MCS索引与编码矩阵类型的对应关系；
    MCS索引与码率的对应关系；
    MCS索引、码率、以及编码矩阵类型的对应关系。
  13. 一种通信装置，其特征在于，所述通信装置包括处理器、存储器以及存储在存储器上并可在处理器上运行的指令，当所述指令被运行时，使得所述通信装置执行如权利要求1至6任一项所述的方法。
  14. 一种计算机可读存储介质，包括指令，当其在通信装置上运行时，使得通信装置执行如权利要求1至6任一项所述的方法。
  15. 一种计算机程序，其特征在于，当所述程序被执行时，使得通信装置执行如权利要求1-6任一项所述的方法。
PCT/CN2018/099904 2017-08-11 2018-08-10 通信方法和装置 WO2019029690A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18842878.3A EP3657707B1 (en) 2017-08-11 2018-08-10 Communication method and device
US16/787,958 US11368241B2 (en) 2017-08-11 2020-02-11 Communication method and communications apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710687631.9 2017-08-11
CN201710687631 2017-08-11
CN201710807911.9 2017-09-08
CN201710807911.9A CN109391367B (zh) 2017-08-11 2017-09-08 通信方法和装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/787,958 Continuation US11368241B2 (en) 2017-08-11 2020-02-11 Communication method and communications apparatus

Publications (1)

Publication Number Publication Date
WO2019029690A1 true WO2019029690A1 (zh) 2019-02-14

Family

ID=65271020

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/099904 WO2019029690A1 (zh) 2017-08-11 2018-08-10 通信方法和装置

Country Status (1)

Country Link
WO (1) WO2019029690A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1953335A (zh) * 2005-10-21 2007-04-25 中兴通讯股份有限公司 支持任何码率/码长的低密度奇偶校验码编码装置和方法
CN101325474A (zh) * 2007-06-12 2008-12-17 中兴通讯股份有限公司 Ldpc码的混合自动请求重传的信道编码及调制映射方法
CN102412842A (zh) * 2010-09-25 2012-04-11 中兴通讯股份有限公司 一种低密度奇偶校验码的编码方法及装置
US20170026976A1 (en) * 2015-07-20 2017-01-26 Qualcomm Incorporated Flexible coding schemes
WO2017065942A1 (en) * 2015-10-14 2017-04-20 Intel IP Corporation Modulation and coding scheme codes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1953335A (zh) * 2005-10-21 2007-04-25 中兴通讯股份有限公司 支持任何码率/码长的低密度奇偶校验码编码装置和方法
CN101325474A (zh) * 2007-06-12 2008-12-17 中兴通讯股份有限公司 Ldpc码的混合自动请求重传的信道编码及调制映射方法
CN102412842A (zh) * 2010-09-25 2012-04-11 中兴通讯股份有限公司 一种低密度奇偶校验码的编码方法及装置
US20170026976A1 (en) * 2015-07-20 2017-01-26 Qualcomm Incorporated Flexible coding schemes
WO2017065942A1 (en) * 2015-10-14 2017-04-20 Intel IP Corporation Modulation and coding scheme codes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3657707A4 *

Similar Documents

Publication Publication Date Title
US11689220B2 (en) Method and device for interleaving data
CN109391367B (zh) 通信方法和装置
US11374591B2 (en) Apparatus and method for channel coding in communication system
JP6815537B2 (ja) 情報処理方法、機器、及び通信装置
CN108282246B (zh) 信息处理的方法、设备和通信系统
WO2019158031A1 (zh) 编码的方法、译码的方法、编码设备和译码设备
US11277153B2 (en) Method and apparatus for low density parity check channel coding in wireless communication system
JP2020522934A (ja) チェックマトリックスを決定するための方法および装置、ならびにコンピュータ記憶媒体
BR112019019253B1 (pt) método para realizar codificação com base na matriz de verificação de paridade do código de verificação de paridade de baixa densidade (ldpc) em um sistema de comunicação sem fio e terminal utilizando o mesmo
WO2020147526A1 (zh) 一种级联crc码的极化码编码方法及装置
WO2020098461A1 (zh) Polar码编码方法及装置
CN108282259A (zh) 一种编码方法及装置
WO2020147527A1 (zh) 一种极化编译码方法及装置
WO2019001477A1 (zh) 信息处理的方法、装置和通信设备
WO2018218466A1 (zh) 信息处理的方法和通信装置
WO2018218692A1 (zh) 信息处理的方法和通信装置
WO2018161946A1 (zh) 数据处理的方法和装置
WO2019029690A1 (zh) 通信方法和装置
TW202239153A (zh) 用於執行資料傳輸的區塊交插的方法和設備
CN108574555B (zh) 干扰随机化方法及设备
CN109067407B (zh) 信息处理的方法、装置和通信设备
WO2018201597A1 (zh) 信息处理的方法、通信装置
US20240323927A1 (en) Channel coding method and apparatus
WO2024164763A1 (zh) 数据传输方法、通信装置及存储介质
WO2018201609A1 (zh) 信息处理的方法和通信装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18842878

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018842878

Country of ref document: EP

Effective date: 20200217