WO2019001369A1

WO2019001369A1 - Driver for serialization/deserialization link transmitter

Info

Publication number: WO2019001369A1
Application number: PCT/CN2018/092455
Authority: WO
Inventors: 黄银涛; 罗多纳; 俞捷; 罗星云; 俞恢春
Original assignee: 华为技术有限公司
Priority date: 2017-06-29
Filing date: 2018-06-22
Publication date: 2019-01-03
Also published as: CN109213708B; CN109213708A

Abstract

A driver for a serialization/deserialization link transmitter, comprising: a first-stage driving circuit, used for amplifying a data signal received in real time to obtain and output a real-time pre-drive signal; a common-mode voltage adjustment circuit, connected to the first-stage driving circuit and used for responding to voltage adjustment indication information in real time so as to adjust the common-mode voltage of the real-time pre-drive signal in real time, thus obtaining an adjusted real-time pre-drive signal; and a second-stage driving circuit, connected to the voltage adjustment circuit and used for amplifying the adjusted real-time pre-drive signal and matching the impedance thereof to obtain and output a real-time differential data code stream.

Description

A serial deserial link transmitter driver

This application claims priority to Chinese Patent Application No. JP-A No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. Combined in this application.

Technical field

The embodiments of the present invention relate to the field of communications technologies, and in particular, to a driver for a serial deserial link transmitter.

Background technique

With the continuous development of communication technology, the high-speed Serializer/Deserializer (SERDES) communication link has become a research hotspot of high-speed data communication due to its large amount of data and fast communication speed.

The high-speed SERDES communication link has multiple connection modes. Please refer to Figure 1, which is a schematic diagram of the backplane communication SERDES link, which is a kind of high-speed SERDES communication link. In FIG. 1 , the communication daughter board is connected to the back board through the backplane connector, and the number of the communication daughter boards may be two, as shown in FIG. 1 , and of course, two or more may be provided. Taking FIG. 1 as an example, one of the communication sub-boards in FIG. 1 is provided with a signal transmitter chip, and the other communication sub-board is provided with a signal receiver chip. A differential data stream generated by the signal transmitter chip, via a Print Circuit Board (PCB) trace and board level passive components in the communication daughter board, to a backplane connection to the communication daughter board And then transmitting the differential data stream to the backplane connector connected to the communication daughter board configured with the signal receiver chip through the backplane signal link in the backplane, and configuring the signal receiver chip The board-level passive components of the communication daughter board, PCB traces, etc., finally arrive at the signal receiver chip.

Generally speaking, in high-speed PCB and system design, high-frequency signal lines, integrated circuit pins, various types of connectors, etc. may become radiation interference sources with antenna characteristics, and emit electromagnetic waves, thereby causing electromagnetic interference (Electromagnetic Interference) , EMI), causing some devices in the system or other adjacent systems to malfunction, signal distortion transmitted in the system, and the like. With the increase of integration, the distance of each radiation interference source in the high-speed SERDES communication link is closer, and the problem of EMI becomes more and more serious. It can be seen that solving the problem of EMI of high-speed SERDES communication links is extremely urgent.

EMI is mainly divided into two types: common-mode radiation (CM radiation) interference and differential-mode radiation (DM radiation) interference. The research shows that regardless of the connection mode of the high-speed SERDES communication link, the common mode radiation interference of EMI is more significant than the differential mode radiation interference. Therefore, in high-speed SERDES communication links, controlling common-mode radiated interference is especially important in solving EMI problems.

In the prior art, common mode radiated interference can be controlled by compensating for the rising and falling edges of the differential data stream. Specifically, by adjusting the slew rate of the rising edge and/or the falling edge of the differential data stream, the rising and falling edges of the differential data stream are always in a matching state, thereby weakening the common mode noise component at a single frequency point.

The above technical solution essentially spreads the common mode noise component at a single frequency point evenly over the entire wideband spectrum, while eliminating the peak of the common mode noise component at a single frequency point, thereby reducing the totality of the differential data stream to a certain extent. Modulo noise, however, when the slew rate of the rising and/or falling edges of the differential data stream is adjusted, the jitter of the data on the rising and/or falling edges is increased, resulting in a difference in the output. The quality of the data stream eye diagram is degraded, which affects the communication quality. Therefore, how to reduce the common mode noise of the differential data stream and minimize the impact on the communication quality is a technical problem to be solved.

Summary of the invention

Embodiments of the present invention provide a driver for a serial deserial link transmitter for reducing a common mode noise component of a differential data stream while preserving the performance of a high speed SERDES communication link.

In a first aspect, a driver for a serial deserial link transmitter is provided, the driver comprising a first stage drive circuit, a common mode voltage regulation circuit, and a second stage drive circuit. The first stage driving circuit is configured to amplify the real-time received data signal to obtain and output a real-time pre-driving signal; the common-mode voltage adjusting circuit is connected to the first-level driving circuit for real-time response voltage adjustment indication Information, in real time adjusting the common mode voltage of the real-time pre-drive signal to obtain an adjusted real-time pre-drive signal; the second-stage drive circuit is connected to the voltage adjustment circuit for real-time pre-drive of the adjustment The signal is amplified and impedance matched, and a real-time differential data stream is obtained and output.

In the embodiment of the present invention, an adjustment circuit is added under the structure of the two-stage cascade output drive of the existing first-stage driving circuit and the second-stage driving circuit, and the input signal of the second-stage driving circuit is passed through the common-mode voltage adjusting circuit. The common mode voltage is adjusted in real time to enable the differential data stream when the difference between the amplitude of the differential data stream output by the second stage drive circuit and the amplitude required by the SERDES link transmitter is less than or equal to a predetermined threshold The common mode noise reaches a small value of the adjustment process, that is, when the differential data code stream is output, the common mode noise can be reduced, thereby fundamentally reducing the common mode noise. Moreover, since the common mode noise of the differential data stream has been reduced at the time of output, there is no need to perform other processing, such as modulation processing, on the differential data stream, which may change the eye pattern of the differential data stream. Therefore, there is no problem that the bit error rate is high due to the change of the eye pattern of the differential data stream, and the influence on the communication quality can be reduced.

Moreover, in the embodiment of the present invention, only the adjustment circuit is added in the circuit structure of the original driver, so that the effect of fundamentally reducing the common mode noise of the differential data code stream can be realized under the premise of introducing fewer auxiliary circuits, and the implementation manner is simple. .

In a possible design, the driver further includes: a common mode voltage regulation indicating circuit, wherein an input end of the common mode voltage regulation indicating circuit is connected to an output end of the second stage driving circuit, and the output of the common mode voltage adjusting indicating circuit The terminal is connected to the voltage regulating circuit, configured to generate the voltage adjustment indication information according to the common mode noise of the real-time differential data code stream output by the second-stage driving circuit, and output the voltage adjustment indication information to the common mode voltage regulating circuit Therefore, the voltage regulating circuit generates a control voltage according to the received voltage adjustment indication information, and obtains the adjusted real-time pre-drive signal by the common mode voltage of the real-time pre-drive signal by the control voltage.

In the above technical solution, the common mode voltage adjustment indication circuit is capable of generating voltage adjustment indication information according to the real-time differential data code stream output by the second-stage driving circuit, so that the voltage adjustment module can self-mode noise according to the real-time differential data code stream. Adapting to the common mode voltage of the pre-driver signal simplifies the adjustment process.

In one possible design, the common mode voltage regulation indication circuit includes a common mode noise component detection module and a voltage adjustment indication generation module, wherein:

An input end of the common mode noise component detecting module is connected to an output end of the second stage driving circuit, and an output end of the common mode noise component detecting module is connected to an input end of the voltage regulating indication generating module of the common mode voltage adjusting indicating circuit And detecting common mode noise of the real-time differential data stream output by the second-stage driving circuit, and moving the frequency of the common-mode noise of the real-time differential data stream from N times the Nyquist frequency to the direct current, Outputting the obtained real-time DC component to the voltage adjustment indication generating module; wherein N is a multiple of 2;

The output of the voltage regulation indication generating module is connected to the common mode voltage regulating circuit, and configured to generate the voltage adjustment indication information according to the received real-time DC component, and output the voltage adjustment indication information to the common mode voltage adjustment circuit.

In the above technical solution, the common mode voltage adjustment indication circuit is divided into a common mode noise component detection module and a voltage adjustment indication generation module, and the common mode noise component detection module firstly uses the common mode noise component detection module to share the common mode noise of the real time differential data stream. The frequency is moved to the DC, and then the voltage adjustment indication generating module generates the voltage adjustment indication information according to the DC component, the circuit is simple to implement, and the DC component is directly processed, and the processing amount of the voltage adjustment indication generation module can be reduced.

In one possible design, the voltage adjustment indication generation module includes a sampling unit, a comparison unit, and an integration unit, wherein:

The input end of the sampling unit is connected to the output end of the common mode noise component detecting module, and the output end of the sampling unit is connected to the input end of the comparing unit for performing real-time DC component output by the common mode noise component detecting module. Sampling, outputting the obtained real-time sampling signal to the comparison unit;

The output end of the comparison unit is connected to the input end of the integration unit, and is used for comparing the real-time sampling signal in the current sampling period with the sampling signal in one sampling period before the current sampling period, and realizing the obtained sampling signal in real time. The comparison result is output to the integration unit;

An output end of the integration unit is connected to the common mode voltage adjustment circuit, and is configured to integrate the received real-time comparison result of the sampling signal, generate the voltage adjustment indication information according to the integration result, and output the obtained voltage adjustment indication information to the Common mode voltage regulation circuit.

In the above technical solution, the voltage adjustment instruction generation module is realized by a simple structure of the sampling unit, the comparison unit, and the integration unit, and the implementation manner is simple.

In one possible design, the drive also includes:

a bias current adjustment circuit is connected to the first stage driving circuit for real-time response to the current adjustment indication information to perform real-time adjustment of the bias current of the first stage driving circuit, and output the adjusted real-time bias current to The first stage driving circuit outputs the real-time pre-drive signal under the adjusted real-time bias current.

In the above technical solution, in addition to improving the common mode noise of the real-time differential data stream by adjusting the common mode voltage of the real-time pre-drive signal, the bias of the first-stage driving circuit can be adjusted in real time before the real-time pre-drive signal is output. By setting the current and adjusting the amplitude of the real-time pre-drive signal, combined with the amplitude of the real-time pre-drive signal and the common-mode voltage, the common-mode noise of the real-time differential data stream can be further reduced.

In one possible design, the drive further includes:

a current adjustment indicating circuit, wherein an input end of the current regulating indicating circuit is connected to an output end of the second stage driving circuit, and an output end of the current regulating indicating circuit is connected to the bias adjusting circuit for driving according to the second stage driving circuit The amplitude of the output real-time differential data stream generates current adjustment indication information and outputs the current adjustment indication information to the bias current adjustment circuit.

In the above technical solution, by connecting the current adjustment indicating circuit at the output end of the second-stage driving circuit, the bias current of the first-stage driving circuit is adjusted in real time through the amplitude of the real-time differential data code stream output by the second-stage driving circuit, thereby realizing Adaptive feedback adjustment simplifies the adjustment process.

In one possible design, the current regulation indicating circuit includes an amplitude detecting module and a current regulating indicating generating module, wherein:

An input end of the amplitude detecting module is connected to an output end of the second stage driving circuit, and an output end of the amplitude detecting module is connected to an input end of the current adjusting indication generating module, and is configured to detect a real-time output of the second-level driving circuit The amplitude of the differential data stream is output to the detected current adjustment indication code generating module;

The output of the current adjustment indication generating module is connected to the bias current adjustment circuit, and is configured to compare the amplitude of the received real-time differential data stream with a preset amplitude, according to the amplitude of the real-time differential data stream and the pre- The result of the comparison of the amplitudes generates the current adjustment indication information, and the obtained current adjustment indication information is output to the bias current adjustment circuit.

In the above technical solution, the current adjustment indicating circuit is divided into two parts: an amplitude detecting module and a current adjusting indicating generating module. First, the amplitude of the real-time differential data stream is obtained by the amplitude detecting module, and then according to the amplitude of the real-time differential data stream. Generating current adjustment indication information according to the magnitude relationship of the preset amplitude. For example, if the amplitude of the real-time differential data stream is less than the preset amplitude, generating current adjustment indication information for increasing the bias current, otherwise generating a bias current reduction Current adjustment indication information, the circuit is simple to implement.

In a second aspect, a driver for a serial deserial link transmitter is provided, the driver comprising a first stage driving circuit, a bias current adjusting circuit and a second stage driving circuit, wherein: a bias current adjusting circuit, and the a first-level driving circuit connection for real-time response to current adjustment indication information, real-time adjustment of the bias current of the first-stage driving circuit, and outputting the adjusted real-time bias current; the first-level driving circuit is used for Under the adjusted real-time bias current, the real-time received data signal is amplified to obtain and output a real-time pre-drive signal; the second-stage driving circuit is connected to the first-stage driving circuit for The real-time pre-drive signal is subjected to amplification processing and impedance matching processing to obtain and output a real-time differential data stream.

In the embodiment of the present invention, under the structure of the two-stage cascade output drive of the existing first-stage driving circuit and the second-stage driving circuit, the bias current adjusting circuit is added, and the first stage is adjusted by bias current adjustment indication information. The bias current of the input signal of the driving circuit is adjusted to change the amplitude of the real-time pre-drive signal output by the first-stage driving circuit to the amplitude of the real-time differential data stream outputted by the second-stage driving circuit and the SERDES link transmitter When the difference between the required amplitudes is less than or equal to the preset threshold, the common mode noise component of the differential data stream can be made to reach a smaller value of the adjustment process, that is, the common mode noise of the differential data stream when outputting The component can be reduced, thereby fundamentally reducing the common mode noise component; and since the common mode noise component of the differential data stream has been reduced at the output, there is no need to add a choke and no need Performing other processing on the differential data stream that may change the eye pattern of the differential data stream, for example, modulation processing, etc., so that there is no reduction in SERDES link transmission. Data transfer rate or error rate change due to problems caused by eye differential data stream, affecting the quality of communication can be reduced machine.

In one possible design, the drive further includes:

In one possible design, the current regulation indicating circuit includes an amplitude detecting module and a current regulating indication generating module, wherein:

In the embodiment of the present invention, the common mode voltage adjustment circuit and/or the bias current adjustment circuit are added by the two-stage cascade output drive structure of the existing first stage drive circuit and the second stage drive circuit, thereby Real-time adjustment of the common mode voltage of the input signal of the second stage driving circuit by the common mode voltage adjusting circuit and/or real-time adjustment of the signal amplitude of the output signal of the first stage driving circuit by the bias current adjusting circuit When the difference between the amplitude of the differential data stream output by the secondary driving circuit and the amplitude required by the SERDES link transmitter is less than or equal to a preset threshold, the common mode noise component of the differential data stream can be compared to the adjustment process. A small value, that is, when the differential data stream is output, its common mode noise component can be reduced, thereby fundamentally reducing the common mode noise component, thereby eliminating the need to change the differential data stream again. Other processing of the eye diagram of the data stream will naturally not reduce the data transmission rate of the SERDES link transmitter or the eye diagram due to the differential data stream. Problems resulting error rate is increased, the influence of the communication quality can be reduced.

DRAWINGS

1 is a schematic diagram of a backplane communication SERDES link in the prior art;

2 is a block diagram showing the basic structure of a high-speed SERDES communication link in the prior art;

3 is a schematic diagram showing the P-channel signal and the N-channel signal of the differential data code stream exhibiting a rising edge and a falling edge mismatch, and a spectrum diagram of the differential data code stream;

4 is a schematic diagram showing relationship between amplitudes of input signals and amplitudes of output signals and common mode noise of output signals obtained by testing multiple sets of current mode logic driving circuits according to an embodiment of the present invention;

5 is a schematic diagram showing relationship between a common mode voltage of an input signal and a magnitude of an output signal and a common mode noise of an output signal obtained by testing a plurality of sets of current mode logic driving circuits according to an embodiment of the present invention;

6 is a first structural block diagram of a driver of a SERDES link transmitter according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a connection manner between a common mode voltage adjustment circuit 602 and a first stage driving circuit 601 according to an embodiment of the present invention;

FIG. 8 is a circuit diagram of a specific implementation of a common mode voltage adjustment circuit 602 according to an embodiment of the present invention;

FIG. 9 is a second structural block diagram of a driver of a SERDES link transmitter according to an embodiment of the present invention;

FIG. 10 is a circuit diagram of a specific implementation of a common mode noise component detecting module 6041 according to an embodiment of the present invention;

FIG. 11 is a circuit diagram of a specific implementation of a voltage adjustment indication generating module 6042 according to an embodiment of the present invention;

12A is a schematic diagram of a first waveform accumulated by an integrator according to a comparison result according to an embodiment of the present invention;

12B is a schematic diagram of a second waveform accumulated by the integrator according to the comparison result according to an embodiment of the present invention;

FIG. 13 is a third structural block diagram of a driver of a SERDES link transmitter according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a connection manner between a bias current adjustment circuit 1302 and a first-stage driving circuit 1301 according to an embodiment of the present invention;

FIG. 15 is a circuit diagram of a specific implementation of a bias current adjustment circuit 1302 according to an embodiment of the present invention;

16 is a fourth structural block diagram of a driver of a SERDES link transmitter according to an embodiment of the present invention;

FIG. 17 is a circuit diagram of a specific implementation of the amplitude detecting module 13041 according to an embodiment of the present invention;

FIG. 18 is a circuit diagram of a specific implementation of a current adjustment indication generating module 13042 according to an embodiment of the present invention;

FIG. 19 is a fifth structural block diagram of a driver of a SERDES link transmitter according to an embodiment of the present invention;

FIG. 20 is a sixth structural block diagram of a driver of a SERDES link transmitter according to an embodiment of the present invention.

Detailed ways

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

The term "and/or" in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist separately. B these three situations. In addition, the character "/" in this article, unless otherwise specified, generally indicates that the contextual object is an "or" relationship. The character "," in this article, unless otherwise specified, generally means that the contextual object is a kind of " And the relationship.

First, the structure of the high-speed SERDES communication link is briefly introduced.

Please refer to FIG. 2, which is a basic structural block diagram of a high speed SERDES communication link. The high speed SERDES communication link includes three basic modules: a SERDES link transmitter 20, a passive link 21, and a SERDES link receiver 22. The SERDES link transmitter 20 includes an encoder, a clock generation circuit, a parallel-serial conversion circuit, and a driver; the SERDES link receiver 22 includes a decoder, a clock recovery circuit, a serial-to-parallel conversion circuit, and a receiver; and the passive link 21 Including PCB traces, connectors, etc.

The high-speed SERDES communication link shown in Figure 2 works as follows when performing data transmission:

The SERDES link transmitter 20 receives the parallel differential signal to be transmitted, encodes the parallel differential signal via an encoder in the SERDES link transmitter 20, and then the parallel-serial conversion circuit in the SERDES link transmitter 20 transmits using the SERDES link The high-speed clock generated by the clock generating circuit in the machine 20 serially transmits the encoded parallel differential signals to the driver in the SERDES link transmitter 20 in order from low to high, and finally passes the parallel-to-serial conversion circuit through the driver. The transmitted serial differential signal is subjected to signal amplification and impedance matching processing, and the obtained differential data stream is output to the passive link 21 of the high-speed SERDES communication link, and transmitted to the SERDES of the high-speed SERDES communication link via the passive link 21. Link receiver 22. The SERDES link receiver 22 first receives the differential data stream transmitted by the SERDES link transmitter 20 through the receiver in the SERDES link receiver 22, and then the differential data code through the serial to parallel conversion circuit in the SERDES link receiver 22. The stream is subjected to deserialization processing, and the demultiplexed differential data code stream is decoded by the decoder in the SERDES link receiver 22, and finally the parallel differential signal to be transmitted is obtained, thereby realizing the parallel differential signal transmission.

In a specific implementation, the high-speed SERDES communication link may have multiple implementation manners, such as the backplane communication SERDES link shown in FIG. 1, or a SERDES link connected by a coaxial cable, etc., in the embodiment of the present invention. There is no limitation on the specific implementation structure of the high speed SERDES communication link.

According to the above description of the high-speed SERDES communication link, when the parallel-serial conversion circuit in the high-speed SERDES communication link transmits the serial differential signal to the driver, the driver performs signal amplification and impedance matching processing on the serial differential signal. However, due to the nonlinear characteristics of the transistors in the driver or the improper setting of the static operating point of the driver, the driver operates in a nonlinear region, which causes nonlinear distortion of the differential data bit stream output by the driver.

When the differential data stream is nonlinearly distorted, as shown in FIG. 3, the rising edge and the falling edge time of the P signal and the N signal of the differential data bit stream are different, and the rising edge and the falling edge do not match. Wherein, the amplitude of the N signal is reduced to half of the original amplitude, and the adjusted N signal is obtained, and the adjusted N signal and the P signal are superimposed to obtain a common mode component of the differential data stream, and P The path signal is subtracted from the N channel signal to obtain a differential mode component of the differential data stream. The common mode component and the differential mode component are separately spectrally transformed to obtain a schematic diagram of the spectrum on the right side of FIG. As can be seen from the spectrum diagram, the common mode component and the differential mode component exhibit a single-frequency noise component at a Nyquis frequency of an integer multiple of 3, such as twice the Nyquist frequency point, the quadruple Nyquist frequency point, and eight. Times Nyquist frequency points. However, since the single-frequency noise component at twice the Nyquist frequency point is the largest, and the noise component at the quadruple Nyquist frequency point or the eight-fold Nyquist frequency point belongs to the harmonic component of the noise component at twice the Nyquist frequency point, the signal is transmitted. Attenuation occurs during the process, so the harmonic components may be small and difficult to detect. Therefore, in practical engineering applications, only the common mode noise component of the common mode component of the differential data stream at twice the Nyquist frequency is observed. And a differential mode noise component of the differential mode component at twice the Nyquist frequency. In the following description, the common mode noise is a common mode noise component at twice the Nyquist frequency point, and the differential mode noise is a differential mode noise component at twice the Nyquist frequency point as an example.

In the EMI problem, the noise of the common mode component is more easily radiated into the space by the PCB traces or connectors and other connection structures in the passive link than the noise of the differential mode component, and the energy is relatively large. The single-frequency noise component exacerbates the EMI problem. Therefore, the single-frequency noise component of the common-mode component at twice the Nyquist frequency is a major factor affecting the EMI problem of the high-speed SERDES communication link. It is further known that if the single-frequency noise component of the common-mode component of the differential data stream in the high-speed SERDES communication link at twice the Nyquist frequency is suppressed, the EMI problem of the high-speed SERDES communication link is solved.

Below, a way to address EMI issues in high-speed SERDES communication links is described:

In the driver that outputs the differential data stream, two output nodes are added, wherein the first output node is used to make the rising edge of the output differential data stream have a higher conversion rate than the falling edge of the output differential data stream The slew rate, the second output node is used to cause the slew rate of the rising edge of the output differential data stream to be less than the slew rate of the falling edge of the output differential data stream.

In the specific implementation process, the output of the driver is feedback-adjusted by monitoring the matching of the rising edge and the falling edge of the output differential data stream in real time. If the rising edge of the differential data stream output by the driver lags the falling edge, the signal in the driver is processed by the first output node in the driver before the differential code stream is output; if the differential data code output by the driver The rising edge of the stream leads the falling edge, and the signal in the driver is processed by the second output node in the driver before the differential code stream is output, so that the rising edge of the differential data stream output by the driver is The falling edge is always in a matching state.

By changing the matching state of the rising edge and the falling edge of the differential data stream outputted by the driver, the output of the differential data stream is uniformly dispersed to the spectrum of the entire differential data stream at a single-frequency noise component at twice the Nyquist frequency. Broadband, which reduces the peak of the noise component at twice the Nyquist frequency, reduces the single-frequency noise component of the common-mode component at twice the Nyquist frequency, and thus solves the EMI problem to some extent.

In the above technical solution, although the data modulation technique reduces the influence of the single-frequency noise component of the common mode component at the double Nyquist frequency point on the EMI characteristics of the high-speed SERDES communication system, the differential data is adopted by the data modulation technique. When the rising edge and the falling edge of the code stream are switched, the jitter of the rising edge and the falling edge is increased, so that the quality of the output of the differential data stream is degraded, which affects the communication quality, for example, increasing the bit error rate.

And the analysis of the foregoing technical solution shows that the differential data code stream outputted in the above technical solution still has a large common mode noise component, but after the differential data code stream is generated, the differential data code stream is further performed. Some modulation processing weakens the influence of the single-frequency noise component of the common-mode noise component at twice the Nyquist frequency on the EMI problem, and does not fundamentally eliminate the above-mentioned large common-mode noise. That is to say, if the above-mentioned large common mode noise is fundamentally eliminated, that is, the differential data code stream output by the SERDES link transmitter itself does not have a large common mode noise component, the EMI problem is solved; Moreover, the differential data code stream is generated without further processing, and the eye diagram of the differential data stream is not affected, thereby reducing the impact on communication quality. Accordingly, embodiments of the present invention are directed to a driver for a SERDES link transmitter capable of fundamentally reducing a single frequency noise component of a common mode component of a differential data stream at twice the Nyquist frequency.

In order to determine how to fundamentally reduce or eliminate the single-frequency noise component of the common-mode component of the differential data stream at twice the Nyquist frequency, the embodiment of the present invention applies multiple sets of Current Mode Logic (CML) driving circuits. Performing tests to maintain the rate of the output differential data stream of the multiple sets of CML driver circuits, and measure the amplitude of the input signal, the common mode voltage of the input signal, the common mode noise of the output signal, and the amplitude of the output signal, and The average value of each measurement parameter is obtained, and the schematic diagrams of FIG. 4 and FIG. 5 are obtained.

Figure 4 is a schematic diagram showing the relationship between the amplitude of the input signal and the amplitude of the output signal and the common mode noise of the output signal. It can be seen from Fig. 4 that the amplitude of the output signal is proportional to the amplitude of the input signal, and the common mode noise of the output signal is proportional to the amplitude of the input signal, and the amplitude of the output signal is also proportional to the common mode noise of the output signal. Further, as can be seen from FIG. 4, when the amplitude of the output signal is maintained at a large value, for example, greater than 300 mv, that is, the shaded area in FIG. 4, at this time, the smaller the amplitude of the input signal, the smaller the common mode noise of the output signal. That is, by limiting the amplitude of the input signal, the common mode noise of the output signal can be effectively suppressed.

Figure 5 is a schematic diagram showing the relationship between the common mode voltage of the input signal and the amplitude of the output signal and the common mode noise of the output signal. As can be seen from FIG. 5, when the amplitude of the output signal is maintained at a large value, for example, greater than 300 mv, that is, the shaded area in FIG. 5, the larger the common mode voltage of the input signal, the smaller the common mode noise of the output signal. That is, by increasing the common mode voltage of the input signal, the common mode noise of the output signal can be suppressed. Of course, the reduced relationship between the common mode voltage of the input signal and the common mode noise of the output signal may be different from the linear reduction in FIG. 5, for example, may be stepwise reduction or sawtooth reduction, which is implemented in the present application. There are no restrictions in the examples.

Therefore, the embodiment of the present invention considers that the common mode noise of the differential data stream should be fundamentally reduced, including but not limited to the following three modes:

The first way: adjust the amplitude of the input signal of the driver of the SERDES link transmitter;

The second way: adjusting the common mode voltage of the input signal of the driver of the SERDES link transmitter;

The third way is to adjust the amplitude of the input signal of the driver of the SERDES link transmitter and the common mode voltage of the input signal.

In the following, the manner of adjusting the common mode voltage of the input signal of the driver of the SERDES link transmitter is first introduced.

Embodiments of the present invention provide a driver for a SERDES link transmitter, which increases a common mode voltage adjustment circuit by using a two-stage cascade output drive structure of an existing first stage drive circuit and a second stage drive circuit, and The common mode voltage of the input signal of the second stage driving circuit is adjusted in real time by the common mode voltage regulating circuit to the difference between the amplitude of the differential data stream outputted by the second stage driving circuit and the amplitude required by the SERDES link transmitter When the value is less than or equal to the preset threshold, the common mode noise component of the differential data stream can reach a smaller value of the adjustment process, that is, when the differential data stream is output, the common mode noise component can be reduced. Thereby, the common mode noise component can be fundamentally reduced; and since the common mode noise component of the differential data stream has been reduced at the output, there is no need to perform the differential data stream again, possibly changing the differential data code Other processing of the stream's eye diagram, such as modulation processing, etc., so that there is no eye diagram that reduces the data rate of the SERDES link transmitter or due to the differential data stream The problem of high bit error rate caused by the change reduces the impact on communication quality.

Moreover, in the embodiment of the present invention, only the adjustment circuit is added in the circuit structure of the original driver, so that the effect of fundamentally reducing the common mode noise component of the differential data code stream can be realized under the premise of introducing fewer auxiliary circuits. simple.

The technical solution provided by the embodiment of the present invention is described below with reference to the accompanying drawings. In the following description, the technical solution provided by the present invention is applied to the application scenario shown in FIG. 2 as an example.

Referring to FIG. 6, an embodiment of the present invention provides a driver for a SERDES link transmitter, the driver including a first stage driving circuit 601, a common mode voltage adjusting circuit 602, and a second stage driving circuit 603. When the first stage driving circuit 601 receives the data signal, the data signal received in real time is amplified, and then the obtained real-time pre-driving signal is output to the common mode voltage adjusting circuit 602. After receiving the real-time pre-drive signal, the common-mode voltage adjustment circuit 602 adjusts the common-mode voltage of the real-time pre-drive signal according to the voltage adjustment indication information, so that the common-mode voltage of the pre-drive signal is adjusted to enable the output of the driver. The common mode noise of the real-time differential data stream reaches a predetermined value of a smaller value, thereby obtaining an adjusted real-time pre-drive signal, and the adjusted real-time pre-drive signal is used as an input signal of the second stage adjustment circuit 603. After receiving the adjusted real-time pre-drive signal, the second-stage driving circuit 603 performs amplification and impedance matching processing on the adjusted real-time pre-drive signal, and finally outputs real-time differential data for transmission in the high-speed SERDES link. Code stream.

In practical applications, since the first stage driving circuit 601 is mainly used to drive the second stage driving circuit 603 to operate, the first stage driving circuit 601 can be implemented by a driver having a relatively small size and power, for example, forming the first The size of the driver of the stage driving circuit 601 is less than or equal to half the size of the driver constituting the second stage driving circuit 603, and the specific size and power need to be determined according to the demand of the SERDES link and the magnitude or magnitude of the voltage of the received data signal. There are no restrictions here.

The common mode voltage adjustment circuit 602 is connected to the first stage drive circuit 601. In the process of adjusting the common mode voltage of the real-time pre-drive signal by the common mode voltage adjustment circuit 602, it is necessary to monitor the amplitude of the real-time differential data stream output by the second-stage driving circuit 603 and the common mode noise component in real time, for example, The oscilloscope monitors in real time the amplitude of the differential data stream output by the driver of the SERDES transmitter and the common mode noise component at twice the Nyquist frequency. If the amplitude of the differential data stream output by the driver of the SERDES transmitter does not satisfy the preset amplitude requirement, for example, less than 300 mv or less than 500 mv, the common mode voltage of the input signal shown in FIG. 5 and the common mode of the output signal may be used. The relationship between the noise is outputted to the common mode voltage adjustment circuit 602 by manual operation or other control device outside the driver, so that the common mode voltage adjustment circuit 602 increases the pre-drive under the action of the voltage adjustment indication information. The common mode voltage of the signal until the amplitude of the differential data stream output by the driver of the SERDES transmitter satisfies a preset amplitude requirement, for example, 300 mv or more and 330 mv or less, or 500 mv or more and 520 mv or less. If the amplitude of the differential data stream output by the driver of the SERDES transmitter meets the preset amplitude requirement, the voltage adjustment indication information may be output to the common mode voltage adjustment circuit 602 by manual operation or other control devices outside the driver. Therefore, the common mode voltage adjustment circuit 602 adjusts the common mode voltage of the pre-drive signal under the action of the voltage adjustment indication information. For example, continue to increase the common mode voltage of the pre-drive signal, and monitor the change of the common mode noise component of the differential data bit stream of the driver output of the SERDES transmitter at twice the Nyquist frequency point by an oscilloscope in real time: if the adjusted The common mode noise component of the differential data stream at twice the Nyquist frequency is larger than the common mode noise component of the differential data stream before the adjustment at twice the Nyquist frequency, and the common mode voltage adjustment circuit is controlled by the voltage adjustment indication information. 602 reducing the common mode voltage of the pre-drive signal; if the adjusted differential data stream has a common mode noise component at twice the Nyquist frequency point than the differential data stream before the adjustment, the common mode noise at twice the Nyquist frequency point When the component is small, the common mode voltage adjustment circuit 602 is controlled by the voltage adjustment indication information to increase the common mode voltage of the pre-drive signal. After a plurality of adjustments, for example, the adjustment process takes a preset time period or the preset number of times reaches a preset number of times, determining the common mode of the differential data code stream output by the driver of the SERDES transmitter at twice the Nyquist frequency point. The common mode voltage of the pre-drive signal when the noise component is the minimum value in the multiple adjustment process is a preset voltage, or the differential data code stream outputting the driver of the SERDES transmitter is determined to be at twice the Nyquist frequency point. The mode noise component is less than a common mode voltage of the pre-drive signal corresponding to the common mode noise component of the differential data bit stream of the SERDES transmitter before the multiple adjustment is corresponding to the common mode noise component of the Nyquist frequency point, And through the voltage adjustment indication information, the control common mode voltage adjustment circuit 602 sets the common mode voltage of the pre-drive signal to the preset voltage. Thus, the common mode noise component of the differential data stream output by the driver of the SERDES link transmitter is improved when the above adjustment process is completed.

In practical applications, the differential data stream is usually output as two signals of the P signal and the N signal. Therefore, the first stage driving circuit 601 also outputs the signal by using two signals, that is, the first stage driving. Circuit 601 has two outputs. Therefore, the common mode voltage adjusting circuit 602 and the first stage driving circuit 601 can be connected in series between two output terminals of the first stage driving circuit 601, and the common mode voltage adjusting circuit 602 is set in two. Between the resistive elements, for example, the common mode voltage regulating circuit 602 is connected to point A of the two resistive elements as shown in FIG. The common mode voltage adjustment circuit 602 generates and outputs a control voltage, and the divided voltage between the two output terminals of the first stage driving circuit 601 is adjusted by the control voltage, so that the two output ends of the first stage driving circuit 601 are output. The common mode voltage of the pre-drive signal is adjusted to the preset voltage.

Specifically, the common mode voltage adjustment circuit 602 can be implemented by a digital analog converter (DAC). As shown in FIG. 8, the V ₀ in FIG. 8 is connected to the point A in FIG. The communication interface of the SERDES link transmitter configuration, such as the Serial Peripheral Interface (SPI), modifies the control word data of the DAC stored in the register of the SERDES link transmitter, ie, S ₀ , S ₁ , S ₂ ... S _n-1 , to control the weight of the resistor network of each R-2R in FIG. 8 and the gain multiplier of the operational amplifier connected to the resistor network of the R-2R, thereby adjusting the control voltage of the DAC output. For example, the common mode voltage of the pre-drive signal can be adjusted using a monotonically increasing or monotonically decreasing adjustment, and the DAC control word corresponding to the preset voltage is stored in a register of the SERDES link transmitter. Of course, there are many specific circuit designs of the adjustment circuit 602, which are not limited in the embodiment of the present invention.

After the above adjustment process is completed, the common mode voltage adjustment circuit 602 adjusts the common mode voltage of the pre-drive signal according to the DAC control word stored in the register, thereby obtaining the adjusted pre-drive signal.

The second stage driving circuit 603 is connected to the common mode voltage adjusting circuit 602. In practical applications, the differential data bit stream output by the second stage driving circuit 603 needs to drive PCB traces, backplane connectors, etc. outside the SERDES link transmitter. Therefore, the second stage driving circuit 603 is generally large in size. Drive implementation of power consumption. The specific size and power need to be determined according to the requirements of the SERDES link and the magnitude or magnitude of the voltage of the received pre-drive signal received, which is not limited herein.

In the embodiment of the present invention, the common mode voltage of the input signal of the second stage driving circuit 603 is adjusted by the common mode voltage adjusting circuit 602, so that the common mode noise component of the differential data bit stream output by the driver of the SERDES link transmitter is obtained. It has been improved at the output, thereby fundamentally reducing the common mode noise component of the differential data stream output by the SERDES link transmitter.

Although the driver of the above structure has fundamentally reduced the common mode noise component of the differential data bit stream output by the SERDES link transmitter, the adjustment process of the common mode voltage regulating circuit 602 is complicated, in order to simplify the common mode voltage regulating circuit. Referring to FIG. 9, the driver further includes a common mode voltage adjustment indicating circuit 604 for replacing the differential data stream of FIG. 6 for real-time monitoring of the driver output of the SERDES transmitter with the common mode voltage adjustment indicating circuit 604. The amplitude and the oscilloscope of the common mode noise component at twice the Nyquist frequency and the manual operation for outputting the voltage regulation indication information or the regulation device outside the driver. An input end of the common mode voltage adjustment indicating circuit 604 is connected to an output end of the second stage driving circuit 603, and an output end of the common mode voltage adjusting indicating circuit 604 is connected to the common mode voltage adjusting circuit 602 for use according to the real time differential data stream. The common mode noise generates voltage adjustment indication information, and outputs the voltage adjustment indication information to the common mode voltage adjustment circuit 602, so that the common mode voltage adjustment circuit 602 generates and outputs a control voltage according to the received voltage adjustment indication information, and passes the The control voltage adjusts the common mode voltage of the pre-drive signal. Therefore, by detecting the common mode noise in the differential data bit stream output by the second stage driving circuit 603, the common mode voltage adjusting circuit 602 is feedback controlled to realize adaptive adjustment, which simplifies the adjustment process.

In the embodiment of the present invention, the common mode voltage adjustment indication circuit 604 includes a common mode noise component detection module 6041 and a voltage adjustment indication generation module 6042. among them:

The input end of the common mode noise component detecting module 6041 is connected to the output end of the second stage driving circuit 603, and the output end of the common mode noise component detecting module 6041 is connected to the input end of the voltage adjusting instruction generating module 6042 for detecting the driver output. The differential data code stream is at a common mode noise component at twice the Nyquist frequency point, and the frequency of the common mode noise component is shifted to DC, and the obtained DC noise component is output to the voltage adjustment indication generating module 6042;

The output of the voltage adjustment indication generating module 6042 is connected to the common mode voltage adjustment circuit 602 for generating the voltage adjustment indication information according to the received DC noise component, and outputting the voltage adjustment indication information to the common mode voltage adjustment circuit 602.

As an example, the common mode noise component detection module 6041 may be composed of two capacitive elements, a down mixer, a frequency source, and a low pass filter, as shown in FIG. The two capacitive elements are respectively disposed at the two output ends of the second stage driving circuit 603 for acquiring the common mode noise component of the differential data code stream output by the driver at twice the Nyquist frequency point. One input of the down mixer is disposed between the two capacitive elements, the other input is connected to the frequency source, the output is connected to the input of the low pass filter, and the output of the low pass filter and the voltage adjustment indication The generating module 6042 is connected, and the down mixer is used to shift the frequency of the obtained differential data stream to the common mode noise component at twice the Nyquist frequency to four by the local oscillator signal of the Nyquist frequency output by the frequency source. Multiple times the Nyquist frequency point, and moving down to DC, then the downmixer will get the quadratic Nyquist frequency point common mode noise component and DC component into the low pass filter, by the low pass filter The common mode noise component at four times the Nyquist frequency point and other high frequency hash signals are filtered out, the low frequency DC component is retained, and the DC component is then sent to the voltage regulation indication generation module 6042.

As an example, referring to FIG. 11 , the voltage adjustment indication generation module 6042 includes a sampling unit 1101 , a comparison unit 1102 , and an integration unit 1103 . among them:

The input end of the sampling unit 1101 is connected to the output end of the common mode noise component detecting module 6041, and the output end of the sampling unit 1101 is connected to the input end of the comparing unit in the voltage adjustment indication generating module 6042 for the common mode noise component detecting module 6041. The output DC component is sampled, and the obtained sampling signal is output to the comparing unit 1102;

The output end of the comparison unit 1102 is connected to the input end of the integration unit 1103 for comparing the sampling signal in the current sampling period with the sampling signal in one sampling period before the current sampling period, and comparing the obtained sampling signals. Output to the integration unit 1103;

The output end of the integration unit 1103 is connected to the common mode voltage adjustment circuit 602 for integrating the received comparison result of the sampling signal, generating the voltage adjustment indication information according to the integration result, and outputting the obtained voltage adjustment indication information to the common mode voltage. Adjustment circuit 602.

In practical applications, the sampling unit 1101 may specifically be a sampling circuit. The low frequency DC signal is sampled by a sampling circuit and stored in a register or an energy storage device, such as in a capacitor. In order to simplify the structure of the circuit, the sampling circuit can also directly adopt the sample-and-hold circuit, and maintain the sampling signal by the function of the sample-and-hold circuit itself having a short hold data, so that no additional register or energy storage device is needed in the circuit.

After the sampling unit 1101 acquires and stores the sampling signal, the sampling signal is output to the comparison unit 1102. The comparison unit 1102 can include a comparator and a delayer disposed on one input of the comparator for comparing the voltage values of the sampled signals input by the two inputs. When the two input terminals of the comparator input the sampling signal of the current sampling period, since the sampling signal of the current sampling period becomes the sampling signal of the previous adoption period after passing the delay device, the comparator compares the current The voltage of the sampling signal of the sampling period and the voltage of the sampling signal of the previous sampling period are compared. For example, when the comparison result is +1, it means that the voltage of the sampling signal of the current sampling period is smaller than the voltage of the sampling signal of the previous sampling period; when the comparison result is -1, it means that the voltage of the sampling signal of the current sampling period is greater than before. The voltage of the sampled signal of the subsampling period.

When the comparison unit 1102 obtains the comparison result, the comparison result is output to the integration unit 1103. The integration unit 1103 can include an integrator. The integrator integrates the comparison result, and generates voltage adjustment indication information according to the integration result, and outputs the voltage adjustment indication information to the common mode voltage adjustment circuit 602. For example, when the comparison result is +1, the waveform accumulated by the integrator may be a rising waveform as shown in FIG. 12A, and then according to the waveform diagram, the integrator generates a DAC control for increasing the common mode voltage of the pre-drive signal. Word, the DAC control word is the voltage adjustment indication information; when the comparison result is -1, the waveform accumulated by the integrator can be a falling waveform, as shown in FIG. 12B, and then according to the waveform diagram, the integrator is generated for subtraction The DAC control word of the common mode voltage of the small pre-drive signal, that is, the voltage regulation indication information, causes the common mode voltage adjustment circuit 602 to adjust the common mode voltage of the pre-drive signal according to the received DAC control word.

Thus, the common mode voltage adjustment indication circuit 604 implements automatic detection of the common mode noise of the differential data stream of the driver output of the SERDES link transmitter, and adjusts the SERDES link transmission by detecting the common mode noise feedback of the differential data stream. The common mode voltage of the input signal of the second stage driving circuit 603 of the machine makes the adjustment process more convenient.

The above embodiment uses a common mode voltage that regulates the input signal to the SERDES link transmitter to reduce the common mode noise of the differential data stream output by the SERDES link transmitter. The manner in which the amplitude of the input signal to the driver of the SERDES link transmitter is adjusted is described below.

Referring to FIG. 13, an embodiment of the present invention provides a driver for a serial deserial link transmitter, where the driver includes a first stage driving circuit 1301, a bias current adjusting circuit 1302, and a second stage driving circuit 1303. The current adjustment circuit 1302 is connected to the first stage driving circuit 1301. After the first stage driving circuit 1301 receives the data signal, the bias current adjusting circuit 1302 adjusts the bias of the first stage driving circuit 1301 according to the bias current adjustment indication information. The current is set to adjust the bias current of the first stage driving circuit 1301 to a preset current value, so that the first stage driving circuit 1301 performs the received data signal under the bias current of the preset current value. The amplification process is performed, and the obtained real-time pre-drive signal is output to the second-stage drive circuit 1303 connected to the first-stage drive circuit 1301. After receiving the real-time pre-drive signal, the second-stage driving circuit 1303 performs amplification processing and impedance matching processing on the real-time pre-drive signal to obtain and output a real-time differential data code stream for transmission in the high-speed SERDES link.

In the above technical solution, the bias current adjustment circuit 1302 is added under the structure of the two-stage cascade output driving of the existing first-stage driving circuit 1301 and the second-stage driving circuit 1303, and the bias current adjustment instruction information is The bias current of the input signal of the first stage driving circuit 1301 is adjusted to change the amplitude of the real-time pre-drive signal output by the first stage driving circuit 1301. Since the first stage driving circuit 1301 is connected to the second stage driving circuit 1303, the output of the first stage driving circuit 1301 is the input signal of the second stage driving circuit 1303, that is, the output of the first stage driving circuit 1301 is adjusted. The amplitude of the real-time pre-drive signal is also the amplitude of the real-time input signal of the second stage drive circuit 1303. The bias current of the first stage driving circuit 1301 is adjusted by the bias current adjusting circuit 1302 to increase the amplitude of the real-time differential data stream outputted by the second-stage driving circuit 1303 and the amplitude required by the SERDES link transmitter. When the difference is less than or equal to the preset threshold, the common mode noise component of the differential data stream is brought to a smaller value of the adjustment process, that is, the common mode noise component of the differential data stream is reduced when outputting, Therefore, the common mode noise component is fundamentally reduced; and since the common mode noise component of the differential data stream has been reduced at the output, there is no need to increase the choke and there is no need to further the differential data stream. Perform other processing of the eye diagram that may change the differential data stream, such as modulation processing, etc., so that there is no error in reducing the data transmission rate of the SERDES link transmitter or the eye diagram of the differential data stream. The problem of high code rate reduces the impact on communication quality.

In the practical application, the first-stage driving circuit 1301 is the same as the first-stage driving circuit 601 in FIG. 6, and the second-level driving circuit 1303 is the same as the second-level driving circuit 603 in FIG. 6, and details are not described herein again.

When the bias current adjustment circuit 1302 first adjusts the bias current of the first-stage driving circuit 1301, the bias current of the first-stage driving circuit 1301 can be adjusted to a default value, which can be preset. After the second stage driving circuit 1303 outputs the differential data code stream, the adjusting circuit 1302 can monitor the amplitude of the differential data code stream output by the second stage driving circuit 1303 in real time, by manual operation or other regulating device outside the driving device. The bias current of the first stage driving circuit 1301 is adjusted. For example, an oscilloscope is used to monitor the amplitude of the differential data stream of the driver output of the SERDES transmitter in real time, if the amplitude of the differential data stream output by the SERDES transmitter does not meet the preset amplitude requirement, for example, less than 300 mv or less than 500 mv. According to the relationship between the amplitude of the input signal and the common mode noise of the output signal in FIG. 4, the bias current adjustment instruction information is output to the bias current adjustment circuit 1302 by manual operation or other control device outside the driver, thereby increasing The bias current of the large first stage driving circuit 1301 until the amplitude of the differential data code stream output by the driver of the SERDES transmitter satisfies a preset amplitude requirement, for example, 300 mv or more and 330 mv or less and 500 mv or more and 520 mv or less. When the amplitude of the differential data stream output by the driver of the SERDES transmitter satisfies a preset amplitude requirement, the bias current adjustment circuit 1302 is controlled to adjust the first stage driving circuit by manual operation or other regulating means outside the driver. The bias current of 1301 causes the pre-drive of the output of the first stage drive circuit 1301 The magnitude of numbers to meet the minimum requirements of a preset amplitude. As can be seen from FIG. 3, as long as the amplitude of the input signal is set to a minimum value such that the amplitude of the output signal satisfies the preset amplitude requirement, the common mode noise of the output signal is reduced to a small value. At this time, when the amplitude of the differential data stream output by the driver of the SERDES transmitter satisfies a preset amplitude requirement, the bias current of the first stage driving circuit 1301 can be reduced by the adjusting circuit 1302. After a plurality of adjustments, for example, the adjustment process takes a preset time period or the preset number of times reaches a preset number of times, determining the common mode of the differential data code stream output by the driver of the SERDES transmitter at twice the Nyquist frequency point. The noise component is a preset current corresponding to the minimum value of the first stage driving circuit 102 corresponding to the minimum value in the multiple adjustment process, or determining that the differential data code stream output by the driver of the SERDES transmitter is twice the Nyquist frequency The common mode noise component at the point is less than the bias of the first stage drive circuit 102 corresponding to the common mode noise component of the differential data bitstream of the driver output of the SERDES transmitter before the multiple adjustments at twice the Nyquist frequency point. The current is set to a preset current, and the bias current of the first stage driving circuit 1301 is controlled by the bias current adjusting circuit 1302 to be the preset current, so that the driver output of the SERDES link transmitter is completed after the above adjustment process is completed. The common mode noise component of the differential data stream is improved.

In practical applications, the bias current of the first stage driving circuit 1301 is generally provided by an adjustable current source inside the first stage driving circuit 1301. Therefore, the bias current adjusting circuit 1302 and the first stage driving circuit 1301 can be internalized. Adjustable current source connections, as shown in Figure 14. The bias current adjustment circuit 1302 generates current adjustment indication information to be output to the adjustable current source inside the first stage driving circuit 1301, so that the adjustable current source inside the first stage driving circuit 1301 generates an offset having the preset current value. Current. Of course, the adjustable current source inside the first stage driving circuit 1301 can also be removed, and the bias current of the first stage driving circuit 1301 is directly provided by the bias current adjusting circuit 1302, or the bias current adjusting circuit 1302 includes the The adjustable current source of the first stage driving circuit 1301, together with the adjustable current source, adjusts the bias current of the first stage driving circuit 1301, which is not limited in the embodiment of the present invention.

Specifically, the bias current adjustment circuit 1302 can be implemented by a digital analog converter (DAC). As shown in FIG. 15, the left side input reference current I _ref of the bias current adjustment circuit 1302, the reference current I _ref It may be provided by an adjustable current source inside the first stage driving circuit 1301, or may be provided by other current sources. M _ref , M ₀ ... M _n-1 are respectively transistors of different sizes, and the control DAC can be used to modify the DAC stored in the register of the SERDES link transmitter through the communication interface configured by the SERDES link transmitter, such as the SPI bus interface. The control word data, that is, D ₀ , D ₁ ... D _n-1 , controls the direction of each switch. When D _n is 0, the switch is directly connected to the VDD terminal, so that the transistor does not output current; D _n takes a value. When 1, the switch is connected to the I _out terminal, so that the transistor outputs a current, and the current outputted by the transistor corresponding to the control word is superimposed to form a bias current having a preset current value, and drives the first-stage driving circuit 1301. For example, the magnitude of the bias current can be adjusted using a monotonically increasing or monotonically decreasing adjustment, and the DAC control word corresponding to the preset current value is stored in a register of the SERDES link transmitter. Of course, there are many specific circuit designs of the bias current adjustment circuit 1302, which are not limited in the embodiment of the present invention.

After completing the above adjustment process, the bias current adjustment circuit 1302 adjusts the bias current of the first stage driving circuit 1301 according to the DAC control word stored in the register, so that the output of the first stage driving circuit 1301 enables the SERDES link to be transmitted. The pre-drive signal of the differential data stream of the differential output of the machine output reaches the minimum value.

In the embodiment of the present invention, the amplitude of the input signal of the second stage driving circuit 1303 is adjusted by the bias current adjusting circuit 1302, so that the common mode noise component of the differential data bit stream output by the driver of the SERDES link transmitter is output. At that time, improvements have been made to fundamentally reduce the common mode noise component of the differential data stream output by the SERDES link transmitter.

Although the driver of the above structure has fundamentally reduced the common mode noise component of the differential data bit stream output by the SERDES link transmitter, the adjustment process of the bias current adjusting circuit 1302 is complicated, in order to simplify the bias current regulating circuit. Referring to FIG. 16, the driver further includes: a current adjustment indicating circuit 1304, an input end of the current adjustment indicating circuit 1304 is connected to an output end of the second stage driving circuit 1303, and an output end of the current adjusting indicating circuit 1304 is The bias current adjustment circuit 1302 is connected to generate current adjustment indication information according to the amplitude of the differential data code stream, and output the current adjustment indication information to the bias current adjustment circuit 1302, so that the bias current adjustment circuit 1302 is received according to the The current adjustment indication information adjusts the bias current of the first stage drive circuit 1301 to the preset current value. Therefore, by detecting the common mode noise in the differential data bit stream output by the second stage driving circuit 1303, the bias current adjusting circuit 1302 is feedback-controlled to realize adaptive adjustment, which simplifies the adjustment process.

In the embodiment of the present invention, the current adjustment indication circuit 1304 includes: an amplitude detection module 13041 and a current adjustment indication generation module 13042, where:

The input end of the amplitude detecting module 13041 is connected to the output end of the second stage driving circuit 1303, and the output end of the amplitude detecting module 13041 is connected to the input end of the current adjusting indication generating module 13042 for detecting the amplitude of the differential code stream, and detecting The amplitude of the differential data code stream is output to the current adjustment indication generating module 13042;

The output of the current adjustment indication generating module 13042 is connected to the bias current adjustment circuit 1302, and is configured to compare the amplitude of the received differential data code stream with a preset amplitude, according to the amplitude of the differential data code stream and the preset amplitude. The comparison result generates the current adjustment indication information, and the obtained current adjustment instruction information is output to the bias current adjustment circuit 1302.

In practical applications, the amplitude detecting module 13041 may be an amplitude detecting circuit. As shown in FIG. 17, the pin 2 of the AD820 chip is used to input a differential data stream, and the pin 3 of the AD820 chip has a series resistor R1 and an adjustable sliding varistor. R _RP1 , resistor R1 and the adjustable sliding varistor R _RP1 are connected to the other end of the circuit through the NPN transistor to the pin 6 of the AD820 chip. The pin 6 of the AD820 chip is connected to the pin 3 of the AD654 chip. The capacitor C1 is connected in series between the pin 6 and the pin 7, and finally the frequency f of the differential data bit stream is output by the pin 1 of the AD654 chip, and then the amplitude of the differential data bit stream is calculated by using the calculation relationship between the amplitude and the frequency. value. Of course, the amplitude detection circuit has a variety of design methods, for example, directly using the MSP430G2553 microcontroller for amplitude testing, etc., without limitation.

The current adjustment indication generating module 13042 can include a comparator and an integrator. As shown in FIG. 18, the output of the amplitude detecting module 13041 is connected to one input of the comparator, for example, the negative terminal of the comparator and the other input of the comparator. For example, the positive terminal of the comparator is set to a preset amplitude V _ref , the output of the comparator is connected to the input of the integrator, and the output of the integrator is connected to the adjustable current source of the first-stage driving circuit 1301. When the amplitude detecting module 13041 outputs the amplitude of the differential data stream to one input of the comparator, the comparator compares the amplitude of the differential data stream with the preset amplitude V _ref to obtain a comparison result. For example, when the comparison result is +1, it indicates that the amplitude of the differential data code stream is less than a preset amplitude; when the comparison result is -1, it indicates that the amplitude of the differential data code stream is greater than or equal to a preset amplitude.

When the comparator gets the comparison result, the comparison result is output to the integrator. The integrator integrates the comparison result, and outputs current adjustment indication information to the bias current adjustment circuit 1302 based on the integration result. For example, when the comparison result is +1, the waveform accumulated by the integrator may be a rising waveform as shown in FIG. 12A, and then according to the waveform diagram, the integrator generates a bias current for increasing the first-stage driving circuit 1301. The DAC control word, the DAC control word is the current adjustment indication information; when the comparison result is -1, the waveform accumulated by the integrator can be a falling waveform, as shown in FIG. 12B, and then according to the waveform diagram, the integrator generates a DAC control word for reducing the bias current of the first stage driving circuit 1301, that is, current adjustment indication information, so that the bias current adjusting circuit 1302 biases the bias current of the first stage driving circuit 1301 according to the received DAC control word. Make adjustments.

Thus, the amplitude of the differential data stream of the driver output of the SERDES link transmitter is automatically detected by the common mode voltage regulation indicating circuit 1304, and the first of the SERDES link transmitters is adjusted by the amplitude feedback of the detected differential data stream. The bias current of the stage driving circuit 1301 makes the adjustment process more convenient.

The above two embodiments use a common mode voltage or input signal amplitude of the input signal of the SERDES link transmitter to adjust the common mode noise of the differential data bit stream output by the SERDES link transmitter. The manner in which the amplitude of the input signal of the driver of the SERDES link transmitter and the common mode voltage of the input signal are adjusted will be described below.

Referring to FIG. 19, an embodiment of the present invention provides a driver for a serial deserial link transmitter, where the driver includes a first stage driving circuit 1901, an adjusting circuit 1902, and a second stage driving circuit 1903, wherein the adjusting circuit 1902 includes A bias current adjustment circuit 13021 and a common mode voltage adjustment circuit 19022 connected to the first stage drive circuit 1901, respectively. After the first stage driving circuit 1901 receives the data signal, the bias current adjusting circuit 19021 adjusts the bias current of the first stage driving circuit 1901 to a preset current value, thereby causing the first stage driving circuit 1301 to be at the preset current. Under the action of the bias current of the value, the received data signal is amplified, and the difference between the amplitude of the differential data stream that can be output by the second-stage driving circuit 1903 and the amplitude required by the SERDES link transmitter is obtained. The pre-drive signal having a value less than or equal to the preset threshold is output to the common mode voltage adjustment circuit 19022. After receiving the pre-drive signal, the adjustment circuit 1902 adjusts the common mode voltage of the pre-drive signal, and adjusts the common mode voltage of the pre-drive signal to a common mode noise of the differential data bit stream that can be output by the driver. The preset voltage of the small value is such that the adjusted pre-drive signal is obtained, and the adjusted pre-drive signal will be used as the input signal of the second stage adjustment circuit 1903. After the second stage driving circuit 1903 receives the adjusted pre-drive signal, the adjusted pre-drive signal is amplified and impedance matched, and finally the differential data code stream for transmission in the high-speed SERDES link is output.

In a practical application, the first stage driving circuit 1901 is the same as the first stage driving circuit 601 in FIG. 6, and the second stage driving circuit 1903 is the same as the second stage driving circuit 603 in FIG. 6, and details are not described herein again.

When the bias current of the first stage driving circuit 1901 is first adjusted by the bias current adjusting circuit 19021 in the adjusting circuit 1902, the bias current of the first stage driving circuit 1901 can be adjusted to a default value, which can be previously Set it up. Then, the bias current adjustment indication information is output to the bias current adjustment circuit 19021 and the common mode voltage adjustment indication information is output to the common mode voltage adjustment circuit 19022 by manual operation or other regulation means outside the driver, to the first stage. When the bias current of the driving circuit 1901 and the common mode voltage of the pre-drive signal output from the first-stage driving circuit 1901 are adjusted, it is necessary to monitor the amplitude of the differential data bit stream and the common mode noise component outputted by the second-stage driving circuit 1903 in real time. For example, an oscilloscope is used to monitor the amplitude of the differential data stream of the driver output of the SERDES transmitter in real time, if the amplitude of the differential data stream output by the SERDES transmitter does not meet the preset amplitude requirement, for example, less than 300 mv or less than 500 mv. Then, the bias current adjustment indication information is output to the bias current adjustment circuit 19021 by manual operation or other regulating means outside the driver to increase the bias current of the first stage driving circuit 1301 until the driver output of the SERDES transmitter The amplitude of the differential data stream satisfies a preset amplitude requirement, for example, 300 mv or more and 330 mv or less or 500 mv or more and 520 mv or less. After a plurality of adjustments, for example, the adjustment process takes a preset time period or the preset number of times reaches a preset number of times, and then determines that the amplitude of the differential data code stream output by the driver of the SERDES transmitter satisfies a preset amplitude requirement. The bias current of the first stage driving circuit 1901 is a preset current, or the differential data stream of the driver output of the SERDES transmitter is determined to have a common mode noise component at twice the Nyquist frequency point is less than The differential data stream of the driver output of the SERDES transmitter before the second adjustment is at a preset current of the first stage driving circuit 102 corresponding to the common mode noise component at twice the Nyquist frequency, and is adjusted by the bias current. The circuit 19021 controls the bias current of the first stage driving circuit 1901 to be the preset current.

Then, according to the common mode noise component of the differential data stream displayed in the oscilloscope at twice the Nyquist frequency point, the voltage adjustment indication information is output to the common mode voltage adjustment circuit 19022 by manual operation or other control device outside the driver, Adjust the common mode voltage of the pre-drive signal. For example, increasing the common mode voltage of the pre-drive signal and observing the variation of the common-mode noise component of the differential data stream output by the driver of the SERDES transmitter at twice the Nyquist frequency point through an oscilloscope: if the adjusted differential data The common mode noise component of the code stream at twice the Nyquist frequency point is larger than the common mode noise component of the differential data stream before the adjustment at twice the Nyquist frequency point, and then by manual operation or other control device outside the driver, The common mode voltage adjustment circuit 19022 outputs voltage adjustment indication information to reduce the common mode voltage of the pre-drive signal; if the adjusted differential data code stream has a common mode noise component at twice the Nyquist frequency point than the differential data stream before adjustment When the common mode noise component at twice the Nyquist frequency is small, the voltage adjustment indication information is output to the common mode voltage adjustment circuit 19022 by manual operation or other control means outside the driver, and the common mode voltage of the pre-drive signal is increased. After a plurality of adjustments, for example, the adjustment process takes a preset time period or the preset number of times reaches a preset number of times, determining the common mode of the differential data code stream output by the driver of the SERDES transmitter at twice the Nyquist frequency point. The common mode voltage of the pre-drive signal when the noise component is the minimum value in the multiple adjustment process is a preset voltage, or the differential data code stream outputting the driver of the SERDES transmitter is determined to be at twice the Nyquist frequency point. The mode noise component is less than a common mode voltage of the pre-drive signal corresponding to the common mode noise component of the differential data bit stream of the SERDES transmitter before the multiple adjustment is corresponding to the common mode noise component of the Nyquist frequency point, The common mode voltage of the pre-drive signal is controlled by the common mode voltage adjustment circuit 19022 to be the preset voltage.

Thus, the common mode noise component of the differential data stream output by the driver of the SERDES link transmitter is improved when the above adjustment process is completed. It should be noted that, when the bias current of the first stage driving circuit 1901 is the preset current through the bias current adjusting circuit 19021, the common mode noise component of the differential data bit stream output by the driver of the SERDES link transmitter is illustrated. Has been reduced; when the common mode voltage of the pre-drive signal is again controlled by the common mode voltage adjustment circuit 19022 to be the predetermined voltage, the common mode noise component of the differential data bit stream output by the driver of the SERDES link transmitter is further reduced. small.

In practical applications, the bias current adjustment circuit 19021 is the same as the bias current adjustment circuit 1302 of FIG. 13, and the common mode voltage adjustment circuit 19022 is the same as the common mode voltage adjustment circuit 602 of FIG. 6, and will not be described herein.

Although the driver of the above structure has fundamentally reduced the common mode noise component of the differential data bit stream outputted by the SERDES link transmitter, the adjustment process of the adjustment circuit 1902 is complicated. In order to simplify the adjustment process of the adjustment circuit 1902, please Referring to FIG. 20, the driver further includes: a current adjustment indicating circuit 1904 and a common mode voltage adjustment indicating circuit 1905. The input end of the current adjusting indicating circuit 1304 is connected to the output end of the second stage driving circuit 1903, and the output of the current adjusting indicating circuit 1904 is output. The terminal is connected to the bias current adjustment circuit 19021, and configured to generate current adjustment indication information according to the amplitude of the differential data code stream, and output the current adjustment indication information to the bias current adjustment circuit 19021, so that the bias current adjustment circuit 19021 The bias current of the first stage driving circuit 1901 is adjusted to the preset current value according to the received current adjustment indication information. The input end of the common mode voltage adjustment indicating circuit 1905 is connected to the output end of the second stage driving circuit 1903, and the output end of the common mode voltage adjusting indicating circuit 1905 is connected to the common mode voltage adjusting circuit 19022 for sharing according to the differential data bit stream. The mode noise generates voltage adjustment indication information, and outputs the voltage adjustment indication information to the common mode voltage adjustment circuit 19022, so that the common mode voltage adjustment circuit 19022 generates and outputs a control voltage according to the received voltage adjustment indication information, and passes the control. The voltage adjusts the common mode voltage of the pre-drive signal to the preset voltage. Therefore, by detecting the amplitude and common mode noise in the differential data bit stream output by the second stage driving circuit 1303, the adjusting circuit 1902 is feedback-controlled to realize adaptive adjustment, which simplifies the adjustment process.

It should be noted that, if the common mode voltage adjustment circuit 19022 adjusts the common mode voltage of the pre-drive signal, the amplitude of the differential data stream changes, and the preset amplitude requirement is not met, the first stage drive needs to be re-adjusted. The bias current of circuit 1901. After adjusting the bias current of the first stage driving circuit 1901, it may be necessary to adjust the common mode voltage of the pre-drive signal again through the common mode voltage adjusting circuit 19022, thereby outputting the differential data code stream by iteratively adjusting the two adjustment modes to each other. Common mode noise is minimized.

In the embodiment of the present invention, the current adjustment indication circuit 1904 is the same as the current adjustment indication circuit 1304 in FIG. 16 , and the common mode voltage adjustment indication circuit 1905 is the same as the common mode voltage adjustment indication circuit 604 in FIG. 9 , and details are not described herein again. .

In the above technical solution, the amplitude and common mode noise of the differential data bit stream of the driver output of the SERDES link transmitter are automatically detected by the bias current adjustment circuit 19021 and the common mode voltage adjustment circuit 19022, and the differential data is detected. The amplitude feedback of the code stream adjusts the bias current of the first stage driver circuit 1901 of the SERDES link transmitter, and adjusts the output of the first stage driver circuit 1901 of the SERDES link transmitter through the common mode noise feedback of the detected differential data stream. The common mode voltage of the pre-drive signal makes the adjustment process more convenient.

In summary, the embodiment of the present invention provides a driver for a SERDES link transmitter, which is added by a two-stage cascaded output driving structure of the existing first-stage driving circuit and the second-stage driving circuit. a mode voltage regulating circuit and/or a bias current regulating circuit for real-time adjustment of a common mode voltage of an input signal of the second stage driving circuit by a common mode voltage regulating circuit and/or driving of the first stage by a bias current adjusting circuit The signal amplitude of the output signal of the circuit is adjusted in real time to make the difference data when the difference between the amplitude of the differential data stream output by the second stage driving circuit and the amplitude required by the SERDES link transmitter is less than or equal to a preset threshold The common mode noise component of the code stream can reach a small value of the adjustment process, that is, the common mode noise component of the differential data bit stream can be reduced at the output, thereby fundamentally reducing the common mode noise component. Furthermore, there is no need to perform other processing on the differential data stream that may change the eye pattern of the differential data stream, and naturally there is no reduction in the SERDES link transmitter. Data transmission rate or the error rate due to problems caused by changes in eye differential data stream occurs, reducing the impact on the communication quality.

It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, it is intended that the present invention cover the modifications and variations of the embodiments of the present invention.

Claims

A driver for a serial deserial link transmitter, comprising:

The first stage driving circuit is configured to amplify and process the data signal received in real time, and obtain and output a real-time pre-drive signal;

a common mode voltage adjustment circuit is connected to the first stage driving circuit for real-time response to the voltage adjustment indication information to perform real-time adjustment of the common mode voltage of the real-time pre-drive signal to obtain an adjusted real-time pre-drive signal;

The second stage driving circuit is connected to the voltage adjusting circuit, and is configured to perform amplification processing and impedance matching processing on the adjusted real-time pre-drive signal to obtain and output a real-time differential data code stream.
The driver of claim 1 wherein said driver further comprises:

a common mode voltage adjustment indicating circuit, wherein an input end of the common mode voltage regulation indicating circuit is connected to an output end of the second stage driving circuit, and an output end of the common mode voltage adjusting indicating circuit is connected to the voltage adjusting circuit, Generating the voltage adjustment indication information according to the common mode noise of the real-time differential data code stream output by the second-stage driving circuit, and outputting the voltage adjustment indication information to the common mode voltage adjustment circuit;

The voltage regulating circuit is configured to generate a control voltage according to the received voltage adjustment indication information, and obtain a adjusted real-time pre-drive signal by using the common voltage of the real-time pre-drive signal by the control voltage.
The driver according to claim 2, wherein said common mode voltage adjustment indicating circuit comprises a common mode noise component detecting module and a voltage regulating indicating generating module, wherein:

An input end of the common mode noise component detecting module is connected to an output end of the second stage driving circuit, an output end of the common mode noise component detecting module and a voltage adjusting indication generating module of the common mode voltage adjusting indicating circuit The input terminal is connected to detect common mode noise of the real-time differential data stream output by the second-stage driving circuit, and the frequency of the common mode noise of the real-time differential data stream is N times Nyquist Moving to DC at a frequency, and outputting the obtained real-time DC component to the voltage adjustment indication generating module; wherein N is a multiple of 2;

An output end of the voltage adjustment indication generating module is connected to the common mode voltage adjustment circuit, configured to generate the voltage adjustment indication information according to the received real-time DC component, and output the voltage adjustment indication information to the Common mode voltage regulation circuit.
The driver according to claim 3, wherein said voltage adjustment instruction generation module comprises a sampling unit, a comparison unit, and an integration unit, wherein:

An input end of the sampling unit is connected to an output end of the common mode noise component detecting module, and an output end of the sampling unit is connected to an input end of the comparing unit for outputting the common mode noise component detecting module The real-time DC component is sampled, and the obtained real-time sampling signal is output to the comparison unit;

An output end of the comparison unit is connected to an input end of the integration unit, and is configured to compare a real-time sampling signal in a current sampling period with a sampling signal in a sampling period before the current sampling period, and the obtained The real-time comparison result of the sampled signal is output to the integration unit;

An output end of the integration unit is connected to the common mode voltage adjustment circuit, and is configured to integrate the received real-time comparison result of the sampling signal, generate the voltage adjustment indication information according to the integration result, and adjust the obtained voltage The indication information is output to the common mode voltage regulation circuit.
The driver according to any one of claims 1 to 4, wherein the driver further comprises:

a bias current adjustment circuit connected to the first stage driving circuit for real-time response to the current adjustment indication information to perform real-time adjustment of the bias current of the first stage driving circuit, and output the adjusted real-time bias current So that the first stage driving circuit outputs the real-time pre-drive signal under the adjusted real-time bias current.
The driver of claim 5 wherein said driver further comprises:

a current adjustment indicating circuit, an input end of the current adjustment indicating circuit is connected to an output end of the second stage driving circuit, and an output end of the current regulating indicating circuit is connected to the bias adjusting circuit, according to the The amplitude of the real-time differential data stream output by the second-stage driving circuit generates current adjustment indication information, and outputs the current adjustment indication information to the bias current adjustment circuit.
The driver of claim 6 wherein said current regulation indicating circuit comprises an amplitude detecting module and a current regulating indicating generating module, wherein:

An input end of the amplitude detecting module is connected to an output end of the second stage driving circuit, and an output end of the amplitude detecting module is connected to an input end of the current adjustment indicating generating module, and is configured to detect the second level The amplitude of the real-time differential data code stream output by the driving circuit outputs the detected amplitude of the real-time differential data code stream to the current adjustment indication generating module;

The output of the current adjustment indication generating module is connected to the bias current adjustment circuit, and is configured to compare the amplitude of the received real-time differential data code stream with a preset amplitude, according to the real-time differential data stream The comparison result of the amplitude and the preset amplitude generates the current adjustment indication information, and outputs the obtained current adjustment indication information to the bias current adjustment circuit.
A driver for a serial deserial link transmitter, comprising: a first stage driving circuit, a bias current adjusting circuit and a second stage driving circuit, wherein:

a bias current adjustment circuit connected to the first stage driving circuit for real-time response to the current adjustment indication information to perform real-time adjustment of the bias current of the first stage driving circuit, and output the adjusted real-time bias current ;

a first stage driving circuit, configured to amplify the real-time received data signal under the adjusted real-time bias current to obtain and output a real-time pre-drive signal;

The second stage driving circuit is connected to the first stage driving circuit, and is configured to perform amplification processing and impedance matching processing on the real-time pre-drive signal to obtain and output a real-time differential data code stream.
The driver of claim 8 wherein said driver further comprises:

a current adjustment indicating circuit, an input end of the current adjustment indicating circuit is connected to an output end of the second stage driving circuit, and an output end of the current regulating indicating circuit is connected to the bias adjusting circuit, according to the The amplitude of the real-time differential data stream output by the second-stage driving circuit generates current adjustment indication information, and outputs the current adjustment indication information to the bias current adjustment circuit.
The driver of claim 9 wherein said current regulation indicating circuit comprises an amplitude detecting module and a current regulating indicating generating module, wherein:

An input end of the amplitude detecting module is connected to an output end of the second stage driving circuit, and an output end of the amplitude detecting module is connected to an input end of the current adjustment indicating generating module, and is configured to detect the second level The amplitude of the real-time differential data code stream output by the driving circuit outputs the detected amplitude of the real-time differential data code stream to the current adjustment indication generating module;

The output of the current adjustment indication generating module is connected to the bias current adjustment circuit, and is configured to compare the amplitude of the received real-time differential data code stream with a preset amplitude, according to the real-time differential data stream The comparison result of the amplitude and the preset amplitude generates the current adjustment indication information, and outputs the obtained current adjustment indication information to the bias current adjustment circuit.