JP2024061131A - Photoreceiver, optical communication system, and on-vehicle optical communication network system - Google Patents

Abstract

To provide a photoreceiver that has high transmission signal quality by suppressing DC wanders after burst signal reception while reducing consumption current of a differential amplifier circuit in a burst signal non-signal period.SOLUTION: A photoreceiver 10 comprises: a photoelectric conversion element 20 for converting a burst signal to a current signal; a TIA circuit 30 for converting the current signal to a voltage signal; an output buffer circuit 40 for amplifying the voltage signal; a burst signal detection circuit 60 for detecting a burst signal; a DC voltage output circuit 70 for outputting predetermined voltage; and a current source control circuit 80 that actuates a current source of the output buffer circuit 40 in the case of detecting the burst signal and stopping the current source of the output buffer circuit 40 in the case of not detecting the burst signal. DC wanders are suppressed by an output changeover circuit 90 that outputs an output voltage of the output buffer circuit 40 in the case of detecting the burst signal and outputs an output voltage of the DC voltage output circuit 70 in the case of not detecting the burst signal.SELECTED DRAWING: Figure 3

Description

The present invention relates to an optical receiver, an optical communication system, and an in-vehicle optical communication network system.

The development of optical communication systems, such as PON (Passive Optical Network) systems, is progressing rapidly. Optical communication systems are not limited to the telecommunications industry, and applications to in-vehicle optical communication networks are being considered. The optical receiver of an optical communication system is equipped with a transimpedance amplifier (TIA). The TIA is placed immediately after the photodiode that performs optical/electrical signal conversion, and has the function of converting and amplifying the weak current signal generated by the photodiode into a voltage signal with an amplitude large enough to be processed by the downstream circuit.

The optical signal in a PON system is a burst signal that has a preamble period and a payload period. Therefore, in an optical communication system that uses a burst signal method, signals are transmitted at arbitrary timing, so at the optical receiver, there are periods of no signal between frame signals, which are a group of burst signals.

In an in-vehicle optical communication network system, multiple optical receivers (e.g., N units) are connected in a ring shape using optical fibers. In this case, a signal-free period of (N-1) times the frame length occurs for the frame length of the frame signal received by one optical receiver.

In optical communication networks that use burst signaling, current flows through the differential amplifier that constitutes the output buffer, consuming power even during periods when no signals are being received. Therefore, reducing power consumption during periods when no signals are being received is an effective way of reducing power consumption throughout the system.

As a method to reduce power consumption during periods of no signal, a separate communication protocol could be defined, the timing of burst signal reception at each optical receiver managed by a time table, and an external control signal given to the optical receiver based on the time table would be given to control the on/off operation of the optical receiver. However, this method requires additional control lines, making the system configuration complicated. Also, it is difficult to apply this method to burst signal systems that transmit at arbitrary timing.

Regarding the reduction of power consumption in optical communication systems that employ burst signaling, Patent Document 1 describes a technology for reducing unnecessary power consumption in subscriber equipment based on a PON system by switching on and off the drive voltage and current of a clock data recovery circuit (CDR) and electronic circuits downstream of the CDR. Patent Document 2 describes a technology for cutting off the supply of current used to operate the main amplifier circuit when a signal interruption (no-signal period) of the optical signal (burst signal) is detected in an optical receiver equipped with an amplitude limiting amplifier circuit.

International Publication No. WO2016/186176 JP 2011-166658 A

When the current to the differential amplifier circuit is cut off during the signal-free period of the burst signal, the output signal level of the differential amplifier circuit transitions and deviates significantly from the original baseline immediately after receiving the burst signal, and transitions between the original baselines through a transient response. This phenomenon is called DC wander or baseline wander (referred to as DC wander in the present invention). However, neither Patent Document 1 nor Patent Document 2 mentions DC wander. Simply cutting off the current to the differential amplifier circuit during the signal-free period of the burst signal can cause bit errors in the signal processing of the downstream circuit, resulting in a problem of degrading the quality of the transmission signal.

The object of the present invention is to provide an optical receiver, optical communication system, and in-vehicle optical communication network system that have high transmission signal quality by reducing the current consumption of a differential amplifier circuit during periods when there is no signal in a burst signal, while suppressing DC wander after receiving a burst signal.

The optical receiver according to the present invention comprises a photoelectric conversion element that converts a burst signal, which is an optical signal, into a current signal and outputs it, a TIA circuit that converts the current signal into a voltage signal, an output buffer circuit that amplifies the amplitude of the voltage signal and outputs it, a burst signal detection circuit that detects whether a burst signal has been received, a DC voltage output circuit that outputs a predetermined voltage, and a current source control circuit that is configured to operate the current source of the output buffer circuit when a burst signal is detected and to stop the current source of the output buffer circuit when a burst signal is not detected, and further comprises an output switching circuit that outputs the voltage of the output buffer circuit when a burst signal is detected and outputs the voltage of the DC voltage output circuit when a burst signal is not detected.

According to the above configuration, during the no-signal period when no burst signal is being received, the current source of the output buffer circuit can be stopped to reduce power consumption. Furthermore, during the no-signal period when no burst signal is being received, the voltage of the DC voltage output circuit is output, so that the DC wander that occurs after receiving a burst signal can be suppressed.

Here, it is preferable that the voltage of the DC voltage output circuit coincides with the average/median value of the voltage of the output buffer circuit when a burst signal is received. With the above configuration, it is possible to effectively suppress DC wander that occurs after receiving a burst signal.

The output switching circuit preferably has a first switch for switching the voltage of the output buffer circuit on and off, and a second switch for switching the voltage of the DC voltage output circuit on and off, and the first switch and the second switch are configured to change their on and off states exclusively depending on whether or not a burst signal is received. According to the above configuration, the voltage of the DC voltage output circuit is output during the period when there is no burst signal, and the voltage of the output buffer circuit is output during the period when a burst signal is received, thereby making it possible to reduce the change in the average value of the output voltage before and after the reception of a burst signal, and effectively suppress the occurrence of DC wander.

The current source of the output buffer circuit may be a constant current circuit having a transistor, and the current source control circuit may be configured to cut off the current flowing through the transistor when a burst signal is not detected. According to the above configuration, the current source control circuit can be configured to turn off the transistor of the constant current circuit to cut off the current, thus simplifying the configuration.

The optical communication system of the present invention is characterized by comprising: a plurality of home devices; an optical/electrical signal conversion device having an optical coupler that combines signals from optical fibers connected to each of the plurality of home devices and outputs an optical signal; and any of the optical receivers described above that receives the optical signal output by the optical coupler; and a signal processing device that receives the differentially amplified signal output by the optical/electrical signal conversion device.

The above configuration makes it possible to realize an optical communication system that can reduce power consumption during periods when no burst signal is present and suppress DC wander that occurs when a burst signal is received.

The in-vehicle optical communication network system of the present invention is an in-vehicle optical communication network system in which a master and multiple gateways are connected in a ring shape by optical fibers, and each of the multiple gateways is equipped with any of the optical receivers described above.

The above configuration makes it possible to realize an in-vehicle optical communication network system that can reduce power consumption during periods when there is no burst signal and suppress DC wander that occurs when a burst signal is received.

The present invention makes it possible to reduce the current consumption of the differential amplifier circuit during periods when there is no burst signal, while suppressing DC wander after receiving a burst signal, thereby realizing an optical receiver, optical communication system, and in-vehicle optical communication network system with high transmission signal quality.

1 is a configuration diagram of an optical communication system according to a first embodiment. 1 is a configuration diagram of an in-vehicle optical communication network system according to a first embodiment. FIG. 2A is a configuration diagram of an optical receiver according to a first embodiment, and FIG. 2B is a configuration diagram of a TIA circuit according to the first embodiment. FIG. 1 is a configuration diagram of a conventional optical receiver. FIG. 2 is a circuit diagram of a burst signal detection circuit according to the first embodiment. 5 is an operational waveform diagram of the burst signal detection circuit; FIG. 1A is a diagram showing an example of the configuration of an output buffer circuit, and FIG. 1B is a circuit diagram of a constant current source of the output buffer circuit. FIG. 2 is a block diagram of an optical receiver according to the first embodiment. 1 shows operational waveforms of various parts of an optical receiver, where (a) is a waveform when no DC wander reduction technology is used, and (b) is a waveform when the DC wander reduction technology is used. 3A and 3B are equivalent circuit diagrams of the optical receiver according to the first embodiment, in which FIG. 3A is an equivalent circuit diagram of a no-signal period of a burst signal, and FIG. 3B is an equivalent circuit diagram of a reception period of a burst signal. 13 shows the operating waveforms of each part of the optical receiver, where (a) is the input current of the TIA, (b) is the output voltage of the low-pass filter, the reference voltage of the comparator CP, and the burst signal detection voltage, (c) is the output voltage of the comparative example, and (d) is the output voltage of the embodiment. FIG. 13 is a diagram showing power consumption in an embodiment. 10A is a configuration diagram of an optical receiver according to a second embodiment, and FIG. 10B is a circuit diagram of a burst signal detection circuit according to the second embodiment.

The following describes in detail an embodiment of the present invention with reference to the drawings. In the following description, specific shapes, directions, values, etc. are merely examples to facilitate understanding of the present invention, and may be modified as appropriate to suit the application, purpose, specifications, etc. In addition, it is anticipated from the beginning that the components of the embodiments and modified examples described below may be selectively combined.

First Embodiment
1 is a configuration diagram of an optical communication system 200 of the present invention using a Passive Optical Network (PON) system. The PON system is a type of optical communication system, and is a technology in which optical signals transmitted from a plurality of ONUs (Optical Network Units) 202 (202A, 202B, 202C, etc.) via optical fibers are combined by an optical coupler 204 and guided to an optical line terminal (OLT) (not shown) installed in a communication station. In recent years, application of the PON system to an in-vehicle optical network has been considered.

The optical communication system 200 in FIG. 1 has multiple on-premises devices (ONUs) 202, an optical coupler 204, an optical/electrical signal conversion device 206, and a signal processing device 208, but the configuration is not limited to this. The optical communication system 200 in FIG. 1 shows only the upstream communication path in which optical signals from the on-premises devices 202A to 202C travel to the OLT in the communication station.

The home devices 202A to 202C are optical line terminals installed in ordinary homes. The home devices 202A to 202C are connected to networks and computers within the home. Each of the home devices 202A to 202C is paired with an optical line terminal installed in a communication station to transmit and receive optical signals.

The optical combiner 204 combines the optical signals transmitted from the multiple home devices 202A-202C via the optical cable into a series of optical signals. The series of optical signals combined by the optical combiner 204 is the burst signal of the present invention.

The optical/electrical signal conversion device 206 has an optical/electrical signal conversion function for converting the burst signal, which is an optical signal received from the optical coupler 204, into a current signal, a current/voltage conversion function for converting the current signal into a voltage signal, and a differential amplification function for further amplifying the voltage signal and converting the single-phase signal into a differential signal. The optical/electrical signal conversion device 206 is the optical receiver 10 described below.

The signal processing device 208 receives the differential signal output from the optical/electrical signal conversion device 206 and performs signal processing. Specifically, the signal processing device 208 relays the signal received from the optical line to the line or device on the upper network side. In addition, the signal processing device 208 also has a function of combining the optical signals to be transmitted to each of the home devices 202 in the downstream communication path (not shown) and sending them to the optical line, but this is omitted in the present invention.

Figure 2 shows the configuration of an in-vehicle optical communication network system 300, which is an application of the PON system. In the in-vehicle optical communication network system 300 in Figure 2, only the configuration of the receiving system is shown. The in-vehicle optical communication network system 300 is equipped with one master 302 and multiple gateways (GW) 304-1 to 304-N. Each gateway is connected by a unidirectional ring-shaped optical fiber 306. The master 302 transmits signals to all gateways 304-1 to 304-N by burst signals via the optical fiber 306. The signals of each gateway 304-1 to 304-N are received by optical switches SW1 to SWN. The signals received by the optical switches SW1 to SWN are input to optical communication receiving devices RX1 to RXN. The optical signals are converted to current signals by photodiodes in the optical communication receiving devices RX1 to RXN, and the current signals are converted to voltage signals and amplified by TIA. The amplified signals are transferred to the subsequent ECU1 to ECUN.

In the in-vehicle optical communication network system 300 of FIG. 2, each gateway 304-1 to 304-N has optical communication receiving devices RX1 to RXN that convert the optical burst signal into a current signal, convert the current signal into a voltage signal, amplify the voltage signal, and convert the single-phase signal into a differential signal, just like the optical communication system of FIG. 1. The optical communication receiving devices RX1 to RXN are optical receivers 10, which will be described later.

In the in-vehicle optical communication network system shown in Figure 2, multiple gateways are usually connected. If the number of connected gateways is N, then each gateway will have a no-signal period that is (N-1) times the frame length. In the case of conventional technology, even during the no-signal period, current flows through the differential amplifier that constitutes the output buffer circuit, consuming power, and system power consumption becomes an issue.

Next, the optical receiver 10 according to the first embodiment of the present invention will be described in detail with reference to FIG. 3. FIG. 3(a) is a configuration diagram of the optical receiver 10 according to the present embodiment, and FIG. 3(b) is a configuration diagram of the TIA circuit 30 included in the optical receiver 10. FIG. 4 is a configuration diagram of a conventional optical receiver 410. Both of FIG. 3 and FIG. 4 show a DC blocking capacitor C _{1 B} and a subsequent circuit 100. The DC blocking capacitor C _{1 B} is a circuit that is inserted between circuits of different logic levels and blocks low-frequency components including DC components of the output of the previous circuit. The optical receiver 10 corresponds to the optical/electrical signal conversion device 206 in the optical communication system 200 in FIG. 1.

The optical receiver 10 of this embodiment includes a photoelectric conversion element 20 that converts a burst signal, which is an optical signal, into a current signal and outputs it, a TIA circuit 30 that converts the current signal into a voltage signal, an output buffer circuit 40 that amplifies the amplitude of the voltage signal and outputs it, a burst signal detection circuit 60 that detects whether a burst signal is received, a DC voltage output circuit 70 that outputs a predetermined voltage, and a current source control circuit 80 that is configured to operate the current source of the output buffer circuit 40 when a burst signal is detected and to stop the current source of the output buffer circuit 40 when a burst signal is not detected. The optical receiver 10 further includes an output switching circuit 90 that suppresses DC wander after receiving a burst signal by outputting the output voltage of the output buffer circuit 40 when a burst signal is detected and outputting the output voltage of the DC voltage output circuit 70 when a burst signal is not detected.

The photoelectric conversion element 20 is composed of, for example, a photodiode PD. The photodiode PD receives a burst signal, which is an optical signal, converts it into a current signal, and outputs it to the downstream TIA circuit 30.

The TIA circuit 30 is a circuit for converting and amplifying a weak current signal generated by the photodiode PD into a voltage signal with an amplitude that can be processed by the subsequent circuit 100. As shown in FIG. 3B, the TIA circuit 30 has a TIA core circuit 32 consisting of an amplifier circuit (e.g., an inverting amplifier circuit INV) and a feedback resistor _Rf , a low-pass filter 34, and a single-phase differential conversion circuit 36. The low-pass filter 34 has a function of switching the time constant of the low-pass filter 34 in order to output an intermediate voltage during the preamble period and the payload period of the burst signal. Switching the time constant of the low-pass filter 34 has the effect of improving the responsiveness of the optical receiver 10 to the burst signal.

The output buffer circuit 40 is provided to adjust the output voltage (differential voltage) of the TIA circuit 30 to an output voltage suitable for the subsequent circuit 100 connected to the output terminal 50. The output buffer circuit 40 is composed of multiple stages of differential amplifier circuits.

The output voltage of the optical receiver 10 is output to the output terminal 50. The optical receiver 10 is configured such that during the period when a burst signal is being received, the output voltage of the output buffer circuit 40 is output to the output terminal 50, and during the period when there is no signal of the burst signal, the output voltage of the DC voltage output circuit 70, which will be described later, is output to the output terminal 50. Details will be described later.

The burst signal detection circuit 60 is a circuit for detecting whether a burst signal is received. In Fig. 3(a), the burst signal detection circuit 60 is configured to output a burst signal detection voltage V _DET that is at a high level when a burst signal is received and at a low level when a burst signal is not received. The burst signal detection voltage V _DET is output to a DC voltage output circuit 70, a current source control circuit 80, and an output switching circuit 90, which will be described later. Furthermore, the burst signal detection voltage V _DET is also used as a timing signal for switching the time constant of the low-pass filter 34, and is also output to the TIA circuit 30.

The DC voltage output circuit 70 is a circuit that outputs a predetermined voltage, and is configured to output a voltage to the output terminal 50 at least during the no-signal period of the burst signal. In FIG. 3(a), the DC voltage output circuit 70 receives a signal that is obtained by logically inverting the burst signal detection voltage V _DET by an inverter INV1. The DC voltage output circuit 70 is configured so that the average/median value of the output voltage of the output buffer circuit 40 during the period when the burst signal is received is equal to the output voltage of the DC voltage output circuit 70. The DC voltage output circuit 70 in FIG. 3(a) has a configuration in which the inverting input/output terminals of one stage of the differential amplifier circuit of the output buffer circuit 40 are connected to each other (a configuration in which the drain and gate of each FET constituting a differential pair, not shown, are shorted), but is not limited to this. The power supply voltage V _DD may be divided by a resistor. In addition, since the voltage of the DC voltage output circuit 70 is output during the no-signal period of the burst signal, there is no need to match impedance, and the output impedance of the DC voltage output circuit 70 may be set to a high resistance value from the viewpoint of reducing current consumption.

The current source control circuit 80 is a circuit for controlling the amount of current of the current source of the output buffer circuit 40. The current source control circuit 80 operates the current source of the output buffer circuit 40 during a period in which the burst signal detection voltage V _DET is input and a burst signal is detected. On the other hand, the current source control circuit 80 is configured to stop the current source of the output buffer circuit 40 during a no-signal period in which a burst signal is not detected. The current source control circuit 80 can reduce power consumption by stopping the current supply to the current source of the output buffer circuit 40 during the no-signal period of the burst signal.

The output switching circuit 90 is a circuit that switches between the output voltage of the output buffer circuit 40 and the output voltage of the DC voltage output circuit 70. The output switching circuit 90 is configured to output the output voltage of the output buffer circuit 40 to the output terminal 50 during a period in which a burst signal is detected, and to output the output voltage of the DC voltage output circuit 70 to the output terminal 50 during a no-signal period in which a burst signal is not detected. The output switching circuit 90 has a first switch 92 connected between the output of the output buffer circuit 40 and the output terminal 50, and a second switch 94 connected between the output of the DC voltage output circuit 70 and the output terminal 50. The first switch 92 and the second switch 94 are configured to change their on/off states exclusively depending on the presence or absence of a burst signal.

The first switch 92 is composed of two transmission gates TG connected between the differential output terminals of the output buffer circuit 40 and the output terminal 50. The transmission gate TG is configured by connecting the source terminals and drain terminals of an n-type MOSFET and a p-type MOSFET in inverse parallel. The transmission gate TG can be operated as a switch by inputting voltages whose logic is inverted to each other to the gate terminals. Specifically, the transmission gate TG has a low resistance (on state) between the drain and source of the transmission gate TG by inputting a high level voltage to the gate terminal of the n-type MOSFET and a low level voltage to the gate terminal of the p-type MOSFET, and has a high resistance (off state) between the drain and source of the transmission gate TG by inputting a low level voltage to the gate terminal of the n-type MOSFET and a high level voltage to the gate terminal of the p-type MOSFET. The transmission gate TG constituting the second switch 94 and the transmission gates TG ₁ to TG ₃ in FIG. 5 also operate in the same manner.

3A, the transmission gate TG constituting the first switch 92 is configured so that the burst signal detection voltage _VDET is input to the gate terminal of the n-type MOSFET, and an inverted signal of the burst signal detection voltage _VDET is input to the gate terminal of the p-type MOSFET. Therefore, the first switch 92 is turned on when the burst signal detection voltage _VDET is at a high level, and turned off when the burst signal detection voltage _VDET is at a low level.

The second switch 94 has the same configuration as the first switch 92, but the transmission gate TG of the second switch 94 is configured to receive a signal that is logically inverted from that of the first switch 92. As a result, the first switch 92 and the second switch 94 change their on/off states exclusively, and operate to output one of the outputs of the output buffer circuit 40 and the DC voltage output circuit 70 to the output terminal 50.

Next, the burst signal detection circuit 60 will be described in detail with reference to Fig. 5. Fig. 5 is a circuit diagram of the burst signal detection circuit 60. The burst signal is detected by comparing the output voltage _VLPF of the low-pass filter 34 having a time constant switching function with a reference voltage _VRef .

The time constant of the low-pass filter 34 is set so that the output voltage V _LPF converges to the intermediate value of the output voltage V _TIA of the TIA core circuit 32 within the preamble period of the burst signal. The burst signal can be detected by setting the reference voltage V _Ref of the comparator CP between the maximum value and the intermediate value of the output voltage V _TIA of the TIA core circuit 32. The burst signal detection circuit 60 of FIG. 5 uses the inverted output of the comparator CP as the burst signal detection voltage V _DET . During the no-signal period of the burst signal and the beginning of the preamble period, while the output voltage V _LPF of the low-pass filter 34 is greater than the reference voltage V _Ref , the output of the comparator CP becomes a high level, and the burst signal detection voltage V _DET becomes a low level. On the other hand, when the output voltage V _LPF of the low-pass filter 34 falls below the reference voltage V _Ref , the output of the comparator CP becomes a low level, and the burst signal detection voltage V _DET becomes a high level.

The time constant of the low-pass filter 34 is changed over by using the burst signal detection voltage V _DET and switching the resistors R ₁ , R ₂ and the capacitors C ₁ , C ₂ by the transmission gates TG ₁ to TG ₃ .

The transmission gates _TG1 to _TG3 have a burst signal detection voltage _VDET and its inverted signal input to their gate terminals, and their on/off states change according to the logic of the burst signal detection voltage _VDET . When the burst signal detection voltage _VDET is at a low level, the transmission gates _TG1 and _TG2 are on (closed), and _TG3 is off (open). On the other hand, when the burst signal detection voltage _VDET is at a high level, the transmission gates _TG1 and _TG2 are off, and _TG3 is on.

6 shows the waveforms of the output voltage V _TIA of the TIA core circuit 32, the output voltage V _LPF of the low-pass filter 34, and the reference voltage V _Ref during the signal-free period of the burst signal and the subsequent preamble period. During the signal-free period of the burst signal, the output voltage V _TIA of the TIA core circuit 32 is constant, but during the preamble period of the burst signal, the output voltage V _TIA of the TIA core circuit 32 has a waveform corresponding to the input signal (however, the waveform is inverted due to inversion amplification). Since the duty ratio during the preamble period is 50%, the output of the low-pass filter 34 approaches the intermediate value between the maximum and minimum values of the output voltage of the TIA core circuit 32.

Therefore, by setting the reference voltage V _Ref of the comparator CP between the maximum value and the intermediate value of the output voltage of the TIA core circuit 32, it becomes possible to detect a burst signal (timing T _DET in FIG. 6). However, since the output voltage V _LPF of the low-pass filter 34 needs to reach a steady state during the preamble period, it is set to satisfy τ _PA ≦T _PA /4. Here, T _PA is the time width of the preamble period, and τ _PA is the time constant of the preamble period. With the above configuration, the inverted signal of the output voltage of the comparator CP is at a high level when a burst signal is received and at a low level during a no-signal period.

<Reducing power consumption during periods when burst signals are not in use>
The burst signal is composed of a preamble period and a payload (net data) period, and the preamble period usually uses a pattern of repeating 1 and 0. During the preamble period, gain adjustment of the TIA core circuit 32, common mode voltage generation of the single-phase differential conversion circuit 36, and synchronous operation of the clock data recovery circuit, which is a subsequent circuit, are performed.

The output of the TIA core circuit 32 is converted to a differential signal via the single-phase differential conversion circuit 36, so the output buffer circuit 40 is also differential. A CML (Current Mode Logic) circuit is generally used as a differential output buffer for high-speed signal transmission.

The CML circuit has a constant current source (e.g., an n-type MOSFET) connected to a differential pair, so when common-mode noise is input to the CML circuit, there is almost no fluctuation in the differential output voltage, making it a circuit with excellent common-mode noise resistance.

The output buffer circuit 40 is composed of multiple CML circuits (see FIG. 3) to supply an output voltage to the subsequent circuit 100, and the current of the constant current source must be designed to be larger for the subsequent CML circuits. For example, in a 50Ω system, the load resistance of the final stage CML circuit is set to 50Ω, so the constant current amount is often set to 8mA (assuming an output of 400mV) or more. Therefore, the current consumption of the output buffer circuit 40 accounts for a large proportion of the entire system. Furthermore, the CML circuit is configured to pass current to the constant current source even when no signal is input. Therefore, current consumption is generated by the constant current source of the CML circuit even during the signal-free period of the burst signal.

FIG. 7(a) shows a circuit diagram of a CML circuit constituting the output buffer circuit 40. Two n-type MOSFETs ( _T1 , _T2 ) form a differential pair. A constant current source is connected in series to the differential pair. FIG. 7(b) shows a circuit diagram of the constant current source. The current amount of the constant current source can be controlled by applying a voltage to the gate terminal of the n-type MOSFET ( _T3 ). The CML circuit of this embodiment is configured such that a switch made of another n-type MOSFET (not shown) is connected in series to the constant current source, and a low-level signal is applied to the gate terminal of the switch to turn off the switch and stop the operation of the constant current source.

The current source control circuit 80 of this embodiment is configured to output a burst signal detection voltage V _DET to each of the constant current sources of the individual CML circuits of the output buffer circuit 40 as shown in FIG. 3. In the no-signal period of the burst signal, the burst signal detection voltage V _DET becomes a low level, and the constant current source of the CML circuit to which the low-level signal is input stops operating. This reduces the power consumption in the no-signal period of the burst signal. When a burst signal is received, the burst signal detection voltage V _DET becomes a high level, and the constant current source of the CML circuit to which the high-level signal is input operates. Note that the control of the constant current source in the no-signal period of the burst signal is not limited to this. The current may be controlled by controlling the voltage applied to the gate terminal of the n-type MOSFET constituting the constant current source. Alternatively, the current of the constant current source may be controlled by controlling the voltage applied to the gate terminal of the n-type MOSFET (T ₁ , T ₂ ) constituting the differential pair.

<DC wonder reduction technology>
8 and 9, a description will be given of the cause of DC wander caused by the current source control of the output buffer circuit 40 and a DC wander reduction technique as a countermeasure therefor. Here, the DC wander reduction technique refers to suppressing DC wander after receiving a burst signal by outputting the output voltage of the output buffer circuit 40 when a burst signal is detected and outputting the output voltage of the DC voltage output circuit 70 when a burst signal is not detected.

Different types of circuits may have different logic levels (particularly common mode voltages). For example, signal standards include LVDS (Low Voltage Differential System), ECL (Emitter Coupled Logic), CML, etc. Therefore, in order to provide a common mode voltage according to the logic level of the subsequent circuit 100, a DC blocking capacitor C _B (hereinafter referred to as a DC block) is usually inserted as shown in FIG. 8 to block low-frequency components including DC components of the output of the previous circuit.

In the block diagram of FIG. 8, FIG. 9 shows the waveforms at each terminal (A) to (C) when a current signal corresponding to a burst signal is input to the TIA circuit 30. FIG. 9(a) shows the waveform when there is no DC wander reduction technology, and FIG. 9(b) shows the waveform when there is DC wander reduction technology. Note that in both FIG. 9(a) and (b), control is performed to stop the constant current source of the output buffer circuit 40 during the signal-free period of the burst signal.

9A and 9B, (A) is the input current waveform to the TIA circuit 30, (B) is the output voltage waveform of the output buffer circuit 40, and (C) is the output voltage waveform of the DC block _CB . At T1 in the figure, the period without a burst signal is switched to the reception period. However, the period required for switching the signal is omitted.

The output voltage of the DC block C _B shown in FIG. 9A(C) transitions at a signal level that deviates significantly from the original baseline after receiving a burst signal. The original baseline is 0 V, and the original signal level is the level shown by the dashed line.

The capacitance of the DC block C _B is at least 1 nF, and in a 50Ω transmission system, the time required for the DC wander to converge is 250 ns or more (5τ is set as the steady state). This time is longer than the preamble period, and the operation cannot be stabilized during the preamble period. As a result, there is a possibility that bit errors will occur during the payload period, causing deterioration of the transmission signal quality.

The cause of DC wander is that the output voltage of the output buffer circuit 40 does not match the DC level during the no-signal period of the burst signal and when the burst signal is being received. Therefore, in this embodiment, a configuration (DC wander reduction technology) is added that provides an appropriate voltage level during the no-signal period so that the voltage level of the output buffer circuit 40 during the no-signal period matches the common mode voltage (median voltage) of the preamble period.

The output voltage of the output buffer circuit 40 in FIG. 9(b) is set to 1.0 V during the signal-free period of the burst signal, as shown in (B). This is achieved by switching to the DC voltage output circuit 70 connected in parallel to the output buffer circuit 40 using the output switching circuit 90 shown in FIG. 3.

<Output switching circuit>
Next, the operation of the output switching circuit 90 of the optical receiver 10 of this embodiment will be described with reference to Fig. 10. Fig. 10(a) is an equivalent circuit diagram of the optical receiver 10 during a no-signal period of a burst signal, and Fig. 10(b) is an equivalent circuit diagram of the optical receiver 10 during a reception period of a burst signal.

A burst signal detection voltage _VDET and its inverted signal are applied as control signals to the transmission gates TG of the first switch 92 and the second switch 94. When the burst signal detection voltage is at a low level (no signal period), the DC voltage output circuit 70 is connected to the output terminal 50 as shown in FIG. 10(a), and when it is at a high level (burst signal reception period), the output buffer circuit 40 is connected to the output terminal 50 as shown in FIG. 10(b).

10A, the current source control circuit 80 receives a burst signal detection voltage _VDET of low level and stops the current of the current source of the output buffer circuit 40. At the same time, the burst signal detection voltage _VDET is input to the gate terminal of the n-type MOSFET of the transmission gate TG of the first switch 92, and an inverted signal of the burst signal detection voltage _VDET is input to the gate terminal of the p-type MOSFET, turning the first switch 92 off (open state), and the output of the output buffer circuit 40 is disconnected.

On the other hand, the DC voltage output circuit 70 receives an inverted signal of the burst signal detection voltage V _DET and outputs a predetermined DC voltage. A signal inverted from that of the first switch 92 is input to each gate terminal of the transmission gate TG of the second switch 94, turning it on (closed state), and the DC voltage output circuit 70 is connected to the output terminal 50. As already explained, the DC voltage output circuit 70 is configured to match the average (median) voltage of the output during the preamble period, and is prepared to suppress DC wander immediately after receiving the burst signal. Note that the match here does not only mean a perfect match, but also allows for an error of about 10%.

10B, the current source control circuit 80 receives a high-level burst signal detection voltage V _DET and operates the current source of the output buffer circuit 40. At the same time, the burst signal detection voltage V _DET is input to the gate terminal of the n-type MOSFET of the transmission gate TG of the first switch 92, and an inverted signal of the burst signal detection voltage V _DET is input to the gate terminal of the p-type MOSFET, turning the first switch 92 on (closed state) and connecting the output buffer circuit 40 to the output terminal 50.

On the other hand, the DC voltage output circuit 70 receives an inverted signal of the burst signal detection voltage V _DET and stops operating (in the case of a CML circuit configuration). A signal inverted from that of the first switch 92 is input to each gate terminal of the transmission gate TG of the second switch 94, turning it off (open state), and the output of the DC voltage output circuit 70 is disconnected from the output terminal 50.

As described above, the optical receiver 10 of this embodiment can reduce power consumption during the no-signal period by stopping the current to the current source of the output buffer circuit 40 during the no-signal period of the burst signal and operating the current source of the output buffer circuit 40 during the reception period of the burst signal. Furthermore, the output voltage of the DC voltage output circuit 70 is output to the output terminal 50 during the no-signal period of the burst signal, and when a burst signal is received, the output voltage of the output buffer circuit 40 is output to the output terminal 50, so that DC wander can be suppressed. Therefore, high-quality signal transmission can be realized. Furthermore, the optical receiver 10 of this embodiment can detect the presence or absence of a burst signal without using an external control signal, so that the system configuration can be simplified.

<Example>
11 and 12 show an embodiment of the optical receiver 10 of the present invention. Figures 11(a), (b), and (d) show simulation results of the waveforms at each terminal when a burst signal is input to the TIA circuit 30 of the optical receiver 10, and Figure 11(c) also shows the results of a comparative example. Here, the optical receiver of the embodiment has a power consumption reduction function and DC wander reduction technology during periods when there is no burst signal, while the optical receiver of the comparative example has a power consumption reduction function during periods when there is no burst signal, but does not have DC wander reduction technology.

Figure 11 (a) shows the input current waveform of the TIA circuit 30 corresponding to a burst signal. The burst signal is a signal consisting of a silent period of 1 ns, followed by a preamble period of 20 ns and a payload period of 40 ns. During the preamble period, signals of 0 and 1 are repeated alternately. In order to check the system's resistance to consecutive identical digits (CID), 66 bits of CID are inserted at both the high and low levels during the payload period.

11B shows the output voltage V _LPF of the low-pass filter 34 and the reference voltage V _Ref of the comparator CP (both on the left scale) and the burst signal detection voltage V _DET (on the right scale) in FIG. 5. It can be seen that the output voltage V _LPF of the low-pass filter 34 falls below the reference voltage V _Ref at the beginning of the preamble period, and the burst signal detection voltage V _DET transitions from a low level to a high level during the preamble period after a certain delay time, and the input of the burst signal is detected. In order to ensure sufficient time for charging the capacitor that constitutes the low-pass filter 34, in this simulation, a delay time is provided from the timing when the output voltage V _LPF of the low-pass filter 34 falls below the reference voltage V _Ref , so that the burst signal detection voltage V _DET rises.

11(c) shows the output voltage waveform of the comparative example. A burst signal is output at the timing of the level transition of the burst signal detection voltage V _DET , but it is observed that the burst signal significantly deviates from the original baseline shown by the dashed line. Therefore, in this state of the waveform, bit errors may occur in the signal processing of the subsequent circuit, causing degradation of signal quality.

Figure 11 (d) shows the output voltage waveform of the embodiment. It can be seen that there is almost no baseline fluctuation before and after receiving the burst signal, and DC wander is suppressed. Therefore, according to the present invention, it is possible to ensure signal quality.

Next, FIG. 12 shows the results of a simulation of the power consumption of the entire circuit, the TIA circuit 30, and the output buffer circuit 40 in this embodiment. Note that the power consumption of the output buffer circuit 40 in this graph includes the power consumption of the single-phase differential conversion circuit and the power consumption of various logic circuits required to implement the present invention, and the power consumption reduction method during the signal-free period of the burst signal is not applied to these.

The output buffer circuit 40 in this embodiment is composed of three stages of CML circuits, and the current amounts of the constant current sources are approximately 6 mA, 8 mA, and 12 mA, respectively.

At 13 ns when the burst signal detection voltage V _DET rises, the constant current power supply of the output buffer circuit 40 is turned on, and the total power consumption is 52.2 mW. Even after 62 ns when the burst signal disappears, V _DET maintains a high level for a while because the time constant of the low-pass filter 34 is large, and the total power consumption is also maintained.

The burst signal detection voltage V _DET transitions to a low level approximately 20 ns after the burst signal disappears. At this timing, the constant current source of the output buffer circuit 40 is turned off, and power consumption is reduced to 23.9 mW. From the above, it can be seen that power consumption during the no-signal period compared to the burst signal reception period is reduced by 54.2%.

<Embodiment 2>
Next, Fig. 13 shows an optical receiver 510 of the second embodiment. Fig. 13(a) is a configuration diagram of the optical receiver 510 of the second embodiment, and Fig. 13(b) is a circuit diagram of a low-pass filter 534 and a burst signal detection circuit 60. In the second embodiment, the same components as those in the first embodiment are given the same reference numerals as those in the first embodiment, and detailed explanations are omitted. The optical receiver 510 of the second embodiment differs in that the low-pass filter 534 of the TIA circuit 30 does not have a time constant switching function, and other configurations are the same as those in the first embodiment.

In this embodiment as well, a burst signal is detected by comparing the output voltage V _LPF of the low-pass filter 534 with the reference voltage V _Ref . Similarly to the first embodiment, the burst signal detection voltage V _DET is output to the DC voltage output circuit 70, the current source control circuit 80, and the output switching circuit 90. In the second embodiment, the low-pass filter 534 does not have a time constant switching function, so the burst signal detection voltage V _DET is not output to the TIA circuit 530.

Other configurations and operations are the same as those of the first embodiment, and the optical receiver 510 of this embodiment also has a power consumption reduction function that stops the current source of the output buffer circuit 40 during the signal-free period of the burst signal. In addition, during the signal-free period of the burst signal, the voltage of the DC voltage output circuit 70 is output to the output terminal 50, and when a burst signal is received, the voltage of the output buffer circuit 40 is output to the output terminal 50, thereby reducing DC wander.

From the above, the optical receiver of the present invention can reduce power consumption during periods when there is no signal in a burst signal. Furthermore, the periods when there is no signal in a burst signal in an optical receiver are generally longer than the reception period of the burst signal. Therefore, it can be seen that the optical receiver of the present invention can reduce power consumption during periods when there is no signal in a burst signal, thereby significantly reducing power consumption during the operation period of the system. Similarly, optical communication systems and in-vehicle optical network systems that employ the optical receiver of the present invention can also significantly reduce power consumption. Furthermore, the optical receiver of the present invention detects periods when there is no signal in a burst signal without using an external control signal, which simplifies the system configuration.

The present invention is not limited to the above-described embodiment and its variations, and various modifications and improvements are possible within the scope of the claims of this application.

10 Optical receiver, 20 Photoelectric conversion element, 30 TIA, 32 TIA core circuit, 34 Low-pass filter, 36 Single-phase differential conversion circuit, 40 Output buffer circuit, 50 Output terminal, 60 Burst signal detection circuit, 70 DC voltage output circuit, 80 Current source control circuit, 82 Current interruption circuit, 90 Output switching circuit, 92 First switch, 94 Second switch, 100 Subsequent circuit, 200 Optical network system, 202 In-home device, 204 Optical coupler, 206 Optical receiver, 208 Signal processing device, 300 Vehicle-mounted optical network system, 302 Master, 304 Gateway, 306 Optical fiber

Claims (6)

a photoelectric conversion element that converts a burst signal, which is an optical signal, into a current signal and outputs the current signal;
a TIA circuit for converting the current signal into a voltage signal;
an output buffer circuit that amplifies the amplitude of the voltage signal and outputs the amplified voltage signal;
a burst signal detection circuit for detecting whether or not the burst signal is received;
A DC voltage output circuit that outputs a predetermined voltage;
a current source control circuit configured to operate a current source of the output buffer circuit when the burst signal is detected and to stop the current source of the output buffer circuit when the burst signal is not detected;
an output switching circuit that outputs the voltage of the output buffer circuit when the burst signal is detected, and outputs the voltage of the DC voltage output circuit when the burst signal is not detected. The voltage of the DC voltage output circuit is configured to match the average/mean value of the voltage of the output buffer circuit when receiving the burst signal.
2. The optical receiver according to claim 1. The output switching circuit includes:
a first switch for switching on and off a voltage of the output buffer circuit;
a second switch that switches the voltage of the DC voltage output circuit on and off;
the first switch and the second switch are configured to change their on/off states exclusively depending on whether or not the burst signal is received.
3. The optical receiver according to claim 2. the current source of the output buffer circuit is a constant current circuit having a transistor;
The current source control circuit is configured to cut off a current flowing through the transistor when the burst signal is not detected.
4. The optical receiver according to claim 1. A plurality of home devices;
an optical coupler that combines signals from optical fibers connected to each of the plurality of home devices and outputs an optical signal;
an optical/electrical signal conversion device having an optical receiver according to any one of claims 1 to 3 for receiving the optical signal output from the optical coupler;
a signal processing device that receives the differentially amplified signal output by the optical/electrical signal conversion device;
An optical communication system comprising: An in-vehicle optical communication network system in which a master and a plurality of gateways are connected in a ring shape by optical fibers,
An in-vehicle optical communication network system, wherein any one of the plurality of gateways includes the optical receiver according to any one of claims 1 to 3.

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