WO2019000761A1 - Power component having stable switching performance - Google Patents
Power component having stable switching performance Download PDFInfo
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- WO2019000761A1 WO2019000761A1 PCT/CN2017/108954 CN2017108954W WO2019000761A1 WO 2019000761 A1 WO2019000761 A1 WO 2019000761A1 CN 2017108954 W CN2017108954 W CN 2017108954W WO 2019000761 A1 WO2019000761 A1 WO 2019000761A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Definitions
- the invention belongs to the field of semiconductor technology, and in particular relates to a power device with stable switching performance.
- Power devices include power ICs and power discrete devices.
- Power discrete devices mainly include semiconductor devices such as power MOSFETs, high-power transistors, and IGBTs.
- Power devices are used in almost all electronic manufacturing industries, including notebooks and PCs in the computer field. , servers, displays and various peripherals; mobile phones, telephones and other various terminal and central office equipment in the field of network communication; traditional black and white household appliances and various digital products in the field of consumer electronics; industrial PCs in industrial control, various types Instrumentation and various control equipment.
- power devices can also effectively save energy. Due to the demand for electronic products and the continuous improvement of energy efficiency requirements, the Chinese power device market has maintained a relatively fast development speed.
- Power semiconductor devices are an important part of power electronic circuits.
- An ideal power semiconductor device should have good static and dynamic characteristics. It can withstand high voltage and leakage current in the off state, and can flow through in the on state. High current and very low tube voltage drop have short on and off times during switching, and on-state loss, off-state loss and switching loss are small. At the same time, it can withstand high di/dt and du/dt and has full control function.
- the existing power devices have extremely fast switching characteristics to achieve higher power conversion efficiency, but during the disconnection and closing of the power device, the gate is prone to oscillation, which causes the switching state of the power device to be instantaneously uncontrollable, and the power device is prone to error.
- the action reduces the switching stability of the power device.
- the present invention proposes a power device with stable switching performance, and a shunt circuit is arranged at the gate of the device.
- a shunt circuit is arranged at the gate of the device.
- a power device having stable switching performance including:
- a substrate of a first conductivity type having a drain of a device of a MOS power device at a bottom end thereof, and an epitaxial layer of a first conductivity type disposed at an upper end of the substrate;
- a body region of a second conductivity type disposed at an upper portion of the channel and the epitaxial layer, wherein the body region covers at least an upper end of two adjacent channels to form an adjacent body region, wherein the body region a device source of a first conductivity type is disposed, and an upper end of the adjacent body region is configured with a device gate;
- first independent channels, second independent channels and third independent channels not covered by the body regions are present in the channel, and the first independent channel is disposed with a first metal at an upper portion thereof
- An oxide semiconductor field effect transistor, a second metal-oxide semiconductor field effect transistor is disposed on the upper portion of the second independent channel, and an upper resistor and a second resistor are disposed on the upper end of the epitaxial layer, and the gate terminal of the device is connected a gate metal pad, the second resistor is connected between the gate metal pad and the device gate, a first drain of the first metal-oxide semiconductor field effect transistor and the device gate Connecting, the first source of the first metal-oxide semiconductor field effect transistor is connected to the device source through the first resistor, and the first gate of the first metal-oxide semiconductor field effect transistor a second gate and a second drain of the second metal-oxide semiconductor field effect transistor are simultaneously connected to the gate metal pad, and the second source and the second metal-oxide semiconductor field effect transistor The device sources are connected in common.
- the upper end of the epitaxial layer is further insulated and disposed with a third resistor connected between the gate metal pad and the first gate.
- an upper portion of the third independent channel is configured with a PN junction, a cathode of the PN junction is connected to the gate metal pad, and an anode of the PN junction is connected to a control end of the device gate.
- an upper portion of the first independent channel is disposed with a first source region of a first conductivity type and a first drain region, and an upper end of the first source region is provided with the first source, the first The first drain is disposed at an upper end of the drain region, and the first gate is disposed at an upper end of the first source region and the first drain region.
- an upper portion of the second independent channel is disposed with a second source region and a second drain region of a first conductivity type, and an upper end of the second source region is disposed with the second source, the second The second drain is disposed at an upper end of the drain region, and the second gate is disposed at an upper end of the second source region and the second drain region.
- the upper portion of the third independent channel is provided with a base region of a first conductivity type, the upper portion of which is disposed with a first region of a second conductivity type, and the upper portion of the base region is disposed with a second region of a first conductivity type .
- the first conductivity type is an N type
- the second conductivity type is a P type
- the first area is an anode of the PN junction
- the second area is a cathode of the PN junction.
- the first conductivity type is a P type
- the second conductivity type is an N type
- the second area is an anode of the PN junction
- the first area is a cathode of the PN junction.
- the first metal-oxide semiconductor field effect transistor is at least two, and each of the first metal-oxide semiconductor field effect transistors is independently disposed in one of the first independent channels, each of the first metal- Each of the first gates of the oxide semiconductor field effect transistor is connected in parallel, each of the first drains is connected in parallel, and each of the first sources is connected in parallel.
- the device gate is a split gate or a full gate.
- a power device with stable switching performance proposed by the invention has faster switching speed and larger switching capacity
- the switching stability of the power device is stronger, no malfunction occurs, and the reliability is improved.
- Figure 1 is a cross-sectional view of a power device with stable switching performance
- FIG. 2 is a top plan view of a power device with stable switching performance
- Figure 3 is a partially enlarged schematic view of Figure 2.
- the schematic diagrams in the drawings of the specification enlarge the thickness of the layers and regions of the present invention, and the size of the listed figures does not represent the actual size; The scope of the invention should not be limited.
- the embodiments listed in the specification should not be limited to the specific shapes of the regions shown in the drawings of the specification, but include the resulting shapes such as manufacturing-induced deviations, etc., such as the curves obtained by etching generally have the characteristics of being curved or rounded. In the embodiments of the present invention, they are all represented by rectangles.
- the power device with stable switching performance proposed by the present invention includes:
- the first conductivity type substrate 700 has a device drain of a MOS power device disposed at a bottom end thereof, and an epitaxial layer 200 of a first conductivity type is disposed at an upper end of the substrate 700, and the material of the substrate epitaxial layer 200 is preferably silicon. But not limited to silicon;
- the second conductivity type channel 100 is disposed in the epitaxial layer at intervals. As shown in FIG. 1 , only six channels 100 are shown in this embodiment, and the number thereof may be determined according to specific product design requirements.
- the channel 100 is flush with the upper end of the epitaxial layer 200;
- the body region 300 of the second conductivity type is disposed on the upper portion of the channel 100 and the epitaxial layer 200. Specifically, the body region 300 of the second conductivity type covers an upper portion of the plurality of channels 100 so that the second conductive portion is finally The body region 300 of the type is flush with the upper end of the epitaxial layer 200, wherein the body region 300 covers at least the upper ends of the two adjacent channels 100 to form adjacent body regions, and the body region is configured with the first a conductive device source 310, the upper end between the adjacent body regions is provided with a device gate 500, thereby constituting a MOS power device;
- first independent channels not covered by the body region exist in the channel 100 110, a second independent channel 120 and a third independent channel 130
- a first metal-oxide semiconductor field effect transistor is disposed on an upper portion of the first independent channel 110, and an upper portion is disposed on an upper portion of the second independent channel 120 a second metal-oxide semiconductor field effect transistor
- the upper end of the epitaxial layer 200 is insulated and configured with a first resistor 610 and a second resistor 620
- the device gate 500 end is connected to the gate metal pad
- the second resistor 620 is connected Between the gate metal pad and the device gate 500, a first drain 115 of the first metal-oxide semiconductor field effect transistor is connected to the device gate 500, the first metal-oxidation
- the first source 113 of the semiconductor field effect transistor is connected to the device source 310 through the first resistor 610, and the first gate 114 and the second metal of the first metal-oxide semiconductor field effect transistor
- the second gate 124 and the second drain 620 of the oxide semiconductor field effect transistor are
- the first gate When the power device is turned off, the first gate has an oscillating voltage, and when the oscillating voltage is too high, the first metal-oxide semiconductor FET and the second metal-oxide semiconductor FET are diverted to the device source.
- the first resistor and the second resistor effectively slow down the absorption of the high voltage, avoiding the gate voltage oscillation, and when the voltage of the gate of the device is at a normal voltage value, the two metal-oxide semiconductor FETs are turned off, and the current does not pass through the metal.
- the oxide semiconductor field effect tube conducts, and does not consume through the first resistor, thereby reducing the loss of the power device, improving the switching capacity of the power device, effectively eliminating the gate voltage oscillation, the stability of the power device switch, and improving Power device reliability, faster switching speed and higher switching capacity.
- the device gates 500 are all gated gates, that is, the device gates are independently disposed at the upper end of each body region, and no adjacent body regions are connected; or the device gates 500 are Is the full gate gate.
- an insulating film 400 is formed on the upper surface of the power device, a conductive film is formed on the insulating film 400, the conductive film and the insulating film are etched, and the remaining conductive film becomes the a device gate, a first gate, a second gate, and a first resistor and a second resistor, and a third resistor 630 is further formed on the conductive film, and is connected to the gate metal pad and the first Between the gates 114.
- a PN junction is disposed on an upper portion of the third independent channel 130, a cathode of the PN junction is connected to the gate metal pad, and an anode of the PN junction and a gate of the device are controlled. End connection.
- the upper portion of the first independent channel 110 is spaced apart from the first source region 112 and the first drain region 111 of the first conductivity type, as shown in FIGS. 2 and 3, the first source region
- the first source 113 is disposed at an upper end of the first drain region 111
- the first drain electrode is disposed at an upper end of the first drain region 111
- the first gate region is disposed at an upper end of the first drain region and the first drain region 114.
- An upper portion of the second independent channel 120 is disposed with a second source region 122 and a second drain region 121 of a first conductivity type, and an upper end of the second source region 122 is disposed with the second source electrode 123.
- the second drain electrode 125 is disposed at an upper end of the second drain region 121, and the second gate electrode 124 is disposed at an upper end of the second source region and the second drain region.
- the upper portion of the third independent channel 130 is provided with a first conductive type base region 131, and the upper portion thereof is provided with a second conductive type first region 132, and the upper portion of the base region 131 is disposed with a first portion A second region 133 of a conductivity type.
- the first conductivity type is an N type
- the second conductivity type is a P type
- the first area is an anode of the PN junction
- the second area is the PN junction cathode.
- the first conductivity type is a P type
- the second conductivity type is an N type
- the second area is an anode of the PN junction
- the first area is the PN junction cathode.
- the first metal-oxide semiconductor field effect transistor is at least two, and each of the first metal-oxide semiconductor field effect transistors is independently disposed in one of the first independent channels, each of which is Each of the first gates of a metal-oxide semiconductor field effect transistor is connected in parallel, each of the first drains is connected in parallel, and each of the first sources is connected in parallel to enhance the diversion effect of the first gate overvoltage, thereby further reducing gate voltage oscillation. Stabilize the breaking characteristics of power devices.
- the power device with stable switching performance proposed by the present invention has a faster switching speed and a larger switching capacity. At the same time, the switching stability of the power device is stronger, no malfunction occurs, and reliability is improved.
Abstract
Description
Claims (10)
- 一种开关性能稳定的功率器件,其特征在于,包括:A power device with stable switching performance, characterized in that it comprises:第一导电型的衬底,其底端配置有MOS功率器件的器件漏极,所述衬底上端配置有第一导电型的外延层;a substrate of a first conductivity type having a drain of a device of a MOS power device at a bottom end thereof, and an epitaxial layer of a first conductivity type disposed at an upper end of the substrate;第二导电型的沟道,其间隔配置在所述外延层中;a second conductivity type channel disposed at intervals in the epitaxial layer;第二导电型的体区,其配置在所述沟道和外延层上部,其中,所述体区至少覆盖在两个相邻所述沟道的上端形成相邻体区,所述体区内配置有第一导电型的器件源极,所述相邻体区之间的上端配置有器件栅极;a body region of a second conductivity type disposed at an upper portion of the channel and the epitaxial layer, wherein the body region covers at least an upper end of two adjacent channels to form an adjacent body region, wherein the body region a device source of a first conductivity type is disposed, and an upper end of the adjacent body region is configured with a device gate;其中,所述沟道中至少存在三个未被所述体区覆盖的第一独立沟道、第二独立沟道以及第三独立沟道,所述第一独立沟道上部配置有第一金属-氧化物半导体场效应管,所述第二独立沟道上部配置有第二金属-氧化物半导体场效应管,所述外延层上端绝缘配置有第一电阻和第二电阻,所述器件栅极端连接栅极金属垫,所述第二电阻连接在所述栅极金属垫和所述器件栅极之间,所述第一金属-氧化物半导体场效应管的第一漏极与所述器件栅极连接,所述第一金属-氧化物半导体场效应管的第一源极通过所述第一电阻与所述器件源极共接,所述第一金属-氧化物半导体场效应管的第一栅极、第二金属-氧化物半导体场效应管的第二栅极和第二漏极同时共接在栅极金属垫上,所述第二金属-氧化物半导体场效应管的第二源极与所述器件源极共接。Wherein at least three first independent channels, second independent channels and third independent channels not covered by the body regions are present in the channel, and the first independent channel is disposed with a first metal at an upper portion thereof An oxide semiconductor field effect transistor, a second metal-oxide semiconductor field effect transistor is disposed on the upper portion of the second independent channel, and an upper resistor and a second resistor are disposed on the upper end of the epitaxial layer, and the gate terminal of the device is connected a gate metal pad, the second resistor is connected between the gate metal pad and the device gate, a first drain of the first metal-oxide semiconductor field effect transistor and the device gate Connecting, the first source of the first metal-oxide semiconductor field effect transistor is connected to the device source through the first resistor, and the first gate of the first metal-oxide semiconductor field effect transistor a second gate and a second drain of the second metal-oxide semiconductor field effect transistor are simultaneously connected to the gate metal pad, and the second source and the second metal-oxide semiconductor field effect transistor The device sources are connected in common.
- 如权利要求1所述的开关性能稳定的功率器件,其特征在于,所述外延层上端还绝缘配置有第三电阻,其连接在所述栅极金属垫与所述第一栅极之间。The power device with stable switching performance according to claim 1, wherein the upper end of the epitaxial layer is further insulated and disposed with a third resistor connected between the gate metal pad and the first gate.
- 如权利要求2所述的开关性能稳定的功率器件,其特征在于,所述第三独立沟道上部配置有PN结,所述PN结的阴极与所述栅极金属垫连接,所述PN结的阳极极与所述器件栅极的控制端连接。 A power device with stable switching performance according to claim 2, wherein said third independent channel upper portion is provided with a PN junction, said cathode of said PN junction being connected to said gate metal pad, said PN junction The anode pole is connected to the control terminal of the device gate.
- 如权利要求3所述的开关性能稳定的功率器件,其特征在于,所述第一独立沟道的上部间隔配置有第一导电型的第一源区和第一漏区,所述第一源区上端设置有所述第一源极,所述第一漏区上端设置有所述第一漏极,所述第一源区和第一漏区上端配置有所述第一栅极。The power device with stable switching performance according to claim 3, wherein the upper portion of the first independent channel is disposed with a first source region of a first conductivity type and a first drain region, the first source The first source is disposed at an upper end of the region, the first drain is disposed at an upper end of the first drain region, and the first gate is disposed at an upper end of the first source region and the first drain region.
- 如权利要求4所述的开关性能稳定的功率器件,其特征在于,所述第二独立沟道的上部间隔配置有第一导电型的第二源区和第二漏区,所述第二源区上端设置有所述第二源极,所述第二漏区上端设置有所述第二漏极,所述第二源区和第二漏区上端配置有所述第二栅极。The power device with stable switching performance according to claim 4, wherein the upper portion of the second independent channel is disposed with a second source region and a second drain region of the first conductivity type, the second source The second source is disposed at an upper end of the region, the second drain is disposed at an upper end of the second drain region, and the second gate is disposed at an upper end of the second source region and the second drain region.
- 如权利要求5所述的开关性能稳定的功率器件,其特征在于,所述第三独立沟道的上部配置有第一导电型的基区,其上部配置有第二导电型的第一区,所述基区上端配置有第一导电型的第二区。The power device with stable switching performance according to claim 5, wherein the upper portion of the third independent channel is provided with a base region of a first conductivity type, and the upper portion of the third independent channel is configured with a first region of a second conductivity type, A second region of the first conductivity type is disposed at an upper end of the base region.
- 如权利要求6所述的开关性能稳定的功率器件,其特征在于,所述第一导电型为N型,所述第二导电型为P型,所述第一区为所述PN结的阳极,所述第二区为所述PN结的阴极。A power device with stable switching performance according to claim 6, wherein said first conductivity type is N type, said second conductivity type is P type, and said first region is an anode of said PN junction. The second region is the cathode of the PN junction.
- 如权利要求6所述的开关性能稳定的功率器件,其特征在于,所述第一导电型为P型,所述第二导电型为N型,所述第二区为所述PN结的阳极,所述第一区为所述PN结的阴极。A power device with stable switching performance according to claim 6, wherein said first conductivity type is a P type, said second conductivity type is an N type, and said second region is an anode of said PN junction. The first zone is the cathode of the PN junction.
- 如权利要求7或8所述的开关性能稳定的功率器件,其特征在于,所述第一金属-氧化物半导体场效应管至少为2个,每一个第一金属-氧化物半导体场效应管独立配置在一个所述第一独立沟道中,每一个第一金属-氧化物半导体场效应管的各个第一栅极并联、各个第一漏极并联、各个第一源极并联。A power device with stable switching performance according to claim 7 or 8, wherein said first metal-oxide semiconductor field effect transistor has at least two, each of which is independent of the first metal-oxide semiconductor field effect transistor. In each of the first independent channels, each of the first gates of each of the first metal-oxide semiconductor field effect transistors is connected in parallel, each of the first drains is connected in parallel, and each of the first sources is connected in parallel.
- 如权利要求1所述的开关性能稳定的功率器件,其特征在于,所述器件栅极为分栅栅极或全栅栅极。 The power device with stable switching performance according to claim 1, wherein the gate of the device is a split gate or a full gate.
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CN107393923B (en) | 2020-06-23 |
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