CN107393923B - Power device with stable switching performance - Google Patents
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- CN107393923B CN107393923B CN201710511930.7A CN201710511930A CN107393923B CN 107393923 B CN107393923 B CN 107393923B CN 201710511930 A CN201710511930 A CN 201710511930A CN 107393923 B CN107393923 B CN 107393923B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 230000005669 field effect Effects 0.000 claims abstract description 38
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 38
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 38
- 210000000746 body region Anatomy 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a power device with stable switching performance, which comprises: the device comprises a substrate of a first conduction type, a first electrode and a second electrode, wherein a device drain electrode is arranged at the bottom end of the substrate, and an epitaxial layer is arranged at the upper end of the substrate; a channel of a second conductivity type, a body region of the second conductivity type, a device source and a device gate being arranged in the body region; the power device comprises an epitaxial layer, wherein a first independent channel, a second independent channel and a third independent channel are arranged in the channels, a first metal-oxide semiconductor field effect transistor is arranged on the upper portion of the first independent channel, a second metal-oxide semiconductor field effect transistor is arranged on the upper portion of the second independent channel, a first resistor and a second resistor are arranged at the upper end of the epitaxial layer in an insulating mode, and the first metal-oxide semiconductor field effect transistor and the second metal-oxide semiconductor field effect transistor are connected in the power device as a flow guiding loop. The invention solves the technical problem of unstable switching performance of the power device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a power device with stable switching performance.
Background
The power device comprises a power IC and a power discrete device, the power discrete device mainly comprises semiconductor devices such as a power MOSFET, a high-power transistor and an IGBT, the power device is almost used in all electronic manufacturing industries, and applied products comprise a notebook computer, a PC, a server, a display and various peripherals in the field of computers; mobile phones, telephones and other various terminals and local-end equipment in the field of network communication; traditional black and white appliances and various digital products in the consumer electronics field; industrial PCs, instruments and control devices in industrial control systems. Besides ensuring the normal operation of the devices, the power device can also play an effective energy-saving role. Due to the continuous improvement of the requirements of electronic products and energy efficiency, the market of Chinese power devices keeps a faster development speed.
The power semiconductor device is an important component of a power electronic circuit, an ideal power semiconductor device has good static and dynamic characteristics, can bear high voltage and small leakage current in an off state, can flow large current and very low tube voltage drop in an on state, and has short on and off time in switching; the on-state loss, off-state loss and switching loss are all small. Meanwhile, the system can bear high di/dt and du/dt and has a full control function.
The conventional power device has extremely fast switching characteristics and realizes higher power conversion efficiency, but in the process of opening and closing the power device, a grid easily generates oscillation, so that the switching state of the power device is uncontrollable instantaneously, the power device is easy to malfunction, and the switching stability of the power device is reduced.
Disclosure of Invention
Aiming at the technical problems, the invention provides the power device with stable switching performance, the grid electrode of the device is provided with the shunt circuit, when the grid voltage of the power device vibrates excessively, the voltage is guided through the shunt circuit, the grid voltage is prevented from vibrating, and the technical problem of unstable switching performance of the power device is solved.
To achieve these objects and other advantages in accordance with the purpose of the invention, there is provided a power device with stable switching performance, including:
the MOS power device comprises a substrate of a first conduction type, a first power source and a second power source, wherein the bottom end of the substrate of the first conduction type is provided with a device drain of the MOS power device, and the upper end of the substrate is provided with an epitaxial layer of the first conduction type;
a channel of a second conductivity type disposed at an interval in the epitaxial layer;
a body region of a second conductivity type disposed above the channel and the epitaxial layer, wherein the body region covers at least upper ends of two adjacent channels to form an adjacent body region, a device source of the first conductivity type is disposed in the body region, and a device gate is disposed at an upper end between the adjacent body regions;
the first conductive type is an N type, the second conductive type is a P type, the first region is an anode of the PN junction, and the second region is a cathode of the PN junction;
the first conductive type is a P type, the second conductive type is an N type, the second region is an anode of the PN junction, and the first region is a cathode of the PN junction;
wherein, there are at least three first independent channels, second independent channels and third independent channels which are not covered by the body region in the channel, a first metal-oxide semiconductor field effect transistor is arranged on the upper portion of the first independent channel, a second metal-oxide semiconductor field effect transistor is arranged on the upper portion of the second independent channel, a first resistor and a second resistor are arranged on the upper end of the epitaxial layer in an insulating way, the grid end of the device is connected with a grid metal pad, the second resistor is connected between the grid metal pad and the grid of the device, the first drain of the first metal-oxide semiconductor field effect transistor is connected with the grid of the device, the first source of the first metal-oxide semiconductor field effect transistor is connected with the source of the device through the first resistor in a common way, and the first grid of the first metal-oxide semiconductor field effect transistor, The second grid and the second drain of the second metal-oxide semiconductor field effect transistor are connected on the grid metal pad at the same time, the second source of the second metal-oxide semiconductor field effect transistor is connected with the device source, the number of the first metal-oxide semiconductor field effect transistors is at least 2, each first metal-oxide semiconductor field effect transistor is independently configured in one first independent channel, and each first grid, each first drain and each first source of each first metal-oxide semiconductor field effect transistor are connected in parallel.
Preferably, the upper end of the epitaxial layer is further provided with a third resistor in an insulating manner, and the third resistor is connected between the gate metal pad and the first gate.
Preferably, a PN junction is disposed at an upper portion of the third independent channel, a cathode of the PN junction is connected to the gate metal pad, and an anode of the PN junction is connected to a control terminal of the gate of the device.
Preferably, a first source region and a first drain region of a first conductivity type are spaced apart from each other at an upper portion of the first isolation channel, the first source region is provided at an upper end thereof with the first source electrode, the first drain region is provided at an upper end thereof with the first drain electrode, and the first gate electrode is provided at upper ends of the first source region and the first drain region.
Preferably, a second source region and a second drain region of the first conductivity type are spaced apart from each other at an upper portion of the second isolation channel, the second source region is disposed at an upper end of the second source region, the second drain region is disposed at an upper end of the second drain region, and the second gate electrode is disposed at upper ends of the second source region and the second drain region.
Preferably, a base region of the first conductivity type is disposed above the third isolated channel, a first region of the second conductivity type is disposed above the base region, and a second region of the first conductivity type is disposed above the base region.
Preferably, the device gate is a split gate or a full gate.
The invention at least comprises the following beneficial effects:
1. the power device with stable switching performance provided by the invention has the advantages that the switching speed is higher, and the switching capacity is larger;
2. the power device has stronger switching stability, can not generate misoperation, and improves the reliability.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
Fig. 1 is a cross-sectional view of a power device with stable switching performance;
FIG. 2 is a top view of a power device with stable switching performance;
fig. 3 is a partially enlarged schematic view of fig. 2.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic diagrams listed in the drawings of the specification enlarge the thicknesses of the layers and regions of the present invention, and the sizes of the listed figures do not represent actual sizes; the drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure. The embodiments listed in the specification should not be limited to the specific shapes of the regions shown in the drawings of the specification, but include the resulting shapes such as manufacturing-induced variations and the like, and the curves obtained by etching generally have curved or rounded features, which are represented by rectangles in the embodiments of the present invention.
As shown in fig. 1 to 3, the power device with stable switching performance proposed by the present invention includes:
a substrate 700 of a first conductivity type, a device drain of a MOS power device being disposed at a bottom end of the substrate 700, an epitaxial layer 200 of the first conductivity type being disposed at an upper end of the substrate 700, the substrate epitaxial layer 200 preferably being made of silicon, but not limited to silicon;
the trenches 100 of the second conductivity type are arranged in the epitaxial layer at intervals, as shown in fig. 1, only 6 trenches 100 are shown in this embodiment, the number of the trenches 100 can be determined according to the design requirement of a specific product, and the trenches 100 are flush with the upper end of the epitaxial layer 200;
a body region 300 of the second conductivity type, which is disposed above the trenches 100 and the epitaxial layer 200, specifically, the body region 300 of the second conductivity type is disposed over several trenches 100, so that the body region 300 of the second conductivity type is finally flush with the upper end of the epitaxial layer 200, wherein the body region 300 at least covers the upper ends of two adjacent trenches 100 to form adjacent body regions, a device source 310 of the first conductivity type is disposed in the body regions, and a device gate 500 is disposed at the upper end between the adjacent body regions, thereby forming a MOS power device;
wherein, at least three first independent channels 110, second independent channels 120 and third independent channels 130 which are not covered by the body region exist in the channel 100, a first metal-oxide semiconductor field effect transistor is arranged on the upper portion of the first independent channel 110, a second metal-oxide semiconductor field effect transistor is arranged on the upper portion of the second independent channel 120, a first resistor 610 and a second resistor 620 are arranged on the upper end of the epitaxial layer 200 in an insulating way, the device gate 500 end is connected with a gate metal pad, the second resistor 620 is connected between the gate metal pad and the device gate 500, the first drain 115 of the first metal-oxide semiconductor field effect transistor is connected with the device gate 500, and the first source 113 of the first metal-oxide semiconductor field effect transistor is connected with the device source 310 through the first resistor 610, the first gate 114 of the first metal-oxide semiconductor field effect transistor, the second gate 124 of the second metal-oxide semiconductor field effect transistor and the second drain 620 are connected to the gate metal pad in common, and the second source 123 of the second metal-oxide semiconductor field effect transistor is connected to the device source 310 in common. The electrodes and the resistors are connected by metal wires, which is not described in the present embodiment.
When the power device is turned off, oscillation voltage appears on the first grid, when the oscillation voltage is too high, the first metal-oxide semiconductor field effect transistor and the second metal-oxide semiconductor field effect transistor conduct current to the source electrode of the device, high voltage is effectively relieved and absorbed through the first resistor and the second resistor, grid voltage oscillation is avoided, when the voltage of the grid electrode of the device is in a normal voltage value, the two metal-oxide semiconductor field effect transistors are cut off, current cannot conduct current through the metal-oxide semiconductor field effect transistors, and the current cannot be consumed through the first resistor, so that loss of the power device is reduced, switching capacity of the power device is improved, grid voltage oscillation is effectively eliminated, stability of switching of the power device is improved, reliability of the power device is improved, switching speed is higher, and switching capacity is higher.
In one embodiment, the device gates 500 are split-gate gates, that is, the device gates are independently disposed at the upper end of each body region, and do not connect two adjacent body regions; or the device gates 500 are all full gate gates.
In one embodiment, an insulating film 400 is formed on the upper surface of the power device, a conductive film is formed on the insulating film 400, the conductive film and the insulating film are etched, and the remaining conductive film becomes the device gate, the first gate, the second gate, the first resistor, and the second resistor, and a third resistor 630 is formed on the conductive film and connected between the gate metal pad and the first gate 114.
In one embodiment, a PN junction is disposed above the third isolated channel 130, a cathode of the PN junction is connected to the gate metal pad, and an anode of the PN junction is connected to a control terminal of the device gate.
In one embodiment, a first source region 112 and a first drain region 111 of the first conductivity type are spaced apart from an upper portion of the first isolation channel 110, as shown in fig. 2 and 3, the first source 113 is disposed at an upper end of the first source region 112, the first drain 115 is disposed at an upper end of the first drain region 111, and the first gate 114 is disposed at upper ends of the first source region and the first drain region.
A second source region 122 and a second drain region 121 of the first conductivity type are spaced apart from each other at an upper portion of the second isolation channel 120, the second source 123 is disposed at an upper end of the second source region 122, the second drain 125 is disposed at an upper end of the second drain region 121, and the second gate 124 is disposed at upper ends of the second source region and the second drain region.
In one embodiment, a base region 131 of the first conductivity type is disposed above the third independent channel 130, a first region 132 of the second conductivity type is disposed above the third independent channel, and a second region 133 of the first conductivity type is disposed above the base region 131.
In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the first region is an anode of the PN junction, and the second region is a cathode of the PN junction.
In one embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the second region is an anode of the PN junction, and the first region is a cathode of the PN junction.
In one embodiment, the number of the first metal-oxide semiconductor field effect transistors is at least 2, each first metal-oxide semiconductor field effect transistor is independently configured in one first independent channel, and each first gate, each first drain and each first source of each first metal-oxide semiconductor field effect transistor are connected in parallel, so that the diversion effect of the first gate overvoltage is enhanced, gate voltage oscillation is further reduced, and the turn-off characteristic of the power device is stabilized.
In view of the above, the power device with stable switching performance provided by the invention has faster switching speed and larger switching capacity; meanwhile, the power device has stronger switching stability, can not generate misoperation, and improves the reliability.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (7)
1. A power device with stable switching performance, comprising:
the MOS power device comprises a substrate of a first conduction type, a first power source and a second power source, wherein the bottom end of the substrate of the first conduction type is provided with a device drain of the MOS power device, and the upper end of the substrate is provided with an epitaxial layer of the first conduction type;
a channel of a second conductivity type disposed at an interval in the epitaxial layer;
a body region of a second conductivity type disposed above the channel and the epitaxial layer, wherein the body region covers at least upper ends of two adjacent channels to form an adjacent body region, a device source of the first conductivity type is disposed in the body region, and a device gate is disposed at an upper end between the adjacent body regions;
wherein, there are at least three first independent channels, second independent channels and third independent channels which are not covered by the body region in the channel, a first metal-oxide semiconductor field effect transistor is arranged on the upper portion of the first independent channel, a second metal-oxide semiconductor field effect transistor is arranged on the upper portion of the second independent channel, a first resistor and a second resistor are arranged on the upper end of the epitaxial layer in an insulating way, the grid end of the device is connected with a grid metal pad, the second resistor is connected between the grid metal pad and the grid of the device, the first drain of the first metal-oxide semiconductor field effect transistor is connected with the grid of the device, the first source of the first metal-oxide semiconductor field effect transistor is connected with the source of the device through the first resistor in a common way, and the first grid of the first metal-oxide semiconductor field effect transistor, A second grid and a second drain of the second metal-oxide semiconductor field effect transistor are simultaneously connected to the grid metal pad in a common mode, and a second source of the second metal-oxide semiconductor field effect transistor is connected to the device source in a common mode;
a base region of the first conductivity type is arranged above the third independent channel, a first region of the second conductivity type is arranged above the base region, and a second region of the first conductivity type is arranged at the upper end of the base region;
the number of the first metal-oxide semiconductor field effect transistors is at least 2, each first metal-oxide semiconductor field effect transistor is independently configured in one first independent channel, and each first grid electrode, each first drain electrode and each first source electrode of each first metal-oxide semiconductor field effect transistor are connected in parallel.
2. The switching performance stabilized power device according to claim 1, wherein a third resistor is further disposed on an upper end of the epitaxial layer in an insulated manner, and is connected between the gate metal pad and the first gate.
3. The switching performance stabilized power device according to claim 2, wherein a PN junction is disposed above the third independent channel, a cathode of the PN junction is connected to the gate metal pad, and an anode of the PN junction is connected to the control terminal of the device gate.
4. The power device with stable switching performance according to claim 3, wherein a first source region and a first drain region of the first conductivity type are spaced apart from each other at an upper portion of the first isolation channel, the first source region is provided with the first source electrode at an upper end thereof, the first drain region is provided with the first drain electrode at an upper end thereof, and the first gate electrode is provided at upper ends of the first source region and the first drain region.
5. The power device with stable switching performance according to claim 4, wherein a second source region and a second drain region of the first conductivity type are spaced apart from each other at an upper portion of the second isolation channel, the second source region is disposed at an upper end of the second source region, the second drain region is disposed at an upper end of the second drain region, and the second gate electrode is disposed at upper ends of the second source region and the second drain region.
6. The switching performance stabilized power device of claim 3, wherein said first conductivity type is N-type, said second conductivity type is P-type, said first region is an anode of said PN junction, and said second region is a cathode of said PN junction.
7. The switching performance stabilized power device of claim 3, wherein said first conductivity type is P-type, said second conductivity type is N-type, said second region is an anode of said PN junction, and said first region is a cathode of said PN junction.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710511930.7A CN107393923B (en) | 2017-06-27 | 2017-06-27 | Power device with stable switching performance |
| PCT/CN2017/108954 WO2019000761A1 (en) | 2017-06-27 | 2017-11-01 | Power component having stable switching performance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710511930.7A CN107393923B (en) | 2017-06-27 | 2017-06-27 | Power device with stable switching performance |
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| CN107393923A CN107393923A (en) | 2017-11-24 |
| CN107393923B true CN107393923B (en) | 2020-06-23 |
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| CN201710511930.7A Active CN107393923B (en) | 2017-06-27 | 2017-06-27 | Power device with stable switching performance |
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| WO (1) | WO2019000761A1 (en) |
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| US5304802A (en) * | 1992-01-06 | 1994-04-19 | Fuji Electric Co., Ltd. | Semiconductor device including overvoltage protective circuit |
| CN101019319A (en) * | 2004-08-03 | 2007-08-15 | 飞思卡尔半导体公司 | A semiconductor switch arrangement and an electronic device |
| CN103151348A (en) * | 2011-12-06 | 2013-06-12 | 英飞凌科技奥地利有限公司 | Integrated circuit including a power transistor and an auxiliary transistor |
| TW201411809A (en) * | 2012-09-05 | 2014-03-16 | Silicongear Corp | Power MOSFET element |
| CN105161491A (en) * | 2015-09-22 | 2015-12-16 | 苏州东微半导体有限公司 | Integrated gate driver transistor (IGDT) power device and manufacturing method thereof |
| WO2016173394A1 (en) * | 2015-04-30 | 2016-11-03 | 苏州东微半导体有限公司 | Semiconductor super-junction power device and manufacturing method therefor |
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| US7952145B2 (en) * | 2007-02-20 | 2011-05-31 | Texas Instruments Lehigh Valley Incorporated | MOS transistor device in common source configuration |
| US9070571B2 (en) * | 2013-03-15 | 2015-06-30 | Infineon Technologies Ag | Power switching module with reduced oscillation |
| US9893175B2 (en) * | 2013-09-30 | 2018-02-13 | Infineon Technologies Austria Ag | Integrated circuit with a power transistor and a driver circuit integrated in a common semiconductor body |
| CN104867972B (en) * | 2014-02-20 | 2017-09-05 | 北大方正集团有限公司 | DMOS devices of integrated driving resistance and preparation method thereof |
| CN104795445A (en) * | 2015-04-01 | 2015-07-22 | 苏州东微半导体有限公司 | Low-loss super-junction power device and manufacturing method thereof |
| CN106024869A (en) * | 2016-05-24 | 2016-10-12 | 电子科技大学 | Power semiconductor device |
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2017
- 2017-06-27 CN CN201710511930.7A patent/CN107393923B/en active Active
- 2017-11-01 WO PCT/CN2017/108954 patent/WO2019000761A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304802A (en) * | 1992-01-06 | 1994-04-19 | Fuji Electric Co., Ltd. | Semiconductor device including overvoltage protective circuit |
| CN101019319A (en) * | 2004-08-03 | 2007-08-15 | 飞思卡尔半导体公司 | A semiconductor switch arrangement and an electronic device |
| CN103151348A (en) * | 2011-12-06 | 2013-06-12 | 英飞凌科技奥地利有限公司 | Integrated circuit including a power transistor and an auxiliary transistor |
| TW201411809A (en) * | 2012-09-05 | 2014-03-16 | Silicongear Corp | Power MOSFET element |
| WO2016173394A1 (en) * | 2015-04-30 | 2016-11-03 | 苏州东微半导体有限公司 | Semiconductor super-junction power device and manufacturing method therefor |
| CN105161491A (en) * | 2015-09-22 | 2015-12-16 | 苏州东微半导体有限公司 | Integrated gate driver transistor (IGDT) power device and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| WO2019000761A1 (en) | 2019-01-03 |
| CN107393923A (en) | 2017-11-24 |
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