WO2018233363A1 - 一种音频处理电路及终端设备 - Google Patents

一种音频处理电路及终端设备 Download PDF

Info

Publication number
WO2018233363A1
WO2018233363A1 PCT/CN2018/083521 CN2018083521W WO2018233363A1 WO 2018233363 A1 WO2018233363 A1 WO 2018233363A1 CN 2018083521 W CN2018083521 W CN 2018083521W WO 2018233363 A1 WO2018233363 A1 WO 2018233363A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
operational amplifier
voltage
ramp
resistance
Prior art date
Application number
PCT/CN2018/083521
Other languages
English (en)
French (fr)
Inventor
尹德杨
李君�
李定
杜帅
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18820785.6A priority Critical patent/EP3641338B1/en
Publication of WO2018233363A1 publication Critical patent/WO2018233363A1/zh
Priority to US16/720,771 priority patent/US10903801B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3264—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits in audio amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/305—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in case of switching on or off of a power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/02—Circuits for transducers, loudspeakers or microphones for preventing acoustic reaction, i.e. acoustic oscillatory feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/231—Indexing scheme relating to amplifiers the input of an amplifier can be switched on or off by a switch to amplify or not an input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/312—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising one or more switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/381—An active variable resistor, e.g. controlled transistor, being coupled in the output circuit of an amplifier to control the output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/396—Indexing scheme relating to amplifiers the output of an amplifier can be switched on or off by a switch to couple the output signal to a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/421—Multiple switches coupled in the output circuit of an amplifier are controlled by a circuit

Definitions

  • the present application relates to the field of circuit technologies, and in particular, to an audio processing circuit and a terminal device.
  • the op amp path establishment process involves the establishment of the op amp operating point and the establishment of the op amp path. Since each op amp circuit in an audio circuit is not an ideal device, there may be an offset voltage at each stage of the op amp circuit. The voltage offset generated by the preamplifier circuit is transferred to the post-stage op amp circuit. There is a voltage difference between the output voltage of the preamplifier circuit and the ideal voltage. This will cause the op amp operating point to be established or the op amp. During the path establishment process, the output node generates an offset voltage, which eventually causes the transient voltage waveform of the output node to be abnormal.
  • the audio load When the abnormal voltage is transmitted from the output node to the audio load, the audio load generates POP noise. Since the waveform of the POP noise generated during the operation of the operational point of the operational amplifier is a narrow pulse in the audio range, the POP noise will have a strong current impact on the human ear, which is likely to cause discomfort to the human ear.
  • the present application provides an audio processing circuit and a terminal device, which can solve the problem of POP noise generated in the process of establishing an operational path in the prior art.
  • the first aspect of the present application provides an audio processing circuit, which may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more circuits corresponding to the functions described above, which may be software and/or hardware.
  • the circuit may include a cascaded operational amplifier circuit, a pull-down circuit, and an output node, and the node in which the cascaded operational amplifier circuit is electrically connected to the audio load is an output node.
  • the cascade operational amplifier circuit includes a first operational amplifier circuit and a second operational amplifier circuit, wherein the first operational amplifier circuit is a front stage operational amplifier of the second operational amplifier circuit, and the first operational amplifier circuit A main operational amplifier and a secondary operational amplifier are included, and the primary operational amplifier and the secondary operational amplifier are connected in parallel.
  • the cascade operational amplifier circuit is configured to amplify an input voltage and output the amplified voltage to the output node.
  • the pull down circuit is coupled to the output node, and the other end of the pull down circuit is grounded or a common mode voltage module.
  • the pull-down circuit is configured to pull down a voltage of the output node after the first operational amplifier circuit is turned on.
  • the second operational amplifier circuit is configured to control a voltage of the auxiliary operational amplifier to change from a low to a high voltage after the auxiliary operational amplifier is turned on, thereby controlling a voltage of the output node to follow a gradual change of the output resistance, from a low a high gradation; the main operational amplifier is turned on when the voltage gain of the auxiliary operational amplifier reaches a preset gain.
  • a second operational amplifier circuit outputted as a subsequent operational amplifier pulls down the output node in the pull-down circuit
  • the first operational amplifier circuit and the second operational amplifier circuit After being turned on, by controlling the output resistance of the second operational amplifier circuit to change from high to low, the voltage of the output node is controlled to follow the gradual change of the output resistance, and the gradation changes from low to high, so that the operation path is established.
  • the voltage of the output node can be slowly increased, thereby reducing the generation of POP noise, and also transmitting the offset voltage of the first operational amplifier circuit as the front stage operational amplifier to the load, thereby showing that the audio circuit structure of the present application is adopted. It can effectively suppress POP noise during the establishment of the op amp path.
  • the second op amp circuit further includes a variable resistance circuit.
  • the main operational amplifier is coupled in parallel with a first series circuit, the first series circuit comprising: the auxiliary operational amplifier and the variable resistance circuit connected in series.
  • the variable resistance circuit is configured to control the output resistance of the first series circuit to change from high to low, thereby controlling the voltage gain of the auxiliary operational amplifier to change from low to high, thereby controlling the voltage of the output node from Low to high gradients, or gradients from high to low.
  • the variable resistance circuit includes a ramp signal controller and a variable resistor. Since there may be a positive/negative offset voltage in the audio circuit, the positive/negative offset voltage is in the process of establishing the op amp path. POP noise is generated, and the generated POP noise can be reduced by the ramp signal controller. Therefore, the variable resistor may include at least one of a first ramp resistor and a second ramp resistor, respectively suppressing POP noise caused by a positive/negative offset voltage.
  • the output level of the first ramp resistor is a first level
  • the output level of the second ramp resistor is a second level.
  • the ramp signal controller may control a gradation value of an output resistance of the variable resistor by controlling a gradation value of the first level or a gradation value of the second level.
  • the ramp signal controller is further configured to: after the first operational amplifier circuit and the auxiliary operational amplifier are turned on, control an output resistance of the variable resistor to be not less than the first resistance value to cut off The path between the cascaded op amp circuit and the output node.
  • the ramp signal controller is specifically configured to control the output resistance of the variable resistor to be not less than after the first operational amplifier circuit and the auxiliary operational amplifier are both turned on.
  • the first resistance is to intercept a path between the cascade operational amplifier circuit and the output node.
  • the ramp signal controller is used to:
  • the first operational amplifier circuit and the auxiliary operational amplifier are both turned on, controlling the resistance of the variable resistor to be changed from the first resistance value to the second resistance value, so that the voltage of the output node follows the The gradual value of the resistance of the variable resistor rises until the voltage of the output node approaches the first voltage value.
  • the first resistance value is greater than the second resistance value.
  • the first voltage value refers to a positive voltage value
  • the resistance change of the variable resistor characterizes a change in output resistance of the first series circuit
  • the main operational amplifier is configured to be turned on after the ramp signal controller controls that the voltage of the output node approaches the first voltage value, so that the output voltage of the cascade op amp circuit drives the Said output node.
  • the ramp signal controller is specifically configured to control the first after the first operational amplifier circuit and the auxiliary operational amplifier are turned on
  • a ramp resistor has a resistance not less than the first resistance to intercept a path between the cascaded op amp circuit and the output node.
  • the resistance of the first ramp resistor is controlled to be high impedance, so that the op amp circuit and the output node can be directly cut off, and the voltage of the output node is not abruptly changed, so that the audio load pair of the POP noise transmission can be effectively avoided. Interference from the human ear.
  • the ramp signal controller is configured to provide a first ramp signal after the first operational amplifier circuit and the second operational amplifier circuit are both turned on.
  • the first ramp signal is used to control the level value of the first level to be changed from the first level value to the second level value, thereby controlling the resistance of the first ramp resistor to change from high to low.
  • the voltage of the output node ramps from low to high until the voltage of the output node approaches the first voltage value, the first level value being greater than the second level value. Wherein, the voltage of the output node can be gradually changed according to the gradient of the resistance of the first ramp resistor.
  • the output voltage of the cascaded operational amplifier circuit outputs the output node,
  • the third resistance is greater than or equal to the second resistance. It can be seen that the gradual change of the level of the first level causes the output node to slowly reach the offset voltage, so that the entire op amp path is slowly established, in preparation for subsequent activation of the main operational amplifier.
  • the path between the cascaded operational amplifier circuit and the output node is disconnected in an initial state in which the resistance of the first ramp resistor follows a change gradient of the first ramp signal.
  • the output voltage of the operational amplifier circuit cannot output the output node, and the voltage of the output node is not abruptly changed. Therefore, the offset voltage of the cascaded op amp circuit is not transmitted to the output node during the operation of the op amp path. Therefore, the output node does not pass the offset voltage to the audio load, so that no POP noise is generated when the op amp path is established.
  • the ramp signal controller is used to:
  • the change in resistance of the variable resistor characterizes a change in the output resistance of the first series circuit.
  • the primary operational amplifier is then operative to turn on after the ramp signal controller controls the voltage of the output node to converge toward the second voltage value such that an output voltage of the cascaded operational amplifier circuit drives the output node.
  • the ramp signal controller is specifically configured to control the first after the first operational amplifier circuit and the auxiliary operational amplifier are turned on
  • the resistance of the two ramp resistors is not less than the first resistance to intercept the path between the cascade operational amplifier circuit and the output node.
  • the resistance of the second ramp resistor is controlled to be high impedance.
  • the ramp signal controller is configured to provide a second ramp signal when both the first op amp circuit and the auxiliary operational amplifier are turned on.
  • the second ramp signal is used to control the level value of the second level to be changed from the third level value to the fourth level value, thereby controlling the resistance of the second ramp resistor to change from high to low.
  • the voltage of the output node ramps from low to high until the voltage of the output node approaches the second voltage value, the third level value being less than the fourth level value.
  • the voltage of the output node can be gradually changed according to the gradient of the resistance of the second ramp resistor.
  • the gradation of the level value of the second level is controlled by the second ramp signal, so that the second level can be gradually gradual, and no sudden change occurs, since the resistance of the second ramp resistor follows the second
  • the gradation of the level changes from high to low, so that the voltage of the output node follows the gradual change of the resistance of the second ramp resistor from low to high, so that the output node is established during the operation of the op amp path.
  • the voltage rises slowly and eventually tends to the second voltage value, which significantly reduces the generation of POP noise compared to the existing mechanism.
  • the third resistance is greater than or equal to the second resistance.
  • the ramp signal controller further includes a pulse signal generation circuit and a ramp signal control logic circuit, the ramp signal controller further comprising at least one of a first ramp current source and a second ramp current source.
  • the pulse signal generating circuit is connected in series with the ramp signal control logic circuit, and the first ramp current source and the second ramp current source are connected in parallel.
  • the pulse signal generating circuit is configured to generate a pulse signal from the input clock signal and input the pulse signal to the ramp signal control logic circuit.
  • the ramp signal control logic circuit is configured to receive a pulse signal input from the pulse signal generating circuit, generate a ramp signal according to the input pulse signal, and input the generated ramp signal into a ramp current source, the ramp signal
  • the first ramp signal or the second ramp signal is included, and the ramp current source includes the first ramp current source or the second ramp current source.
  • a slack slope signal can be generated with a smaller capacitor, which can save cost and not reduce the entire circuit. Integration.
  • the step size and slope of the ramp signal can also be flexibly adjusted by adjusting the frequency of the clock signal, the width of the pulse signal, the output current of the ramp current source, and the magnitude of the capacitance to smooth the ramping of the ramp signal.
  • the ramp signal controller when the ramp signal controller includes a first ramp current source and a second ramp current source, the ramp signal controller further includes a single pole double throw switch, the single pole double throw switch for:
  • the first ramp current source is connected when a ramp signal generated by the ramp signal control logic circuit is identical or similar to a characteristic of the first ramp signal.
  • the second ramp current source is connected.
  • a closed-loop feedback network will form during the operation of the op amp path, and oscillations may occur in the feedback network.
  • the oscillation will produce sudden and sharp POP noise. Therefore, in order to further eliminate the POP noise caused by the oscillation during the operation of the op amp path, the present application can also add a compensation circuit to avoid the POP noise caused by the oscillating signal in the feedback network.
  • a loop compensation circuit may also be disposed in the audio processing circuit, and the loop compensation circuit is configured to:
  • the oscillating signal in the closed loop is suppressed by the sinking current loop, on the one hand, the POP noise generated by the oscillating signal is suppressed, and on the other hand, the stability of the closed loop system gain is maintained.
  • the cascaded op amp circuit is a cascade op amp
  • the cascade op amp circuit includes at least one of the second op amp circuits
  • at least one of the second op amp circuits includes the A secondary operational amplifier and the ramp signal controller.
  • This application is not limited to whether each of the operational amplifier circuits is equipped with a secondary operational amplifier and a variable resistance circuit. Any operational amplifier circuit can be equipped with a auxiliary operational amplifier and a variable resistance circuit, so that the offset voltage can be blocked from being transmitted to the output node, and the application does not limit the level of operation of the auxiliary operational amplifier and the variable resistance circuit.
  • auxiliary operational amplifier and the variable resistance circuit may be provided only at the non-ideal device that has a large influence on the POP noise. If the offset voltage of the main operational amplifier in the second operational amplifier circuit is higher than a preset threshold, then A main operational amplifier with an offset voltage above a predetermined threshold can be provided with a secondary operational amplifier and a variable resistance circuit.
  • the auxiliary operational amplifier and the variable resistance circuit may be provided for these non-ideal devices in whole or in part, which is not limited in this application.
  • a second aspect of the present application provides a terminal device comprising an audio load and the audio processing circuit of the first aspect described above.
  • a further aspect of the present application provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform the operations of any of the above aspects The operations performed by the audio processing circuitry.
  • a further aspect of the present application provides a computer program product comprising computer software instructions executable by a processing circuit to effect execution of the audio processing circuit of any of the above aspects Operation.
  • the operational amplifier circuit in the audio circuit includes a first operational amplifier circuit and a second operational amplifier circuit, and the first operational amplifier circuit is the second operational amplifier circuit.
  • the operational amplifier outputs a preamplifier, and the second operational amplifier circuit, which is the output of the operational amplifier of the second stage, pulls down the output node in the pull-down circuit, and the first operational amplifier circuit and the second operational amplifier circuit are both turned on, Controlling the output resistance of the second operational amplifier circuit from high to low to control the voltage of the output node to follow the gradual change of the output resistance, from low to high gradual, so that the voltage of the output node during the operation of the op amp path It can be slowly incremented to reduce the generation of POP noise, and can also transmit the offset voltage of the first operational amplifier circuit as the front stage operational amplifier to the load. It can be seen that the audio circuit structure of the present application can effectively suppress the operation. The POP noise during the path establishment process.
  • FIG. 1 is a schematic structural diagram of an audio circuit in an existing mechanism
  • FIG. 2 is a schematic structural diagram of an audio processing circuit according to an embodiment of the present invention.
  • FIG. 3 is another schematic structural diagram of an audio processing circuit according to an embodiment of the present invention.
  • 4a is a schematic structural diagram of a second operational amplifier circuit according to an embodiment of the present invention.
  • 4b is a schematic diagram showing a curve of a second ramp signal according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a ramp signal controller according to an embodiment of the present invention.
  • FIG. 6 is another schematic structural diagram of an audio processing circuit according to an embodiment of the present invention.
  • FIG. 7 is another schematic structural diagram of an audio processing circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing timing changes of voltages of respective nodes in an audio processing circuit when an offset voltage is negative according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram showing timing changes of voltages of respective nodes in an audio processing circuit when the offset voltage is positive in the embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing voltage changes of each node in an audio processing circuit for controlling a DC output structure by RAMP according to an embodiment of the present invention
  • FIG. 11 is a schematic diagram showing voltage changes of respective nodes in an audio processing circuit for controlling an AC coupling structure by RAMP according to an embodiment of the present invention
  • FIG. 12 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • circuits may be combined or integrated into another system, or some features may be ignored or not executed, and in addition, displayed or discussed between each other
  • the coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection between the circuits may be electrical or the like, which is not limited in the present application.
  • the circuit or sub-circuit described as the separate component may or may not be physically separated, may or may not be a physical circuit, or may be distributed to a plurality of circuit circuits, and some or all of them may be selected according to actual needs.
  • the circuit implements the objectives of the present application.
  • the present application provides an audio processing circuit and a terminal device, which can be used for an audio circuit, such as an audio accessory such as a headset or a mobile phone, or a terminal device having an audio playback function.
  • an audio circuit such as an audio accessory such as a headset or a mobile phone, or a terminal device having an audio playback function.
  • the existing mechanism as shown in Figure 1, before the op amp is turned on, it exhibits high resistance. Because of the common mode voltage (English name: Common Mode Voltage, VCM) switch and load, the output (OUT) node is VCM (for AC coupling) or GND (for DC output).
  • VCM Common Mode Voltage
  • VCM+Vos Vos is the full-path offset voltage, also called offset
  • DC output The output will drive the OUT node to GND+Vos.
  • the op amp itself has a bias Vos_op, and the op amp's preamplifier also passes a preamp bias Vos_front to the op amp, and the op amp is established, the op amp's preamp There will be a level difference between the discharge and the OUT node (VACdif for AC coupling and VDCdif for DC output).
  • the feedback coefficient (Rfb_p/Rin_p) and the feedback coefficient (Rfb_n/Rin_n) also differ by ⁇ , then, finally
  • the output voltage offset of the OUT node is approximately VACdif* ⁇ or VDCdif* ⁇ .
  • the present application mainly provides one of the following circuits:
  • An auxiliary op amp circuit is connected in parallel only between the op amp circuit of the last stage of the cascade op amp (ie, the op amp circuit electrically connected to the OUT node).
  • An auxiliary operational amplifier circuit is connected in parallel at both ends of the operational amplifier circuit of each stage of the cascaded operational amplifier.
  • Only one auxiliary operational amplifier circuit is connected in parallel at both ends of the first stage operational amplifier circuit in the cascaded operational amplifier.
  • the auxiliary operational amplifier circuits of the above four types of circuits all include a variable resistance circuit. After adopting any of the above four types of circuits, only the operational amplifier circuit of the auxiliary operational amplifier circuit is turned on in the initial stage of the operation of the operational amplifier path. The preamplifier circuit and the auxiliary op amp circuit are turned on. In the initial state of the op amp path, the resistance of the variable resistor in the auxiliary op amp circuit is externally reflected as high impedance, so that the offset voltage of the op amp circuit in which it is located It will not be passed to the OUT node, so it will not drive the OUT node to supply voltage to the audio load. When the op amp path is established, the entire cascaded op amp will be cut off from the OUT node.
  • variable resistance circuit in each auxiliary op amp circuit is externally reflected as a slow increase or decrease in resistance, showing a change in slope type (including uphill or downhill), so that the entire auxiliary operation
  • the output voltage of the discharge circuit also rises slowly, gradually reaching the offset voltage to drive the OUT node.
  • the operational amplifier circuit connected in parallel with the auxiliary operational amplifier circuit can be turned on, so that the entire operational path is completed.
  • the following provides an example of an audio processing circuit, which can be used for AC (English full name: Alternative current, AC abbreviation: AC) coupling scene and DC (English full name: Direct current, English abbreviation: DC) Output scene.
  • the circuit can include a cascaded op amp circuit, an output node, and a pull down circuit.
  • the cascade operational amplifier circuit includes a first operational amplifier circuit and a second operational amplifier circuit, wherein the first operational amplifier circuit is a front stage operational amplifier of the second operational amplifier circuit, and the first operational amplifier circuit A main operational amplifier and a secondary operational amplifier are included, and the primary operational amplifier and the secondary operational amplifier are connected in parallel.
  • the cascaded op amp circuit is used to amplify the input voltage and output the amplified voltage to the output node. After the first operational amplifier circuit amplifies the voltage input thereto, the amplified voltage is input to the second operational amplifier circuit, so that the second operational amplifier circuit processes the voltage input thereto, and then outputs the voltage to the second operational amplifier circuit. The output node.
  • the pull-down circuit is configured to pull down the voltage of the output node after the first operational amplifier circuit is turned on, wherein the pull-down refers to pulling the voltage of the output node from high (H) to low (L) ).
  • the second operational amplifier circuit is configured to control a voltage of the auxiliary operational amplifier to change from a low to a high voltage after the auxiliary operational amplifier is turned on, thereby controlling a voltage of the output node to follow a gradual change of the output resistance, from a low a high gradation; the main operational amplifier is turned on when the voltage gain of the auxiliary operational amplifier reaches a preset gain.
  • the voltage of the output node from the low to the high gradation here refers to the absolute value of the voltage of the output node, and is not limited to positive or negative.
  • the second operational amplifier circuit as the output of the rear operational amplifier pulls down the output node in the pull-down circuit, and after the first operational amplifier circuit and the second operational amplifier circuit are both turned on, Controlling the output resistance of the second operational amplifier circuit from high to low to control the voltage of the output node to follow the gradual change of the output resistance, from low to high gradual, so that the voltage of the output node during the operation of the op amp path It can be slowly incremented to reduce the generation of POP noise, and can also transmit the offset voltage of the first operational amplifier circuit as the front stage operational amplifier to the load. It can be seen that the audio circuit structure of the present application can effectively suppress the operation. The POP noise during the path establishment process.
  • the cascaded op amp circuit may include at least one of the second op amp circuits.
  • the control can be controlled by controlling the output resistance of the first operational amplifier circuit from high to low.
  • at least one of the second operational amplifier circuits may further include: a variable resistance circuit, the main operational amplifier being connected in parallel with the first series circuit, the first series circuit comprising: the auxiliary operational amplifiers connected in series The variable resistance circuit.
  • variable resistance circuit can be used to control the output resistance of the variable resistor to change from high to low, thereby controlling the voltage gain of the auxiliary operational amplifier to change from low to high, thereby controlling the voltage of the output node from low
  • the highest gradation causes the gain of the cascaded op amp circuit to fade from low to high.
  • the voltage of the output node may be graded following a gradual change in the output resistance of the variable resistor.
  • the main operational amplifier is turned on, so that an operational path of the first operational amplifier circuit and the main operational amplifier to the output node is established.
  • the main operational amplifier and the auxiliary operational amplifier share the same pre-amplifier (ie, the first operational amplifier circuit) and share the same external feedback network, thus ensuring the offset of the path through the main operational amplifier and the auxiliary operational amplifier.
  • the same voltage offset value also ensures that the feedback coefficients of the main and auxiliary op amps are the same.
  • the present application does not limit whether each of the operational amplifier circuits is equipped with a secondary operational amplifier and a variable resistance circuit.
  • Any operational amplifier circuit can be equipped with a auxiliary operational amplifier and a variable resistance circuit, so that the offset voltage of the operational amplifier circuit can be blocked from being transmitted to the output node, and the present application does not limit the setting of the auxiliary operational amplifier and the variable resistance circuit.
  • Which stage of the op amp circuit, or which stage of the op amp circuit For a specific circuit circuit diagram, reference may be made to a structure shown in FIG. 3, and the circuit circuit may be modified or modified based on FIG. 3, which is not limited in this application.
  • the gradation of the output resistance of the variable resistor may be controlled by inputting a signal
  • the variable resistance circuit may include a variable resistor and a ramp signal controller (as shown in FIG. 4a).
  • the ramp signal controller can control the output resistance of the variable resistor
  • the ramp signal controller can also be considered to control the resistance change of the variable resistor.
  • the stress signal controller in the present application may directly generate a ramp signal to control a resistance change of the variable resistor, or may control a resistance change of the variable resistor based on a control signal transmitted from another circuit, and the specific structure is The application is not limited.
  • the ramp signal controller needs to control the gradation of the output resistance of the variable resistor according to the positive/negative of the offset voltage.
  • the offset voltage is positive
  • the ramp signal controller is configured to control a resistance of the variable resistor to be changed from a first resistance value to a second resistance value after the first operational amplifier circuit and the auxiliary operational amplifier are both turned on, so that the output is The voltage of the node follows the gradual value of the resistance of the variable resistor until the voltage of the output node approaches the first voltage value.
  • the first resistance value may be greater than the second resistance value, and the first resistance value may be set to a high resistance, so that the path between the operational amplifier circuit and the output node is directly cut off at the initial stage of the operation of the op amp path; or It may simply be set such that the output voltage of the op amp circuit is unable to drive the output node during the op amp path setup process.
  • the first voltage value refers to a positive voltage value
  • the resistance change of the variable resistor characterizes a change in output resistance of the first series circuit
  • the offset voltage of the cascaded operational amplifier circuit refers to the The output voltage of the cascaded op amp circuit is offset offset.
  • the first voltage value may be determined by an offset voltage of the operational amplifier circuit before the second operational amplifier circuit, and the offset voltage of the operational amplifier circuit before the second operational amplifier circuit may include: an offset voltage of the first operational amplifier circuit, or The offset voltage of the operational amplifier circuit before the first operational amplifier circuit is not limited in this application.
  • the first voltage value may be calculated according to a parameter such as a feedback coefficient.
  • the main operational amplifier is configured to be turned on after the ramp signal controller controls that the voltage of the output node approaches the first voltage value, so that an output voltage of the cascade op amp circuit drives the Output node. Since the output node has reached the final offset voltage before the main operational amplifier is turned on, turning on the main operational amplifier will not cause a sudden change in the voltage state of the output node. Therefore, the voltage at the output node can be ramped. After slowly reaching the preset offset and then turning on the main operational amplifier, the POP noise generated by the sudden change of the output node voltage can be effectively reduced.
  • the variable resistance circuit includes a ramp signal controller, and the ramp signal controller is configured to:
  • the second voltage value may be determined by an offset voltage of the operational amplifier circuit before the second operational amplifier circuit, and the offset voltage of the operational amplifier circuit before the second operational amplifier circuit may include: an offset voltage of the first operational amplifier circuit, or The offset voltage of the operational amplifier circuit before the first operational amplifier circuit is not limited in this application.
  • the second voltage value can also be calculated according to parameters such as a feedback coefficient.
  • the main operational amplifier is configured to be turned on after the ramp signal controller controls that the voltage of the output node approaches the second voltage value, so that the output voltage of the cascade operational amplifier circuit is driven.
  • the output node is configured to be turned on after the ramp signal controller controls that the voltage of the output node approaches the second voltage value, so that the output voltage of the cascade operational amplifier circuit is driven.
  • the ramp signal controller in the present application may also be a separate external circuit, or may be integrated in the variable resistance circuit, and the ramp signal for driving the variable resistance of the variable resistor may be provided by the ramp signal controller. It may be provided by other circuits than the variable resistance circuit, and is not limited herein.
  • the auxiliary op amp and the variable resistor circuit can be used to slowly establish the offset voltage of the full path of the op amp feedback network, thereby slowly establishing the op amp path until the op amp path is completely established, so that the other circuits of the channel can be released.
  • the offset voltage is constrained.
  • the variable resistor may include at least one of a first ramp resistor and a second ramp resistor, and the first ramp resistor or the second ramp resistor is controlled by the ramp signal controller.
  • the first ramp resistance means that the resistance of the ramp resistor decreases as the voltage across the ramp resistor decreases, and increases as the voltage across the ramp resistor increases; the second ramp resistor refers to the ramp resistor. The resistance decreases as the voltage across the ramp resistor increases and decreases as the voltage across the ramp resistor decreases.
  • the ramp signal controller can switch between the first ramp resistor and the second ramp resistor, and can simultaneously control the resistance of the first ramp resistor and the second ramp resistor
  • the value changes and provides a corresponding ramp signal to control the gradual change of the variable resistor to accommodate multiple variations of the circuit.
  • an output level of the first ramp resistor is a first level
  • an output level of the second ramp resistor is a second level.
  • the variable resistance circuit may be provided only for the negative offset voltage, or the variable resistance circuit may be provided only for the positive offset voltage, and the variable resistance circuit for the negative offset voltage and the positive offset voltage may be simultaneously provided.
  • the first ramp resistor and/or the second ramp resistor are provided in the circuit to suppress POP noise caused by the negative/positive offset voltage, respectively.
  • the variable resistor in the variable resistance circuit can be set as a first ramp resistance whose resistance value is gradually ramped, and the first ramp resistor can be controlled by the ramp signal controller The gradient of the resistance.
  • the ramp signal controller is specifically configured to: after the first operational amplifier circuit and the auxiliary operational amplifier are turned on, control a resistance of the second ramp resistor to be not less than the first resistance value, To intercept the path between the cascaded op amp circuit and the output node. For example, the resistance of the second ramp resistor is controlled to be high impedance.
  • variable resistor in the variable resistance circuit can be set to a second ramp resistance that is negatively graded, and the second ramp resistor can be controlled by the ramp signal controller.
  • the gradient of the resistance is specifically configured to control, after the first operational amplifier circuit and the auxiliary operational amplifier are turned on, that the resistance of the first ramp resistor is not less than the first resistance value, To intercept the path between the cascaded op amp circuit and the output node.
  • the resistance of the first ramp resistor is controlled to be high impedance, so that the op amp circuit and the output node can be directly cut off, and the voltage of the output node is not abruptly changed, so that the audio load pair of the POP noise transmission can be effectively avoided. Interference from the human ear.
  • a negative offset voltage or a positive offset voltage may be generated in stages, so as to comprehensively solve the problem of positive/negative offset voltage
  • the present application can also simultaneously set a variable resistor for the negative offset voltage and the positive offset voltage, that is,
  • the variable resistor circuit is set to a first ramp resistor whose resistance value is gradually ramped, and the variable resistor is set to a second ramp resistor whose resistance is negatively graded, and then one of the ramp resistors is gated during the operation of the op amp path (
  • the first ramp resistor or the second ramp resistor is strobed, and the ramp of the first ramp resistor/second ramp resistor is controlled by the ramp signal controller; or, the first ramp resistor and the second gate are simultaneously strobed;
  • the ramp resistance is controlled by a ramp signal controller to control the gradient of the resistance of the first ramp resistor/second ramp resistor.
  • the ramp signal controller is specifically configured to control a gradation value of an output resistance of the variable resistor by controlling a gradation value of the first level or controlling a gradation value of the second level.
  • the ramp signal controller includes the first ramp resistor, it can solve the POP noise generated when the offset voltage is positive during the process of establishing the op amp path.
  • the ramp signal controller may be configured to: after the first operational amplifier circuit and the auxiliary operational amplifier are turned on, control a resistance of the first ramp resistor to be not less than the first resistance value, so that The output voltage of the cascaded op amp circuit is unable to drive the output node and even intercept the path between the cascaded op amp circuit and the output node.
  • the ramp signal controller may provide a first ramp signal to the variable resistor circuit when both the first op amp circuit and the second op amp circuit are turned on.
  • the first ramp signal is used to control the level value of the first level to be changed from the first level value to the second level value, thereby controlling the resistance of the first ramp resistor to change from high to low.
  • the voltage of the output node follows a gradual change in the resistance of the first ramp resistor from low to high until the voltage of the output node approaches the first voltage value.
  • the first voltage value refers to a positive voltage value
  • the resistance change of the variable resistor characterizes a change in output resistance of the first series circuit.
  • the first level value is greater than the second level value, that is, the first ramp signal can control the slow decrease of the level value of the first level, thereby controlling the slow decrease of the resistance of the first ramp resistor.
  • the gradation of the level value of the first level is controlled by the first ramp signal, so that the first level can be gradually gradual, and no sudden change occurs, since the resistance of the first ramp resistor follows the first
  • the gradation of the level changes from high to low, so that the voltage of the output node follows the gradual change of the resistance of the first ramp resistor from low to high, so that the output node is established during the operation of the op amp path.
  • the voltage rises slowly and eventually tends to a preset bias (such as a first voltage value or a second voltage value), which significantly reduces the generation of POP noise compared to existing mechanisms.
  • the cascaded operational amplifier after the voltage of the output node follows the gradual change of the resistance of the first ramp resistor from low to high, when the resistance of the first ramp resistor is lower than the third resistance.
  • An output voltage of the circuit can drive the output node, the third resistance being greater than or equal to the second resistance. It can be seen that the gradation of the level value of the first level can make the output node slowly reach the output voltage, so that the entire op amp path is slowly established, and the preparation for the subsequent main operational amplifier is started.
  • the output voltage of the cascaded operational amplifier circuit increases, the voltage of the output node is gradually increased.
  • the output node can output the cascaded operational amplifier circuit. Passed to the audio load that is electrically connected to it, the op amp feedback loop is turned on, which in turn drives the audio load to work. Subsequently, the resistance of the first ramp resistor continues to ramp from the third resistance to the second resistance.
  • the output voltage of the operational amplifier circuit if the output voltage of the operational amplifier circuit is low in the initial stage of the operation of the operational amplifier, if the output voltage is lower than the lowest level of the output node, the output voltage of the cascaded operational amplifier circuit cannot drive the output.
  • the node works.
  • the offset voltage of the op amp circuits at the beginning of the op amp path is not instantaneously transmitted to the audio load behind the output node, but is truncated or sharply reduced at the output node.
  • the cascaded operational amplifier circuit exhibits a high resistance state at the initial stage of the operation of the operational amplifier path, that is, in the initial state in which the output resistance of the variable resistance is changed following the change of the first ramp signal, the cascaded operational amplifier
  • the path between the circuit and the output node is disconnected, and the offset voltage of the cascaded operational amplifier circuit is not transmitted to the output node, and is not transmitted to the audio load connected to the output node, thus effectively avoiding
  • the op amp path establishes the POP noise generation of the device.
  • the ramp signal controller includes the second ramp resistor, it can solve the POP noise generated when the offset voltage is negative during the process of establishing the op amp path.
  • the ramp signal controller may be configured to: after the first operational amplifier circuit and the auxiliary operational amplifier are turned on, control the second ramp resistance not less than the first resistance value, so that the level The output voltage of the intermodal operational amplifier circuit is unable to drive the output node and even intercept the path between the cascaded operational amplifier circuit and the output node.
  • the ramp signal controller may provide a second ramp signal to the second ramp resistor when both the first op amp circuit and the auxiliary operational amplifier are turned on.
  • the second ramp signal is used to control the level value of the second level to be changed from the third level value to the fourth level value, thereby controlling the resistance of the second ramp resistor to change from high to low.
  • the voltage of the output node follows a gradual change in the resistance of the second ramp resistor from low to high until the voltage of the output node tends to the second voltage value.
  • the third level value is smaller than the fourth level value, that is, the second ramp signal can control the level value of the second level to rise slowly, thereby controlling the resistance of the second ramp resistor to be slow. reduce.
  • the first resistance value is greater than the second resistance value, and the second voltage value refers to a negative polarity voltage value, and the resistance value change of the variable resistor characterizes a change in output resistance of the first series circuit.
  • the resistance value of the second ramp resistor is controlled to be high resistance when the level value of the second level is gradually changed, the resistance of the second ramp resistor is following the In the initial state of the change of the two ramp signals, the path between the cascaded operational amplifier circuit and the output node is disconnected, and the operational amplifier circuit and the output node can be directly cut off, and the offset voltage of the operational amplifier circuit can be completely eliminated. Passed to the output node.
  • the gradation of the level value of the second level is controlled by the second ramp signal, so that the second level can be gradually gradual, and no sudden change occurs, since the resistance of the second ramp resistor follows the second
  • the gradation of the level changes from high to low, so that the voltage of the output node follows the gradual change of the resistance of the second ramp resistor from low to high, so that the output node is established during the operation of the op amp path.
  • the voltage rises slowly and eventually tends to the second voltage value, which significantly reduces the generation of POP noise compared to the existing mechanism.
  • the output node is driven, and the path between the cascaded operational amplifier circuit and the output node through.
  • the third resistance value is greater than or equal to the second resistance value, and then the resistance value of the second ramp resistance continues to gradually change from the third resistance value to the second resistance value.
  • the ramp signal controller further includes a pulse signal generating circuit and a ramp signal control logic circuit, wherein the ramp signal controller further includes a first ramp current source and a second ramp current source At least one of them.
  • pulse signal generating circuit is connected in series with the ramp signal control logic circuit.
  • the pulse signal generating circuit is configured to generate a pulse signal from the input clock signal and input the pulse signal to the ramp signal control logic circuit.
  • the ramp signal control logic circuit is configured to receive a pulse signal input from the pulse signal generating circuit, generate a ramp signal according to the input pulse signal, and input the generated ramp signal into a ramp current source, the ramp signal
  • the first ramp signal or the second ramp signal is included, and the ramp current source includes the first ramp current source or the second ramp current source.
  • the first ramp current source may be connected in parallel with the second ramp current source, and when the offset voltage is positive, the first The ramp signal supplies current to the first ramp current source; when the offset voltage is negative, the first ramp signal is generated to supply current to the second ramp current source, and the manner of switching between the first current source and the second current source is specifically The single-pole double-throw switch, the two-way controllable switch or the enable signal is used to control the gating, etc., and the specific switching manner is not limited in this application.
  • the ramp signal controller can include a single pole double throw switch, the single pole double throw switch for:
  • the first ramp current source is connected when a ramp signal generated by the ramp signal control logic circuit is identical or similar to a characteristic of the first ramp signal.
  • the second ramp current source is connected.
  • a slope signal with a gentle slope can be generated with a small capacitance, which can save cost and reduce the integration degree of the entire circuit.
  • the slope signal can also be flexibly adjusted by adjusting the frequency of the clock signal (English full name: clock, English abbreviation: CLK), the width of the pulse signal, the output current Iramp of the ramp current source, and the size of the capacitor.
  • CLK clock signal
  • the step size and slope are used to smooth the gradient of the ramp signal.
  • the power supply can be optimized by segmenting the slope of the ramp signal. time. Specifically, it is possible to speed up the ramp signal in the phase that affects Vos insensitivity and slow down the ramp signal speed in the phase that affects Vos sensitivity.
  • the first ramp signal or the second ramp signal may be composed of a plurality of segmentation functions, and the slope of each segment function in the micro is almost the same, so that the variation is relatively smooth. It can be controlled by the length of the switching time.
  • the slope signal is 1pmA, the shorter time can be set, and the next hop is set to 1umA, which can be set longer. This can smooth the sudden change of the ramp signal to reduce the sudden change of voltage.
  • the resulting POP noise can be represented by the curve shown in Figure 4b.
  • a narrow pulse period signal is generated by the clock to charge the capacitor in the variable resistance circuit, thereby generating a ramp signal that is sufficiently slow to climb (ie, RAMP_P/ RAMP_N).
  • RAMP-N and RAMP-P are respectively connected to a ramp signal, and when POP noise suppression is started, one of them can be electrically connected.
  • a closed-loop feedback network is formed during the process of establishing an op amp path, and oscillation may occur in the feedback network, and the oscillation may generate sudden and sharp POP noise. Therefore, in order to further eliminate the POP noise caused by the oscillation during the operation of the op amp path, the present application can also add a compensation circuit to avoid the POP noise caused by the oscillating signal in the feedback network.
  • a loop compensation circuit (English definition: (compensation module) may also be provided in the above audio processing circuit, which may also be used to maintain the stability of the closed-loop system gain. The loop compensation circuit is used to:
  • the voltage for outputting the output node in the op amp path in which the auxiliary operational amplifier is located suppresses the oscillating signal in the closed loop by the current sinking cycle during the gradual change of the output voltage from low to high, wherein the output voltage refers to the The voltage used to drive the output node in the op amp path where the auxiliary operational amplifier is located, that is, the output voltage of the entire second operational amplifier circuit.
  • the main operational amplifier with the offset voltage higher than the preset threshold may be equipped with a secondary operational amplifier and a variable resistance circuit in the audio processing.
  • the circuit there are many op amp circuits similar to the main operational amplifier in the second operational amplifier circuit.
  • an audio circuit structure as shown in FIG. 6 is used when the entire operational amplifier circuit is a current-type digital-to-analog conversion circuit (English name: digital-analog converter, English abbreviation: DAC).
  • DAC digital-analog converter
  • the inverter circuit (English full name: invert voltage, English abbreviation: INV), and then use any of the above-mentioned POPs as shown in Figure 2 - Figure 5 and Figure 7 - Figure 11 below.
  • the noise suppression process can be turned on to turn on the main operational amplifier, and finally the OUT node in Figure 6 is driven, and will not be described here.
  • the current type DAC can control the current switch pair by input data, and direct current to the output terminal or the complementary output terminal.
  • POP noise is also generated during the power-off process of the audio processing circuit, and the suppression process of the POP noise may still pass the first operational amplifier circuit and the main device described in the foregoing embodiments.
  • the operational amplifier, the auxiliary operational amplifier and the variable resistance circuit are cooperatively completed, and the entire POP suppression process is an inverse process of the POP suppression process in the process of establishing the operational path, for example, controlling the output resistance of the variable resistor from low to high, so that the output The voltage of the node changes from low to high, or from high to low.
  • the shared op amp preamp (OP_MAIN), which is controlled by PD_HP.
  • the main output stage (OUTSTAGE_M) at work which is controlled by PD_MAIN.
  • the auxiliary output stage (OUTSTAGE_A), which is controlled by PD_AUX, is used to suppress POP noise during the op amp path setup process, in parallel with the main output stage (OUTSTAGE_M).
  • the OUT node is the node of the entire cascaded op amp and audio load, that is, the output node for driving the audio load operation.
  • the audio processing circuit of Figure 7 includes two input voltages (including VIN_N and VIN_P), two pairs of input resistors (including Rin_N and Rin_P), and two pairs of feedback resistors (including Rfb_N and Rfb_P). Among them, Rin_N and Rfb_N, and Rin_P and Rfb_P respectively constitute the feedback network of the op amp.
  • the output stage cascaded operational amplifier may also include a compensation circuit to ensure stability in the POP noise suppression process.
  • the loop transfer function refers to the transfer function of Vos about the feedback network (including the feedback network composed of Rin_N and Rfb_N, and the feedback network composed of Rin_P and Rfb_P).
  • a ramp voltage generator (RAMP_GEN) that produces a slowly varying ramp voltage signal that causes the loop to build slowly.
  • the RAMP_GEN in the present application may be a circuit that is externally connected during the operation of the op amp path, and is detachably electrically connected to the auxiliary output stage (OUTSTAGE_A). It may also be a circuit module integrated in the above-mentioned output stage cascade operation, which is not limited in this application. The following describes the POP noise suppression process implemented based on the circuit structure of FIG. 7:
  • the output signal of RAMP_GEN is configured to generate a RAMP signal for controlling the level of RAMP_P by its internal sequential circuit. For example, it can be generated by the directional ramp circuit (English full name: directional ramp, RAMP_DIR) in FIG. 7, and RAMP_DIR can generate orientation. A ramp signal through which the directivity of the signal can be changed.
  • OP_MAIN Since OP_MAIN is a non-ideal device, OP_MAIN generates POP noise.
  • RAMP_GEN controls the output voltage of RAMP_P to be at a high level H
  • the MOS transistor variable resistor controlled by RAMP_P is high impedance, so the op amp at this time does not drive the OUT node.
  • the POP noise generated during the process of establishing the working point by RAMP_GEN is blocked by the MOS transistor variable resistor controlled by RAMP_P, so the POP noise generated by the preamplifier stage is not transmitted to the OUT node, and the voltage of the OUT node is not A jump occurs, and the audio load connected to the OUT node does not generate POP noise.
  • RAMP_DIR in RAMP_GEN changes direction, causing the voltage of RAMP_P to slowly decrease.
  • the resistance of the variable resistor controlled by RAMP follows the voltage of RAMP_P and slowly decreases.
  • VOUT vos*(1+Rfb/Rin). Since the voltage of RAMP_P slowly decreases, VOUT will slowly ramp from GND to the final output voltage offset until the variable resistor is reduced enough. Small, the op amp feedback loop is turned on, and finally the voltage division of the audio load is slowly increased, and finally driven, correspondingly, the OUT node will reach the final output voltage offset value.
  • variable resistor is gradually reduced, the OUTSTAGE_A gain is gradually increased, and finally the OUTSTAGE_A is established to the steady state, and finally the RAMP_P reaches the low level L, and the variable resistance of the RAMP-GEN is minimized, and the Loop Gain reaches the maximum at this time.
  • the OUT node reaches the final output voltage offset value.
  • OUTSTAGE_A and OUTSTAGE_M have a common op amp pre-stage (OP_MAIN), the op amp path offsets of both OUTSTAGE_A and OUTSTAGE_M are the same.
  • O_MAIN op amp pre-stage
  • the output signal of RAMP_GEN is configured, and a RAMP signal for controlling the level of RAMP_N is generated by its internal sequential circuit, that is, generated by RAMP_DIR in FIG.
  • the RAMP_DIR is changed in direction, so that the voltage of RAMP_N rises slowly, and the resistance of the variable resistor controlled by RAMP follows the voltage of RAMP_N to rise slowly and slowly decreases.
  • VOUT vos*(1+Rfb/Rin)
  • VOUT will slowly ramp from GND to the final output voltage offset until the variable resistor is reduced sufficiently small that the op amp feedback loop Turning on, eventually making the voltage division of the audio load rise slowly, and finally being driven, correspondingly, the OUT node reaches the final output voltage offset value.
  • variable resistor is gradually reduced, the OUTSTAGE_A gain is gradually increased, and finally the OUTSTAGE_A is established to the steady state. Finally, the RAMP_N reaches the high level H, and the variable resistance of the RAMP-GEN is minimized, and the Loop Gain reaches the maximum at this time. The OUT node reaches the final output voltage offset value.
  • OUTSTAGE_A and OUTSTAGE_M have a common op amp pre-stage (OP_MAIN), the op amp path offsets of both OUTSTAGE_A and OUTSTAGE_M are also the same, and after opening OUTSTAGE_M, the opening of the OUTSTAGE_M path will not generate new POP noise. .
  • FIG. 11 is a POP noise suppression circuit diagram of an AC-coupled audio circuit structure.
  • AC coupling refer to the circuit structure diagram shown in FIG. 11, specifically for the POP noise suppression analysis process in the process of establishing an op amp path. Narration.
  • the first operational amplifier circuit, the second operational amplifier circuit, the main operational amplifier, the auxiliary operational amplifier, the variable resistance circuit, the ramp signal controller, the ramp signal, the offset voltage, and the like in the embodiments corresponding to FIGS. 2-11 The same applies to the embodiment corresponding to FIG. 12 in the present application, and the subsequent similarities are not described again.
  • the present application further provides a terminal device, which may include an audio load and an audio processing circuit in the embodiment corresponding to FIG. 2 to FIG. 11 .
  • the audio processing circuit provides a driving voltage for the audio load, and the specific structure may refer to the figure. 12.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the circuit is only a logical function division.
  • there may be another division manner for example, multiple circuits or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or circuit, and may be in an electrical, mechanical or other form.
  • circuits described as separate components may or may not be physically separate, and the components displayed as circuits may or may not be physical circuits, that is, may be located in one place or may be distributed over a plurality of network circuits. Some or all of the circuits may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional circuit in each embodiment of the present application may be integrated into one processing circuit, or each circuit may exist physically separately, or two or more circuits may be integrated into one circuit.
  • the above integrated circuit can be implemented in the form of hardware or in the form of a software function circuit.
  • the integrated circuitry, if implemented in the form of a software functional circuit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, service circuit or data
  • the center transmits to another website site, computer, service circuit, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be stored by a computer or a data storage device such as a service circuit, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Otolaryngology (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

一种音频处理电路及终端设备，所述电路包括级联运放电路、输出节点和下拉电路，级联运放电路用于对输入电压进行放大，并将放大后的电压输出至输出节点。级联运放电路包括第一运放电路和第二运放电路，第一运放电路为第二运放电路的前级运放；第一运放电路包括并联的主运算放大器和辅运算放大器；下拉电路的一端耦合至输出节点，下拉电路的另一端接地或共模电压模块，下拉电路用于当第一运放电路开启后，下拉输出节点的电压；第二运放电路用于开启辅运算放大器后，控制辅运算放大器的电压增益从低至高渐变，从而控制输出节点的电压跟随输出电阻的渐变，从低至高渐变。通过采用本方案提供的电路，能够有效的抑制运放通路建立过程中的POP噪声。

Description

一种音频处理电路及终端设备
本申请要求于2017年6月23日提交中国专利局、申请号为201710487751.4、发明名称为“一种音频处理电路及终端设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，特别涉及一种音频处理电路及终端设备。
背景技术
在音频电路上电后，运放通路建立过程会涉及到运放工作点的建立和运放通路的建立。由于音频电路中的各运放电路并非为理想器件，因此各级运放电路都可能存在失调电压。前级运放电路产生的电压偏置会传递到后级运放电路，前级运放电路的输出电压与理想电压之间就会存在电压差异，这样会导致运放工作点建立过程或者运放通路建立过程中输出节点产生失调电压，最后导致输出节点的瞬态电压波形异常，当该异常的电压从输出节点传输到音频负载后，音频负载则会产生POP噪声。由于运放工作点建立过程中产生的POP噪声的波形在音频范围内为较窄的尖脉冲，所以，该POP噪音会对人耳产生较强的电流冲击，容易造成人耳不适。
发明内容
本申请提供了一种音频处理电路及终端设备，能够解决现有技术中运放通路建立过程中产生的POP噪声的问题。
本申请第一方面提供一种音频处理电路，所述音频处理电路可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的电路，所述电路可以是软件和/或硬件。在本申请中，所述电路可包括级联运放电路、下拉电路和输出节点，所述级联运放电路与音频负载电连接的节点为输出节点。
其中，所述级联运放电路包括第一运放电路和第二运放电路，所述第一运放电路为所述第二运放电路的前级运放，所述第一运放电路包括主运算放大器和辅运算放大器，所述主运算放大器和所述辅运算放大器并联。
所述级联运放电路用于对输入电压进行放大，并将放大后的电压输出至所述输出节点。
所述下拉电路耦合至所述输出节点，下拉电路的另一端接地或共模电压模块。所述下拉电路，用于当所述第一运放电路开启后，下拉所述输出节点的电压。
所述第二运放电路，用于开启所述辅运算放大器后，控制所述辅运算放大器的电压增益从低至高渐变，从而控制所述输出节点的电压跟随所述输出电阻的渐变，从低至高渐变；当所述辅运算放大器的电压增益达到预设增益后，开启所述主运算放大器。
相较于现有机制，本申请中，作为后级运放输出的第二运放电路在所述下拉电路下拉所述输出节点，且所述第一运放电路和所述第二运放电路均开启后，通过控制所述第二运放电路的输出电阻从高至低渐变，来控制所述输出节点的电压跟随所述输出电阻的渐变，从低至高渐变，使得运放通路建立过程中，输出节点的电压能够缓慢的递增，从而减少POP噪声的产生，也能将作为前级运放的第一运放电路的失调电压传递到负载，由此可见，采用本申请的音频电路结构，能够有效的抑制运放通路建立过程中的POP噪声。
在一些可能的设计中，所述第二运放电路还包括可变电阻电路。所述主运算放大器与 第一串联电路并联，所述第一串联电路包括：串联的所述辅运算放大器与所述可变电阻电路。
其中，所述可变电阻电路用于控制所述第一串联电路的输出电阻从高至低渐变，从而控制所述辅运算放大器的电压增益从低至高渐变，进而控制所述输出节点的电压从低至高渐变，或者从高至低渐变。通过控制第一串联电路的输出电阻的阻值的渐变，使得辅运算放大器所在的通路对输出节点的输出能力是逐步、缓慢的渐变，最终递增到驱动所述输出节点，达到缓慢建立运放通路的效果。
在一些可能的设计中，所述可变电阻电路包括斜坡信号控制器和可变电阻，由于音频电路中可能会存在正/负的失调电压，正/负的失调电压在运放通路建立过程中都会产生POP噪声，都可由斜坡信号控制器消减产生的POP噪声。所以，所述可变电阻可包括第一斜坡电阻和第二斜坡电阻中的至少一个，分别针对正/负的失调电压导致的POP噪声进行抑制。所述第一斜坡电阻的输出电平为第一电平，所述第二斜坡电阻的输出电平为第二电平。所述斜坡信号控制器可通过控制所述第一电平的渐变值或者控制所述第二电平的渐变值，从而控制所述可变电阻的输出电阻的渐变值。此外，所述斜坡信号控制器还用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的输出电阻不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。
具体来说，在运放通路建立过程中，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的输出电阻不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。
以下分别进行说明。
一、抑制在运放通路建立过程中由正的失调电压产生的POP噪声
所述斜坡信号控制器用于：
在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的阻值从第一阻值渐变至第二阻值，使得所述输出节点的电压跟随所述可变电阻的阻值的渐变值升高，直至所述输出节点的电压趋于第一电压值。其中所述第一阻值大于所述第二阻值。
其中，所述第一电压值是指正极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化。
相应的，所述主运算放大器则用于在所述斜坡信号控制器控制所述输出节点的电压趋于所述第一电压值后开启，以使所述级联运放电路的输出电压驱动所述输出节点。
在失调电压为正，且所述可变电阻包括第一斜坡电阻时，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述第一斜坡电阻的阻值不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。例如控制所述第一斜坡电阻的阻值为高阻，这样就可以直接截断运放电路和输出节点，保证输出节点的电压不会发生突变，这样能够有效避免产生的POP噪声传递之音频负载对人耳的干扰。
可选的，在一些可能的设计中，当所述第一运放电路和所述第二运放电路均开启后，所述斜坡信号控制器用于提供第一斜坡信号。
其中，所述第一斜坡信号用于控制第一电平的电平值从第一电平值渐变至第二电平值，从而控制所述第一斜坡电阻的阻值从高至低渐变，所述输出节点的电压从低至高渐变，直 至所述输出节点的电压趋于所述第一电压值，所述第一电平值大于所述第二电平值。其中，所述输出节点的电压可跟随第一斜坡电阻的阻值的渐变而渐变。
在第一电平的电平值的渐变过程中，当所述第一斜坡电阻的阻值低于第三阻值后，所述级联运放电路的输出电压输出所述输出节点，所述第三阻值大于或等于所述第二阻值。可见，通过第一电平的电平值的渐变，使得输出节点缓慢的达到失调电压，使得整个运放通路缓慢的建立，为后续开启主运算放大器做准备。
可见，在所述第一斜坡电阻的阻值在跟随所述第一斜坡信号的变化渐变的初始状态下，所述级联运放电路和所述输出节点之间的通路断开。这样，在第一斜坡信号渐变的初始状态下，运放电路的输出电压无法输出输出节点，保证输出节点的电压不会发生突变。因此，级联运放电路的失调电压在运放通路建立过程中不会传递到输出节点，所以，输出节点不会将失调电压传递到音频负载，这样在运放通路建立就不会产生POP噪声。
二、抑制在运放通路建立过程中由负的失调电压产生的POP噪声
所述斜坡信号控制器用于：
在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的输出电阻从第一阻值渐变至第二阻值，使得所述输出节点的电压跟随所述可变电阻的阻值的渐变值降低，直至所述输出节点的电压趋于第二电压值；其中所述第一阻值大于所述第二阻值，所述第二电压值是指负极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化。
所述主运算放大器则用于在所述斜坡信号控制器控制所述输出节点的电压趋于所述第二电压值后开启，使得所述级联运放电路的输出电压驱动所述输出节点。
在失调电压为负，且所述可变电阻包括第二斜坡电阻时，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述第二斜坡电阻的阻值不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。例如控制所述第二斜坡电阻的阻值为高阻。
在一些可能的设计中，当所述第一运放电路和所述辅运算放大器均开启时，所述斜坡信号控制器用于提供第二斜坡信号。
其中，所述第二斜坡信号用于控制第二电平的电平值从第三电平值渐变至第四电平值，从而控制所述第二斜坡电阻的阻值从高至低渐变，所述输出节点的电压从低至高渐变，直至所述输出节点的电压趋于所述第二电压值，所述第三电平值小于所述第四电平值。其中，所述输出节点的电压可跟随第二斜坡电阻的阻值的渐变而渐变。
可见，通过所述第二斜坡信号控制第二电平的电平值的渐变，使得第二电平能够缓慢的渐变，不会出现突变，由于所述第二斜坡电阻的阻值会跟随第二电平的渐变从高至低渐变，因此，最终会使得所述输出节点的电压跟随所述第二斜坡电阻的阻值的渐变从低至高渐变，这样就使得运放通路建立过程中，输出节点的电压缓慢的上升，最终趋于第二电压值，与现有机制相比，明显消减POP噪声的产生。
在所述第二电平的电平值的渐变过程中，当所述可变电阻路的输出电阻低于第三阻值后，所述级联运放电路和所述输出节点之间的通路导通，所述第三阻值大于或等于所述第二阻值。可见，通过第一电平的电平值的渐变，可以使得输出节点缓慢的达到驱动电压， 使得整个运放通路缓慢的建立，为后续开启主运算放大器做准备。
在一些可能的设计中，所述斜坡信号控制器还包括脉冲信号生成电路和斜坡信号控制逻辑电路，所述斜坡信号控制器还包括第一斜坡电流源和第二斜坡电流源中的至少一个。
其中，所述脉冲信号生成电路与所述斜坡信号控制逻辑电路串联，所述第一斜坡电流源和所述第二斜坡电流源并联。
所述脉冲信号生成电路用于将输入的时钟信号生成脉冲信号，并将所述脉冲信号输入所述斜坡信号控制逻辑电路。
所述斜坡信号控制逻辑电路用于接收自所述脉冲信号生成电路输入的脉冲信号，根据输入的所述脉冲信号生成斜坡信号，并将生成的所述斜坡信号输入斜坡电流源，所述斜坡信号包括所述第一斜坡信号或所述第二斜坡信号，所述斜坡电流源包括所述第一斜坡电流源或所述第二斜坡电流源。
通过由第一斜坡电流源或第二斜坡电流源所提供的小电流进行间隙性充电的方法，用较小的电容即可产生斜率较缓的斜坡信号，可以节约成本，也不降低整个电路的集成度。
在一些实施方式中，还可通过调节时钟信号的频率、脉冲信号的宽度、斜坡电流源的输出电流以及电容大小，以灵活调节斜坡信号的步长和斜率，以平滑斜坡信号的渐变。
在一些可能的设计中，当所述斜坡信号控制器包括第一斜坡电流源和第二斜坡电流源时，所述斜坡信号控制器还包括单刀双掷开关，所述单刀双掷开关用于：
当所述斜坡信号控制逻辑电路生成的斜坡信号与所述第一斜坡信号的特性相同或相似时，连通所述第一斜坡电流源。
或者，当所述斜坡信号控制逻辑电路生成的斜坡信号与所述第二斜坡信号的特性相同或相似时，连通所述第二斜坡电流源。
通过该电路结构，实现了只需要一个音频电路就能够解决运放通路建立过程中，由于运放的正/负失调电压所导致POP噪声问题，并且可以灵活的切换。
在一些可能的设计中，由于运放通路建立过程中，会形成一个闭环的反馈网络，反馈网络中可能会出现震荡，震荡会产生突然尖锐的POP噪声。所以，为了进一步消除运放通路建立过程中由于震荡导致的POP噪声，本申请还可以增加一个补偿电路来避免反馈网络中的震荡信号引起POP噪声。具体来说，还可在上述音频处理电路中设置环路补偿电路，所述环路补偿电路用于：
通过灌电流循环抑制闭环回路中的震荡信号，一方面抑制由震荡信号产生的POP噪声，另一方面还能维持闭环系统增益的稳定性。
在一些可能的设计中，所述级联运放电路为级联运放，所述级联运放电路包括至少一个所述第二运放电路，至少一个所述第二运放电路包括所述辅运算放大器与所述斜坡信号控制器。本申请不限定是否分别为每个运放电路都配备一个辅运算放大器和可变电阻电路。可以为任意运放电路配备一个辅运算放大器和可变电阻电路，这样就都可以阻断失调电压传递到输出节点，本申请也不限定将辅运算放大器和可变电阻电路设置在哪一级运放电路，或者哪几级的运放电路。
还可仅限定仅在产生POP噪声影响大的非理想器件处配备辅运算放大器和可变电阻电路，若所述第二运放电路中的主运算放大器的失调电压高于预设阈值，那么，可以为失调 电压高于预设阈值的主运算放大器配备辅运算放大器和可变电阻电路。在设计POP噪声抑制电路时，可以全部或部分的考虑为这些非理想器件配备辅运算放大器和可变电阻电路，本申请不作限定。
本申请第二方面提供一种终端设备，其包括音频负载和上述第一方面所述的音频处理电路。
本申请的又一方面提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面中任意一项的所述的音频处理电路执行的操作。
本申请的又一方面提供了一种计算机程序产品，该计算机程序产品包括计算机软件指令，该计算机软件指令可通过处理电路进行加载来实现上述各方面中任意一项的所述的音频处理电路执行的操作。
相较于现有技术，本申请提供的方案中，音频电路中的运放电路包括第一运放电路和第二运放电路，所述第一运放电路为所述第二运放电路的运放输出前级，作为后级运放输出的第二运放电路在所述下拉电路下拉所述输出节点，且所述第一运放电路和所述第二运放电路均开启后，通过控制所述第二运放电路的输出电阻从高至低渐变，来控制所述输出节点的电压跟随所述输出电阻的渐变，从低至高渐变，使得运放通路建立过程中，输出节点的电压能够缓慢的递增，从而减少POP噪声的产生，也能将作为前级运放的第一运放电路的失调电压传递到负载，由此可见，采用本申请的音频电路结构，能够有效的抑制运放通路建立过程中的POP噪声。
附图说明
图1为现有机制中音频电路的一种结构示意图；
图2为本发明实施例中音频处理电路的一种结构示意图；
图3为本发明实施例中音频处理电路的另一种结构示意图；
图4a为本发明实施例中第二运放电路的一种结构示意图；
图4b为本发明实施例中第二斜坡信号的曲线示意图；
图5为本发明实施例中斜坡信号控制器的一种结构示意图；
图6为本发明实施例中音频处理电路的另一种结构示意图；
图7为本发明实施例中音频处理电路的另一种结构示意图；
图8为本发明实施例中失调电压为负时，音频处理电路中各节点电压时序变化的一种示意图；
图9为本发明实施例中失调电压为正时，音频处理电路中各节点电压时序变化的一种示意图；
图10为本发明实施例中通过RAMP控制DC输出结构的音频处理电路中各节点电压变化的一种示意图；
图11为本发明实施例中通过RAMP控制AC耦合结构的音频处理电路中各节点电压变化 的一种示意图；
图12为本发明实施例中终端设备的一种结构示意图。
具体实施方式
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或电路的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或电路，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或电路，本申请中所出现的电路的划分，仅仅是一种逻辑上的划分，实际应用中实现时可以有另外的划分方式，例如多个电路可以结合成或集成在另一个系统中，或一些特征可以忽略，或不执行，另外，所显示的或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，电路之间的间接耦合或通信连接可以是电性或其他类似的形式，本申请中均不作限定。并且，作为分离部件说明的电路或子电路可以是也可以不是物理上的分离，可以是也可以不是物理电路，或者可以分布到多个电路电路中，可以根据实际的需要选择其中的部分或全部电路来实现本申请方案的目的。
本申请供了一种音频处理电路及终端设备，可用于音频电路，例如耳机、手机等音频配件或具备音频播放功能的终端设备。现有机制中，如图1所示，运放开启之前，其呈现高阻，由于共模电压(英文全称：Common Mode Voltage，英文简称：VCM)开关和负载的原因，输出(OUT)节点为VCM(AC耦合时)或GND(DC输出时)。运放开启之后，由于运放本身的非理想性，AC耦合时，运放会将OUT节点驱动到VCM+Vos(Vos为全通路失调电压，也可称为offset)，或DC输出时，运放会将OUT节点驱动到GND+Vos。
由于该运放自身会有偏置Vos_op，以及该运放的前级运放也会传递一个前级偏置Vos_front给该运放，而该运放通路建立过程中，该运放的前级运放与OUT节点之间会存在电平差(AC耦合时为VACdif，DC输出时为VDCdif)，同时，反馈系数(Rfb_p/Rin_p)与反馈系数(Rfb_n/Rin_n)也存在差异Δ，那么，最终OUT节点的输出电压offset约为VACdif*Δ或VDCdif*Δ。
由此可见，对于OUT节点的电压从VCM到VCM+Vos的变化过程中，或者从GND到GND+Vos的变化过程中，产生的offset都会传递到音频负载，从而产生POP噪声。
为解决上述技术问题，本申请主要提供以下几种电路之一：
1、仅在级联运放最后一级的运放电路(即与OUT节点电连接的运放电路)两端并联一个辅助运放电路。
2、在级联运放的每一级的运放电路两端都并联一个辅助运放电路。
3、仅在运放失调电压超过预设阈值的运放电路两端并联一个辅助运放电路。
4、仅在级联运放中的前几级运放电路两端并联一个辅助运放电路。
上述4种电路中的辅助运放电路都包括可变电阻电路，在采用上述4种电路中的任一种后，在运放通路建立初期，仅开启并联了辅助运放电路的运放电路的前级运放电路，以及开启辅助运放电路，在运放通路建立的初始状态，辅助运放电路中的可变电阻的阻值对 外体现为高阻，使得其所在的运放电路的失调电压不会传递到OUT节点，这样就不会驱动OUT节点为音频负载提供电压，从开始建立运放通路时，就将整个级联运放与OUT节点截断。
在运放通路建立过程中，各辅助运放电路中的可变电阻电路对外体现为电阻缓慢的升高或者降低，呈现斜坡式(包括上坡式或下坡式)的变化，使得整个辅助运放电路的输出电压也缓慢的升高，渐渐的达到失调电压，以驱动OUT节点。在辅助运放电路的输出电压达到失调电压后，可开启与辅助运放电路并联的运放电路，这样，最终整个运放通路建立完成。
请参照图2，以下对本申请提供一种音频处理电路进行举例说明，所述电路可用于交流(英文全称：Alternative current，英文简称：AC)耦合场景和直流(英文全称：Direct current，英文简称：DC)输出场景。所述电路可包括级联运放电路、输出节点和下拉电路。
其中，所述级联运放电路包括第一运放电路和第二运放电路，所述第一运放电路为所述第二运放电路的前级运放，所述第一运放电路包括主运算放大器和辅运算放大器，所述主运算放大器和所述辅运算放大器并联。级联运放电路用于对输入电压进行放大，并将放大后的电压输出至输出节点。其中，在所述第一运放电路对输入其的电压放大后，将放大后的电压输入第二运放电路，使得所述第二运放电路对输入其的电压进行处理后，再输出至所述输出节点。
所述下拉电路的一端耦合至所述输出节点，所述下拉电路的另一端可接地(DC输出时)或共模电压模块(AC耦合时)。所述下拉电路，用于当所述第一运放电路开启后，下拉(Pull down)所述输出节点的电压，其中，下拉是指将输出节点的电压由高(H)拉到低(L)。
所述第二运放电路，用于开启所述辅运算放大器后，控制所述辅运算放大器的电压增益从低至高渐变，从而控制所述输出节点的电压跟随所述输出电阻的渐变，从低至高渐变；当所述辅运算放大器的电压增益达到预设增益后，开启所述主运算放大器。需要说明的是，此处的从低至高渐变的输出节点的电压是指该输出节点的电压的绝对值，不限定正负。
本发明实施例中，作为后级运放输出的第二运放电路在所述下拉电路下拉所述输出节点，且所述第一运放电路和所述第二运放电路均开启后，通过控制所述第二运放电路的输出电阻从高至低渐变，来控制所述输出节点的电压跟随所述输出电阻的渐变，从低至高渐变，使得运放通路建立过程中，输出节点的电压能够缓慢的递增，从而减少POP噪声的产生，也能将作为前级运放的第一运放电路的失调电压传递到负载，由此可见，采用本申请的音频电路结构，能够有效的抑制运放通路建立过程中的POP噪声。
可选的，在一些发明实施例中，所述级联运放电路可包括至少一个所述第二运放电路。在上述实施例中，通过控制辅运算放大器的电压增益从低至高渐变来控制输出节点的电压从低至高渐变时，可以通过控制第一运放电路的输出电阻从高至低的渐变来实现控制输出节点的电压的渐变。具体来说，至少一个所述第二运放电路还可包括：可变电阻电路，所述主运算放大器与第一串联电路并联，所述第一串联电路包括：串联的所述辅运算放大器与所述可变电阻电路。
其中，所述可变电阻电路可用于控制所述可变电阻的输出电阻从高至低渐变，从而控制所述辅运算放大器的电压增益从低至高渐变，进而控制所述输出节点的电压从低至高渐 变，即使得所述级联运放电路的增益从低至高渐变。所述输出节点的电压可跟随所述可变电阻的输出电阻的渐变而渐变。
相应的，在所述可变电阻电路控制可变电阻的输出电阻渐变结束后，开启所述主运算放大器，使得第一运放电路、所述主运算放大器到输出节点的运放通路建立。
可见，主运算放大器和辅运算放大器共用相同的前级运放(即第一运放电路)，并且共用相同的外部反馈网络，这样就能够保证经由主运算放大器和辅运算放大器所在的通路的失调电压offset值相同，也能保证主运算放大器和辅运算放大器的反馈系数也相同。采用该电路结构后，通过先开启辅运算放大器所在的通路，以此来等效主运算放大器的驱动所述输出节点的驱动能力，并且，辅运算放大器所在的通路对输出节点的驱动能力是逐步、缓慢的渐变，最终递增到驱动所述输出节点，也就是输出所述音频负载。然后再开启主运算放大器，这样就将运放通路切回到主运算放大器所在的通路了。最终可以大幅度降低运放通路建立过程中产生的POP噪声，进而消减POP噪声给人耳带来的不适。
所述级联运放电路为级联运放时，本申请不限定是否分别为每个运放电路都配备一个辅运算放大器和可变电阻电路。可以为任意运放电路配备一个辅运算放大器和可变电阻电路，这样就都可以阻断运放电路的失调电压传递到输出节点，本申请也不限定将辅运算放大器和可变电阻电路设置在哪一级运放电路，或者哪几级的运放电路。具体的电路电路图可参考图3所示的一种结构，可以基于图3进行电路电路的增加、修改等变形，具体本申请不作限定。
可选的，在一些实施方式中，可以通过输入一个信号控制所述可变电阻的输出电阻的渐变，所述可变电阻电路可包括可变电阻和斜坡信号控制器(如图4a所示的电路结构图)，该所述斜坡信号控制器可控制所述可变电阻的输出电阻，也可以认为所述斜坡信号控制器控制上述可变电阻的阻值变化。可选的，本申请中的胁迫信号控制器可以直接生成斜坡信号来控制可变电阻的阻值变化，也可以基于从其他电路传递的控制信号来控制可变电阻的阻值变化，具体结构本申请不作限定。
具体来说，上述音频处理电路上电后，由于运放通路建立过程中，可能会存在运放电路的失调电压为正/负两种情况。所以，所述斜坡信号控制器在所述第一运放电路和所述辅运算放大器均开启后，需要分别根据失调电压的正/负来控制所述可变电阻的输出电阻的渐变。以下对上电后的运放通路建立过程中的POP抑制流程分别进行说明：
一、失调电压为正时
所述斜坡信号控制器用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的阻值从第一阻值渐变至第二阻值，使得所述输出节点的电压跟随所述可变电阻的阻值的渐变值升高，直至所述输出节点的电压趋于第一电压值。
其中，可设所述第一阻值大于所述第二阻值，第一阻值可以设置为高阻，使得在运放通路建立初期直接截断运放电路和输出节点之间的通路；或者还可以仅仅设置为：使得运放电路的输出电压无法在运放通路建立过程中驱动所述输出节点。
所述第一电压值是指正极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化。
可以理解的是，当输出节点的电压达到第一电压值时，则表示所述输出节点的电压达 到所述级联运放电路的失调电压，所述级联运放电路的失调电压是指所述级联运放电路的输出电压偏置offset。
其中，第一电压值可由第二运放电路之前的运放电路的失调电压决定，第二运放电路之前的运放电路的失调电压可包括：第一运放电路的失调电压、或者还可以包括第一运放电路之前的运放电路的失调电压，具体本申请不作限定。可选的，第一电压值可根据反馈系数等参数计算得到。
相应的，所述主运算放大器用于在所述斜坡信号控制器控制所述输出节点的电压趋于所述第一电压值后开启，以使所述级联运放电路的输出电压驱动所述输出节点。由于在开启主运算放大器之前，输出节点已经达到最终的失调电压(offset)，故开启主运算放大器后就不会再导致输出节点的电压状态突变，因此，在输出节点的电压就可以爬坡式的慢慢达到预设的offset后，再开启主运算放大器，就可以有效的减少由于输出节点的电压突变产生的POP噪声。
二、失调电压为负时
所述可变电阻电路包括斜坡信号控制器，所述斜坡信号控制器用于：
在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的输出电阻从第一阻值渐变至第二阻值，使得所述输出节点的电压跟随所述可变电阻的输出电阻的渐变值降低，直至所述输出节点的电压趋于第二电压值。可以理解的是，当输出节点的电压达到第二电压值时，则表示所述输出节点的电压达到所述级联运放电路的失调电压。
其中，第二电压值可由第二运放电路之前的运放电路的失调电压决定，第二运放电路之前的运放电路的失调电压可包括：第一运放电路的失调电压、或者还可以包括第一运放电路之前的运放电路的失调电压，具体本申请不作限定。第二电压值也可根据反馈系数等参数计算得到。
相应的，所述主运算放大器则是用于在所述斜坡信号控制器控制所述输出节点的电压趋于所述第二电压值后开启，以使所述级联运放电路的输出电压驱动所述输出节点。
需要说明的是，本申请中，当运放电路的失调电压为正时，该输出节点的节点电压的渐变值为负向增长；当运放电路的失调电压为负时，该输出节点的电压的渐变值为正向增长。此外，本申请中的斜坡信号控制器还可以是单独设置的外挂电路，也可以集成于可变电阻电路中，驱动可变电阻的阻值渐变的斜坡信号可以是由斜坡信号控制器提供，也可以是由可变电阻电路之外的其他电路提供，具体本申请不作限定。
由此可见，可以通过辅运算放大器和可变电阻电路来缓慢建立运放反馈网络全通路的失调电压，以此来缓慢建立运放通路，直到完全建立运放通路，这样可以释放对通路其他电路的失调电压的约束。
可选的，在一些发明实施例中，所述可变电阻可包括第一斜坡电阻和第二斜坡电阻中的至少一个，由上述斜坡信号控制器控制第一斜坡电阻或第二斜坡电阻。其中第一斜坡电阻是指该斜坡电阻的阻值随着该斜坡电阻两端的电压降低而减小，随着该斜坡电阻两端的电压升高而增大；第二斜坡电阻是指该斜坡电阻的阻值随着该斜坡电阻两端的电压升高而降低，随着该斜坡电阻两端的电压降低而减小。
当电路同时设置了第一斜坡电阻和第二斜坡电阻时，斜坡信号控制器可在第一斜坡电 阻和第二斜坡电阻之间切换，也可同时控制第一斜坡电阻和第二斜坡电阻的阻值变化，并提供相应的斜坡信号来控制可变电阻的渐变值，以适应电路的多样变化。为便于表述，可定义：所述第一斜坡电阻的输出电平为第一电平，所述第二斜坡电阻的输出电平为第二电平。在一个音频处理电路中，既可以仅针对负失调电压设置可变电阻电路，也可以仅针对正失调电压设置可变电阻电路，还可以同时设置针对负失调电压和正失调电压的可变电阻电路。
在电路中设置第一斜坡电阻和/或第二斜坡电阻，可分别针对负/正的失调电压导致的POP噪声进行抑制。
当针对负失调电压设置可变电阻电路时，可以将可变电阻电路中的可变电阻设置为阻值正向渐变的第一斜坡电阻，且可由斜坡信号控制器来控制该第一斜坡电阻的阻值的渐变。具体来说，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述第二斜坡电阻的阻值不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。例如控制所述第二斜坡电阻的阻值为高阻。
当针对正失调电压设置可变电阻电路时，可以将可变电阻电路中的可变电阻设置为阻值负向渐变的第二斜坡电阻，且可由斜坡信号控制器来控制该第二斜坡电阻的阻值的渐变。具体来说，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述第一斜坡电阻的阻值不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。例如控制所述第一斜坡电阻的阻值为高阻，这样就可以直接截断运放电路和输出节点，保证输出节点的电压不会发生突变，这样能够有效避免产生的POP噪声传递之音频负载对人耳的干扰。
当然，在电路中，可能阶段性的产生负失调电压或者正失调电压，为综合解决正/负失调电压的问题，本申请还可以同时设置针对负失调电压和正失调电压的可变电阻，也就是将可变电阻电路设置为阻值正向渐变的第一斜坡电阻，和将可变电阻设置为阻值负向渐变的第二斜坡电阻，然后在运放通路建立过程中选通其中一个斜坡电阻(选通第一斜坡电阻或者第二斜坡电阻)即可，并且由斜坡信号控制器来控制第一斜坡电阻/第二斜坡电阻的阻值的渐变；或者，同时选通第一斜坡电阻和第二斜坡电阻，由斜坡信号控制器来控制第一斜坡电阻/第二斜坡电阻的阻值的渐变。这样就可以应对多样化的电压偏置导致的POP噪声场景。
所述斜坡信号控制器具体用于通过控制所述第一电平的渐变值或者控制所述第二电平的渐变值，从而控制所述可变电阻的输出电阻的渐变值。
下面分别对通过控制第一斜坡电阻和第二斜坡电阻的阻值来控制输出节点的电压的方式进行说明：
一、所述斜坡信号控制器包括第一斜坡电阻时，可解决运放通路建立过程中，失调电压为正时产生的POP噪声。
所述斜坡信号控制器可被设置为：在所述第一运放电路和所述辅运算放大器均开启后，控制所述第一斜坡电阻的阻值不小于所述第一阻值，以使所述级联运放电路的输出电压无法驱动所述输出节点，甚至截断所述级联运放电路和所述输出节点之间的通路。
在运放通路建立过程中，当所述第一运放电路和所述第二运放电路均开启后，所述斜 坡信号控制器可向可变电阻电路提供第一斜坡信号。其中，所述第一斜坡信号用于控制第一电平的电平值从第一电平值渐变至第二电平值，从而控制所述第一斜坡电阻的阻值从高至低渐变，所述输出节点的电压跟随所述第一斜坡电阻的阻值的渐变从低至高渐变，直至所述输出节点的电压趋于所述第一电压值。其中，所述第一电压值是指正极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化。其中所述第一电平值大于所述第二电平值，也就是第一斜坡信号可控制第一电平的电平值缓慢的下降，从而控制第一斜坡电阻的阻值缓慢的降低。在所述第一斜坡电阻的阻值在跟随所述第一斜坡信号的变化渐变的初始状态下，所述级联运放电路和所述输出节点之间的通路断开，这样运放通路建立初期的电压突变产生的POP噪声则不会传递到输出节点，更不会通过输出节点传递到音频负载。
可见，通过所述第一斜坡信号控制第一电平的电平值的渐变，使得第一电平能够缓慢的渐变，不会出现突变，由于所述第一斜坡电阻的阻值会跟随第一电平的渐变从高至低渐变，因此，最终会使得所述输出节点的电压跟随所述第一斜坡电阻的阻值的渐变从低至高渐变，这样就使得运放通路建立过程中，输出节点的电压缓慢的上升，最终趋于预设的偏置(例如第一电压值或者第二电压值)，与现有机制相比，明显消减POP噪声的产生。
在所述输出节点的电压跟随所述第一斜坡电阻的阻值的渐变从低至高渐变过程中，当所述第一斜坡电阻的阻值低于第三阻值后，所述级联运放电路的输出电压可驱动所述输出节点，所述第三阻值大于或等于所述第二阻值。可见，通过第一电平的电平值的渐变，可以使得输出节点缓慢的达到输出电压，使得整个运放通路缓慢的建立，为后续开启主运算放大器做准备。这样随着所述级联运放电路的输出电压的升高，也渐渐使得所述输出节点的电压升高，当所述输出节点被驱动后，输出节点就可以将级联运放电路的输出传递至与其电连接的音频负载，运放反馈环路导通，进而驱动音频负载工作。随后，所述第一斜坡电阻的阻值继续从第三阻值开始渐变至第二阻值。
在一些实施方式中，在运放通路建立初期，如果运放电路的输出电压很低，若该输出电压低于输出节点的最低高电平，那么级联运放电路的输出电压是无法驱动输出节点工作的。这样，运放通路建立初期的各级运放电路的失调电压并不会瞬间传送到输出节点后面的音频负载，而是在输出节点处被截断或锐减。
若级联运放电路在运放通路建立初期呈现高阻状态，也就是在所述可变电阻的输出电阻在跟随所述第一斜坡信号的变化渐变的初始状态下，所述级联运放电路和所述输出节点之间的通路是断开的，级联运放电路的失调电压不会传送到输出节点，更不会传送到连接在输出节点的音频负载上，这样就能够有效的避免运放通路建立器件的POP噪音的产生。
二、所述斜坡信号控制器包括第二斜坡电阻时，可解决运放通路建立过程中，失调电压为负时产生的POP噪声。
所述斜坡信号控制器可被设置为：在所述第一运放电路和所述辅运算放大器均开启后，控制所述第二斜坡电阻不小于所述第一阻值，以使所述级联运放电路的输出电压无法驱动所述输出节点，甚至截断所述级联运放电路和所述输出节点之间的通路。
在运放通路建立过程中，当所述第一运放电路和所述辅运算放大器均开启时，所述斜坡信号控制器可向第二斜坡电阻提供第二斜坡信号。
其中，所述第二斜坡信号用于控制第二电平的电平值从第三电平值渐变至第四电平值，从而控制所述第二斜坡电阻的阻值从高至低渐变，所述输出节点的电压跟随所述第二斜坡电阻的阻值的渐变从低至高渐变，直至所述输出节点的电压趋于所述第二电压值。
其中，所述第三电平值小于所述第四电平值，也就是第二斜坡信号可控制第二电平的电平值缓慢的升高，从而控制第二斜坡电阻的阻值缓慢的降低。所述第一阻值大于所述第二阻值，所述第二电压值是指负极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化。
可选的，若在第二电平的电平值渐变初始状态时，控制所述第二斜坡电阻的阻值呈现为高阻，那么在所述第二斜坡电阻的阻值在跟随所述第二斜坡信号的变化渐变的初始状态下，所述级联运放电路和所述输出节点之间的通路断开，即可直接截断运放电路与输出节点，可以完全杜绝运放电路的失调电压传递到输出节点。
可见，通过所述第二斜坡信号控制第二电平的电平值的渐变，使得第二电平能够缓慢的渐变，不会出现突变，由于所述第二斜坡电阻的阻值会跟随第二电平的渐变从高至低渐变，因此，最终会使得所述输出节点的电压跟随所述第二斜坡电阻的阻值的渐变从低至高渐变，这样就使得运放通路建立过程中，输出节点的电压缓慢的上升，最终趋于第二电压值，与现有机制相比，明显消减POP噪声的产生。
在第二斜坡信号的控制过程中，当所述第二斜坡电阻的阻值低于第三阻值后，输出节点被驱动，所述级联运放电路和所述输出节点之间的通路导通。所述第三阻值大于或等于所述第二阻值，随后，所述第二斜坡电阻的阻值继续从第三阻值开始渐变至第二阻值。
可选的，在一些发明实施例中，所述斜坡信号控制器还包括脉冲信号生成电路和斜坡信号控制逻辑电路，所述斜坡信号控制器还包括第一斜坡电流源和第二斜坡电流源中的至少一个。
其中，所述脉冲信号生成电路与所述斜坡信号控制逻辑电路串联。
所述脉冲信号生成电路用于将输入的时钟信号生成脉冲信号，并将所述脉冲信号输入所述斜坡信号控制逻辑电路。
所述斜坡信号控制逻辑电路用于接收自所述脉冲信号生成电路输入的脉冲信号，根据输入的所述脉冲信号生成斜坡信号，并将生成的所述斜坡信号输入斜坡电流源，所述斜坡信号包括所述第一斜坡信号或所述第二斜坡信号，所述斜坡电流源包括所述第一斜坡电流源或所述第二斜坡电流源。
若所述斜坡信号控制器同时包括第一斜坡电流源和第二斜坡电流源，那么所述第一斜坡电流源可与所述第二斜坡电流源并联，当失调电压为正时，产生第一斜坡信号为第一斜坡电流源提供电流；当失调电压为负时，产生第一斜坡信号为第二斜坡电流源提供电流，具体在第一电流源和第二电流源之间进行切换的方式可采用单刀双掷开关、双向可控开关或者使能信号来控制选通等，具体切换的方式本申请不作限定。
可选的，在一些实施方式中，如图5所示的可变电阻电路的另一种电路结构示意图。当所述斜坡信号控制器包括第一斜坡电流源和第二斜坡电流源时，所述斜坡信号控制器可包括单刀双掷开关，所述单刀双掷开关用于：
当所述斜坡信号控制逻辑电路生成的斜坡信号与所述第一斜坡信号的特性相同或相似 时，连通所述第一斜坡电流源。
或者，当所述斜坡信号控制逻辑电路生成的斜坡信号与所述第二斜坡信号的特性相同或相似时，连通所述第二斜坡电流源。
可见，通过该种电路结构，实现了只需要一个音频电路就能够解决运放通路建立过程中，由于运放的正/负失调电压所导致POP噪声问题，并且可以灵活的切换。
图5中，通过小电流间隙性充电的方法，用较小的电容即可产生斜率较缓的斜坡信号，可以节约成本，也不降低整个电路的集成度。
在一些实施方式中，还可通过调节时钟信号(英文全称：clock，英文简称：CLK)的频率、脉冲信号的宽度、斜坡电流源的输出电流Iramp以及电容大小，以灵活调节斜坡信号(RAMP)的步长和斜率，以平滑斜坡信号的渐变。
此外，由于在不同阶段RAMP_P或RAMP_N的渐变对级联运放电路最终的输出的失调电压(Vos)变化的影响的灵敏度也会不同，故可以通过分段调节斜坡信号斜率的方法来优化上电时间。具体来说，可以在影响Vos不灵敏的阶段加快斜坡信号速度，以及在影响Vos灵敏的阶段减缓斜坡信号速度。
在本申请实施例中，第一斜坡信号或第二斜坡信号都可由多个分段函数组成，微观里每段函数的斜率几乎相近，这样变化就比较平滑。可通过切换时间的长短来控制，例如本次斜坡信号为1pmA，可设较短的时间，下一跳设置1umA，可以设较长的时间，这样可以平滑斜坡信号的突变，以减少由于电压突变导致的POP噪声。例如第二斜坡信号可图4b所示的曲线表示。
由于斜坡信号需要足够的缓慢，并且不能增加较大的电容，故通过时钟产生窄脉冲周期信号来对可变电阻电路内的电容进行充电，从而可产生足够缓慢爬坡的斜坡信号(即RAMP_P/RAMP_N)。此外，RAMP-N和RAMP-P分别接一个斜坡信号，在启动POP噪声抑制时，电连接其中一个即可。
可选的，在一些发明实施例中，由于运放通路建立过程中，会形成一个闭环的反馈网络，反馈网络中可能会出现震荡，震荡会产生突然尖锐的POP噪声。所以，为了进一步消除运放通路建立过程中由于震荡导致的POP噪声，本申请还可以增加一个补偿电路来避免反馈网络中的震荡信号引起POP噪声。具体来说，还可在上述音频处理电路中设置环路补偿电路(英文全称：(compensation module)，其还可以用于维持闭环系统增益的稳定性。所述环路补偿电路用于：
在所述辅运算放大器所在的运放通路中用于输出所述输出节点的电压在输出电压从低至高渐变过程中，通过灌电流循环抑制闭环回路中的震荡信号，其中输出电压是指所述辅运算放大器所在的运放通路中用于驱动所述输出节点的电压，也就是整个第二运放电路的输出电压。采用环路补偿电路来抑制震荡信号后，一方面抑制由震荡信号产生的POP噪声，另一方面还能维持运放通路建立过程中闭环系统增益的稳定性。
可选的，在一些发明实施例中，还可仅限定仅在产生POP噪声影响大的非理想器件处配备辅运算放大器和可变电阻电路。若所述第二运放电路中的主运算放大器的失调电压高于预设阈值，那么，可以为失调电压高于预设阈值的主运算放大器配备辅运算放大器和可变电阻电路，在音频处理电路中，类似第二运放电路中的主运算放大器的运放电路还有很 多，在设计POP噪声抑制电路时，可以全部或部分的考虑为这些非理想器件配备辅运算放大器和可变电阻电路，本申请不作限定。
可选的，在一些发明实施例中，如图6所示的一种音频电路结构，当整个运放电路为电流型数模转换电路(英文全称：digital-analog converter，英文简称：DAC)输入结构时，若要消除该音频电路在运放通路建立过程中产生的POP噪声，可参考上述图2-图5、下述图7-图11中任意所述的实施例，相应增加本申请中所述的辅运算放大器和可变电阻电路等。在运放通路建立过程中，则只需要先开启逆变电路(英文全称：invert voltage，英文简称：INV)，然后以上述图2-图5、下述图7-图11任意所述的POP噪声抑制流程去开启主运算放大器即可，最后驱动图6中的OUT节点，此处不再赘述。其中，电流型DAC可由输入数据控制电流开关对，将电流导向输出端或者互补输出端。
可选的，在一些发明实施例中，针对音频处理电路下电过程中也会产生POP噪声，对此POP噪声的抑制流程依旧可以通过上述各个实施例中所述的第一运放电路、主运算放大器、辅运算放大器和可变电阻电路来协作完成，其整个POP抑制流程为运放通路建立过程中的POP抑制流程的逆过程，例如控制可变电阻的输出电阻从低至高渐变，使得输出节点的电压从低至高渐变，或者从高至低渐变。具体的分析过程可参考本申请中的任意实施例，此处不作赘述。
下面以DC输出的音频电路结构为例，如图7所示，其中虚线框中的区域即为作为输出级的级联运放(英文全称：Operational amplifier，英文简称：OP)，其包括三部分：
共用的运放前级(OP_MAIN)，其由PD_HP控制。
工作时的主输出级(OUTSTAGE_M)，其由PD_MAIN控制。
辅助输出级(OUTSTAGE_A)，其由PD_AUX控制，用于抑制运放通路建立过程中的POP噪声，其与主输出级(OUTSTAGE_M)并联。
图7中，OUT节点为整个级联运放与音频负载的节点，也就是用于驱动所述音频负载工作的输出节点。图7中的音频处理电路包括两种输入电压(包括VIN_N和VIN_P)，两对输入电阻(包括Rin_N和Rin_P)以及两对反馈电阻(包括Rfb_N和Rfb_P)。其中，Rin_N和Rfb_N，以及Rin_P和Rfb_P分别构成了运放的反馈网络。
该输出级级联运放还可包括环路补偿电路(compensation module)用来确保在POP噪声抑制流程的稳定性，环路传递函数不停变化的时候，环路不会因为震荡而发生不稳定的情况。环路传递函数是指Vos的关于反馈网络(包括由Rin_N和Rfb_N构成的反馈网络，以及由Rin_P和Rfb_P构成的反馈网络)的传递函数。
斜坡电压生成器(RAMP_GEN)，其可产生缓慢变化的斜坡电压信号，从而使环路缓慢建立。本申请中的RAMP_GEN可以是在运放通路建立过程中外挂的电路，与辅助输出级(OUTSTAGE_A)为可拆卸电连接。其也可以是上述输出级级联运放中集成的电路模块，具体本申请不作限定。下面对基于图7的电路结构所实现的POP噪声抑制流程进行说明：
一、针对运放电路的失调电压(Vos)为正时，通过斜坡电阻(RAMP_P)的输出电压变化来抑制POP噪声，可参考图7所示的电路、图8所示的各节点的电压变化时序图、以及图10所示的各个器件的变化过程。
运放开启流程如下：
1、初始状态，下拉电路(PULL_EN)导通，OUT节点同时被负载与地(GND)开关下拉到GND。
2、配置RAMP_GEN的输出信号，由其内部时序电路产生控制RAMP_P的电平的RAMP信号，例如可由图7中的定向斜坡电路(英文全称：directional ramp，英文简称：RAMP_DIR)产生，RAMP_DIR可产生定向斜坡信号，可通过其改变信号的方向性。
然后，将OP_MAIN的掉电电压(PD_HP)从1置为0开启OP_MAIN，将OUTSTAGE_A的掉电电压(PD_AUX)从1置为0开启OUTSTAGE_A。
由于OP_MAIN为非理想器件，所以OP_MAIN会产生POP噪声。由RAMP_GEN控制此时RAMP_P的输出电压为高电平H，则由RAMP_P控制的MOS管可变电阻为高阻，所以此时的运放不会驱动OUT节点。可见，由RAMP_GEN建立工作点过程中所产生的POP噪声会被RAMP_P控制的MOS管可变电阻阻断，所以不会将运放前级产生的POP噪声传递到OUT节点，OUT节点的电压就不会出现跳变，进而与OUT节点连接的音频负载不会产生POP噪声。
此时由于运放反馈环路断开，整个OP可等效为一个比较器，故根据offset可知OUT_A节点的电压VOUT_A为正电源，即VOUT_A＝VDD。
3、RAMP_GEN中的RAMP_DIR变向，使得RAMP_P的电压缓慢下降，RAMP控制的可变电阻阻值跟随RAMP_P的电压缓慢下降而缓慢减小。
一开始VOUT_A保持为VDD，但在RAMP_DIR变向过程中，VOUT_A则跟随可变电阻、PULL_EN开关及音频负载的分压关系从高至低渐变，最后VOUT_A＝min。在这个渐变过程中，环路增益(Loop Gain)也相应的缓慢增大。
具体来说，OUT节点的电压VOUT＝vos*(1+Rfb/Rin)，由于RAMP_P的电压缓慢降低，所以VOUT会缓慢的从GND渐变至最终的输出电压offset，直到可变电阻减小到足够小，运放反馈环路导通，最终使得音频负载的分压缓慢上升，最终被驱动，相应的，OUT节点会达到最终的输出电压offset值。
此后随着可变电阻减小，运放反馈环路的环路增益则逐步增加。此过程中由于OUT节点变化速率极慢，故并不会产生POP噪声。
4、可变电阻逐步减小，OUTSTAGE_A增益逐步增大，最终OUTSTAGE_A建立到稳态，最终RAMP_P达到低电平L，RAMP-GEN的可变电阻阻值达到最小，此时的Loop Gain达到最大，OUT节点达到最终的输出电压offset值。
5、开启OUTSTAGE_M(将PD_MAIN从1置为0)，由于之前OUT节点已经达到最终的输出offset值，故此时开启OUTSTAGE_M并不会导致OUT节点状态突变，也不会产生POP噪声。
由于OUTSTAGE_A和OUTSTAGE_M具有共同的运放前级(OP_MAIN)，所以OUTSTAGE_A和OUTSTAGE_M二者所在的运放通路offset也相同，进而开启OUTSTAGE_M后，OUTSTAGE_M通路的开启也不会产生新的POP噪声。
二、针对输出电压offset为负时，通过RAMP_N的输出电压变化来抑制POP噪声，可参考图7所示的电路、图9所示的各节点的电压变化时序图、以及图10所示的各个器件的变化过程。
运放开启流程如下：
1、初始状态，PULL_EN导通，OUT节点同时被负载与GND开关下拉到GND。
2、配置RAMP_GEN的输出信号，由其内部时序电路产生控制RAMP_N的电平的RAMP信号，即由图7中的RAMP_DIR产生。
然后开启OP_MAIN和OUTSTAGE_A(PD_AUX从1置为0)，由于OP_MAIN为非理想器件，所以OP_MAIN会产生POP噪声。由RAMP_GEN控制此时RAMP_N的输出电压为低电平L，则由RAMP_N控制的MOS管可变电阻为高阻。所以，由RAMP_GEN建立工作点过程中所产生的POP噪声会被RAMP_N控制的MOS管可变电阻阻断，所以不会将运放前级产生的POP噪声传递到OUT节点，OUT节点的电压就不会出现跳变，进而与OUT节点连接的音频负载不会产生POP噪声。
此时由于运放反馈环路断开，当前的OP可等效为一个比较器，故根据offset可知OUT_A节点的电压VOUT_A为负电源，即VOUT_A＝VSS。
3、RAMP_DIR变向，使得RAMP_N的电压缓慢上升，RAMP控制的可变电阻阻值跟随RAMP_N的电压缓慢上升而缓慢减小。
一开始VOUT_A保持为VSS，但在RAMP_DIR变向过程中，VOUT_A则跟随可变电阻、PULL_EN开关及音频负载的分压关系从低至高渐变，最后VOUT_A＝max。在这个渐变过程中，Loop Gain也相应的缓慢增大。
而VOUT＝vos*(1+Rfb/Rin)，由于RAMP_N的电压缓慢上升，所以VOUT会缓慢的从GND渐变至最终的输出电压offset，直到可变电阻减小到足够小，运放反馈环路导通，最终使得音频负载的分压缓慢上升，最终被驱动，相应的，OUT节点达到最终的输出电压offset值。
此后随着可变电阻减小，运放反馈环路的环路增益则逐步增加。此过程中，由于OUT节点变化速率极慢，故并不会产生POP噪声。
4、可变电阻逐步减小，OUTSTAGE_A增益逐步增大，最终OUTSTAGE_A建立到稳态，最终RAMP_N到达高电平H，RAMP-GEN的可变电阻阻值达到最小，此时的Loop Gain达到最大，OUT节点达到最终的输出电压offset值。
5、开启OUTSTAGE_M(将PD_MAIN从1置为0)，由于之前OUT节点已经达到最终的输出offset值，故此时开启OUTSTAGE_M并不会导致OUT节点状态突变，也不会产生POP噪声。
同理，由于OUTSTAGE_A和OUTSTAGE_M具有共同的运放前级(OP_MAIN)，所以OUTSTAGE_A和OUTSTAGE_M二者所在的运放通路offset也相同，进而开启OUTSTAGE_M后，OUTSTAGE_M通路的开启也不会产生新的POP噪声。
运放关闭流程：与开启流程相反，不作赘述。
同理，图11为AC耦合的音频电路结构的一种POP噪声抑制电路图，AC耦合的情况可参考图11所示的电路结构示意图，具体针对运放通路建立过程中的POP噪声抑制分析流程不作赘述。
图2-图11所对应的实施例中的第一运放电路、第二运放电路、主运算放大器、辅运算放大器、可变电阻电路、斜坡信号控制器、斜坡信号、失调电压等特征也同样适用于本申请中的图12所对应的实施例，后续类似之处不再赘述。
本申请还提供一种终端设备，该终端设备可包括音频负载和上述图2-图11所对应的实施例中的音频处理电路，音频处理电路为音频负载提供驱动电压，具体的结构可参考图12。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和电路的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述电路的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个电路或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或电路的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的电路可以是或者也可以不是物理上分开的，作为电路显示的部件可以是或者也可以不是物理电路，即可以位于一个地方，或者也可以分布到多个网络电路上。可以根据实际的需要选择其中的部分或者全部电路来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能电路可以集成在一个处理电路中，也可以是各个电路单独物理存在，也可以两个或两个以上电路集成在一个电路中。上述集成的电路既可以采用硬件的形式实现，也可以采用软件功能电路的形式实现。所述集成的电路如果以软件功能电路的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务电路或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务电路或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务电路、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上对本申请所提供的技术方案进行了详细介绍，本申请中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种音频处理电路，其特征在于，所述电路包括：级联运放电路、输出节点和下拉电路；
    其中，所述级联运放电路包括第一运放电路和第二运放电路，所述第一运放电路为所述第二运放电路的前级运放，所述第一运放电路包括并联的主运算放大器和辅运算放大器；所述级联运放电路用于对输入电压进行放大，并将放大后的电压输出至所述输出节点；
    所述下拉电路的一端耦合至所述输出节点，所述下拉电路的另一端接地或共模电压模块，所述下拉电路，用于当所述第一运放电路开启后，下拉所述输出节点的电压；
    所述第二运放电路，用于开启所述辅运算放大器后，控制所述辅运算放大器的电压增益从低至高渐变，从而控制所述输出节点的电压跟随所述输出电阻的渐变，从低至高渐变；当所述辅运算放大器的电压增益达到预设增益后，开启所述主运算放大器。
  2. 根据权利要求1所述的电路，其特征在于，所述第二运放电路还包括可变电阻电路，所述主运算放大器与第一串联电路并联，所述第一串联电路包括：串联的所述辅运算放大器与所述可变电阻电路；
    所述可变电阻电路用于控制所述第一串联电路的输出电阻从高至低渐变，从而控制所述辅运算放大器的电压增益从低至高渐变，控制所述输出节点的电压从低至高渐变。
  3. 根据权利要求2所述的电路，其特征在于，所述可变电阻电路包括斜坡信号控制器和可变电阻，当所述级联运放电路的失调电压为正时，所述斜坡信号控制器用于：
    在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的阻值从第一阻值渐变至第二阻值，使得所述输出节点的电压跟随所述可变电阻的阻值的渐变值升高，直至所述输出节点的电压趋于第一电压值，其中所述第一阻值大于所述第二阻值，所述第一电压值是指正极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化；
    所述主运算放大器，用于在所述斜坡信号控制器控制所述输出节点的电压趋于所述第一电压值后开启，以使所述级联运放电路的输出电压驱动所述输出节点。
  4. 根据权利要求2所述的电路，其特征在于，所述可变电阻电路包括斜坡信号控制器和可变电阻，当所述级联运放电路的失调电压为负时，所述斜坡信号控制器用于：
    在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的阻值从第一阻值渐变至第二阻值，使得所述输出节点的电压跟随所述可变电阻的阻值的渐变值降低，直至所述输出节点的电压趋于第二电压值，其中所述第一阻值大于所述第二阻值，所述第二电压值是指负极性电压值，所述可变电阻的阻值变化表征了所述第一串联电路的输出电阻的变化；
    所述主运算放大器，用于在所述斜坡信号控制器控制所述输出节点的电压趋于所述第二电压值后开启，使得所述级联运放电路的输出电压驱动所述输出节点。
  5. 根据权利要求3或4所述的电路，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的输出电阻不小于所述第一阻值，以截断所述级联运放电路和所述输出节点之间的通路。
  6. 根据权利要求3或4所述的电路，其特征在于，所述可变电阻包括第一斜坡电阻和 第二斜坡电阻中的至少一个，所述第一斜坡电阻的输出电平为第一电平，所述第二斜坡电阻的输出电平为第二电平；
    所述斜坡信号控制器具体用于通过控制所述第一电平的渐变值或者控制所述第二电平的渐变值，从而控制所述可变电阻的阻值的渐变值。
  7. 根据权利要求6所述的电路，当所述第一运放电路和所述第二运放电路均开启后，所述斜坡信号控制器用于提供第一斜坡信号；
    其中，所述第一斜坡信号用于控制第一电平的电平值从第一电平值渐变至第二电平值，从而控制所述第一斜坡电阻的阻值从高至低渐变，所述输出节点的电压从低至高渐变，直至所述输出节点的电压趋于所述第一电压值，所述第一电平值大于所述第二电平值。
  8. 根据权利要求7所述的电路，其特征在于，当所述第一斜坡电阻的阻值低于第三阻值后，所述级联运放电路的输出电压驱动所述输出节点，所述第三阻值大于或等于所述第二阻值。
  9. 根据权利要求7或8所述的电路，其特征在于，在所述第一斜坡电阻在跟随所述第一斜坡信号的变化渐变的初始状态下，所述级联运放电路和所述输出节点之间的通路断开。
  10. 根据权利要求5-9任一所述的电路，所述斜坡信号控制器具体用于在所述第一运放电路和所述辅运算放大器均开启后，控制所述可变电阻的输出电阻不小于所述第一阻值，从而截断所述级联运放电路和所述输出节点之间的通路。
  11. 根据权利要求10所述的电路，其特征在于，当所述第一运放电路和所述辅运算放大器均开启时，所述斜坡信号控制器用于提供第二斜坡信号；
    其中，所述第二斜坡信号用于控制第二电平的电平值从第三电平值渐变至第四电平值，从而控制所述第二斜坡电阻的阻值从高至低渐变，所述输出节点的电压从低至高渐变，直至所述输出节点的电压趋于所述第二电压值，所述第三电平值小于所述第四电平值。
  12. 根据权利要求11所述的电路，其特征在于，当所述第二斜坡电阻的阻值低于第三阻值后，所述级联运放电路和所述输出节点之间的通路导通，所述第三阻值大于或等于所述第二阻值。
  13. 根据权利要求11或12所述的电路，其特征在于，在所述第二斜坡电阻的阻值渐变的初始状态下，所述级联运放电路和所述输出节点之间的通路断开。
  14. 根据权利要求3-13任一所述的电路，其特征在于，所述斜坡信号控制器还包括脉冲信号生成电路和斜坡信号控制逻辑电路，所述斜坡信号控制器还包括第一斜坡电流源和第二斜坡电流源中的至少一个；
    其中，所述脉冲信号生成电路与所述斜坡信号控制逻辑电路串联，所述第一斜坡电流源和所述第二斜坡电流源并联；
    所述脉冲信号生成电路用于将输入的时钟信号生成脉冲信号，并将所述脉冲信号输入所述斜坡信号控制逻辑电路；
    所述斜坡信号控制逻辑电路用于接收自所述脉冲信号生成电路输入的脉冲信号，根据输入的所述脉冲信号生成斜坡信号，并将生成的所述斜坡信号输入斜坡电流源，所述斜坡信号包括所述第一斜坡信号或所述第二斜坡信号，所述斜坡电流源包括所述第一斜坡电流源或所述第二斜坡电流源。
  15. 根据权利要求14所述的电路，其特征在于，当所述斜坡信号控制器包括第一斜坡电流源和第二斜坡电流源时，所述斜坡信号控制器还包括单刀双掷开关，所述单刀双掷开关用于：
    当所述斜坡信号控制逻辑电路生成的斜坡信号与所述第一斜坡信号的特性相同或相似时，连通所述第一斜坡电流源；
    或者，当所述斜坡信号控制逻辑电路生成的斜坡信号与所述第二斜坡信号的特性相同或相似时，连通所述第二斜坡电流源。
  16. 根据权利要求1-15任一所述的电路，其特征在于，所述电路还包括环路补偿电路，所述环路补偿电路用于：
    通过灌电流循环抑制闭环回路中的震荡信号。
  17. 根据权利要求2所述的电路，其特征在于，所述级联运放电路为级联运放，所述级联运放电路包括至少一个所述第二运放电路，至少一个所述第二运放电路包括所述辅运算放大器与所述斜坡信号控制器。
  18. 根据权利要求2或17所述的电路，其特征在于，所述第二运放电路中的主运算放大器的失调电压高于预设阈值。
  19. 一种终端设备，其特征在于，所述终端设备包括音频负载，以及如权利要求1-18任一所述的音频负载电路。
PCT/CN2018/083521 2017-06-23 2018-04-18 一种音频处理电路及终端设备 WO2018233363A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18820785.6A EP3641338B1 (en) 2017-06-23 2018-04-18 Audio processing circuit and terminal device
US16/720,771 US10903801B2 (en) 2017-06-23 2019-12-19 Audio processing circuit and terminal device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710487751.4 2017-06-23
CN201710487751.4A CN109121043B (zh) 2017-06-23 2017-06-23 一种音频处理电路及终端设备

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/720,771 Continuation US10903801B2 (en) 2017-06-23 2019-12-19 Audio processing circuit and terminal device

Publications (1)

Publication Number Publication Date
WO2018233363A1 true WO2018233363A1 (zh) 2018-12-27

Family

ID=64733187

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/083521 WO2018233363A1 (zh) 2017-06-23 2018-04-18 一种音频处理电路及终端设备

Country Status (4)

Country Link
US (1) US10903801B2 (zh)
EP (1) EP3641338B1 (zh)
CN (1) CN109121043B (zh)
WO (1) WO2018233363A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114125658B (zh) * 2020-08-25 2023-12-19 上海艾为电子技术股份有限公司 动态范围控制电路、音频处理芯片及其音频处理方法
CN117714940B (zh) * 2024-02-05 2024-04-19 江西斐耳科技有限公司 一种aux功放链路底噪优化方法及系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2317644A1 (en) * 2009-10-30 2011-05-04 ST-Ericsson SA Amplifier activation
US20120146719A1 (en) * 2010-12-13 2012-06-14 Broadcom Corporation Amplifier with reduced on/off transient and multi-point offset compensation
CN105048980A (zh) * 2015-08-18 2015-11-11 矽力杰半导体技术(杭州)有限公司 一种d类音频放大器
US20170063309A1 (en) * 2015-08-27 2017-03-02 Qualcomm Incorporated Methods and apparatus for reducing transient glitches in audio amplifiers

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2585249B2 (ja) 1987-03-06 1997-02-26 株式会社東芝 音声増幅器のシヨツク音防止回路
US7092534B2 (en) 2004-03-02 2006-08-15 Via Telecom Co., Ltd. Method and system for reducing pop noise of a sound broadcasting instrument
EP1689075B1 (en) 2005-02-03 2018-07-11 Texas Instruments Inc. Multi-stage amplifier to reduce pop noise
EP1689076B1 (en) 2005-02-03 2019-08-07 Texas Instruments Inc. Track and hold circuit to reduce pop noise
US9014396B2 (en) * 2008-01-31 2015-04-21 Qualcomm Incorporated System and method of reducing click and pop noise in audio playback devices
JP2010087811A (ja) * 2008-09-30 2010-04-15 Sharp Corp 音声出力装置
CN102065352B (zh) * 2010-11-08 2014-09-10 中兴通讯股份有限公司 一种消除capless音频功放pop音的装置及方法
US9020165B2 (en) * 2012-10-09 2015-04-28 Silicon Laboratories Inc. Pop/click noise reduction circuitry for power-up and power-down of audio output circuitry
US9225294B2 (en) * 2013-06-28 2015-12-29 Qualcomm Incorporated Amplifier with improved noise reduction
CN103716737B (zh) * 2013-12-31 2017-07-14 杭州士兰微电子股份有限公司 音量调节电路及方法
FR3025373B1 (fr) * 2014-08-26 2018-06-08 Dolphin Integration Sa Circuit de reduction de bruit de commutation
EP3210300A4 (en) * 2014-10-24 2018-04-11 Cirrus Logic, Inc. Amplifier with adjustable ramp up/down gain for minimizing or eliminating pop noise
CN104378715B (zh) * 2014-11-25 2018-07-06 小米科技有限责任公司 降低耳机pop音的装置和方法
CN204697276U (zh) * 2015-05-25 2015-10-07 深圳市战音科技有限公司 一种音响输出音调可调的控制电路
CN205195953U (zh) * 2015-07-28 2016-04-27 东莞市东源音响灯光工程有限公司 抑制噪声干扰音频电路
US9641128B2 (en) * 2015-07-29 2017-05-02 Qualcomm Incorporated High linearity structure for amplifier
CN107994873B (zh) * 2016-10-26 2021-03-23 博通集成电路（上海）股份有限公司 在音频运算放大器中用于压制振荡噪音的方法和电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2317644A1 (en) * 2009-10-30 2011-05-04 ST-Ericsson SA Amplifier activation
US20120146719A1 (en) * 2010-12-13 2012-06-14 Broadcom Corporation Amplifier with reduced on/off transient and multi-point offset compensation
CN105048980A (zh) * 2015-08-18 2015-11-11 矽力杰半导体技术(杭州)有限公司 一种d类音频放大器
US20170063309A1 (en) * 2015-08-27 2017-03-02 Qualcomm Incorporated Methods and apparatus for reducing transient glitches in audio amplifiers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3641338A4

Also Published As

Publication number Publication date
CN109121043A (zh) 2019-01-01
US20200127613A1 (en) 2020-04-23
US10903801B2 (en) 2021-01-26
EP3641338B1 (en) 2024-02-21
CN109121043B (zh) 2021-09-03
EP3641338A1 (en) 2020-04-22
EP3641338A4 (en) 2020-07-01

Similar Documents

Publication Publication Date Title
US10720888B2 (en) Systems and methods for dynamic range enhancement using an open-loop modulator in parallel with a closed-loop modulator
EP2375566B1 (en) Duplicate feedback network in class D amplifiers
US8344797B2 (en) Systems and methods for offset cancellation method for DC-coupled audio drivers
TWI508430B (zh) 具有防爆音功能之單端輸出ｄ類放大器
US9917557B1 (en) Calibration for amplifier with configurable final output stage
US20240097633A1 (en) Audio amplifier circuitry
WO2019085427A1 (zh) 音频播放电路以及音频播放设备
TWI500258B (zh) 具有減小的輸出瞬變的放大器及其方法
WO2018233363A1 (zh) 一种音频处理电路及终端设备
US8686789B2 (en) Transient signal suppression for a class-D audio amplifier arrangement
US10321230B2 (en) Switching in an audio system with multiple playback paths
US8204251B2 (en) Amplifier apparatus and method
US9225294B2 (en) Amplifier with improved noise reduction
TWI531153B (zh) 音訊放大裝置
US8717097B2 (en) Amplifier with improved noise reduction
WO2018196507A1 (zh) 一种pop音的抑制方法、音频输出电路和终端
US10008992B1 (en) Switching in amplifier with configurable final output stage
JP5749137B2 (ja) オーディオ信号処理回路およびそれを用いた電子機器
TW202203581A (zh) 輸出驅動器及其預充電方法
CN109565261A (zh) 一种供电电路及音频播放设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18820785

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018820785

Country of ref document: EP

Effective date: 20200114