WO2018230232A1 - Dispositif de chauffage de tranche et dispositif de fabrication de semi-conducteur - Google Patents

Dispositif de chauffage de tranche et dispositif de fabrication de semi-conducteur Download PDF

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Publication number
WO2018230232A1
WO2018230232A1 PCT/JP2018/018843 JP2018018843W WO2018230232A1 WO 2018230232 A1 WO2018230232 A1 WO 2018230232A1 JP 2018018843 W JP2018018843 W JP 2018018843W WO 2018230232 A1 WO2018230232 A1 WO 2018230232A1
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WO
WIPO (PCT)
Prior art keywords
wafer
zones
wafer mounting
mounting surface
chamber
Prior art date
Application number
PCT/JP2018/018843
Other languages
English (en)
Japanese (ja)
Inventor
成伸 先田
健司 新間
悦弘 西本
晃 三雲
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to JP2019525223A priority Critical patent/JPWO2018230232A1/ja
Publication of WO2018230232A1 publication Critical patent/WO2018230232A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B3/00—Ohmic-resistance heating
    • H05B3/10—Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B3/00—Ohmic-resistance heating
    • H05B3/20—Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B3/00—Ohmic-resistance heating
    • H05B3/68—Heating arrangements specially adapted for cooking plates or analogous hot-plates
    • H05B3/74—Non-metallic plates, e.g. vitroceramic, ceramic or glassceramic hobs, also including power or control circuits

Definitions

  • the present disclosure relates to a wafer heater and a semiconductor manufacturing apparatus.
  • This application claims priority based on Japanese Patent Application No. 2017-116605 filed on June 14, 2017, and incorporates all the description content described in the above Japanese application.
  • a semiconductor manufacturing apparatus that manufactures semiconductor devices such as LSIs
  • various thin film processes such as film forming processes and etching processes represented by CVD and sputtering are performed on a semiconductor substrate (semiconductor wafer) that is an object to be processed.
  • These thin film processes are generally performed in a state where the semiconductor substrate is heated to a predetermined temperature. Therefore, a wafer heater called a susceptor for heating the semiconductor substrate placed on the placement surface from the lower surface is mounted in the vacuum chamber in which the processing is performed.
  • the wafer heater includes a wafer mounting table made of a ceramic disk-shaped member having a flat wafer mounting surface on the upper surface, and a cylindrical shape that supports the wafer mounting table from the lower surface side. And a supporting member.
  • a heating circuit composed of an electric heating coil, a thin-film resistance heating element, and the like is embedded in a plane parallel to the wafer mounting surface.
  • a pair of terminal portions provided on the lower surface side of the wafer mounting table are electrically connected to both ends of the heat generating circuit, and the heat generating circuit is connected from an external power source through the pair of terminal portions and the lead wires. Is supplied with power.
  • the wafer heater it is required to heat the semiconductor substrate uniformly over the entire surface by improving the thermal uniformity on the wafer mounting surface so that the quality of the semiconductor device as a product does not vary. .
  • the circuit pattern of the heat generating circuit is made minute so that temperature unevenness does not occur, or the wafer mounting surface is divided into a plurality of zones (multi-zones), and power is individually supplied to the heat generating circuits arranged in each of them.
  • the temperature is finely controlled for each zone.
  • the wafer heater according to the present disclosure is a wafer heater used in a chamber having a disk-shaped member made of ceramic having an upper surface as a wafer mounting surface and having a wall surface low-temperature part in a part of the inner side wall. .
  • the wafer mounting surface is demarcated into a plurality of zones as viewed from the upper surface side, and the disk-like member is provided with an individual heating circuit in each of the plurality of zones. At least one of the plurality of zones is configured such that the peripheral edge is arranged at a position facing the wall surface low temperature portion.
  • the present application discloses a semiconductor manufacturing apparatus including the wafer heater and a chamber having a wall surface low temperature part in a part of the inner side wall.
  • FIG. 1 is a schematic cross-sectional schematic diagram of a semiconductor manufacturing apparatus including a wafer heater according to a specific example of the present disclosure.
  • FIG. 2 is a schematic plan view of the semiconductor manufacturing apparatus of FIG.
  • FIG. 3 is a schematic plan view of an alternative example of the semiconductor manufacturing apparatus of FIG.
  • FIG. 4A is a schematic plan view of a semiconductor manufacturing apparatus according to an embodiment of the present disclosure.
  • FIG. 4B is a schematic plan view of a semiconductor manufacturing apparatus of a comparative example.
  • the structure in the chamber in which the wafer heater is mounted is not uniform with respect to the circumferential direction of the wafer mounting surface of the wafer heater.
  • a load lock opening / closing portion for taking in and out the wafer is provided in a part of the chamber wall. For this reason, the temperature near the opening / closing portion of the load lock on the wafer placement surface may be locally reduced as compared with other portions.
  • An embodiment of the present disclosure is a wafer heater used in a chamber having a ceramic disk-shaped member whose upper surface is a wafer mounting surface and having a wall surface low temperature portion on a part of an inner side wall.
  • the wafer mounting surface is defined by a plurality of zones viewed from the upper surface side, and the disk-like member is provided with an individual heating circuit in each of the plurality of zones. At least one of the plurality of zones is configured such that a peripheral edge thereof is disposed at a position facing the wall surface low temperature portion.
  • the heat generating circuit is embedded in the disk-shaped member.
  • the heat generating circuit is composed of an electric heating coil, a thin-film resistance heating element, or the like, and is preferably embedded in a disk-like member in a plane parallel to the wafer mounting surface.
  • a pair of terminal portions provided on the lower surface side of the wafer mounting table are electrically connected to both ends of each heat generating circuit, and power is supplied from an external power source through the pair of terminal portions.
  • the plurality of zones include a plurality of fan-shaped zones defined by dividing the wafer mounting surface in a circumferential direction of the wafer mounting surface.
  • at least one of the plurality of sector zones is arranged such that the wall surface low temperature portion is included in an angular range from end to end in the circumferential direction of the sector.
  • the wall surface low temperature part is typically exemplified by a load lock opening / closing part.
  • the plurality of zones are a plurality of circular zones that are concentric with the center of the wafer mounting surface and a ring-shaped portion that surrounds the periphery of the circular zone on the wafer mounting surface in the circumferential direction. It has a sector zone, and at least one of the plurality of sector zones is preferably arranged so that the wall surface low temperature portion is included in an angular range from end to end in the circumferential direction of the sector.
  • the plurality of heat generating circuits may each have a pair of power feeding terminal portions.
  • an embodiment of the semiconductor manufacturing apparatus includes the wafer heater, and a chamber that includes the wafer heater and has a wall surface low-temperature portion at a part of the inner side wall.
  • FIG. 1 is a schematic cross-sectional schematic diagram of a semiconductor manufacturing apparatus including a wafer heater according to a specific example of the present disclosure.
  • FIG. 1 shows a state in which a longitudinal section of the semiconductor manufacturing apparatus is viewed from the front. However, it is not a diagram that accurately shows a cross section cut by one straight line passing through the center of the wafer mounting table, but a diagram that schematically shows a cross-sectional state in order to make it easy to explain the embedded state of components. As shown in FIG.
  • a wafer heater 1 included in a semiconductor manufacturing apparatus 3 is preferably made of ceramics having a wafer mounting surface 10 a on which a semiconductor wafer W is mounted on the upper surface.
  • Flange portions that are bent outward are formed at both upper and lower ends of the support member 20, sealing materials such as O-rings and gaskets (not shown) provided on the annular end surfaces, screws (not shown) that penetrate the flange portions, etc.
  • the upper and lower ends are hermetically joined to the lower surface of the wafer mounting table 10 and the bottom surface of the chamber 2 by the coupling means. Thereby, the inside of the support member 20 can be isolated from the corrosive gas atmosphere in the chamber 2.
  • Ceramics that are suitable materials for the wafer mounting table 10 and the support member 20 include aluminum nitride, silicon nitride, silicon carbide, and aluminum oxide. Of these, aluminum nitride having high thermal conductivity is preferable.
  • the wafer mounting table 10 and the support member 20 are preferably made of the same material. Accordingly, since it can be similarly expanded and contracted during heating and cooling, problems such as warpage of the wafer mounting surface 10a due to thermal stress and damage to the joint between the wafer mounting table 10 and the support member 20 are unlikely to occur. can do.
  • a wafer heater 1 includes a central heating circuit 11 that mainly heats a central region of the wafer mounting surface 10 a in a plane parallel to the wafer mounting surface 10 a inside the wafer mounting table 10.
  • the outer peripheral heat generating circuits 12 and 13 for mainly heating the annular outer peripheral region around the central region are embedded.
  • Each of these three heat generating circuits 11, 12, and 13 has a pair of terminal portions 11a, 12a, and 13a electrically connected to both ends, and a total of these three pairs of terminal portions 11a, 12a, and 13a and those Power can be individually supplied from an external power source (not shown) through the lead wires 11b, 12b, and 13b. Therefore, the temperature of each of the three heat generating circuits 11 to 13 can be individually controlled.
  • FIG. 2 is a schematic plan view illustrating the configuration of the upper surface side of the wafer mounting table when the semiconductor manufacturing apparatus 3 of FIG. 1 is viewed in plan.
  • the wafer mounting table 10 in which the three heat generating circuits 11 to 13 are embedded has a wafer mounting surface 10a on the wafer mounting surface 10a according to the structure in the chamber 2 in which the wafer heater 1 is installed. It is divided into a circular central zone Z1 located in the central part and two fan-shaped outer peripheral zones Z2 and Z3 obtained by dividing an annular outer peripheral region located around the circular central zone Z1 in the circumferential direction.
  • a central heat generating circuit 11 (not shown in FIG. 2) is embedded in the circular central zone Z1, and outer peripheral heat generating circuits 12, 13 (not shown in FIG. 2) are embedded in the fan-shaped outer peripheral zones Z2 and Z3, respectively.
  • the structure in the chamber 2 where the wafer heater 1 is installed is not uniform with respect to the circumferential direction of the wafer mounting table 10 of the wafer heater 1.
  • the wall portion of the chamber 2 surrounding the wafer heater 1 has a rectangular shape when viewed from above, and the load lock serving as the wall surface low temperature portion of the chamber 2 is formed on the upper wall portion of FIG.
  • the opening / closing part 2a is provided. For this reason, under the influence of the load lock opening / closing portion 2a, a portion of the wafer placement surface 10a close to the load lock opening / closing portion 2a may locally become low in temperature.
  • the wall surface low temperature part is not limited to the load lock opening / closing part, and includes a part where the temperature is partially lowered by other factors of the wall surface structure.
  • the load lock opening / closing portion 2a is located within an angular range A1 from end to end in the circumferential direction of the fan-shaped, so that the heat generated in the fan-shaped outer peripheral zone Z2 is embedded.
  • the circuit 12 can set the amount of heat generation higher than other heat generation circuits. Thereby, the thermal uniformity of the wafer mounting surface 10a can be maintained.
  • the wafer mounting surface is divided into a circular central region and an annular outer peripheral region, and the outer peripheral region is equally divided into two in the circumferential direction.
  • the present invention is not limited to this, and various division patterns can be adopted depending on the structure in the chamber that may cause the thermal uniformity of the wafer mounting surface.
  • the wafer mounting surface 100a of the wafer mounting table 100 is divided into a circular central zone Z11, an annular intermediate zone Z12 around the circular central zone Z11, and an outermost annular outer peripheral region equally divided into four in the circumferential direction. It may be divided into four sector-shaped outer peripheral zones Z13 to Z16 obtained.
  • the angle is within an angular range A2 from end to end in the circumferential direction of the fan-shaped.
  • the load lock opening / closing portion 2a can be positioned, and on the two straight lines L1 and L2 drawn from the center point of the wafer mounting surface 110a toward both ends in the circumferential direction of the sector-shaped outer peripheral zone Z13, respectively. Since both end portions of the load lock opening / closing portion 2a can be substantially positioned, it is possible to further improve the thermal uniformity of the wafer mounting surface 110a. It should be noted that a plurality of zones may be included in a range corresponding to the load lock opening / closing portion 2a, that is, a range between the straight lines L1 and L2 in FIG.
  • a semiconductor manufacturing apparatus 3 as shown in FIG. 4A was produced and the thermal uniformity of the wafer mounting surface was evaluated. Specifically, first, 0.5 part by mass of yttrium oxide as a sintering aid was added to 99.5 parts by mass of the aluminum nitride powder, and a binder and an organic solvent were further added, followed by ball mill mixing to prepare a slurry. The obtained slurry was sprayed by a spray drying method to produce granules, which were press-molded to produce three molded bodies. These compacts were degreased at 700 ° C. in a nitrogen atmosphere and then sintered at 1850 ° C. in a nitrogen atmosphere to obtain three aluminum nitride sintered bodies. The obtained sintered body was processed into a disk shape having a diameter of 330 mm and a thickness of 8 mm. At this time, the surface roughness Ra was 0.8 ⁇ m, and the flatness was 50 ⁇ m.
  • One of these three aluminum nitride sintered bodies has a circular central zone Z21 having a diameter of 160 mm on one side thereof, a plurality of concentric circular conductive portions, and adjacent ones of these circular conductive portions
  • a circuit pattern having a line width of 4 mm and a thickness of 20 ⁇ m formed in a single stroke shape with linear conductive portions connecting each other was formed by screen printing tungsten paste.
  • each of the four fan-shaped outer peripheral zones Z22 to Z25 in which the annular region on the outer peripheral side of the central central portion Z21 having a diameter of 160 mm is equally divided into four in the circumferential direction is formed concentrically.
  • a cylindrical support member made of aluminum nitride (AlN) having an inner diameter of 60 mm, a height of 150 mm, and a thickness of 2 mm, having flange portions at both ends, is attached to the wafer mounting table 200 thus manufactured with a screw. Joined. Then, as shown in FIG. 4A, the other end of the support member was fixed to the bottom of the chamber such that the fan-shaped outer peripheral zone Z22 faces the load lock opening / closing part 2a.
  • the heating circuit provided for each zone was connected to a power source so that power could be supplied individually. In this way, the semiconductor manufacturing apparatus 3 of Sample 1 was manufactured.
  • the same wafer mounting table 200 as that used in the semiconductor manufacturing apparatus 3 of the sample 1 is manufactured.
  • an intermediate portion between two adjacent fan-shaped outer peripheral zones Z22 to Z23 is load-locked.
  • a semiconductor manufacturing apparatus 3 of Sample 2 was fabricated in the same manner as Sample 1 except that it was fixed in the chamber so as to face the center of the opening / closing portion 2a.
  • the load lock opening / closing portion 2a is located within the angular range from the end to the end in the circumferential direction of the fan-shaped outer peripheral zone Z22. Therefore, only the fan-shaped outer peripheral zone Z22 is substantially the load lock opening / closing portion 2a. It comes to oppose. Therefore, it is possible to satisfactorily cope with a local temperature decrease in the fan-shaped outer peripheral zone Z22 caused by the load lock opening / closing portion 2a.
  • the sample 2 is different from the sample 1 in that both the fan-shaped outer peripheral zones Z22 and Z23 partially face the load lock opening / closing portion 2a.
  • A1 A2 Angle range W Semiconductor substrate Z1 Circular central zone Z2, Z3 Fan-shaped outer peripheral zone Z11 Circular central zone Z12 Annular intermediate zone Z13-Z16 Fan-shaped outer peripheral zone Z21 Circular central zone Z22-Z25 Fan-shaped outer peripheral zone L1, L2 Linear 1 Wafer heater 2 Chamber 3
  • Semiconductor manufacturing apparatus 2a Load lock opening / closing part 10, 100, 200 Wafer mounting table 20 Support member 10a, 100a Wafer mounting surface 11 Central heating circuit 12, 13 Outer peripheral heating circuit 11a, 12a, 13a Terminal part 11b, 12b , 13b Leader

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Resistance Heating (AREA)

Abstract

L'invention concerne un dispositif de chauffage de tranche comprenant un élément en forme de disque céramique dont la surface supérieure est une surface de montage de tranche et est utilisé à l'intérieur d'une chambre ayant une section à basse température de surface de paroi sur une partie d'une paroi latérale de surface interne, la surface de montage de tranche étant définie en une pluralité de zones vues depuis le côté de surface supérieure. L'élément en forme de disque comprend des circuits de génération de chaleur individuels disposés respectivement dans la pluralité de zones. Au moins l'une de la pluralité de zones est disposée dans une position dans laquelle la périphérie de celle-ci fait face à la section basse température de surface de paroi.
PCT/JP2018/018843 2017-06-14 2018-05-16 Dispositif de chauffage de tranche et dispositif de fabrication de semi-conducteur WO2018230232A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019525223A JPWO2018230232A1 (ja) 2017-06-14 2018-05-16 ウエハ加熱ヒータ及び半導体製造装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017116605 2017-06-14
JP2017-116605 2017-06-14

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WO2018230232A1 true WO2018230232A1 (fr) 2018-12-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115087759A (zh) * 2020-01-15 2022-09-20 应用材料公司 用于碳化合物膜沉积的方法和设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332410A (ja) * 2005-05-27 2006-12-07 Kyocera Corp ウェハ加熱装置およびそれを用いた半導体製造装置
JP2010225941A (ja) * 2009-03-24 2010-10-07 Tokyo Electron Ltd 載置台構造及び処理装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332410A (ja) * 2005-05-27 2006-12-07 Kyocera Corp ウェハ加熱装置およびそれを用いた半導体製造装置
JP2010225941A (ja) * 2009-03-24 2010-10-07 Tokyo Electron Ltd 載置台構造及び処理装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115087759A (zh) * 2020-01-15 2022-09-20 应用材料公司 用于碳化合物膜沉积的方法和设备
EP4090788A4 (fr) * 2020-01-15 2024-01-17 Applied Materials Inc Procédés et appareil de dépôt de film de composé carboné

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