WO2018223963A1 - Circuit de balayage, circuit de commande de grille, panneau d'affichage et procédé de commande associé, et dispositif d'affichage - Google Patents

Circuit de balayage, circuit de commande de grille, panneau d'affichage et procédé de commande associé, et dispositif d'affichage Download PDF

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Publication number
WO2018223963A1
WO2018223963A1 PCT/CN2018/089969 CN2018089969W WO2018223963A1 WO 2018223963 A1 WO2018223963 A1 WO 2018223963A1 CN 2018089969 W CN2018089969 W CN 2018089969W WO 2018223963 A1 WO2018223963 A1 WO 2018223963A1
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Prior art keywords
circuit
signal
type transistor
shift register
terminal
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PCT/CN2018/089969
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English (en)
Chinese (zh)
Inventor
王志冲
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京东方科技集团股份有限公司
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Publication of WO2018223963A1 publication Critical patent/WO2018223963A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • Embodiments of the present disclosure relate to a scan circuit, a gate drive circuit, a display panel, a method of driving the same, and a display device.
  • the Organic Light Emitting Diode (OLED) display device has the characteristics of wide viewing angle, high contrast, and fast response. Moreover, the organic light emitting diode display device has an advantage of higher luminance, lower driving voltage, and the like than the inorganic light emitting display device. Due to the above characteristics and advantages, organic light emitting diode (OLED) display devices have been receiving widespread attention and can be applied to devices having display functions such as mobile phones, displays, notebook computers, digital cameras, instrumentation, and the like.
  • At least one embodiment of the present disclosure provides a scanning circuit including a shift register circuit and a first signal generating circuit.
  • the shift register circuit has a first signal output and is configured to output a first scan signal;
  • the first signal generation circuit has a second signal output and is configured to be based on the first refresh control signal and the first scan signal A second scan signal is generated and output.
  • the scanning circuit further includes a first node; the first signal output is coupled to the first node and configured to output the first scan signal;
  • the first signal generating circuit further has a first signal input end connected to the first node and a second signal input end configured to receive the first scan And a signal, the second signal input end of the first signal generating circuit is connected to the first refresh control signal end to receive the first refresh control signal.
  • the first signal generating circuit includes a first NAND circuit; and the first NAND circuit is configured to pair the first scan signal and the first refresh The control signal performs a NAND operation to generate the second scan signal.
  • the first NAND circuit includes a first N-type transistor for the first NAND circuit, and a second N for the first NAND circuit a transistor, a first P-type transistor for the first NAND circuit, and a second P-type transistor for the first NAND circuit; the first N for the first NAND circuit The first end of the transistor is connected to the second power terminal, and the control terminal of the first N-type transistor for the first NAND circuit is connected to the second signal input terminal of the first signal generating circuit; a first end of the second N-type transistor for the first NAND circuit is connected to the second end of the first N-type transistor for the first NAND circuit, a control end of the first N-type transistor of the first NAND circuit is configured as a first signal input end of the first signal generating circuit, and is connected to the first node, wherein the first NAND circuit is used a second end of the second N-type transistor is coupled to the second signal output; the a first end of the first P-type transistor of the
  • the shift register circuit further has an on signal input terminal, a first clock signal input terminal, and a second clock signal input terminal, and includes an input circuit and an inverter and a Two nodes.
  • the input circuit includes a first end, a second end, a third end, and an output end; the first end of the input circuit and the second end of the input circuit are respectively configured as the first clock signal input end and the a second clock signal input end, and is respectively connected to the first clock signal providing end and the second clock signal providing end to respectively receive the first clock signal and the second clock signal; the third end configuration of the input circuit An on signal input end of the shift register circuit to receive an on signal; the input circuit is configured to generate an input control signal according to the on signal, the first clock signal, and the second clock signal; An output of the circuit is coupled to the second node and configured to output the input control signal.
  • the inverter includes an input end connected to the second node to receive the input control signal, and an output end, the inverter is configured to receive the input control signal Performing an inversion to generate the first scan signal; an output of the inverter is coupled to the first node, and configured as the first signal output for outputting the first scan signal .
  • the input circuit includes a first N-type transistor for the shift register circuit, a second N-type transistor for the shift register circuit, a first P-type transistor of the shift register circuit, a second P-type transistor for the shift register circuit, a third N-type transistor for the shift register circuit, for the shift register a fourth N-type transistor of the circuit, a third P-type transistor for the shift register circuit, and a fourth P-type transistor for the shift register circuit;
  • the first for the shift register circuit a first end of an N-type transistor is coupled to a second power supply terminal, and a control terminal of the first N-type transistor for the shift register circuit is coupled to the second clock signal supply terminal;
  • a first end of the second N-type transistor of the shift register circuit is coupled to the second end of the first N-type transistor for the shift register circuit, the first for the shift register circuit
  • the control terminal of the two N-type transistor and the turn-on signal of the shift register circuit Connected to the input terminal, the second end of the second
  • a second end of the fourth N-type transistor for the shift register circuit is connected to the second node;
  • the second end of the third P-type transistor for the shift register circuit is a second node connected, the control terminal of the third P-type transistor for the shift register circuit being connected to the first node;
  • the fourth P-type transistor for the shift register circuit a first end is connected to the first power supply end, and a control end of the fourth P-type transistor for the shift register circuit is connected to the second clock signal supply end, the A second end of the fourth P-type transistor of the register circuit is coupled to the first end of the third P-type transistor for the shift register circuit.
  • the inverter includes a fifth N-type transistor for the shift register circuit and a fifth P-type transistor for the shift register circuit; the fifth N for the shift register circuit a first end of the transistor is connected to the second power terminal, and a control end of the fifth N-type transistor for the shift register circuit is connected to the second node, the a second end of the fifth N-type transistor of the register circuit is connected to the first node; a first end of the fifth P-type transistor for the shift register circuit is connected to the first power terminal, a control terminal of a fifth P-type transistor for the shift register circuit is connected to the second node, and a second end of the fifth P-type transistor for the shift register circuit and the first A node is connected.
  • the scanning circuit further includes a reset circuit connected to the second node and configured to perform an initial reset on the first node; a reset circuit including a P-type transistor for the reset circuit, the first end of the P-type transistor for the reset circuit being connected to a first power supply terminal, the P-type transistor for the reset circuit The control terminal is configured to receive an initialization reset signal, and the second end of the P-type transistor for the reset circuit is connected to the second node.
  • the scanning circuit further includes a second signal generating circuit having a first signal input terminal, a second signal input terminal, and a third signal An output terminal; a first signal input end of the second signal generating circuit is coupled to the first node, and configured to receive the first scan signal; a second signal input end of the second signal generating circuit is coupled to a second refresh control signal end to receive a second refresh control signal provided by the second refresh control signal end; the second signal generating circuit configured to generate based on the first scan signal and the second refresh control signal The third scan signal.
  • a second signal generating circuit having a first signal input terminal, a second signal input terminal, and a third signal An output terminal; a first signal input end of the second signal generating circuit is coupled to the first node, and configured to receive the first scan signal; a second signal input end of the second signal generating circuit is coupled to a second refresh control signal end to receive a second refresh control signal provided by the second refresh control signal end; the second signal generating circuit configured to generate based on the first scan signal and the
  • the second signal generating circuit includes a second NAND circuit, and the second NAND circuit includes a first input end, a second input end, and a signal output end, which are respectively configured as the first of the second signal generating circuit a signal input end, a second signal input end, and a third signal output end, wherein the second NAND circuit is configured to perform NAND operation on the first scan signal and the second refresh control signal to generate the third Scan the signal.
  • the second NAND circuit includes a first N-type transistor for the second NAND circuit and a second N for the second NAND circuit a transistor, a first P-type transistor for the second NAND circuit, and a second P-type transistor for the second NAND circuit; the first N for the second NAND circuit The first end of the transistor is connected to the second power terminal, and the control terminal of the first N-type transistor for the second NAND circuit is connected to the second signal input terminal of the second signal generating circuit The first end of the second N-type transistor for the second NAND circuit is connected to the second end of the first N-type transistor for the second NAND circuit, a control end of the second N-type transistor of the second NAND circuit is connected to the first node, and the second end of the second N-type transistor for the second NAND circuit is opposite to the third a signal output end is connected; the first end of the first P-type transistor for the second NAND circuit and the first power source Connected, the control end of the first P-
  • At least one embodiment of the present disclosure further provides a gate driving circuit including N cascaded scanning circuits; each stage of the scanning circuit shift register circuit has a signal output end and an open signal input end; The turn-on signal input end of the shift register circuit of the m-th scanning circuit is connected to the first signal output end of the scanning circuit of the m-1th stage, N is an integer greater than or equal to 1, and m is greater than 1 and less than or equal to N The integer.
  • the first refresh control signal terminal connected to the first signal generating circuit of the scanning circuit of the 2k-1th stage is the first signal source; the scanning of the 2kth level
  • the first refresh control signal end connected to the first signal generating circuit of the circuit is a second signal source, and k is an integer greater than or equal to 1 and less than or equal to N/2.
  • each stage of the scanning circuit further includes a second signal generating circuit; and a second refresh control of the second signal generating circuit connection of the 2k-1th stage scanning circuit
  • the signal end is the second signal source
  • the second refresh control signal end connected to the second signal generating circuit of the 2kth stage scanning circuit is the first signal source.
  • At least one embodiment of the present disclosure further provides a display panel including a pixel circuit array and the above-described gate driving circuit.
  • the pixel circuit array includes a plurality of pixel circuits arranged in an array, the plurality of pixel circuits are arranged in N rows in a column direction, and each of the pixel circuits includes a light emitting control end and a selection control end; a first signal output end of the scan circuit is connected to the light emission control end of the pixel circuit of the jth row, and a second signal output end of the jth stage scan circuit is connected to the selection control end of the pixel circuit of the jth row , j is an integer greater than or equal to 1 and less than or equal to N.
  • each of the pixel circuits further includes a reset control terminal; a second signal output of the m-1th stage of the scan circuit is coupled to the pixel circuit of the mth row Reset control terminal.
  • each of the pixel circuits further includes a reset control terminal; each stage of the scan circuit further includes a second signal generation circuit, and the second signal generation circuit includes a third signal And an output terminal; and a third signal output end of the j-th scanning circuit is connected to a reset control terminal of the pixel circuit of the jth row.
  • At least one embodiment of the present disclosure further provides a display device including the above-described scan circuit, gate drive circuit, or display panel.
  • At least one embodiment of the present disclosure further provides a driving method of a display panel, comprising: causing a shift register circuit of the scanning circuit of the jth stage to generate the first scan signal, and the first scan a signal supplied to a first signal input terminal of the first signal generating circuit of the scanning circuit of the jth stage and an emission control terminal of the pixel circuit of the jth row; and a first scan circuit of the jth stage
  • the signal generating circuit generates the second scan signal based on the first scan signal and the first refresh control signal, and supplies the second scan signal to a selection control terminal of the pixel circuit of the jth row.
  • each of the pixel circuits further includes a reset control terminal; the driving method further includes: generating a first signal generating circuit of the scanning circuit of the m-1th stage The second scan signal is supplied to a reset control terminal of the pixel circuit of the mth row; or the third scan signal generated by the second signal generating circuit of the scanning circuit of the jth stage is supplied to the jth The reset control terminal of the pixel circuit of the row.
  • the display period of the display panel includes a refresh phase and a non-refresh phase; the driving method includes: in the non-refresh phase, causing the first signal generating circuit The second signal input receives a low level refresh control signal.
  • the shift register circuit generates the first scan signal in response to a clock signal; the driving method includes: in the refreshing phase, to the shift register circuit Providing a clock signal having a first pulse width, and in the non-refresh phase, providing a clock signal having a second pulse width to the shift register circuit; the first pulse width being greater than the second pulse width.
  • the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first end of all or part of the transistor in the embodiment of the present disclosure is The second end is interchangeable as needed.
  • the first end of the transistor of the embodiment of the present disclosure may be a source, and the second end may be a drain; or the first end of the transistor is a drain and the second end is a source.
  • the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor.
  • the embodiment of the present disclosure does not limit the type of the transistor, and those skilled in the art can implement the N-type and/or P-type transistor according to actual needs. Embodiments disclosed.
  • At least one embodiment of the present disclosure provides a driving circuit for a display panel including an odd-numbered row of GOA cells and an even-numbered row of GOA cells, wherein the odd-numbered rows of GOA cells correspond to driving odd-numbered rows of pixel circuits, and the even-numbered rows of GOA cells correspond to An even row pixel circuit is driven, each of the odd row GOA unit and the even row GOA unit including an input module, an inverter, and a first NAND circuit.
  • the input module first clock signal providing end is connected to the second clock signal providing end, and the input module is configured to receive an initial signal, and according to the initial signal, the first clock signal provided by the first clock signal providing end Generating an input control signal with a second clock signal provided by the second clock signal providing terminal;
  • the inverter is connected to the input module, and the inverter is configured to reverse the input control signal And outputting the first scan signal to the pixel circuit corresponding to the GOA unit of the row;
  • the first NAND circuit the first input end of the first NAND circuit is connected to the inverter, the first NAND circuit
  • the second input end is connected to the refresh control signal end, and the first NAND circuit is configured to perform a NAND operation on the refresh control signal provided by the first scan signal and the refresh control signal end to output a second scan signal a pixel circuit corresponding to the GOA unit of the row.
  • each GOA unit includes an input module, an inverter, and a first NAND circuit, and the first clock provided by the first clock signal providing end according to the initial signal by the input module
  • the signal and the second clock signal provided by the second clock signal providing end generate an input control signal
  • the inverter inverts the input control signal to output the EM signal to the pixel circuit corresponding to the GOA unit of the row
  • the first NAND circuit pair The first scan signal and the refresh control signal provided by the refresh control signal terminal perform NAND operation to output the second scan signal Gate signal to the pixel circuit corresponding to the GOA unit of the row.
  • the first scan signal output by the local GOA unit is used as an initial signal of the next row of GOA units, and the second scan signal output by the local GOA unit is used as the next row of GOA.
  • each of the GOA units further includes a reset circuit for initializing reset of the inverter output.
  • the input module includes: a first NMOS transistor, a first end of the first NMOS transistor is connected to a second power terminal, and a control end of the first NMOS transistor Connected to the second clock signal supply end; the second NMOS transistor, the first end of the second NMOS transistor is connected to the second end of the first NMOS transistor, and the control end of the second NMOS transistor
  • the signal input end is connected to the first PMOS transistor, the first end of the first PMOS transistor is connected to the first power supply end, and the control end of the first PMOS transistor is connected to the first clock signal supply end;
  • a PMOS transistor, a first end of the second PMOS transistor is connected to a second end of the first PMOS transistor, a control end of the second PMOS transistor is connected to the signal input end, and a second PMOS transistor is connected
  • the second end and the second end of the second NMOS transistor are both connected to the second node, the second node serves as an output end of the input module
  • the inverter includes: a fifth NMOS transistor, a first end of the fifth NMOS transistor is connected to the second power terminal, and the fifth NMOS transistor a control terminal connected to the second node; a fifth PMOS transistor, a first end of the fifth PMOS transistor is connected to the first power terminal, and a control end of the fifth PMOS transistor and the second node Connected, the second end of the fifth PMOS transistor and the second end of the fifth NMOS transistor are both connected to the first node, and the first node serves as an output end of the inverter.
  • the first NAND circuit includes: a sixth NMOS transistor, a first end of the sixth NMOS transistor is connected to the second power terminal; and a seventh NMOS transistor a first end of the seventh NMOS transistor is connected to a second end of the sixth NMOS transistor, a control end of the seventh NMOS transistor is connected to the first node, and a seventh PMOS transistor is in a seventh a first end of the PMOS transistor is connected to the first power supply end, and a control end of the seventh PMOS transistor is connected to the control end of the sixth NMOS transistor, and is connected to the refresh control signal end, the seventh PMOS The second end of the tube and the second end of the seventh NMOS tube are both connected to the third node, the third node is the output end of the first NAND circuit; the eighth PMOS tube, the eighth PMOS The first end of the tube is connected to the first power end, the control end of the eighth PMOS tube is connected to the first node, and the second end
  • the reset circuit includes: a sixth PMOS transistor, a first end of the sixth PMOS transistor is connected to the first power terminal, and a control terminal of the sixth PMOS transistor And receiving an initialization reset signal, and the second end of the sixth PMOS transistor is connected to an output end of the input module.
  • the row GOA unit when the row GOA unit is an odd row GOA unit, the row GOA unit further includes a second NAND circuit, the second NAND circuit An input is connected to the inverter, a second input of the second NAND circuit is connected to a second refresh control signal end, and the second NAND circuit is configured to the first scan signal and the The second refresh control signal provided by the second refresh control signal terminal performs a NAND operation to output a reset signal to the pixel circuit corresponding to the LOA unit of the row.
  • the row GOA unit when the row GOA unit is an even row GOA unit, the row GOA unit further includes a second NAND circuit, and the second NAND circuit An input is connected to the inverter, a second input of the second NAND circuit is connected to a second refresh control signal end, and the second NAND circuit is configured to the first scan signal and the The second refresh control signal provided by the second refresh control signal terminal performs a NAND operation to output a reset signal to the pixel circuit corresponding to the LOA unit of the row.
  • the second NAND circuit includes: an eighth NMOS transistor, a first end of the eighth NMOS transistor is connected to the second power terminal; and a ninth NMOS transistor a first end of the ninth NMOS transistor is connected to a second end of the eighth NMOS transistor, a control end of the ninth NMOS transistor is connected to the first node; a ninth PMOS transistor, the ninth a first end of the PMOS transistor is connected to the first power supply end, and a control end of the ninth PMOS transistor is connected to the control end of the eighth NMOS transistor, and corresponding to the second refresh control signal end or the first
  • the second refresh control signal terminal is connected, the second end of the ninth PMOS transistor and the second end of the ninth NMOS transistor are both connected to the fourth node, and the fourth node is used as the output of the second NAND circuit.
  • the first end of the tenth PMOS transistor is connected to the first power terminal, the control end of the tenth PMOS transistor is connected to the first node, and the tenth PMOS transistor is The second end is connected to the fourth node.
  • At least one embodiment of the present disclosure also provides a display device including the above display panel or the above-described driving circuit.
  • 1 is a schematic diagram of a pixel circuit
  • FIG. 2 is a timing diagram for driving the pixel circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a scanning circuit for illustrating one embodiment of the present disclosure
  • FIG. 4 is an exemplary circuit diagram for illustrating a scan circuit provided by one embodiment of the present disclosure
  • FIG. 5 is an exemplary circuit diagram for illustrating another scanning circuit provided by one embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of driving according to an embodiment of the present disclosure.
  • FIG. 7 is another driving timing diagram provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display panel provided in a full-board refresh mode according to at least one embodiment of the present disclosure
  • FIG. 9 is a schematic illustration of a display panel provided in a partial refresh mode according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram for illustrating a scanning circuit provided by another embodiment of the present disclosure.
  • FIG. 11 is an exemplary circuit diagram for illustrating a scan circuit provided by another embodiment of the present disclosure.
  • FIG. 12 is an exemplary circuit diagram for illustrating another scanning circuit provided by an embodiment of the present disclosure.
  • FIG. 13A is an exemplary block diagram of a scan circuit according to an embodiment of the present disclosure.
  • FIG. 13B is an exemplary block diagram of a scan circuit provided by another embodiment of the present disclosure.
  • FIG. 13C is a driving timing diagram of a second signal output circuit according to an embodiment of the present disclosure.
  • FIG. 13D is another driving timing diagram of a second signal output circuit according to an embodiment of the present disclosure.
  • FIG. 13E is a timing diagram of driving provided by another embodiment of the present disclosure.
  • FIG. 14A is an exemplary block diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 14B is an exemplary block diagram of another gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 15A is an exemplary block diagram of a display panel according to at least one embodiment of the present disclosure.
  • 15B is an exemplary block diagram of another display panel provided by at least one embodiment of the present disclosure.
  • 16 is an exemplary block diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 17 is another exemplary block diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 18 is still another driving timing diagram provided by an embodiment of the present disclosure.
  • GOA Gate driver On Array
  • driving a current display panel typically requires at least two gate drive circuits, thereby resulting in a wider frame of the display panel and a reduced user experience. Furthermore, the inventors of the present disclosure have also noticed that the driving power consumption of current display panels is high. An exemplary explanation will be given below with reference to FIGS. 1 and 2.
  • the display panel includes display pixels arranged in an array, each of which has, for example, a pixel circuit having a compensation function (eg, a threshold compensation function) as shown in FIG.
  • the pixel circuit has a light-emitting control terminal EM, a selection control terminal GAT and a reset control terminal RESE, and includes a storage capacitor C1, a light-emitting element EL, a first transistor T1, a second transistor T2, and a third transistor T3.
  • the fifth transistor T5 and the seventh transistor T7 are connected to the reference power supply terminal Vref
  • the first transistor T1 and the fourth transistor T4 are connected to the data terminal DAT and the initial voltage terminal Vini, respectively.
  • the light emitting element EL may be, for example, an OLED (Organic Light-Emitting Diode).
  • the display panel is an OLED display panel.
  • the transistor can be made of, for example, LTPS (Low Temperature Poly-silicon) as a material for the active layer.
  • the light emitting element EL and the third transistor T3 are respectively connected to the first power terminal VDD and the second power terminal VSS, where the first power terminal VDD and the second power terminal VSS may each output a DC voltage, and The voltage outputted by the first power terminal VDD may be greater than the voltage output by the second power terminal VSS, and the second power terminal VSS may be, for example, a ground terminal or a common low voltage terminal, but embodiments of the present disclosure are not limited thereto.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors, that is, in the first transistor.
  • the control terminals of the T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are in an on state when receiving a low level signal (pulse signal) .
  • the third transistor T3 The light emitting element EL can be driven to emit light.
  • the gate driving circuit applies the above-described light emission control signal, selection control signal, and reset control signal to the display pixels of the display panel row by row, display and refresh of the image can be realized.
  • the inventors of the present disclosure have noticed that since the pulse widths of the light emission control signal and the selection control signal are different, it is necessary to separately provide a gate drive circuit for the light emission control terminal EM and the selection control terminal GAT of the pixel circuit (for example, EM GOA needs to be set) Two GOA) with Gate GOA, thus causing the border of the display panel (eg, the left and right borders of the display panel) to be relatively wide, which is contrary to the consumer's expectation of a narrow bezel of the electronic product having the display panel.
  • the inventors of the present disclosure also note that when driving the current display panel, different display pixels of the display panel have the same refresh frequency, which makes the driving power consumption of the display panel higher.
  • Embodiments of the present disclosure provide a scanning circuit, a gate driving circuit, a display panel, a driving method thereof, and a display device, which can respectively provide illumination for an illumination control terminal EM and a selection control terminal GAT of a pixel circuit of a display pixel
  • the control signal and the selection control signal can thereby reduce the size of the gate drive circuit and the width of the display panel bezel.
  • At least one embodiment of the present disclosure provides a scanning circuit including a shift register circuit and a first signal generating circuit.
  • the shift register circuit has a first signal output and is configured to output a first scan signal;
  • the first signal generation circuit has a second signal output and is configured to generate and output a second scan based on the first refresh control signal and the first scan signal signal.
  • the scanning circuit can generate and output a first scan signal and a second scan signal having different pulse widths, and thus can be respectively provided for the illumination control terminal EM and the selection control terminal GAT of the pixel circuit (for example, the pixel circuit shown in FIG. 1) Illumination control signal and selection control signal.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including N cascaded scan circuits described above, whereby the size of the gate driving circuit can be reduced. At least one embodiment of the present disclosure further provides a display panel including a pixel circuit array and the above-described gate driving circuit, whereby the width of the display panel bezel can be reduced.
  • FIG. 13A is a schematic block diagram of a scanning circuit provided by an embodiment of the present disclosure.
  • the scanning circuit 310 includes a shift register circuit 311, a first signal generating circuit 312, and a first node 361.
  • the scanning circuit shown in FIG. 13A can be used for the gate driving circuit 350 shown in FIG. 14A and the display panel 300 shown in FIG. 15A.
  • the shift register circuit 311 has a first signal output terminal OUT1 and is configured to output a first scan signal.
  • the shift register circuit 311 further has an open signal input terminal INP, a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2; the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are respectively connected to the first clock
  • the signal supply terminal CLK and the second clock signal supply terminal CLKB respectively receive the first clock signal and the second clock signal;
  • the turn-on signal input terminal INP is configured to receive the turn-on signal;
  • the first signal output terminal OUT1 is connected to the first node 361 and
  • the first scan signal is configured to be output, and the first scan signal is shifted backward in time by a pulse width of one clock signal compared to the on signal.
  • the first scan signal outputted by the first signal output terminal OUT1 is EM1;
  • the ON signal received by the ON signal input terminal IN 311 is EM1
  • the first scan signal outputted by the first signal output terminal OUT1 is EM2.
  • the ports and functions of the first signal generating circuit 312 will be exemplarily explained below with reference to Figs. 13A, 13C and 13D.
  • the first signal generating circuit 312 has a first signal input terminal IN1, a second signal input terminal IN2, and a second signal output terminal OUT2; the first signal input terminal IN1 of the first signal generating circuit 312 is connected to the first signal input terminal IN1.
  • a node 361 configured to receive the first scan signal;
  • the second signal input terminal IN2 of the first signal generating circuit 312 is coupled to the first refresh control signal terminal REP1 to receive the first refresh control signal;
  • the second scan signal is configured to generate and output a second scan signal based on the first refresh control signal and the first scan signal;
  • the second signal output terminal OUT2 is configured to output the second scan signal.
  • the first signal generating circuit 312 is configured to generate and generate a high level signal when both the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 receive a high level signal.
  • the low level signal is output; the first signal generating circuit 312 is further configured to receive at any one of the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 In the case of a low level signal, a high level signal is generated and output.
  • the specific structure of the first signal generating circuit 312 and the shift register circuit 311 will be explained after explaining the gate driving circuit 350 including the scanning circuit 310 and the display panel 300.
  • the scanning circuit provided by the embodiment of the present disclosure is exemplarily described with reference to FIG. 13C and FIG. 13D for the principle that the illumination control terminal EM and the selection control terminal GAT of the pixel circuit respectively provide the illumination control signal and the selection control signal.
  • the first signal input terminal IN1 of the first signal generating circuit 312 receives the output of the first signal output terminal OUT1.
  • the first scan signal) and the second signal input terminal IN2 receive at least one low level signal.
  • the second signal output terminal OUT2 outputs a high voltage.
  • the third stage st3 the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 31 receive a high level signal.
  • the second signal output terminal OUT2 outputs a low power. Flat signal.
  • the second scan signal output by the second signal output terminal OUT2 shown in FIGS. 13C and 13D can be used as the selection control signal of the pixel circuit, by configuring the first signal generation circuit 312 to be based on the first refresh control signal Generating and outputting a second scan signal with the first scan signal, whereby the scan circuit can respectively provide an illumination control signal and a selection control signal for the illumination control terminal EM of the pixel circuit and the selection control terminal GAT, without the illumination control terminal for the pixel circuit
  • the EM and the selection control terminal GAT set two scanning circuits, which reduces the number of circuits, and thus can reduce the frame size of the display panel including the scanning circuit 310.
  • first stage st1, the second stage st2, the third stage st3, and the fourth stage st4 of FIG. 13C may correspond to the first stage, the second stage, the third stage, and the fourth stage shown in FIG. 6, respectively.
  • first scan signal outputted by the first signal output terminal OUT1, the first refresh control signal output by the first refresh control terminal REP1, and the second scan output signal outputted by the second signal output terminal OUT2 may respectively correspond to the identifier EM1.
  • the specific structure (the pulse width and the low level of the first refresh control signal) provided by the first refresh control signal terminal REP1 may be according to actual application requirements (for example, output to the second signal output terminal OUT2).
  • the requirement of the second scan signal, or the requirement of the pixel circuit for selecting the control signal, is set, and the embodiment of the present disclosure does not specifically limit this.
  • the selection control signal required to select the control terminal GAT may be the second scan signal shown in FIGS. 13C and 13D, that is, in the third stage st3 is low.
  • Flat eg, 0V
  • a second scan signal that is high at the other three stages eg, greater than 0V.
  • the first refresh control signal is at a high level in the third stage st3, that is, the first refresh control signal is made high in a stage where the second scan signal needs to be low. Level.
  • FIGS. 13C and 13D the second scan signal shown in FIGS. 13C and 13D
  • the first refresh control signal may be at a low level in the second phase st2, so that the second scan signal may be at a high level in the second phase st2, and thus the second scan is made
  • the signal and the first scan signal have different pulse widths.
  • the first refresh control signal may be a second scan signal having a low level at both the first stage st1 and the fourth stage st4; and, for example, as shown in FIG. 13D, the first refresh control signal is further It may be that the first stage st1 is at a high level and the fourth stage st4 is at a low level.
  • the first refresh control signal output by the first refresh control signal terminal REP1 may be a square wave signal.
  • the specific structure of the second scan signal output by the second signal output terminal OUT2 can be adjusted by the first refresh control signal to meet the driving requirements of different pixel circuits.
  • the width of the low-level pulse of the second scan signal is equal to the pulse width of the high level of the first refresh control signal, and therefore, the pulse of the high level of the first refresh control signal can be adjusted.
  • the width adjusts the width of the low-level pulse of the second scan signal such that the width of the low-level pulse of the second scan signal is not limited to half the width of the high-level pulse of the first scan signal shown in FIG. 13C.
  • the low-level pulse of the second scan signal can be in the second stage, whereby Meet the driving needs of different pixel circuits.
  • the gate driving circuit 350 provided by the embodiment of the present disclosure will be exemplarily described below with reference to FIG. 14A.
  • the gate driving circuit 350 includes N scanning circuits 310 cascaded (for example, cascaded in the column direction), and the shift register circuit 311 of each stage scanning circuit 310 has a first signal output terminal OUT1 and Turn on the signal input INP.
  • the turn-on signal input terminal INP of the shift register circuit 311 of the mth-th scan circuit 310 is connected to the first signal output terminal OUT1 of the m-1th-th scan circuit 310, and is configured to receive the m-1th.
  • the first scan signal output from the stage scanning circuit 310 serves as an on signal of the shift register circuit 311 of the mth stage scanning circuit 310.
  • N is an integer greater than or equal to 1
  • m is an integer greater than 1 and less than or equal to N.
  • the turn-on signal input terminal INP of the shift register circuit 311 located in the first row is configured to receive the turn-on signal STV (see FIG. 6), which may be provided, for example, by the timing control circuit 330 (see FIG. 15B).
  • the shift register circuit 311 of the first stage scanning circuit 310 outputs the first scan signal EM1 based on the turn-on signal STV, the first clock signal, and the second clock signal, and supplies the first scan signal EM1.
  • the turn-on signal input terminal INP of the shift register circuit 311 of the second-stage scan circuit 310 is output to output the first scan signal EM2, and is supplied to the turn-on signal input terminal INP of the shift register circuit 311 of the third-stage scan circuit 310.
  • the first scan signal EM(n-1) output from the shift register circuit 311 of the N-1th stage first stage scanning circuit 310 is supplied to the shift register circuit 311 of the Nth stage first scan circuit 310 Signal input INP.
  • the first scan signal outputted by the shift register circuit 311 of each stage of the first stage scanning circuit 310 is compared with the first scan signal outputted by the shift register circuit 311 of the previous stage scan circuit 310. , shifting the pulse width of one clock signal backward in time.
  • the first signal generating circuit 312 of the 2k-1th scanning circuit 310 (that is, the scanning circuit 310 located in the odd rows, corresponding to the odd row GOA unit 100 shown in FIG. 4) is connected first.
  • the refresh control signal terminal REP1 is the first signal source ENBO; the second signal scanning circuit 310 (that is, the scan circuit 310 located in the even row, corresponding to the even-line GOA unit 200 shown in FIG. 5) of the first signal generating circuit 312
  • the connected first refresh control signal terminal REP1 is a second signal source ENBE (see FIG.
  • the first signal source ENBO provides a first refresh control signal for the first signal generating circuit 312 of the odd-numbered scanning circuit 310
  • the second signal source ENBE provides a first refresh control signal to the first signal generation circuit 312 of the even-numbered scanning circuit 310.
  • k is an integer greater than or equal to 1 and less than or equal to N/2. It should be noted that, when N is an odd number, the first refresh control signal terminal REP1 connected to the Nth stage scanning circuit 310 is the first signal source ENBO.
  • the second signal input terminal IN2 of the first signal generating circuit 312 of the 2k-1th stage scanning circuit 310 By connecting the second signal input terminal IN2 of the first signal generating circuit 312 of the 2k-1th stage scanning circuit 310 to the first signal source ENBO, and passing the first signal generating circuit 312 of the 2kth stage scanning circuit 310
  • the second signal input terminal IN2 is connected to the second signal source ENBE, and it is not necessary to provide a first refresh control signal terminal REP1 for each row of scanning circuits, whereby the circuit structure can be simplified and the size of the gate driving circuit 350 can be reduced.
  • the number of high-level pulses of the first refresh control signal supplied from the first signal source ENBO and the second signal source ENBE depends on the number of stages of the scan circuit 310 of the gate drive circuit 350.
  • the sum of the number of high-level pulses provided by the first signal source ENBO and the number of high-level pulses of the first refresh control signal provided by the second signal source ENBE may be equal to the scan circuit 310 of the gate driving circuit 350.
  • the number N whereby the first signal source ENBO and the second signal source ENBE cooperate with each other, so that the included second signal output terminal OUT2 of the N-stage scanning circuit outputs N low pulse signals, but the embodiment of the present disclosure does not Limited to this.
  • the number of high-level pulses of the refresh signal provided by the second signal source ENBE is k
  • the high-level pulse of the refresh signal provided by the first signal source ENBO The number of the signals is k or k+1 (in the case where N is an odd number, the number of high-level pulses of the refresh signal supplied from the first signal source ENBO is k+1).
  • the width of the high-level pulse of the first refresh control signal provided by the first signal source ENBO and the second signal source ENBE depends on the pixel circuit's requirement for selecting the pulse width of the control signal. For details, please refer to FIG. 13C and FIG. 13D. The embodiments are not described here.
  • the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 312 of the second-kth scanning circuit 310 respectively receive the first scan.
  • the refresh signal provided by the signal EM2 and the second signal source ENBE generates and outputs a second scan signal Gate2.
  • the specific principle of generating the second scan signal Gate2 refer to the principle that the first signal generating circuit 312 generates the second scan signal Gate1, and details are not described herein again.
  • the first refresh control signal provided by the first signal source ENBO and the second signal source ENBE is not limited to the form shown in FIG. 6. According to actual application requirements, the first signal source ENBO and the second signal source ENBE are further It may be in the form that the signals of the first refresh control signal provided by the first signal source ENBO and the second signal source ENBE shown in FIG. 6 are modified in the first stage st1 - the fourth stage st4 to be shown in FIG. 13E.
  • the refresh signal provided by the second signal source ENBE is opposite to the refresh signal level provided by the first signal source ENBO, and the refresh signal provided by the second signal source ENBE can be refreshed, for example, by the first signal source ENBO.
  • the signal is obtained in reverse phase, but embodiments of the present disclosure are not limited thereto.
  • the specific type of the transistor is not limited in the present disclosure, and may be, for example, a TFT (Thin Film Transistor).
  • FIG. 15A An exemplary illustration of a display panel 300 provided by an embodiment of the present disclosure will be described below with reference to FIG. 15A.
  • the display panel shown in FIG. 15A may be an OLED panel.
  • the display panel 300 includes a pixel circuit array, and the gate driving circuit 350 shown in FIG. 14A.
  • the pixel circuit array includes a plurality of pixel circuits 321 arranged in an array.
  • the plurality of pixel circuits 321 are arranged in N rows in the column direction, and each of the pixel circuits 321 includes an emission control terminal EM and a selection control terminal GAT. And reset the control terminal RESET.
  • the first signal output terminal OUT1 of the jth stage scanning circuit 310 is connected to the light emission control terminal EM of the pixel circuit 321 of the jth row; the second signal output terminal OUT2 of the jth stage scanning circuit 310 is connected to the The selection control terminal GAT of the j-row pixel circuit 321; the second signal output terminal OUT2 of the m-1th-th scan circuit 310 is connected to the reset control terminal RESE of the pixel circuit 321 of the m-th row.
  • j is an integer greater than or equal to 1 and less than or equal to N
  • m is an integer greater than 1 and less than or equal to N.
  • the scan circuit may be the light emitting control terminal EM of the pixel circuit, the selection control terminal GAT, and the reset control terminal RESET
  • the illumination control signal, the selection control signal, and the reset control signal are respectively provided, and at least two scanning circuits are not required for the illumination control terminal EM of the pixel circuit, the selection control terminal GAT, and the reset control terminal RESET, thereby further reducing the scanning circuit 310.
  • the driving method of the display panel provided by the embodiment of the present disclosure is exemplarily described below with reference to the display panel 300 illustrated in FIG. 15A.
  • the driving method of the display panel may include the following steps S110-S120.
  • Step S110 The shift register circuit 311 of the scan circuit 310 of the jth stage is caused to generate a first scan signal, and the first scan signal is supplied to the first signal input end of the first signal generation circuit of the scan circuit 310 of the jth stage.
  • Step S120 The first signal generating circuit 312 of the scanning circuit 310 of the jth stage is caused to generate a second scan signal based on the first scan signal and the first refresh control signal, and supply the second scan signal to the pixel circuit 321 of the jth row. Selecting the control terminal GAT; at the same time, for the scan circuit 310 other than the nth stage, the second scan signal generated by the first signal generating circuit 312 of the scanning circuit 310 of the jth stage is supplied to the pixel circuit of the j+1th row The reset control terminal RESE of 321 .
  • the scan circuit can provide the light-emitting control terminal EM, the selection control terminal GAT, and the reset control terminal RESET of the pixel circuit, respectively.
  • the illumination control signal, the selection control signal, and the reset control signal are provided without setting at least two scanning circuits for the illumination control terminal EM, the selection control terminal GAT, and the reset control terminal RESET of the pixel circuit, thereby further reducing the display panel including the scan circuit 310 The border size.
  • the above-described driving method of the display panel can be used not only for the full-plate refresh of the display panel but also for the partial panel brush of the display panel.
  • the full-board refreshing means that, when displaying each frame of image, the selection control terminal GAT of all display pixels included in the display panel is performed row-by-row, so that all display pixels of the display panel can be Receiving the data signal corresponding to the frame image; as shown in FIG.
  • part of the panel refresh means that, when displaying each frame of image, only the selection control terminal GAT of the display pixel located in the partial row of the display panel is turned on, so that the display panel is
  • the display pixels of the partial rows receive the data signals corresponding to the frame images, while the display pixels located in the other rows of the display panel continue to perform the display function using the data signals corresponding to the images of the previous frame.
  • the refresh frequency and the number of charge and discharge times of the partial area of the display panel can be reduced, thereby reducing the driving power consumption of the display panel.
  • the display period of the display panel 300 includes a refresh phase T_REP and a non-refresh phase T_NREP.
  • the driving method of the display panel includes the following step S121.
  • Step S121 In the non-refresh phase T_NREP, the second signal input terminal IN2 of the first signal generating circuit 312 receives the refresh control signal of a low level.
  • n is an integer greater than or equal to 1 and smaller than N.
  • the second signal input terminal IN2 receives the normal first refresh control signal and outputs a pulse having a low level.
  • the control signal Gate(n) is selected such that the pixel circuit of the nth row is capable of receiving the corresponding data signal.
  • the driving method of the display panel includes the following steps S111-S112.
  • Step S111 providing a clock signal having a first pulse width to the shift register circuit 311 in the refresh phase T_REP;
  • Step S112 In the non-refresh phase T_NREP, the clock register signal having the second pulse width is supplied to the shift register circuit 311, and the first pulse width is greater than the second pulse width.
  • the shift register circuit 311 can be lowered by causing the pulse register of the clock signal (the first clock signal and the second clock signal) received by the shift register circuit 311 in the refresh phase T_REP to be larger than the pulse width of the clock signal received in the non-refresh phase T_NREP.
  • the width of the high-level pulse of the first scan signal (for example, EM1, EM2, ... EM_n-2) outputted in the refresh phase T_REP can further reduce the driving power consumption.
  • FIG. 7 can also be used for the local area refreshing of the display panel.
  • the driving sequence diagram shown in FIG. 7 can also be used for the local area refreshing of the display panel.
  • the working principle refer to the embodiment shown in FIG. 18, and details are not described herein again.
  • FIG. 13B is a schematic block diagram of another scanning circuit according to an embodiment of the present disclosure.
  • the scanning circuit 310 includes a shift register circuit 311, a first signal generating circuit 312, a second signal generating circuit 313, and The first node 361.
  • the scanning circuit shown in FIG. 13B can be used to form the gate driving circuit 350 shown in FIG. 14B and the display panel 300 shown in FIG. 15B.
  • the specific structure and function of the shift register circuit 311 and the first signal generating circuit 312 can be referred to the embodiment shown in FIG. 13A, and details are not described herein again.
  • the second signal generating circuit 313 has a first signal input terminal IIN1, a second signal input terminal IIN2, and a third signal output terminal OUT3.
  • the first signal input terminal IIN1 of the second signal generating circuit 313 is connected to the first node 361 and configured to receive the first scan signal
  • the second signal input terminal IIN2 of the second signal generating circuit 313 is connected to the second refresh control signal terminal.
  • REP2 to receive the second refresh control signal provided by the second refresh control signal terminal REP2
  • the second signal generating circuit 313 is configured to generate a third scan signal based on the first scan signal and the second refresh control signal.
  • the third scan signal can be used as a reset control signal for the reset control terminal RESE of the pixel circuit.
  • the second signal generating circuit 313 is configured to generate and output a low level when both the first signal input terminal IIN1 of the second signal generating circuit 313 and the second signal input terminal IIN2 of the second signal generating circuit 313 receive a high level signal.
  • the level signal; the second signal generating circuit 313 is further configured to receive low power at any one of the first signal input terminal IIN1 of the second signal generating circuit 313 and the second signal input terminal IIN2 of the second signal generating circuit 313 A high level signal is generated and output in the case of a flat signal.
  • the third stage st3, and the fourth stage st4 at least one low power is received at the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313.
  • a flat signal therefore, the third signal output terminal OUT3 outputs a high level signal; in the second phase st2, both the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 receive a high level signal Therefore, the third signal output terminal OUT3 outputs a low level signal.
  • the third scan signal outputted by the third signal output terminal OUT3 shown in Fig. 13E can be used as a reset control signal of the pixel circuit.
  • the specific structure of the second refresh control signal provided by the second refresh control signal terminal REP2 may be set according to actual application requirements, which is not specifically limited in the embodiment of the present disclosure.
  • the second refresh control signal provided by the second refresh control signal terminal REP2 is opposite to the first refresh control signal level provided by the first refresh control signal terminal REP1, for example, the second refresh control signal terminal REP2.
  • the supplied second refresh control signal may be obtained by inverting the first refresh control signal supplied from the first refresh control signal terminal REP1, but embodiments of the present disclosure are not limited thereto.
  • the third scan signal shown in FIG. 13E can be acquired as long as the second refresh control signal satisfies the high level in the second stage st2 and is low in the third stage st3.
  • the specific structure of the third scan signal output by the third signal output terminal OUT3 can be adjusted by the second refresh control signal to meet the driving requirements of different pixel circuits.
  • the specific adjustment method refer to the first refresh control. The method of adjusting the second scan signal by signal is not described here.
  • FIG. 14B and 15B illustrate another gate driving circuit 350 and another display panel 300 provided by an embodiment of the present disclosure, and the gate driving circuit 350 and the display panel 300 illustrated in FIGS. 14B and 15B include A scanning circuit 310 is shown in FIG. 13B.
  • the gate driving circuit 350 illustrated in FIG. 14B and the display panel 300 illustrated in FIG. 15B are similar to the gate driving circuit 350 illustrated in FIG. 14A and the display panel 300 illustrated in FIG. 15A, respectively, and only differences will be explained herein. The similarities are not repeated here.
  • the second refresh control signal terminal REP2 connected to the second signal generating circuit 313 of the 2k-1th scanning circuit 310 is the second signal source ENBE.
  • the second refresh control signal terminal REP2 connected to the second signal generating circuit 313 of the 2kth scanning circuit 3100 (corresponding to the even-line GOA unit 200 shown in FIG. 12) is the first signal source ENBO; that is, the first signal The source ENBO provides a second refresh control signal for the second signal generation circuit 313 of the even-numbered scan circuit 310, and the second signal source ENBE provides a second refresh control signal for the second signal generation circuit 313 of the odd-numbered scan circuit 310.
  • the third signal output terminal OUT3 of the jth stage scanning circuit 310 is connected to the reset control terminal RESE of the pixel circuit 321 of the jth row.
  • a third scan signal usable for the reset control signal of the pixel circuit can be generated based on the first scan signal, thereby eliminating the need to use the first signal generating circuit of the upper level scanning circuit
  • the second scan signal output by 312 serves as a reset control signal for the pixel circuit.
  • the specific configurations of the first signal generating circuit 312, the second signal generating circuit 313, and the shift register circuit 311 will be exemplarily described below with reference to FIGS. 3-7 and 10-12.
  • the first signal generating circuit 312 includes a first NAND circuit 30 (eg, the first signal generating circuit 312 can be implemented as the first NAND circuit 30), first The NAND circuit 30 is configured to perform a NAND operation on the first scan signal and the first refresh control signal to generate a second scan signal.
  • first NAND circuit 30 eg, the first signal generating circuit 312 can be implemented as the first NAND circuit 30
  • the NAND circuit 30 is configured to perform a NAND operation on the first scan signal and the first refresh control signal to generate a second scan signal.
  • the first NAND circuit 30 may include a first N-type transistor MN6, a second N-type transistor MN7, a first P-type transistor MP7, and a second P-type for the first NAND circuit 30.
  • Transistor MP8 may include a first N-type transistor MN6, a second N-type transistor MN7, a first P-type transistor MP7, and a second P-type for the first NAND circuit 30.
  • the first end of the first N-type transistor MN6 is connected to the second power supply terminal VSS, and the control end of the first N-type transistor MN6 is connected to the second signal input terminal IN2 of the first signal generating circuit 312;
  • the first end of the second N-type transistor MN7 is connected to the second end of the first N-type transistor MN6, and the control end of the second N-type transistor MN7 is configured as the first signal input terminal IN1 of the first signal generating circuit 312, and A node 361 is connected, the second end of the second N-type transistor MN7 is connected to the second signal output terminal OUT2;
  • the first end of the first P-type transistor MP7 is connected to the first power terminal VDD, and the control of the first P-type transistor MP7
  • the terminal is connected to the second signal input terminal IN2 of the first signal generating circuit 312, the second end of the first P-type transistor MP7 is connected to the second signal output terminal OUT2; the first end of the second P-type transistor MP8 is connected to
  • first power terminal VDD and the second power terminal VSS may each output a voltage, and the voltage outputted by the first power terminal VDD may be greater than the voltage output by the second power terminal VSS, and the second power terminal VSS may be grounded, for example.
  • the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 312 receive a high level signal
  • the first N-type transistor MN6 and the second N-type transistor MN7 are in conduction.
  • the second signal output terminal OUT2 is connected to the second power supply terminal VSS via the turned-on transistors MN6 and MN7, and outputs a low level signal.
  • the voltage value of the high level signal eg, greater than 0 V
  • the voltage value of the low level signal eg, 0 V
  • the transistor MP8 when the first signal input terminal IN1 of the first signal generating circuit 312 receives the low level signal, the transistor MP8 is turned on and the transistor MN7 is turned off, whereby the second signal output terminal OUT2 is turned on via the turned-on transistor MP8. It is connected to the first power terminal VDD and outputs a high level signal.
  • the transistor MP7 when the second signal input terminal IN2 of the first signal generating circuit 312 receives the low level signal, the transistor MP7 is turned on and the transistor MN6 is turned off, whereby the second signal output terminal OUT2 is turned on via the turned-on transistor MP7. It is connected to the first power terminal VDD and outputs a high level signal.
  • the transistor MP7 and the transistor MP8 are turned on and the transistor MN6 and the transistor MN7 are turned off.
  • the second signal output terminal OUT2 is connected to the first power supply terminal VDD via the turned-on transistor MP7 or MP8, and outputs a high level signal.
  • the second signal output terminal OUT2 outputs a low level signal; and in the case where any one of the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 receives the low level signal
  • the second signal output terminal OUT2 outputs a high level signal, that is, the first NAND circuit 30 shown in FIG. 4 can be used to perform NAND operation on the first scan signal and the first refresh control signal to generate a second scan signal.
  • the first signal generating circuit 312 provided by the embodiment of the present disclosure is not limited to the first NAND circuit 30 illustrated in FIG. 4, and the first signal generating circuit 312 may be any capable of pairing the first scanning signal and the first A circuit structure that performs a NAND operation with a refresh control signal.
  • the specific structure of the shift register circuit 311 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this.
  • the structure of the shift register circuit 311 will be exemplarily described below with reference to Figs. 3, 4 and 6.
  • the shift register circuit 311 includes an input circuit 10 and an inverter 20 and a second node 362.
  • the input circuit 10 includes a first end, a second end, a third end, and an output end, and the first end and the second end of the input circuit 10 are respectively configured as a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2, and
  • the first clock signal supply terminal CLK and the second clock signal supply terminal CLKB are respectively connected to receive the first clock signal and the second clock signal, respectively.
  • the third end of the input circuit 10 is configured as an open signal input terminal INP of the shift register circuit 311 to receive an open signal; the input circuit 10 is configured to generate an input control signal according to the turn-on signal, the first clock signal and the second clock signal, and the input circuit
  • the output of 10 is coupled to the second node 362 and is configured to output an input control signal.
  • the inverter 20 includes an input terminal and an output terminal; the input terminal of the inverter 20 is coupled to the second node 362 to receive an input control signal; and the inverter 20 is configured to input an input control signal.
  • the level is inverted to generate a first scan signal, that is, in the case where a high level signal is received at the input of the inverter 20, the output of the inverter 20 is connected to output a low level signal,
  • the output end of the inverter 20 is connected to output a high level signal; the output end of the inverter 20 is connected to the first node 361, and is configured as the first signal.
  • the output terminal OUT1 is for outputting the first scan signal.
  • the specific structure of the input circuit 10 and the inverter 20 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this.
  • the input circuit 10 includes a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, a second P-type transistor MP2, and a third for the shift register circuit 311.
  • the first end of the first N-type transistor MN1 is connected to the second power supply terminal VSS
  • the control end of the first N-type transistor MN1 is connected to the second clock signal supply terminal CLKB
  • the second N-type transistor MN2 is connected.
  • the first end is connected to the second end of the first N-type transistor MN1, the control end of the second N-type transistor MN2 is connected to the turn-on signal input terminal INP of the shift register circuit 311, and the second end of the second N-type transistor MN2 is The second node 362 is connected; the first end of the first P-type transistor MP1 is connected to the first power supply terminal VDD, the control end of the first P-type transistor MP1 is connected to the first clock signal supply terminal CLK; and the second P-type transistor MP2 is The first end is connected to the second end of the first P-type transistor MP1, the control end of the second P-type transistor MP2 is connected to the turn-on signal input terminal INP of the shift register circuit 311, and the second end of the second P-type transistor MP2 is The second node 362 is connected.
  • the transistors MN1, MN2, MP1, and MP2 shown in FIG. 4 may be combined to form a three-state gate (see the triangular structure at the lower left of the input circuit 10 at the
  • the first end of the third N-type transistor MN3 is connected to the second power supply terminal VSS, and the control end of the third N-type transistor MN3 is connected to the first clock signal supply terminal CLK;
  • the fourth N-type transistor MN4 The first end is connected to the second end of the third N-type transistor MN3, the control end of the fourth N-type transistor MN4 is connected to the first node 361, and the second end of the fourth N-type transistor MN4 is connected to the second node 362;
  • the second end of the three P-type transistor MP3 is connected to the second node 362, the control end of the third P-type transistor MP3 is connected to the first node 361; and the first end of the fourth P-type transistor MP3 is connected to the first power supply terminal VDD.
  • the control terminal of the fourth P-type transistor MP3 is connected to the second clock signal supply terminal CLKB, and the second terminal of the fourth P-type transistor MP3 is connected to the first terminal of the third P-type transistor MP3.
  • the combination of transistors MN3, MN4, MP3, and MP4 shown in FIG. 4 may constitute another tri-state gate (see the triangular structure at the upper right of the input circuit 10 at the lower left of FIG. 3).
  • the second clock signal outputted by the second clock signal providing terminal CLKB is opposite to the level of the first clock signal outputted by the first clock signal providing terminal CLK, that is, the second clock signal providing end CLKB outputs the first clock signal.
  • the two clock signals can be obtained by inverting the first clock signal outputted by the first clock signal supply terminal CLK.
  • the inverter 20 includes a fifth N-type transistor MN5 and a fifth P-type transistor MP5.
  • the first end of the fifth N-type transistor MN5 is connected to the second power supply terminal VSS, the control end of the fifth N-type transistor MN5 is connected to the second node 362, and the second end of the fifth N-type transistor MN5 is connected to the first node 361.
  • the first end of the fifth P-type transistor MP5 is connected to the first power supply terminal VDD, the control end of the fifth P-type transistor MP5 is connected to the second node 362, and the second end of the fifth P-type transistor MP5 is connected to the first node 361. Connected.
  • the inverter 20 inverts the level of the input control signal to generate the first scan signal.
  • the transistor MN5 is turned on and the transistor MP5 is turned off.
  • the first node 361 is connected to the second power supply terminal VSS via the turned-on transistor MN5, and the output is low.
  • Level signal in the case where the second node 362 receives the low level signal, the transistor MP5 is turned on and the transistor MN5 is turned off.
  • the first node 361 is connected to the first power terminal VDD via the turned-on transistor MP5. And output a low level signal. Therefore, the inverter 20 shown in FIG. 4 is capable of inverting the level of the input control signal.
  • the turn-on signal input terminal INP, the first clock signal input terminal CLK1, and the second clock signal input terminal CLK2 of the shift register circuit 311 shown in FIG. 4 respectively receive the turn-on signal STV and the first clock signal shown in FIG.
  • the first signal output terminal OUT1 of the shift register circuit 311 outputs the first scan signal shown in FIG. 6 ( Recorded as EM1), and compared to the turn-on signal STV, the first scan signal (denoted as EM1) is shifted back in time by the pulse width of one clock signal.
  • the operation of the shift register circuit 311 will be exemplarily described below with reference to FIGS. 4 and 6.
  • the turn-on signal STV and the first clock signal CLK are at a high level
  • the second clock signal CLKB is at a low level
  • the first node 361 is at a low level
  • the transistor MP3 and the transistor MP4 are turned on (at this time, although the transistor MN2 and the transistor MN3 are turned on but no path is formed)
  • the second node 362 is connected to the first power supply terminal VDD via the turned-on transistor MP3 and the transistor MP4, and is output.
  • High level; the high level output by the second node 362 causes the transistor MN5 to turn on and causes the first node 361 to output a low level.
  • the turn-on signal STV and the second clock signal CLKB are at a high level
  • the first clock signal CLK is at a low level
  • the first node 361 is at a low level
  • the transistor MN1 and the transistor MN2 are turned on (the transistor MP1 and the transistor MP3 are turned on but do not form a path)
  • the second node 362 is connected to the second power supply terminal VSS via the turned-on transistor MN1 and the transistor MN2, and outputs a low level.
  • the low level output by the second node 362 causes the transistor MP5 to turn on and causes the first node 361 to output a high level.
  • the first clock signal CLK is at a high level
  • the turn-on signal STV and the second clock signal CLKB are at a low level
  • the first node 361 is at a high level
  • the transistor MN3 and the transistor MN4 are turned on (the transistor MP2 and the transistor MP4 are turned on but do not form a path)
  • the second node 362 is connected to the second power supply terminal VSS via the turned-on transistor MN3 and the transistor MN4, and outputs a low level.
  • the low level output by the second node 362 causes the transistor MP5 to turn on and causes the first node 361 to output a high level.
  • the second clock signal CLKB is at a high level
  • the turn-on signal STV and the first clock signal CLK are at a low level
  • the first node 361 is at a high level
  • the transistor MP1 and the transistor MP2 are turned on (the transistor MN1 and the transistor MN4 are turned on but no path is formed), and the second node 362 is connected to the first power supply terminal VDD via the turned-on transistor MP1 and the transistor MP2, and outputs a high level
  • the high level output by the second node 362 causes the transistor MP5 to turn on and causes the first node 361 to output a low level.
  • the first scan signal (denoted as EM1) outputted from the first signal output terminal OUT1 of the shift register circuit 311 is shifted rearward by the pulse width of one clock signal in comparison with the turn-on signal STV.
  • the second signal generating circuit 313 further includes a second NAND circuit 50 (for example, the second signal generating circuit 313 can be implemented as the second NAND circuit 50), and the second NAND circuit The 50 is configured to perform a NAND operation on the first scan signal and the second refresh control signal to generate a third scan signal.
  • the second NAND circuit 50 includes a first input terminal, a second input terminal, and a signal output terminal, which are respectively configured as a first signal input terminal IIN1, a second signal input terminal IN2, and a signal third signal of the second signal generating circuit 313. Output OUT3.
  • the second NAND circuit 50 includes a first N-type transistor MN8, a second N-type transistor MN9, a first P-type transistor MP9, and a second P-type transistor MP10.
  • the first end of the first N-type transistor MN8 is connected to the second power supply terminal VSS, and the control end of the first N-type transistor MN8 is connected to the second signal input terminal IIN2 of the second signal generating circuit 313;
  • the first end of the two N-type transistor MN9 is connected to the second end of the first N-type transistor MN8, the control end of the second N-type transistor MN9 is connected to the first node 361, and the second end of the second N-type transistor MN9 is connected to the second end
  • the third signal output terminal OUT3 is connected;
  • the first end of the first P-type transistor MP9 is connected to the first power supply terminal VDD, and the control end of the first P-type transistor MP9 is connected to the second signal input terminal IIN2 of the second signal generating circuit 313.
  • the second end of the first P-type transistor MP9 is connected to the third signal output terminal OUT3; and the first end of the second P-type transistor MP10 is connected to the first power supply terminal VDD, and the control end of the second P-type transistor MP10 is first The node 361 is connected, and the second end of the second P-type transistor MP10 is connected to the third signal output terminal OUT3.
  • the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 both receive a high level signal
  • the first N-type transistor MN8 and the second N-type transistor MN9 are turned on. Therefore, the third signal output terminal OUT3 is connected to the second power supply terminal VSS via the turned-on transistors MN8 and MN9, and outputs a low level signal.
  • the transistor MP10 when the first signal input terminal IIN1 of the second signal generating circuit 313 receives the low level signal, the transistor MP10 is turned on and the transistor MN9 is turned off, whereby the third signal output terminal OUT3 is turned on via the turned-on transistor MP10. It is connected to the first power terminal VDD and outputs a high level signal.
  • the transistor MP9 is turned on and the transistor MN8 is turned off, whereby the third signal output terminal OUT3 passes through the turned-on transistor MP9. It is connected to the first power terminal VDD and outputs a high level signal.
  • the transistors MP9 and MP10 are turned on and the transistors MN8 and MN9 are turned off, whereby The third signal output terminal OUT3 is connected to the first power supply terminal VDD via the turned-on transistor MP9 or MP10, and outputs a high level signal.
  • the third signal output terminal OUT3 outputs the low level signal. And in the case that any one of the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 receives the low level signal, the third signal output terminal OUT3 outputs a high level signal, That is, the second NAND circuit 50 shown in FIG. 11 can be used to perform a NAND operation on the first scan signal and the second refresh control signal to generate a third scan signal.
  • the second signal generating circuit 313 provided by the embodiment of the present disclosure is not limited to the second NAND circuit 50 illustrated in FIG. 11 , and the first signal generating circuit 312 may also be any capable of pairing the first scanning signal and the first The circuit structure of the second refresh control signal for NAND operation.
  • the scan circuit 310 further includes a reset circuit 40 coupled to the second node 362 and configured to perform an initial reset on the first node 361 (ie, to cause the first node 361 to be low Level).
  • the reset circuit 40 includes a P-type transistor MP6 for the reset circuit 40; the first end of the P-type transistor MP6 for the reset circuit 40 is connected to the first power supply terminal VDD for resetting the circuit 40.
  • the control terminal of the transistor MP6 is for receiving the initialization reset signal TT_RST, and the second terminal of the P-type transistor MP6 for the reset circuit 40 is connected to the second node 362.
  • the second node is connected to the first power supply terminal VDD via the turned-on transistor MP6, and causes the transistor MN5 to be turned on. Therefore, the first node 361 The transistor MN5 that is turned on is connected to the second power supply terminal VSS, and outputs a signal of a low level.
  • the reset circuit 40 implements an initial reset of the first node 361.
  • the reset circuit 40 is not limited to a circuit structure including a P-type transistor. According to actual application requirements, the reset circuit 40 can also be implemented as a circuit structure including an N-type transistor. In this case, the initialization reset signal TT_RST needs to be set to High level signal.
  • the time for the resetting and resetting of the first node 361 by the reset circuit 40 may be set according to actual application requirements, which is not specifically limited in the embodiment of the present disclosure.
  • a plurality of pixels included in the display panel may be displayed after each frame of image is displayed and before the next frame image is displayed (that is, a blank time between adjacent display frames).
  • the first node 361 of the circuit simultaneously performs a reset operation.
  • a plurality of pixel circuits included in the display panel may be reset line by line, and details are not described herein again.
  • At least one embodiment of the present disclosure also provides a display device 1 including a pixel circuit array composed of a plurality of pixel circuits 321 as shown in FIG.
  • the display device 1 may further include a data driving circuit.
  • the data driving circuit is electrically connected to the pixel circuit 321 through the data line 332 and used to supply a data signal to the corresponding pixel circuit;
  • the gate driving circuit 310 is electrically connected to the pixel circuit 321 through the gate line 331 and used to provide a gate scanning signal (for example, selection)
  • the control signal is given to the corresponding pixel circuit.
  • At least one embodiment of the present disclosure further provides a display device 1 , as shown in FIG. 17 , the display device includes the scan circuit 310 provided by any embodiment of the present disclosure, and the gate drive circuit provided by any embodiment of the present disclosure. 350 or any of the display panels 300 provided by any of the embodiments of the present disclosure.
  • the display device 1 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, and the like.
  • a product or part that has a display function may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, and the like.
  • an embodiment of the present disclosure further provides a driving circuit for a display panel including an odd row GOA unit 100 and an even row GOA unit 200, and the odd row GOA unit 100 correspondingly drives an odd number.
  • the row pixel circuit 101, the even row GOA unit 200 correspondingly drives the even row pixel circuit 201, and each of the odd row GOA unit 100 and the even row GOA unit 200 includes: an input circuit 10, an inverter 20, and a first AND Circuit 30.
  • the input circuit 10 is connected to the first clock signal supply terminal CLK and the second clock signal supply terminal CLKB, respectively, and the input circuit 10 located in the first row is connected to the signal input terminal INPT to receive an initial signal (for example, an initial The signal STV), the input circuit 10 located in the remaining row, is connected to the output of the inverter 20 located in the upper row to use the EM signal (i.e., the first scan signal) output from the inverter 20 as an initial signal.
  • the input circuit 10 is configured to generate an input control signal based on the initial signal, the first clock signal provided by the first clock signal providing terminal CLK, and the second clock signal provided by the second clock signal providing terminal CLKB.
  • the inverter 20 is connected to the input circuit 10, and the inverter 20 is configured to invert the input control signal to output an EM signal (that is, a first scan signal) to a pixel circuit corresponding to the GOA unit of the row, for example, an odd number.
  • the inverter 20 in the row GOA unit 100 outputs an EM_n signal to the corresponding pixel circuit 101, and the inverter 20 in the even-line GOA unit 200 outputs an EM_n+1 signal to the corresponding pixel circuit 201, and an odd line.
  • the EM signal output from the inverter 20 in the GOA unit 100 can be referred to as EM_O (see FIG. 4), and the EM signal output from the inverter 20 in the even-line GOA unit 200 can be referred to as EM_E (see FIG. 4).
  • the first input end of the first NAND circuit 30 is connected to the inverter 20, and the second input end of the first NAND circuit 30 and the first refresh control signal terminal REP1 (the first signal source ENBO or the second signal source ENBE) Connected, for example, the first refresh control signal end corresponding to the odd row GOA unit 100 is referred to as ENBO, the first refresh control signal end corresponding to the even row GOA unit 200 is denoted as ENBE, and the first NAND circuit 30 is used for the EM signal and the a first refresh control signal provided by the refresh control signal terminal performs a NAND operation to output a second scan signal such as Gate(n) (also referred to as Gate_n) to a pixel circuit corresponding to the GOA unit of the row, for example, an odd-line GOA unit 100 output
  • the Gate_n signal is sent to the corresponding pixel circuit 101, and the even-line GOA unit 200 outputs the Gate_n+1 signal to the corresponding pixel circuit 201.
  • the pixel circuit may be as shown in FIG. 1, which includes seven transistors T1 to T7, but embodiments of the present disclosure are not limited thereto.
  • the driving circuit of the display panel proposed by the embodiment of the present disclosure may enable the EM signal (that is, the first scan signal) and the second scan signal to be output through a single GOA unit, thereby reducing the frame and controlling the first refresh control signal
  • the display panel can be fully refreshed and partially refreshed, so that when the display image change area of different frames displayed on the display panel is small, the display area corresponding to the non-change is not refreshed, thereby Reduce power consumption.
  • the display panel of the present disclosure may also have a partial area display function, whereby a part of the display area of the display panel can be implemented to implement functions according to actual application requirements to reduce power consumption.
  • the first scan signal output by the GOA unit of the row is used as the initial signal of the next row of GOA units, and the second scan signal output by the GOA unit of the row is used as the next row of GOA.
  • each GOA unit further includes a reset circuit 40 for performing an initial reset on the first node 361.
  • the input circuit 10 includes: a first NMOS transistor MN1 (that is, an example of a first N-type transistor for shift register circuit 311) a second NMOS transistor MN2 (that is, an example of a second N-type transistor for shift register circuit 311), a first PMOS transistor MP1 (that is, a first P-type for shift register circuit 311) An example of a transistor), a second PMOS transistor MP2 (ie, an example of a second P-type transistor for shift register circuit 311), and a third NMOS transistor MN3 (ie, for shift register circuits) An example of a third N-type transistor of 311), a fourth NMOS transistor MN4 (that is, an example of a fourth N-type transistor for shift register circuit 311), and a third PMOS transistor MP3 (ie, One example of the third P-type transistor for the shift register circuit 311) and the fourth PMOS transistor MP4 (that is, one example of
  • the first end of the first NMOS transistor MN1 is connected to the second power supply terminal VSS, the control end of the first NMOS transistor MN1 is connected to the second clock signal supply terminal CLKB, and the second NMOS transistor MN2 is connected.
  • the first end is connected to the second end of the first NMOS transistor MN1, the control end of the second NMOS transistor MN2 is connected to the input end of the input circuit 10; the first end of the first PMOS transistor MP1 is connected to the first power supply terminal VDD, The control terminal of the PMOS transistor MP1 is connected to the first clock signal supply terminal CLK; the first terminal of the second PMOS transistor MP2 is connected to the second terminal of the first PMOS transistor MP1, and the control terminal of the second PMOS transistor MP2 and the input circuit 10
  • the input ends are connected, the second end of the second PMOS transistor MP2 and the second end of the second NMOS transistor MN2 are both connected to the second node 362, and the second node 362 is used as the output end of the input circuit 10; as shown in FIG.
  • the first NMOS transistor MN1, the second NMOS transistor MN2, and the first PMOS transistor MP1 and the second PMOS transistor MP2 form a three-state gate.
  • the first end of the third NMOS transistor MN3 is connected to the second power supply terminal VSS, and the control end of the third NMOS transistor MN3 is connected to the first clock signal supply terminal CLK; the first end of the fourth NMOS transistor MN4 and the third NMOS transistor MN3
  • the second end of the third PMOS transistor MP3 is connected to the second end of the fourth NMOS transistor MN4 and is connected to the second node 362.
  • the control terminal of the third PMOS transistor MP3 and the fourth NMOS transistor MN4 are controlled.
  • the terminal is connected to the output terminal of the inverter 20; the first terminal of the fourth PMOS transistor MP4 is connected to the first power terminal VDD, and the control terminal of the fourth PMOS transistor MP4 is connected to the second clock signal supply terminal CLKB.
  • the second end of the PMOS transistor MP4 is connected to the first end of the third PMOS transistor MP3.
  • the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the third PMOS transistor MP3 and the fourth PMOS transistor MP4 constitute another tri-state gate. That is, the input module 20 can be composed of two three-state gates.
  • the inverter 20 includes: a fifth NMOS transistor MN5 (that is, an example of a fifth N-type transistor for shift register circuit 311) And a fifth PMOS transistor MP5 (that is, an example of a fifth P-type transistor for shift register circuit 311).
  • the first end of the fifth NMOS transistor MN5 is connected to the second power supply terminal VSS
  • the control end of the fifth NMOS transistor MN5 is connected to the second node 362
  • the first end of the fifth PMOS transistor MP5 is connected to the first power supply terminal VDD.
  • the control end of the fifth PMOS transistor MP5 is connected to the second node 362, and the second end of the fifth PMOS transistor MP5 and the second end of the fifth NMOS transistor MN5 are connected to the first node 361, that is, the N point.
  • the first node 361 acts as an output of the inverter 20.
  • the first node 361 also serves as the signal input INPT of the next row of GOA units.
  • the first NAND circuit includes a sixth NMOS transistor MN6 (that is, an example of the first N-type transistor for the first NAND circuit 30).
  • a seventh NMOS transistor MN7 that is, an example of a second N-type transistor for the first NAND circuit 30
  • a seventh PMOS transistor MP7 that is, a first NAND circuit 30
  • An example of a P-type transistor An example of a P-type transistor
  • an eighth PMOS transistor MP8 ie, an example of a second P-type transistor for the first NAND circuit 30.
  • the first end of the sixth NMOS transistor MN6 is connected to the second power supply terminal VSS, and the first end of the seventh NMOS transistor MN7 is connected to the second end of the sixth NMOS transistor MN6, and the seventh NMOS is connected.
  • the control terminal of the MN7 is connected to the first node 361; the first end of the seventh PMOS transistor MP7 is connected to the first power terminal VDD, and the control terminal of the seventh PMOS transistor MP7 is connected to the control terminal of the sixth NMOS transistor MN6.
  • a refresh control signal terminal (the first signal source ENBO or the second signal source ENBE) is connected, and the second end of the seventh PMOS transistor MP7 and the second end of the seventh NMOS transistor MN7 are both connected to the third node, and the third node is The output end Gate_O (Gate_E) of the first NAND circuit 30; the first end of the eighth PMOS transistor MP8 is connected to the first power supply terminal VDD, and the control end of the eighth PMOS transistor MP8 is connected to the first node 361, and the eighth PMOS transistor The second end of the MP8 is connected to the third node.
  • the reset circuit 40 includes a sixth PMOS transistor MP6 (that is, an example of a P-type transistor for the reset circuit 40), and the first end of the sixth PMOS transistor MP6 and the first power supply
  • the terminal VDD is connected
  • the control terminal of the sixth PMOS transistor MP6 is configured to receive the initialization reset signal TT_RST
  • the second terminal of the sixth PMOS transistor MP6 is connected to the output terminal of the input circuit 10, that is, the second node 362.
  • the second clock signal provided by the second clock signal providing end corresponding to the CLKB in FIG. 6 corresponds to the first clock signal provided by the first clock signal providing end, where CLKB can be after the CLK is inverted.
  • the TT_RST signal is an initialization reset signal received by the reset circuit 40; for example, after the end of each frame of image display, before the start of the next frame image display, the N point is initialized to a low level by reset; the power of ENBO and ENBE
  • the flats can be reversed and can correspond to odd-line GOA units and even-numbered GOA units, respectively.
  • ENBO and ENBE can perform NAND operations with the EM signal (for example, the EM signal of the line) to generate the line.
  • a second scan signal such as Gate(n) (eg, in some embodiments, can be used as a reset signal for the next row), the pulse width of which is set according to the requirements of the pixel circuit, the number of pulses and the odd or even rows The number is the same.
  • the STV in FIG. 6 is an initial signal received by the input circuit 10 located in the first row, and the initial state of the N point may be a low level.
  • the initial signal STV shifts to form EM1
  • the GOA units located in other rows are shifted backward by line to form EM2, EM3, ... EMn.
  • the line in which EM2 is located is the start line (acting as the EM signal of the second line).
  • MN6, MN7, MP7, and MP8 cooperate to realize the function of the NAND gate circuit, that is, the first NAND circuit, and only the EM signal and the first refresh control signal are high level, the first NAND circuit Only the low level is output, and the rest of the first and second circuit outputs a high level.
  • Gate1 is formed (acting as the Reset signal of the second row), and the first pulse of EM2 and the second signal source ENBE is NANDed.
  • Gate2 serving as the Gate signal of the second row and the Reset signal of the third row
  • the second scan signal (for example, Gate_n) outputted by the previous row of GOA units is used as the reset signal of the pixel circuit in the same row as the GOA unit of the row, and the GOA unit output of the row is output.
  • the second scan signal is a selection control signal of the pixel circuit located in the same row as the GOA unit of the row, and the first scan signal (EM signal) output by the GOA unit of the row is used as the light emission of the pixel circuit in the same row as the GOA unit of the row.
  • the signal is controlled, whereby the progressive driving of the pixel circuit can be achieved.
  • the first scan signal eg, EM signal
  • the second scan signal eg, Gate_n
  • the display panel can realize the full-plate refresh function and the partial refresh function.
  • FIG. 6 is a driving timing diagram of a display panel provided by an embodiment of the present disclosure.
  • the driving timing diagram can be used to implement a full-board refresh function of the display panel, and the driving timing diagram shows waveform diagrams of the EM signal and the Gate signal.
  • 7 is a driving timing diagram of another display panel provided by an embodiment of the present disclosure, which can be used to implement a partial refresh function of the display panel, and shows a waveform diagram of the EM signal and the Gate signal, and a partial refresh function.
  • the display effects corresponding to the display panel full-board refresh and the partial refresh are respectively shown in FIG. 8 and FIG. 9, and in the partial refresh display mode, the partial area of the display image is not refreshed.
  • the pixel circuit of the partial row of the display panel can receive the data signal, and the pixel circuits of the remaining rows do not receive the data signal, thereby realizing partial refresh of the display panel.
  • the pixel circuits of the remaining rows do not receive the data signal, thereby realizing partial refresh of the display panel.
  • the partial refresh refers to that the partial area of the screen displayed by the display panel needs to change the gradation (to display different image information), and most of the rest maintain the original gray scale.
  • the pixel circuit that maintains the original gradation may not receive a new data signal, as shown in FIG.
  • the first refresh control signal corresponding to the row is maintained at a low level, thereby reducing the refresh frequency of the display pixels of the display panel portion, and correspondingly, the data signal can be set to be unchanged to further reduce Driving power consumption; in this case, in the pixel circuit corresponding to the non-refresh row, the selection control signal (Gate signal) received by the pixel circuit is at a high level (the received reset signal may also be a high level), and is related thereto.
  • the TFT T1/T2/T4/T7 is turned off, no current flows, and no capacitor charge and discharge occurs, thereby reducing power consumption.
  • each GOA unit includes an input module, an inverter, and a first NAND circuit, and the first clock signal provided by the first clock signal providing end according to the initial signal by the input module And generating, by the second clock signal provided by the second clock signal providing end, an input control signal, the inverter inverting the input control signal to output the EM signal to the pixel circuit corresponding to the GOA unit of the row; the first NAND circuit pair first And performing a NAND operation on the scan signal and the refresh control signal provided by the first refresh control signal terminal to output the second scan signal to the pixel circuit corresponding to the GOA unit of the row, so that the first scan signal (EM signal) and the second scan signal are made (Gate signal) is output by a single GOA unit, thereby reducing the display frame and improving the user experience, and by controlling the refresh control signal provided by the first refresh control signal end, the full panel refresh function and the partial refresh function of the display panel can be realized. This can reduce power consumption.
  • the display panel may be an OLED panel.
  • the row GOA unit when the row GOA unit is an odd row GOA unit 100, the row GOA unit further includes a second NAND circuit 50, and the second NAND circuit 50
  • the first input terminal is connected to the inverter 20
  • the second input terminal of the second NAND circuit 50 is connected to the second refresh control signal terminal (second signal source ENBE)
  • the second NAND circuit 50 is used for the first scan.
  • the signal EM_n signal and the second refresh control signal provided by the second refresh control signal terminal (second signal source ENBE) perform NAND operation to output the reset signal Reset_n to the pixel circuit 101 corresponding to the GOA unit of the row.
  • the GOA unit of the row When the GOA unit of the row is an even row GOA unit 200, the GOA unit of the row further includes a second NAND circuit 50, and the first input end of the second NAND circuit 50 is connected to the inverter 20, The second input end of the second NAND circuit 50 is connected to the second refresh control signal end (first signal source ENBO), and the second NAND circuit 50 is used for the first scan signal EM_n+1 and the second refresh control signal end ( The second refresh control signal provided by the first signal source ENBO) performs a NAND operation to output a reset signal Reset_n+1 to the pixel circuit 201 corresponding to the LOA unit of the row.
  • the second refresh control signal provided by the first signal source ENBO performs a NAND operation to output a reset signal Reset_n+1 to the pixel circuit 201 corresponding to the LOA unit of the row.
  • the Reset signal and the Gate signal and the EM signal are both generated by a single GOA unit and output to the corresponding pixel circuit.
  • the second NAND circuit 50 includes an eighth NMOS transistor MN8 (that is, a first N-type transistor for the second NAND circuit 50).
  • An example of the ninth NMOS transistor MN9 ie, one example of a second N-type transistor for the second NAND circuit 50
  • the ninth PMOS transistor MP9 ie, for the second NAND circuit 50
  • An example of the first P-type transistor ie, for the second NAND circuit 50
  • the tenth PMOS transistor MP10 that is, one example of the second P-type transistor for the second NAND circuit 50.
  • the first end of the eighth NMOS transistor MN8 is connected to the second power supply terminal VSS, the first end of the ninth NMOS transistor MN9 is connected to the second end of the eighth NMOS transistor MN8, and the control end of the ninth NMOS transistor MN9 is connected to the first node.
  • the first end of the ninth PMOS transistor MP9 is connected to the first power supply terminal VDD, and the control end of the ninth PMOS transistor MP9 is connected to the control end of the eighth NMOS transistor MN8, and corresponding to the second refresh control
  • the signal terminal (the second signal source ENBE or the first signal source ENBO) is connected, and the second end of the ninth PMOS transistor MP9 and the second end of the ninth NMOS transistor MN9 are both connected to the fourth node, and the fourth node is
  • the output end of the second NAND circuit 50 outputs a reset signal; the first end of the tenth PMOS transistor MP10 is connected to the first power terminal VDD, the control end of the tenth PMOS transistor MP10 is connected to the first node 361, and the tenth PMOS transistor MP10 The second end is connected to the fourth node.
  • Embodiments of the present disclosure also provide a display device including the above-described driving circuit of the display panel.
  • the EM signal and the Gate signal can be outputted by a single GOA unit through the driving circuit of the display panel described above, thereby reducing the display frame and improving the user experience; further, by controlling the refresh control signal
  • the refresh control signal provided by the terminal can realize the full panel refresh function and the partial refresh function of the display panel to reduce power consumption.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un circuit de balayage (310), un circuit de commande de grille (350), un dispositif d'affichage (300) et un procédé de commande associé, et un dispositif d'affichage (1). Le circuit de balayage (310) comprend un circuit de registre à décalage (311) et un premier circuit de génération de signal (312). Le circuit de registre à décalage (311) a une première extrémité de sortie de signal (OUT1) et est configuré pour délivrer un premier signal de balayage; le premier circuit de génération de signal (312) a une seconde extrémité de sortie de signal (OUT2) et est configuré pour générer et délivrer en sortie un second signal de balayage sur la base d'un premier signal de commande de rafraîchissement (REP1) et du premier signal de balayage. Le circuit de balayage (310) peut fournir un premier signal de balayage pour une extrémité de commande d'émission lumineuse (EM) du circuit de pixel (321, 101, 201) et un second signal de balayage pour sélectionner une extrémité de commande (GAT).
PCT/CN2018/089969 2017-06-06 2018-06-05 Circuit de balayage, circuit de commande de grille, panneau d'affichage et procédé de commande associé, et dispositif d'affichage WO2018223963A1 (fr)

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CN108806592B (zh) * 2018-05-18 2020-03-24 京东方科技集团股份有限公司 显示驱动电路、显示驱动方法和显示装置
CN108806582B (zh) * 2018-07-02 2021-06-18 上海中航光电子有限公司 阵列基板、电子纸式显示面板及其驱动方法和显示装置
CN108831382A (zh) * 2018-08-29 2018-11-16 京东方科技集团股份有限公司 一种goa单元、goa级联电路及goa单元的驱动方法
CN113299236A (zh) * 2021-05-24 2021-08-24 京东方科技集团股份有限公司 一种显示面板的驱动方法、装置和显示面板
US12118935B2 (en) 2022-01-30 2024-10-15 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display apparatus

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