WO2018223915A1 - 数据传输方法、数据传输电路、显示装置以及存储介质 - Google Patents

数据传输方法、数据传输电路、显示装置以及存储介质 Download PDF

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Publication number
WO2018223915A1
WO2018223915A1 PCT/CN2018/089744 CN2018089744W WO2018223915A1 WO 2018223915 A1 WO2018223915 A1 WO 2018223915A1 CN 2018089744 W CN2018089744 W CN 2018089744W WO 2018223915 A1 WO2018223915 A1 WO 2018223915A1
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Prior art keywords
data
code
stability check
link stability
identifier
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PCT/CN2018/089744
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English (en)
French (fr)
Inventor
郭俊
王鑫
段欣
王洁琼
陈明
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/619,033 priority Critical patent/US11107433B2/en
Priority to EP18812733.6A priority patent/EP3637406A4/en
Publication of WO2018223915A1 publication Critical patent/WO2018223915A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present application relates to the field of display manufacturing, and in particular, to a data transmission method, a data transmission circuit, a display device, and a storage medium.
  • Point-to-point (English: point-to-point, P2P) interface is a display panel internal timing controller (English: Timing controller, referred to as: T-CON) and source driver chip (English: Source) High-speed serial interface between Driver, referred to as SD).
  • T-CON Timing controller
  • SD High-speed serial interface between Driver
  • timing controller and the source driver chip first perform a clock calibration operation, and then the timing controller transmits the data to be transmitted to the source driver chip.
  • Embodiments of the present disclosure provide a data transmission method, a data transmission circuit, a display device, and a storage medium.
  • the technical solution is as follows:
  • a data transmission method for a timing controller, the method comprising: after clock calibration, transmitting preset link stability check data to a source driver chip, receiving the source driver
  • the feedback information sent by the chip is generated when the source driving chip determines that the received link stability check data is correct, and sends the target data to the source driving chip based on the feedback information.
  • the sending the preset link stability check data to the source driving chip includes: sending the link to the source driving chip when the timing controller is to enter a low power awake state Stabilizing the verification data, the low-power wake-up state is a transition state in which the timing controller re-enters the data transmission state by a low-power state that does not need to transmit data.
  • the link stability check data is obtained by using a data format of multiple bytes by using an 8b/10b coding manner, where the data codes of the multiple bytes include a start identifier and a data bit, and the start identifier
  • the data bit carries verification data
  • the data bit is provided with a scrambling code identifier, where the location of the scrambling code identifier is used to indicate that the port of the source driving chip corresponds to the port
  • the initialization time point of the linear feedback register LFSR which is used for scrambling of the target data.
  • the data code of the multiple bytes is a 40-byte data code
  • the start identifier is a 4-byte K2 code
  • the scrambling code is identified as a 4-byte K3 code.
  • the verification data carried by the data bit includes 8 data units, each of the data units includes a 4-byte data code, and at least 4 bytes of data code exists between the start identifier and the scrambling code identifier. .
  • the sending the preset link stability check data to the source driving chip includes: sending the link stability check data to the source driving chip n times for 1 microsecond, wherein the n is greater than Or equal to 5.
  • the method further includes: in response to receiving the transmission interrupt instruction, generating link stability check data including the interrupt identifier, Sending link stability check data including the interrupt identifier to the source driver chip to instruct the source driver chip to stop receiving link stability check data.
  • the interrupt identifier is a K1 code or a K4 code.
  • the target data is display data or configuration data.
  • a data transmission method for a source driver chip, the method comprising:
  • the link stability check data is obtained by using a data format of multiple bytes by using an 8b/10b coding manner, where the data codes of the multiple bytes include a start identifier and a data bit, and the start identifier
  • the data bit carries verification data
  • the data bit is provided with a scrambling code identifier, where the location of the scrambling code identifier is used to indicate that the port of the source driver chip corresponds to the port
  • the initialization time point of the linear feedback register LFSR which is used for scrambling of the target data.
  • the data code of the multiple bytes is a 40-byte data code
  • the start identifier is a 4-byte K2 code
  • the scrambling code is identified as a 4-byte K3 code.
  • the verification data carried by the data bit includes 8 data units, each of the data units includes a 4-byte data code, and at least 4 bytes of data code exists between the start identifier and the scrambling code identifier. .
  • the preset link stability check data sent by the receiving timing controller after the clock calibration includes: receiving the link stability check data sent by the timing controller for n times for 1 microsecond.
  • the n is greater than or equal to 5.
  • the method further includes: responding to receiving the chain that includes the interrupt identifier sent by the timing controller.
  • the road stability check data stops receiving the link stability check data, and the link stability check data including the interrupt identifier is generated by the timing controller when receiving the transmission interrupt instruction.
  • the method further includes: performing the phase calibration operation repeatedly until the received link stability check data is incorrect, until the correct receipt is received.
  • the link is stable to verify the data.
  • the determining whether the received link stability check data is correct includes: decoding the received link stability check data to obtain decoded data, where the decoded data includes the scrambling code identifier, and determining the location Whether the decoded data is the same as the data code of the plurality of bytes, and in response to the decoded data being the same as the data code of the plurality of bytes, determining that the received link stability check data is correct, in response to the The decoded data is different from the data code of the plurality of bytes, and it is determined that the received link stability check data is incorrect.
  • the method further includes: determining a port of the source driver chip according to a location of the scrambling code identifier in the decoded data. An initialization time point of the linear feedback register LFSR corresponding to the port, and the LFSR is initialized for the port according to the initialization time point.
  • a data transmission circuit for a timing controller, the data transmission circuit comprising: a first transmitter, configured to send a preset link stability to the source driver chip after the clock calibration Detecting data, the receiver is configured to receive feedback information sent by the source driving chip, where the feedback information is generated when the source driving chip determines that the received link stability check data is correct, and the second sending And sending the target data to the source driving chip based on the feedback information.
  • the first transmitter is specifically configured to: when the timing controller enters a low power awake state, send the link stability check data to the source driving chip, where the low power
  • the awake state is a transition state in which the timing controller re-enters the data transmission state by a low power state that does not need to transmit data.
  • the link stability check data is encoded by a multi-byte data code by using an 8b/10b coding manner, where the data codes of the multiple bytes include a start identifier and a data bit.
  • the start identifier is used to indicate the start of data transmission, the data bit carries verification data, and the data bit is provided with a scrambling code identifier, and the location of the scrambling code identifier is used to indicate the port of the source driver chip.
  • the data code of the multiple bytes is a 40-byte data code
  • the start identifier is a 4-byte K2 code
  • the scrambling code is identified as a 4-byte K3 code.
  • the verification data carried by the data bit includes 8 data units, each of the data units includes a 4-byte data code, and at least 4 bytes of data code exists between the start identifier and the scrambling code identifier. .
  • the first transmitter is specifically configured to: send the link stability check data to the source driving chip n times for 1 microsecond, and the n is greater than or equal to 5.
  • the data transmission circuit further includes: a generator, configured to generate link stability check data including an interrupt identifier when receiving the transmission interrupt instruction, and a third transmitter for driving to the source
  • the chip transmits link stability check data including the interrupt identifier to instruct the source driver chip to stop receiving link stability check data.
  • the interrupt identifier is a K1 code or a K4 code.
  • the target data is display data or configuration data.
  • a data transmission circuit for a source driving chip, the data transmission circuit comprising: a receiver, configured to receive preset link stability check data sent by the timing controller after clock calibration a determiner, configured to determine whether the received link stability check data is correct, and a generator configured to generate feedback information when the received link stability check data is correct, and send the information to the timing controller The feedback information is caused to cause the timing controller to transmit target data to the source driving chip based on the feedback information.
  • the data transmission circuit further includes: a first processor, configured to stop receiving the link stability check data when receiving the link stability check data that is sent by the timing controller and includes the interrupt identifier, The link stability check data including the interrupt identifier is generated when the timing controller receives the transmission interrupt instruction.
  • the data transmission circuit further includes: a second processor, configured to repeatedly perform a phase calibration operation until the received link stability check data is received when the received link stability check data is incorrect.
  • the determining unit is configured to: decode the received link stability check data, and obtain decoded data, where the decoded data includes the scrambling code identifier, and determine the decoded data and the multiple Whether the data codes of the bytes are the same, in response to the decoded data being the same as the data code of the plurality of bytes, determining that the received link stability check data is correct, in response to the decoded data and the plurality of words
  • the data codes of the sections are different, and it is determined that the received link stability check data is incorrect, wherein the link stability check data is obtained by encoding a plurality of bytes of data codes by using an 8b/10b coding manner, where the multiple
  • the data code of the byte includes a start identifier and a data bit, the start identifier is used to indicate the start of data transmission, the data bit carries the verification data, and the data bit is set with the scrambling code identifier, the interference
  • the location of the code identification is used to indicate the port of the
  • the determining unit is further configured to: determine, according to the location of the scrambling code in the decoded data, a port of the source driving chip and an initialization time point of a linear feedback register LFSR corresponding to the port. And initializing the LFSR for the port according to the initialization time point.
  • a fifth aspect provides a display device including a timing controller and a source driving chip, the timing controller comprising the data transmission circuit of the third aspect, wherein the source driving chip comprises the fourth aspect Data transmission circuit.
  • a computer readable storage medium in a sixth aspect, storing instructions, when the computer readable storage medium is run on a computer, causing the computer to perform any of the first aspect Data transfer method.
  • a seventh aspect a computer readable storage medium having instructions stored therein, when the computer readable storage medium is run on a computer, causing the computer to perform any of the second aspect Data transfer method.
  • FIG. 1 is a schematic diagram of an application environment of a data transmission method according to an embodiment of the present disclosure.
  • FIG. 2 is a flowchart of a data transmission method according to an embodiment of the present disclosure.
  • FIG. 3 is a flowchart of another data transmission method according to an embodiment of the present disclosure.
  • FIG. 4a is a flowchart of still another data transmission method according to an embodiment of the present disclosure.
  • FIG. 4b is a schematic diagram of a 40-byte data code sent to a port according to an embodiment of the present disclosure.
  • 4c is a schematic diagram of a 40-byte data code sent to another port according to an embodiment of the present disclosure.
  • FIG. 4d is a flowchart of determining whether link stability check data is correct according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a data transmission circuit according to an embodiment of the present disclosure.
  • FIG. 5b is a schematic structural diagram of another data transmission circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another data transmission circuit according to an embodiment of the present disclosure.
  • FIG. 6b is a schematic structural diagram of still another data transmission circuit according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of an application environment of a data transmission method according to an embodiment of the present disclosure.
  • the data transmission method is applied to a display device including a timing controller 100 and a plurality of source driving chips 200.
  • the plurality of high-speed signal lines H of the timing controller 100 are connected to the plurality of source driving chips 200 in one-to-one correspondence.
  • the timing controller 100 is further connected with a low-speed signal line L, and the plurality of source driving chips 200 are connected in parallel, and the low-speed The signal line L is connected.
  • the P2P interface is a high-speed serial interface between the timing controller 100 and the source driver chip 200, and data such as display data and configuration data can be transmitted through the P2P interface.
  • clock calibration is an important part of the P2P interface technology.
  • the timing controller 100 directly transmits data after completing the clock calibration operation, and the source driver chip 200 also directly receives data after completing the clock calibration operation.
  • the data transmission state of the link between the timing controller and the source driver chip (also referred to as a P2P interface link) is detected in advance, and in the case where the data transmission state of the link is poor, the timing controller 100 also goes to the source.
  • the drive chip 200 transmits data, and finally the source drive chip 200 is apt to receive erroneous data.
  • the timing controller 100 and the source driving chip 200 detect the data transmission state of the link in advance. When the data transmission state of the link is good, the timing controller 100 drives the chip 200 to the source. Send data such as display data and configuration data.
  • the embodiment of the present disclosure provides a data transmission method for the timing controller 100 in the application environment shown in FIG. 1, as shown in FIG. 2, the method includes:
  • Step 101 After the clock is calibrated, send preset link stability check data to the source driver chip.
  • the source driver chip can be any of the source driver chips in the application environment shown in FIG.
  • Step 102 Receive feedback information sent by the source driving chip, where the feedback information is generated when the source driving chip determines that the received link stability check data is correct.
  • Step 103 Send target data to the source driving chip based on the feedback information.
  • the timing controller can send the link stability check data to the source driver chip, when the link stability mode data received by the source driver chip is correct, indicating The data transmission status of the link is good, and the source driver chip sends feedback information to the timing controller, so that the timing controller can send data to the source driver chip when the data transmission state of the link is good, so the improvement is improved. Reliability and stability of data transmission.
  • An embodiment of the present disclosure provides another data transmission method for any of the source driving chips 200 in the application environment shown in FIG. 1. As shown in FIG. 3, the method includes:
  • Step 201 Receive preset link stability check data sent by the timing controller after the clock calibration.
  • Step 202 Determine whether the received link stability check data is correct.
  • Step 203 When the received link stability check data is correct, generate feedback information, and send feedback information to the timing controller, so that the timing controller sends the target data to the source driver chip based on the feedback information.
  • the source driver chip receives the link stability check data sent by the timing controller after the clock calibration, and the link stable mode data received by the source driver chip is correct.
  • the source driver chip sends feedback information to the timing controller, so that the timing controller can send data to the source driver chip when the data transmission state of the link is good. Therefore, the reliability and stability of data transmission are improved.
  • the embodiment of the present disclosure provides another data transmission method, which is used in the application environment shown in FIG. 1 , as shown in FIG. 4 a , the method includes:
  • Step 301 After the clock is calibrated, the timing controller sends preset link stability check data to the source driver chip. Go to step 302.
  • the source driver chip is any of the source driver chips in the application environment shown in FIG.
  • the timing controller sends preset link stability check data to the source driver chip.
  • the timing controller and the source driving chip first perform a clock calibration operation, and then the timing controller sends link stability check data to the source driving chip to detect the timing controller and the source driving chip. The data transfer status of the link between.
  • the timing controller sends link stability check data to the source driver chip, and the low-power wake-up state is the timing controller A low-power state that does not require data transfer to re-enter the transition state of the data transfer state.
  • the timing controller when the timing controller and the source driver chip do not need to transmit data, the timing controller enters a low power consumption state. When the timing controller and the source driver chip need to transfer data again, the timing controller needs to enter a low-power wake-up state to return to normal operation. When the timing controller is to enter the low power wake state, the timing controller may send link stability check data to the source driver chip to detect the data transmission status of the link between the timing controller and the source driver chip. This method allows the timing controller to quickly recover from a low-power wake-up state to a normal operating state.
  • the timing controller and the source driver chip when the timing controller and the source driver chip need to transmit data again, the timing controller and the source driver chip can be restored to the normal working state without performing a clock calibration operation.
  • the step of transmitting link stability check data may be performed when the timing controller is to enter a low power wake state, and when the timing controller is to enter other states. carried out.
  • the timing controller can transmit link stability check data to the source driver chip to detect the data transmission status of the link between the timing controller and the source driver chip as long as it is restored to the normal working state.
  • the timing controller may send the identifier of the source driving chip to the source driving chip while transmitting the preset link stability check data to the source driving chip.
  • the source driver chip can detect whether the identity sent by the timing controller is the same as its own identity. When the identity identifier sent by the timing controller is the same as its own identity, the source driver chip performs corresponding operations, see steps 302 to 304, and step 306, and the like.
  • the link stability check data is encoded by a multi-byte data code encoded by 8b/10b (that is, 8-bit data is encoded into 10-bit data), and the data code of the multiple bytes includes a start identifier and Data bit.
  • the start identifier is used to indicate the start of data transmission, and the data bit carries the verification data.
  • the data bit is provided with a scrambling code identifier, and the location of the scrambling code identifier is used to indicate the linear feedback corresponding to the port and the port of the source driver chip.
  • the initialization time point of the register (English: Linear Feedback Shift Register, LFSR for short), the LFSR is used for scrambling of the target data. Using some special codes such as initial identification, scrambling code identification, etc., can help the receiving end to perform the restoration work, and early detection of the transmission error of the data code, suppressing the error from continuing.
  • the data code of multiple bytes can be encoded by using the 8b/10b coding method in the related art.
  • the 8b/10b encoding method the verification data carried by the data bits in the data code of multiple bytes is encoded, and it is not necessary to encode the special code (such as the initial identifier and the scrambling code identifier).
  • Encoding with 8b/10b encoding can keep the number of transmitted "0" and “1” basically the same, continuous "0” and “1” no more than 5 digits, that is, every 5 consecutive "1”s A “0” must be inserted, and a “1” must be inserted after every 5 consecutive "0”s to ensure that the signal is DC (DC) balanced.
  • the verification data is encoded by the 8b/10b coding method in the related art
  • a group of consecutive 8-bit data is divided into two parts, and the first 5 bits are 5B/6B (that is, 5 bits (bit) data coding is performed.
  • the 6-bit data is encoded, and the last 3 bits are encoded in 3B/4B (that is, 3-bit data is encoded into 4-bit data).
  • the boundary between each of the two sets of 10-bit data is blurred, and transmission errors are apt to occur. Therefore, in order to ensure that the data to be transmitted can be correctly restored at the receiving end, in the embodiment of the present disclosure, when encoding the verification data, the 8-bit data corresponding to the byte to be encoded of the verification data may be first encoded into 9-bit data.
  • the first bit data of the 9-bit data is detected, and the previous bit data adjacent to the first bit data, when the first bit data and the value of the previous bit data
  • the 9-bit data is inverted, and the 10th bit data indicating that the 9-bit data has undergone the inversion operation is added after the 9-bit data, and 10 bits of data are obtained, when the value of the first bit data and the previous bit data are not
  • the tenth bit data indicating that the 9-bit data has not undergone the inversion operation is added after the 9-bit data, and the 10-bit data is obtained, wherein the 10-bit data is binary data.
  • the tenth bit data indicating that the 9-bit data has not undergone the inversion operation is added after the 9-bit data, and 10 bits of data are obtained.
  • 8-bit data is first encoded into 9-bit data, then the tenth bit is added to obtain 10-bit data, and a transition edge is set between every two adjacent 10-bit data, and the tenth bit data is used. Instructing whether the 9-bit data has undergone the inversion operation can effectively ensure that the data to be transmitted is correctly restored at the receiving end, and the edge of the transition can effectively reduce the transmission error.
  • a multi-byte data code is a 40-byte data code.
  • the start identifier is a 4-byte K2 code
  • the scrambling code is identified as a 4-byte K3 code.
  • the verification data carried by the data bits includes 8 data units, and each data unit includes 4 bytes of data code. . In order to complete at least one data check, there is at least 4 bytes of data code between the start identifier and the scrambling code identifier.
  • the timing controller is connected to the plurality of source driving chips, and each port of each of the source driving chips can adopt a descrambling manner for the received data, and the descrambling method and timing are performed.
  • the controller corresponds to the scrambling method used for the data to be sent. That is, different ports of each source driver chip adopt different descrambling methods.
  • the port of each source driver chip corresponds to one LFSR. The location of the scrambling code identification in the data bit is used to indicate the port of the source driver chip and the initialization time point of the LFSR corresponding to the port.
  • the source driver chip receives the link stability check data sent by the timing controller, and after decoding, the source driver chip determines to initialize the bit according to the position of the K3 code in the data bit.
  • the time point of a port's LFSR The source driver chip has different time points for the port to initialize the LFSR, and the result after descrambling is different.
  • each of the 8 data units included in the verification data may include 0xea, 0xeb, 0xec, and 0xed arranged in sequence.
  • data starting with 0x represents hexadecimal data.
  • a represents decimal 10
  • b represents decimal 11
  • c represents decimal 12
  • d represents decimal 13
  • e represents decimal 14.
  • the source driver chip achieves the purpose of verifying the data based on the verification data. When the source driver chip receives the correct verification data, it indicates that the data transmission status of the link is good.
  • Figure 4b shows a schematic diagram of a 40 byte data code sent to port 01
  • Figure 4c shows a schematic diagram of a 40 byte data code sent to port 02.
  • the position of the K3 code in Figure 4b and Figure 4c is different. It is assumed that the initialization time point of the LFSR corresponding to port 01 is t1, and the initialization time point of the LFSR corresponding to port 01 is t2, then t2 is different from t1.
  • the step 301 may include: sending the n-link stability check data to the source driving chip for 1 microsecond, that is, the timing controller is The total length of time that the source driver chip transmits n times of link stability check data is 1 microsecond. Where n is greater than or equal to 5.
  • Step 302 The source driver chip determines whether the received link stability check data is correct. When the received link stability check data is correct, step 303 is performed. When the received link stability check data is incorrect, step 306 is performed.
  • step 302 may include:
  • Step 3021 The source driver chip decodes the received link stability check data to obtain decoded data.
  • the decoded data includes a scrambling code identification, which, by way of example, includes a K3 code.
  • Step 3022 The source driver chip determines whether the decoded data is the same as the data code of the plurality of bytes. When the decoded data is the same as the data code of the plurality of bytes, step 3023 is performed, and when the decoded data is different from the data code of the plurality of bytes, step 3024 is performed.
  • the source driver chip compares the decoded data with the data code of the plurality of bytes before encoding to determine whether the two are the same.
  • Step 3023 The source driver chip determines that the received link stability check data is correct.
  • the source driver chip determines whether the decoded data is the same as the data code of the plurality of bytes before the encoding. When the decoded data is the same as the data code of the plurality of bytes, the source driver chip determines that the received link is stable. Verify that the data is correct.
  • the method may further include:
  • the source driver chip determines the initialization time point of the LFSR corresponding to the port and the port of the source driver chip according to the location of the scrambling code identification in the decoded data.
  • the source driver chip determines the initialization time point of the LFSR corresponding to the port and the port of the source driver chip according to the position of the scrambling code identifier (such as the K3 code) in the decoded data. .
  • the source driver chip has different time points for initializing the LFSR, and the result after descrambling is different. Therefore, the source driver chip needs to identify the position in the decoded data according to the scrambling code, and obtain the initialization time of the LFSR corresponding to the port. point.
  • the source driver chip can determine the initialization time point of the port and the LFSR corresponding to the port of the source driver chip according to a preset correspondence.
  • the correspondence relationship is used to record the position of the scrambling code identifier in the decoded data, the correspondence between the port of the source driver chip and the initialization time point of the LFSR.
  • the correspondence may be as shown in Table 1.
  • the location of the scrambling code identifier in the decoded data is L1
  • it may be determined that the port of the source driver chip is P01
  • the initialization time point of the LFSR corresponding to the port P01 is T1. That is, the source driver chip needs to initialize its corresponding LFSR for port P01 at the time point T1.
  • the source driver chip initializes the LFSR for the port according to the initialization time point.
  • the LFSR may be initialized according to the initialization time point, so as to facilitate scrambling and descrambling the subsequently transmitted data.
  • Step 3024 The source driver chip determines that the received link stability check data is incorrect.
  • the source driver chip determines that the received link stability check data is incorrect, indicating the link between the timing controller and the source driver chip.
  • the data transmission status is poor. At this time, it is not suitable for transmitting display data, configuration data, and the like.
  • Step 303 When the received link stability check data is correct, the source driver chip generates feedback information. Go to step 304.
  • the source driver chip can generate feedback information and send the feedback information to the timing controller, so as to notify the timing controller that the current link data transmission state is better. Suitable for transmitting display data, configuration data, etc.
  • Step 304 The source driving chip sends feedback information to the timing controller. Go to step 305.
  • the source driver chip sends the generated feedback information to the timing controller to notify the timing controller that the data transmission state of the current link is good, and then the timing controller sends the target data to the source driver chip.
  • Step 305 The timing controller sends the target data to the source driving chip based on the feedback information.
  • the target data is display data or configuration data.
  • Step 306 When the received link stability check data is incorrect, the source driver chip repeatedly performs a phase calibration operation until the correct link stability check data is received.
  • the source driver chip can repeatedly perform a phase calibration operation to perform phase drift until the correct link stability check data is received, thereby enabling The link has a good data transmission status and is more suitable for transmitting target data. Then, steps 303 to 305 are performed to complete the transmission of the target data.
  • the timing controller transmits the target data to the source driver chip, which improves the reliability and stability of the data transmission.
  • the source driver chip may Stop receiving the link stability check data.
  • the method may include the following steps:
  • the timing controller When receiving the transmission interrupt instruction, the timing controller generates link stability check data including the interrupt identifier.
  • the transmission interrupt instruction may be triggered by the user or may be triggered when the display device is abnormal.
  • the user may trigger a transmission interrupt instruction, and when receiving the transmission interruption instruction, the timing controller generates link stability check data including the interrupt identifier, when the display device appears When a fault occurs, a transmission interrupt instruction is also triggered.
  • the timing controller receives the transmission interrupt instruction, the link stability check data including the interrupt identifier is also generated, so that the source driver chip stops the receiving link from being stable based on the interrupt identifier. Verify the data.
  • the interrupt identifier is a K1 code or a K4 code. That is, when the source driver chip receives the K1 code or the K4 code, it stops receiving the link stability check data.
  • the timing controller sends the link stability check data including the interrupt identifier to the source driver chip.
  • the link stability check data is sent to the source driver chip, so that the source driver chip stops receiving the link stability check data based on the interrupt identifier.
  • the source driver chip stops receiving the link stability check data.
  • the source driver chip When the source driver chip receives the link stability check data sent by the timing controller and includes the interrupt identifier (such as K1 code or K4 code), the source driver chip stops receiving the link stability check data.
  • the interrupt identifier such as K1 code or K4 code
  • the data transmission method provided by one embodiment of the present disclosure is applicable to a P2P interface protocol, and the method is applicable to any product or component having a display function using a P2P interface protocol, and the method can enable the P2P interface.
  • the link between the sender and the receiver is more stable.
  • the data transmission method provided by the embodiment of the present disclosure, because the timing controller can send the link stability check data to the source driver chip, when the link stable mode data received by the source driver chip is correct, It indicates that the data transmission state of the link is good, and the source driving chip sends feedback information to the timing controller, so that the timing controller can send data to the source driving chip again when the data transmission state of the link is good.
  • This makes the link more stable and enables the timing controller to quickly recover from a low-power wake-up state to a normal operating state. This method improves the reliability and stability of data transmission.
  • the data transmission circuit 500 includes:
  • the first transmitter 510 is configured to send preset link stability check data to the source driver chip after the clock is calibrated.
  • the receiver 520 is configured to receive feedback information sent by the source driving chip, where the feedback information is generated when the source driving chip determines that the received link stability check data is correct.
  • the second transmitter 530 is configured to send the target data to the source driving chip based on the feedback information.
  • an embodiment of the present disclosure provides a data transmission circuit in which a timing controller can transmit link stability check data to a source driver chip when the link stable mode data received by the source driver chip is correct. , indicating that the data transmission status of the link is good, and the source driving chip sends feedback information to the timing controller, so that the timing controller can send data to the source driving chip when the data transmission state of the link is good, so Improve the reliability and stability of data transmission.
  • the first transmitter 510 is specifically configured to:
  • the link stability check data is sent to the source driver chip, and the low-power wake-up state is that the timing controller re-enters the data transmission state by the low-power state that does not need to transmit data. Transitional state.
  • the link stability check data is encoded by a multi-byte data code by using an 8b/10b coding method, and the data code of the multiple bytes includes a start identifier and a data bit.
  • the start identifier is used to indicate the start of data transmission
  • the data bit carries the verification data
  • the data bit is set with the scrambling code identifier
  • the location of the scrambling code identifier is used to indicate the initialization time of the LFSR corresponding to the port and the port of the source driver chip.
  • LFSR is used for scrambling of target data.
  • the data code of multiple bytes is a 40-byte data code
  • the initial identifier is a 4-byte K2 code
  • the scrambling code is identified as a 4-byte K3 code
  • the verification data carried by the data bits includes 8 data units, each data unit comprising 4 bytes of data code, and at least 4 bytes of data code between the start identifier and the scrambling code identifier.
  • the first transmitter 510 is specifically configured to: send n times of link stability check data to the source driver chip for 1 microsecond, where n is greater than or equal to 5.
  • the data transmission circuit 500 may further include: a generator 540, configured to generate link stability check data including an interrupt identifier when receiving the transmission interrupt instruction.
  • the third transmitter 550 is configured to send the link stability check data including the interrupt identifier to the source driver chip, so that the source driver chip stops receiving the link stability check data.
  • the interrupt identifier is a K1 code or a K4 code.
  • the target data is display data or configuration data.
  • an embodiment of the present disclosure provides a data transmission circuit in which a timing controller can transmit link stability check data to a source driver chip when the link stable mode data received by the source driver chip is correct. , indicating that the data transmission status of the link is good, and the source driving chip sends feedback information to the timing controller, so that the timing controller can send data to the source driving chip when the data transmission state of the link is good, so Improve the reliability and stability of data transmission.
  • the data transmission circuit 600 includes: a receiver 610. For receiving the preset link stability check data sent by the timing controller after the clock calibration.
  • the determiner 620 is configured to determine whether the received link stability check data is correct.
  • the generator 630 is configured to generate feedback information when the received link stability check data is correct, and send feedback information to the timing controller, so that the timing controller sends the target data to the source driver chip based on the feedback information.
  • an embodiment of the present disclosure provides a data transmission circuit in which a source driver chip receives a preset link stability check data sent by a timing controller after clock calibration, and a chain received by a source driver chip.
  • the road stability mode data When the road stability mode data is correct, it indicates that the data transmission status of the link is good, and the source driver chip sends feedback information to the timing controller, so that the timing controller can return to the source when the data transmission state of the link is good.
  • the driver chip transmits data, which improves the reliability and stability of data transmission.
  • the link stability check data is encoded by a multi-byte data code by using an 8b/10b coding method
  • the data code of the multiple bytes includes a start identifier and a data bit
  • the start identifier is used to indicate the start of data transmission.
  • the data bit carries the verification data
  • the data bit is set with the scrambling code identifier.
  • the location of the scrambling code identifier is used to indicate the initialization time point of the LFSR corresponding to the port and the port of the source driver chip, and the LFSR is used for scrambling of the target data.
  • the data code of multiple bytes is a 40-byte data code
  • the initial identifier is a 4-byte K2 code
  • the scrambling code is identified as a 4-byte K3 code
  • the verification data carried by the data bits includes 8 data units, each data unit comprising 4 bytes of data code, and at least 4 bytes of data code between the start identifier and the scrambling code identifier.
  • the receiver 610 is specifically configured to: receive n times of link stability check data sent by the timing controller for 1 microsecond, and n is greater than or equal to 5.
  • the data transmission circuit 600 may further include: a first processor 640, configured to stop receiving the chain when receiving the link stability check data including the interrupt identifier sent by the timing controller.
  • the road stability check data, the link stability check data including the interrupt identifier is generated by the timing controller when receiving the transmission interrupt instruction.
  • the data transmission circuit 600 may further include: a second processor 650, configured to repeatedly perform a phase calibration operation when the received link stability check data is incorrect, until the correct reception is received.
  • the link is stable to verify the data.
  • the determiner 620 is specifically configured to: decode the received link stability check data, obtain decoded data, and the decoded data includes a scrambling code identifier, and determine whether the decoded data is the same as the data code of multiple bytes. When the decoded data is the same as the data code of multiple bytes, it is determined that the received link stability check data is correct. When the decoded data is different from the data code of multiple bytes, the received link stability check data is determined. Incorrect.
  • the determiner 620 is further configured to: determine, according to the location of the scrambling code in the decoded data, determine an initialization time point of the LFSR corresponding to the port and the port of the source driving chip, and initialize the LFSR according to the initialization time point.
  • an embodiment of the present disclosure provides a data transmission circuit in which a source driver chip receives a preset link stability check data sent by a timing controller after clock calibration, and a chain received by a source driver chip.
  • the road stability mode data When the road stability mode data is correct, it indicates that the data transmission status of the link is good, and the source driver chip sends feedback information to the timing controller, so that the timing controller can return to the source when the data transmission state of the link is good.
  • the driver chip transmits data, which improves the reliability and stability of data transmission.
  • One embodiment of the present disclosure also provides a display device including a timing controller and a source driver chip.
  • the timing controller includes the data transmission circuit shown in FIG. 5a or 5b, and the source driver chip includes the data transmission circuit shown in FIG. 6a or 6b.
  • the display device can be a liquid crystal panel, an electronic paper, an organic light-emitting diode (English: Organic Light-Emitting Diode, OLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc.
  • OLED Organic Light-Emitting Diode
  • An embodiment of the present disclosure also provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform FIG. 2 or The data transmission method shown in 4a.
  • An embodiment of the present disclosure also provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform FIG. 3 or The data transmission method shown in 4a.

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Abstract

一种数据传输方法、数据传输电路(500,600)以及显示装置，用于时序控制器(100)的数据传输方法，包括：在时钟校准后，向源极驱动芯片(200)发送预设的链路稳定校验数据(101)，接收源极驱动芯片(200)发送的反馈信息，反馈信息是源极驱动芯片(200)在判断接收到的链路稳定校验数据正确时生成的(102)，基于反馈信息向源极驱动芯片(200)发送目标数据(103)。

Description

数据传输方法、数据传输电路、显示装置以及存储介质
相关专利申请
本申请要求2017年6月9日提交的中国专利申请No.201710433373.10的优先权，其全部内容通过引用并入本文。
技术领域
本申请涉及显示器制造领域，特别涉及一种数据传输方法、数据传输电路、显示装置以及存储介质。
背景技术
点对点(英文：point-to-point，简称：P2P)接口是一种应用于液晶显示器的显示面板内部时序控制器(英文：Timing controller，简称：T-CON)和源极驱动芯片(英文：Source Driver，简称：SD)之间的高速串行接口。通过P2P接口可以完成显示数据和配置数据等数据的传输。
相关技术中有一种数据传输方法，该方法中，时序控制器和源极驱动芯片先执行时钟校准操作，然后时序控制器将需要传输的数据发送至源极驱动芯片。
发明内容
本公开的实施例提供了一种数据传输方法、数据传输电路、显示装置以及存储介质。所述技术方案如下：
第一方面，提供了一种数据传输方法，用于时序控制器，所述方法包括：在时钟校准后，向源极驱动芯片发送预设的链路稳定校验数据，接收所述源极驱动芯片发送的反馈信息，所述反馈信息是所述源极驱动芯片在判断接收到的链路稳定校验数据正确时生成的，基于反馈信息向所述源极驱动芯片发送目标数据。
示例的，所述向源极驱动芯片发送预设的链路稳定校验数据，包括：在所述时序控制器要进入低功耗唤醒状态时，向所述源极驱动芯片发送所述链路稳定校验数据，所述低功耗唤醒状态为所述时序控制器由无需传输数据的低功耗状态重新进入数据传输状态的过渡状态。
示例的，所述链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，所述起始标识用于指示数据传输开始，所述数据位携带有验证数据， 所述数据位中设置有扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
示例的，所述多个字节的数据码为40个字节的数据码，所述起始标识为4个字节的K2码，所述扰码标识为4个字节的K3码，所述数据位携带的验证数据包括8个数据单元，每个所述数据单元包括4个字节的数据码，所述起始标识与所述扰码标识之间存在至少4个字节的数据码。
示例的，所述向源极驱动芯片发送预设的链路稳定校验数据，包括：持续1微秒向所述源极驱动芯片发送n次所述链路稳定校验数据，所述n大于或等于5。
示例的，在所述向源极驱动芯片发送预设的链路稳定校验数据之后，所述方法还包括：响应于接收到传输中断指令，生成包含有中断标识的链路稳定校验数据，向所述源极驱动芯片发送包含有所述中断标识的链路稳定校验数据，以指示所述源极驱动芯片停止接收链路稳定校验数据。
示例的，所述中断标识为K1码或K4码。
示例的，所述目标数据为显示数据或配置数据。
第二方面，提供了一种数据传输方法，用于源极驱动芯片，所述方法包括：
接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，判断接收到的链路稳定校验数据是否正确，响应于接收到的链路稳定校验数据正确，生成反馈信息，并向所述时序控制器发送所述反馈信息，使得所述时序控制器基于所述反馈信息向所述源极驱动芯片发送目标数据。
示例的，所述链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
示例的，所述多个字节的数据码为40个字节的数据码，所述起始 标识为4个字节的K2码，所述扰码标识为4个字节的K3码，所述数据位携带的验证数据包括8个数据单元，每个所述数据单元包括4个字节的数据码，所述起始标识与所述扰码标识之间存在至少4个字节的数据码。
示例的，所述接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，包括：持续1微秒接收所述时序控制器发送的n次所述链路稳定校验数据，所述n大于或等于5。
示例的，在所述接收时序控制器在时钟校准后发送的预设的链路稳定校验数据之后，所述方法还包括：响应于接收到所述时序控制器发送的包含有中断标识的链路稳定校验数据，停止接收链路稳定校验数据，所述包含有中断标识的链路稳定校验数据是所述时序控制器在接收到传输中断指令时生成的。
示例的，在所述判断接收到的链路稳定校验数据是否正确之后，所述方法还包括：响应于接收到的链路稳定校验数据不正确，重复执行相位校准操作，直至接收到正确的链路稳定校验数据。
示例的，所述判断接收到的链路稳定校验数据是否正确，包括：对接收到的链路稳定校验数据进行解码，得到解码数据，所述解码数据包括所述扰码标识，判断所述解码数据与所述多个字节的数据码是否相同，响应于所述解码数据与所述多个字节的数据码相同，确定接收到的链路稳定校验数据正确，响应于所述解码数据与所述多个字节的数据码不相同，确定接收到的链路稳定校验数据不正确。
示例的，在所述确定接收到的链路稳定校验数据正确之后，所述方法还包括：根据所述扰码标识在所述解码数据中的位置，确定所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，根据所述初始化时间点为所述端口初始化所述LFSR。
第三方面，提供了一种数据传输电路，用于时序控制器，所述数据传输电路包括：第一发送器，用于在时钟校准后，向源极驱动芯片发送预设的链路稳定校验数据，接收器，用于接收所述源极驱动芯片发送的反馈信息，所述反馈信息是所述源极驱动芯片在判断接收到的链路稳定校验数据正确时生成的，第二发送器，用于基于反馈信息向所述源极驱动芯片发送目标数据。
示例的，所述第一发送器，具体用于：在所述时序控制器要进入 低功耗唤醒状态时，向所述源极驱动芯片发送所述链路稳定校验数据，所述低功耗唤醒状态为所述时序控制器由无需传输数据的低功耗状态重新进入数据传输状态的过渡状态。
示例的，所述链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，
所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
示例的，所述多个字节的数据码为40个字节的数据码，所述起始标识为4个字节的K2码，所述扰码标识为4个字节的K3码，所述数据位携带的验证数据包括8个数据单元，每个所述数据单元包括4个字节的数据码，所述起始标识与所述扰码标识之间存在至少4个字节的数据码。
示例的，所述第一发送器，具体用于：持续1微秒向所述源极驱动芯片发送n次所述链路稳定校验数据，所述n大于或等于5。
示例的，所述数据传输电路还包括：生成器，用于在接收到传输中断指令时，生成包含有中断标识的链路稳定校验数据，第三发送器，用于向所述源极驱动芯片发送包含有所述中断标识的链路稳定校验数据，以指示所述源极驱动芯片停止接收链路稳定校验数据。
示例的，所述中断标识为K1码或K4码。
示例的，所述目标数据为显示数据或配置数据。
第四方面，提供了一种数据传输电路，用于源极驱动芯片，所述数据传输电路包括：接收器，用于接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，判断器，用于判断接收到的链路稳定校验数据是否正确，生成器，用于在接收到的链路稳定校验数据正确时，生成反馈信息，并向所述时序控制器发送所述反馈信息，使得所述时序控制器基于所述反馈信息向所述源极驱动芯片发送目标数据。
示例的，所述数据传输电路还包括：第一处理器，用于在接收到所述时序控制器发送的包含有中断标识的链路稳定校验数据时，停止接收链路稳定校验数据，所述包含有中断标识的链路稳定校验数据是所述时序控制器在接收到传输中断指令时生成的。
示例的，所述数据传输电路还包括：第二处理器，用于在接收到的链路稳定校验数据不正确时，重复执行相位校准操作，直至接收到正确的链路稳定校验数据。
示例的，所述判断器，具体用于：对接收到的链路稳定校验数据进行解码，得到解码数据，所述解码数据包括所述扰码标识，判断所述解码数据与所述多个字节的数据码是否相同，响应于所述解码数据与所述多个字节的数据码相同，确定接收到的链路稳定校验数据正确，响应于所述解码数据与所述多个字节的数据码不相同，确定接收到的链路稳定校验数据不正确，其中所述链路稳定校验数据由多个字节的数据码采8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有所述扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
示例的，所述判断器，还用于：根据所述扰码标识在所述解码数据中的位置，确定所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，根据所述初始化时间点为所述端口初始化所述LFSR。
第五方面，提供了一种显示装置，包括时序控制器和源极驱动芯片，所述时序控制器包括第三方面所述的数据传输电路，所述源极驱动芯片包括第四方面所述的数据传输电路。
第六方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在计算机上运行时，使得计算机执行第一方面任一所述的数据传输方法。
第七方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在计算机上运行时，使得计算机执行第二方面任一所述的数据传输方法。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种数据传输方法的应用环境示意图。
图2是本公开实施例提供的一种数据传输方法的流程图。
图3是本公开实施例提供的另一种数据传输方法的流程图。
图4a是本公开实施例提供的又一种数据传输方法的流程图。
图4b是本公开实施例提供的向一端口发送的40个字节的数据码的示意图。
图4c是本公开实施例提供的向另一端口发送的40个字节的数据码的示意图。
图4d是本公开实施例提供的一种判断链路稳定校验数据是否正确的流程图。
图5a是本公开实施例提供的一种数据传输电路结构示意图。
图5b是本公开实施例提供的另一种数据传输电路结构示意图。
图6a是本公开实施例提供的再一种数据传输电路结构示意图。
图6b是本公开实施例提供的又一种数据传输电路结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1示出了本公开实施例提供的一种数据传输方法的应用环境示意图。如图1所示，该数据传输方法应用于显示装置中，该显示装置包括时序控制器100和多个源极驱动芯片200。该时序控制器100的多个高速信号线H与多个源极驱动芯片200一一对应连接，该时序控制器100还连接有一低速信号线L，多个源极驱动芯片200并联，且与低速信号线L连接。P2P接口是时序控制器100和源极驱动芯片200之间的高速串行接口，通过P2P接口可以完成显示数据和配置数据等数据的传输。其中，时钟校准是P2P接口技术中的重要部分，相关技术中，时序控制器100在完成时钟校准操作后直接发送数据，源极驱动芯片200也是在完成时钟校准操作后直接接收数据，整个过程没有预先检测时序控制器和源极驱动芯片之间的链路(也称P2P接口链路)的数据传输状态，在链路的数据传输状态较差的情况下，时序控制器100也会向源极驱动芯片200发送数据，最终源极驱动芯片200易接收到错误的数据。
而在本公开实施例中，时序控制器100和源极驱动芯片200会预 先检测链路的数据传输状态，当链路的数据传输状态较好时，时序控制器100再向源极驱动芯片200发送显示数据和配置数据等数据。
本公开实施例提供了一种数据传输方法，用于图1所示应用环境中的时序控制器100，如图2所示，该方法包括：
步骤101、在时钟校准后，向源极驱动芯片发送预设的链路稳定校验数据。
该源极驱动芯片可以为图1所示应用环境中的任一源极驱动芯片。
步骤102、接收源极驱动芯片发送的反馈信息，该反馈信息是源极驱动芯片在判断接收到的链路稳定校验数据正确时生成的。
步骤103、基于反馈信息向源极驱动芯片发送目标数据。
综上所述，本公开实施例提供的数据传输方法，由于时序控制器能够向源极驱动芯片发送链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，所以提高了数据传输的可靠性和稳定性。
本公开实施例提供了另一种数据传输方法，用于图1所示应用环境中的任一源极驱动芯片200，如图3所示，该方法包括：
步骤201、接收时序控制器在时钟校准后发送的预设的链路稳定校验数据。
步骤202、判断接收到的链路稳定校验数据是否正确。
步骤203、当接收到的链路稳定校验数据正确时，生成反馈信息，并向时序控制器发送反馈信息，使得时序控制器基于反馈信息向源极驱动芯片发送目标数据。
综上所述，本公开实施例提供的数据传输方法，源极驱动芯片接收时序控制器在时钟校准后发送的链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，所以提高了数据传输的可靠性和稳定性。
本公开实施例提供了又一种数据传输方法，用于图1所示应用环境，如图4a所示，该方法包括：
步骤301、在时钟校准后，时序控制器向源极驱动芯片发送预设的链路稳定校验数据。执行步骤302。
该源极驱动芯片为图1所示应用环境中的任一源极驱动芯片。
一方面，在时钟校准后，时序控制器向源极驱动芯片发送预设的链路稳定校验数据。
在本公开实施例中，时序控制器和源极驱动芯片先执行时钟校准操作，然后，时序控制器向源极驱动芯片发送链路稳定校验数据，以检测时序控制器和源极驱动芯片之间的链路的数据传输状态。
另一方面，在时钟校准后，且在时序控制器要进入低功耗唤醒状态时，时序控制器向源极驱动芯片发送链路稳定校验数据，该低功耗唤醒状态为时序控制器由无需传输数据的低功耗状态重新进入数据传输状态的过渡状态。
在本公开实施例中，当时序控制器和源极驱动芯片不需要传输数据时，时序控制器进入低功耗状态。当时序控制器和源极驱动芯片需要再次传输数据时，时序控制器需要进入低功耗唤醒状态，以恢复至正常工作状态。在时序控制器要进入低功耗唤醒状态时，时序控制器可以向源极驱动芯片发送链路稳定校验数据，以检测时序控制器和源极驱动芯片之间的链路的数据传输状态。该方法可以使时序控制器从低功耗唤醒状态快速恢复至正常工作状态。
在本公开实施例中，当时序控制器和源极驱动芯片需要再次传输数据时，时序控制器和源极驱动芯片无需执行时钟校准操作即可恢复至正常工作状态。
需要补充说明的是，本公开实施例中发送链路稳定校验数据这一步骤，除了可以在时序控制器要进入低功耗唤醒状态时执行外，还可以在时序控制器要进入其他状态时执行。只要是为了恢复至正常工作状态，时序控制器都可以向源极驱动芯片发送链路稳定校验数据，以检测时序控制器和源极驱动芯片之间的链路的数据传输状态。
在本公开实施例中，时序控制器向源极驱动芯片发送预设的链路稳定校验数据的同时，可以向源极驱动芯片发送该源极驱动芯片的身份标识。源极驱动芯片可以检测时序控制器发送的身份标识是否与自身的身份标识相同。当时序控制器发送的身份标识与自身的身份标识相同时，源极驱动芯片执行相应操作，参见步骤302至304，以及步骤 306等。
示例的，链路稳定校验数据由多个字节的数据码采用8b/10b(即将8比特数据编码成10比特数据)编码方式编码得到，该多个字节的数据码包括起始标识和数据位。
其中，起始标识用于指示数据传输开始，数据位携带有验证数据，该数据位中设置有扰码标识，该扰码标识的位置用于指示源极驱动芯片的端口和端口对应的线性反馈寄存器(英文：Linear Feedback Shift Register，简称：LFSR)的初始化时间点，该LFSR用于目标数据的加扰。利用一些特殊的代码如起始标识、扰码标识等，可以帮助接收端进行还原工作，且在早期发现数据码的传输错误，抑制错误继续发生。
其中，多个字节的数据码可以采用相关技术中的8b/10b编码方式编码得到。采用8b/10b编码方式编码时，是对多个字节的数据码中数据位携带的验证数据进行编码，无需对特殊代码(如起始标识和扰码标识等)进行编码。
采用8b/10b编码方式进行编码，可以使发送的“0”和“1”的数量保持基本一致，连续的“0”和“1”不超过5位，即每5个连续的“1”后必须插入一位“0”，每5个连续的“0”后必须插入一位“1”，从而保证信号DC(直流)平衡。
采用相关技术中的8b/10b编码方式对验证数据进行编码时，具体的，将一组连续的8比特数据划分为两部分，其前5位进行5B/6B(即将5比特(bit)数据编码成6比特数据)编码，后3位则进行3B/4B(即将3比特数据编码成4比特数据)编码。
但是采用相关技术中的8b/10b编码方法编码得到的数据中，每两组10比特数据之间的界限较为模糊，容易出现传输错误。所以为了保证待传输数据在接收端能够被正确复原，在本公开实施例中，在对验证数据编码时，可以先将验证数据的待编码字节对应的8比特数据编码为9比特数据，当待编码字节不是验证数据的首个字节时，检测9比特数据的第一位数据，以及与第一位数据相邻的前一位数据，当第一位数据与前一位数据的数值相同时，将9比特数据取反后在9比特数据后添加用于指示9比特数据经过取反操作的第十位数据，得到10比特数据，当第一位数据与前一位数据的数值不同时，在9比特数据 后添加用于指示9比特数据未经过取反操作的第十位数据，得到10比特数据，其中，该10比特数据为二进制数据。当待编码字节是验证数据的首个字节时，在9比特数据后添加指示9比特数据未经过取反操作的第十位数据，得到10比特数据。该编码过程中，先将8比特数据编码为9比特数据，然后添加第十位得到10比特数据，并且在每两个相邻的10比特数据间设置一个跳变沿，且第十位数据用于指示9比特数据是否经过取反操作，能有效保证待传输数据在接收端被正确复原，且跳变沿可以有效减少传输错误。
示例的，多个字节的数据码为40个字节的数据码。其中，起始标识为4个字节的K2码，扰码标识为4个字节的K3码，数据位携带的验证数据包括8个数据单元，每个数据单元包括4个字节的数据码。为了至少完成一次数据校验，起始标识与扰码标识之间存在至少4个字节的数据码。
在本公开的一个实施例中，时序控制器与多个源极驱动芯片连接，每个源极驱动芯片的每一端口针对接收到的数据可以采用一种解扰方式，该解扰方式与时序控制器对待发送的数据采用的加扰方式相对应。也即是，每个源极驱动芯片的不同端口采用不同的解扰方式。而为了对目标数据进行加扰，每个源极驱动芯片的端口对应一个LFSR。数据位中的扰码标识的位置用于指示源极驱动芯片的端口和该端口对应的LFSR的初始化时间点。示例的，当扰码标识为K3码时，源极驱动芯片接收到时序控制器发送的链路稳定校验数据，解码后，源极驱动芯片会根据K3码在数据位中的位置确定初始化某一端口的LFSR的时间点。源极驱动芯片为端口初始化LFSR的时间点不同，解扰之后的结果就不同。
示例的，验证数据包括的8个数据单元中每个数据单元可以包括依次排列的0xea、0xeb、0xec和0xed。其中，以0x开始的数据表示16进制数据，在16进制数据中，a表示十进制的10，b表示十进制的11，c表示十进制的12，d表示十进制的13，e表示十进制的14。源极驱动芯片根据验证数据达到校验数据的目的。当源极驱动芯片接收到的是正确的验证数据时，表明链路的数据传输状态较好。
示例的，图4b示出了向端口01发送的40个字节的数据码的示意图，图4c示出了向端口02发送的40个字节的数据码的示意图。图4b 和图4c中K3码的位置不同，假设端口01对应的LFSR的初始化时间点为t1，端口01对应的LFSR的初始化时间点为t2，那么t2与t1不同。
进一步的，为了进行多次校验和初始化LFSR，以降低后续错误概率，步骤301可以包括：持续1微秒向源极驱动芯片发送n次链路稳定校验数据，也即，时序控制器向源极驱动芯片发送n次链路稳定校验数据的总时长为1微秒。其中，n大于或等于5。
步骤302、源极驱动芯片判断接收到的链路稳定校验数据是否正确。当接收到的链路稳定校验数据正确时，执行步骤303，当接收到的链路稳定校验数据不正确时，执行步骤306。
具体的，如图4d所示，步骤302可以包括：
步骤3021、源极驱动芯片对接收到的链路稳定校验数据进行解码，得到解码数据。
该解码数据包括扰码标识，示例的，该解码数据包括K3码。
步骤3022、源极驱动芯片判断解码数据与多个字节的数据码是否相同。当解码数据与多个字节的数据码相同时，执行步骤3023，当解码数据与多个字节的数据码不相同时，执行步骤3024。
源极驱动芯片将解码数据与编码之前的多个字节的数据码进行比较，判断两者是否相同。
步骤3023、源极驱动芯片确定接收到的链路稳定校验数据正确。
基于步骤3022，源极驱动芯片判断解码数据与编码之前的多个字节的数据码是否相同，当解码数据与多个字节的数据码相同时，源极驱动芯片确定接收到的链路稳定校验数据正确。
进一步的，在步骤3023之后，该方法还可以包括：
1)源极驱动芯片根据扰码标识在解码数据中的位置，确定源极驱动芯片的端口和端口对应的LFSR的初始化时间点。
当解码数据与多个字节的数据码相同时，源极驱动芯片根据扰码标识(如K3码)在解码数据中的位置，确定源极驱动芯片的端口和端口对应的LFSR的初始化时间点。如上所述，源极驱动芯片为端口初始化LFSR的时间点不同，解扰之后的结果就不同，所以源极驱动芯片需要根据扰码标识在解码数据中的位置，得到端口对应的LFSR的初始化时间点。
示例的，源极驱动芯片可以根据预设的对应关系确定源极驱动芯片的端口和端口对应的LFSR的初始化时间点。该对应关系用于记录扰码标识在解码数据中的位置、源极驱动芯片的端口与LFSR的初始化时间点的对应关系。示例的，该对应关系可以如表1所示。比如，当扰码标识在解码数据中的位置为L1时，可以确定源极驱动芯片的端口为P01，端口P01对应的LFSR的初始化时间点为T1。也即，源极驱动芯片需要在T1时间点为端口P01初始化其对应的LFSR。
表1
Figure PCTCN2018089744-appb-000001
2)源极驱动芯片根据初始化时间点为端口初始化LFSR。
源极驱动芯片得到端口对应的LFSR的初始化时间点之后，可以按照该初始化时间点对该LFSR进行初始化，便于对后续传输的数据进行加扰和解扰。
步骤3024、源极驱动芯片确定接收到的链路稳定校验数据不正确。
当解码数据与编码之前的多个字节的数据码不相同时，源极驱动芯片确定接收到的链路稳定校验数据不正确，表明时序控制器和源极驱动芯片之间的链路的数据传输状态较差，此时，不适合传输显示数据、配置数据等。
步骤303、当接收到的链路稳定校验数据正确时，源极驱动芯片生成反馈信息。执行步骤304。
当源极驱动芯片接收到的链路稳定校验数据正确时，源极驱动芯片可以生成反馈信息，并将反馈信息发送至时序控制器，便于通知时序控制器当前链路的数据传输状态较好，适合传输显示数据、配置数据等。
步骤304、源极驱动芯片向时序控制器发送反馈信息。执行步骤305。
源极驱动芯片将生成的反馈信息发送至时序控制器，通知时序控制器当前链路的数据传输状态较好，然后时序控制器向源极驱动芯片发送目标数据。
步骤305、时序控制器基于反馈信息向源极驱动芯片发送目标数据。
示例的，目标数据为显示数据或配置数据。
步骤306、当接收到的链路稳定校验数据不正确时，源极驱动芯片重复执行相位校准操作，直至接收到正确的链路稳定校验数据。
示例的，当源极驱动芯片接收到的链路稳定校验数据不正确时，源极驱动芯片可以重复执行相位校准操作，进行相位漂移，直至接收到正确的链路稳定校验数据，进而使链路的数据传输状态较好，更适合传输目标数据。然后再执行步骤303至步骤305，完成目标数据的传输。
在本公开的一个实施例中，当源极驱动芯片接收到正确的链路稳定校验数据时，时序控制器才向源极驱动芯片发送目标数据，提高了数据传输的可靠性和稳定性。
进一步的，在本公开的一个实施例中，在传输链路稳定校验数据的过程中，当用户需要中断链路稳定校验数据的传输时，或者显示装置出现异常时，源极驱动芯片可以停止接收链路稳定校验数据，具体的，可以包括如下步骤：
1、当接收到传输中断指令时，时序控制器生成包含有中断标识的链路稳定校验数据。
该传输中断指令可以是用户触发的，也可以是显示装置出现异常时触发的。当用户需要中断链路稳定校验数据的传输时，用户可以触发一传输中断指令，时序控制器接收到该传输中断指令时，生成包含有中断标识的链路稳定校验数据，当显示装置出现异常时也会触发一传输中断指令，时序控制器接收到该传输中断指令时，也会生成包含有中断标识的链路稳定校验数据，便于源极驱动芯片基于该中断标识停止接收链路稳定校验数据。
示例的，中断标识为K1码或K4码。也即，当源极驱动芯片接收到K1码或K4码时，便停止接收链路稳定校验数据。
2、时序控制器向源极驱动芯片发送包含有中断标识的链路稳定校验数据。
时序控制器生成包含有中断标识的链路稳定校验数据后，将该链路稳定校验数据发送至源极驱动芯片，使得源极驱动芯片基于中断标 识停止接收链路稳定校验数据。
3、源极驱动芯片停止接收链路稳定校验数据。
当源极驱动芯片接收到时序控制器发送的包含有中断标识(比如K1码或K4码)的链路稳定校验数据时，源极驱动芯片便停止接收链路稳定校验数据。
需要补充说明的是，本公开的一个实施例提供的数据传输方法，适用于P2P接口协议，该方法适用于任一采用P2P接口协议的具有显示功能的产品或部件，该方法可以使P2P接口的发送端和接收端之间的链路更加稳定。
综上所述，本公开的实施例提供的数据传输方法，由于时序控制器能够向源极驱动芯片发送链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，该方法使得链路更加稳定，且能够使时序控制器从低功耗唤醒状态快速恢复至正常工作状态。该方法提高了数据传输的可靠性和稳定性。
本公开的一个实施例提供了一种数据传输电路，用于图1所示的应用环境中的时序控制器100，如图5a所示，该数据传输电路500包括：
第一发送器510，用于在时钟校准后，向源极驱动芯片发送预设的链路稳定校验数据。
接收器520，用于接收源极驱动芯片发送的反馈信息，该反馈信息是源极驱动芯片在判断接收到的链路稳定校验数据正确时生成的。
第二发送器530，用于基于反馈信息向源极驱动芯片发送目标数据。
综上所述，本公开的一个实施例提供的数据传输电路，由于时序控制器能够向源极驱动芯片发送链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，所以提高了数据传输的可靠性和稳定性。
示例的，第一发送器510，具体用于：
在时序控制器要进入低功耗唤醒状态时，向源极驱动芯片发送链路稳定校验数据，低功耗唤醒状态为时序控制器由无需传输数据的低功耗状态重新进入数据传输状态的过渡状态。
示例的，链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，多个字节的数据码包括起始标识和数据位。
其中，起始标识用于指示数据传输开始，数据位携带有验证数据，数据位中设置有扰码标识，扰码标识的位置用于指示源极驱动芯片的端口和端口对应的LFSR的初始化时间点，LFSR用于目标数据的加扰。
示例的，多个字节的数据码为40个字节的数据码，起始标识为4个字节的K2码，扰码标识为4个字节的K3码，数据位携带的验证数据包括8个数据单元，每个数据单元包括4个字节的数据码，起始标识与扰码标识之间存在至少4个字节的数据码。
示例的，第一发送器510，具体用于：持续1微秒向源极驱动芯片发送n次链路稳定校验数据，n大于或等于5。
进一步的，如图5b所示，该数据传输电路500还可以包括：生成器540，用于在接收到传输中断指令时，生成包含有中断标识的链路稳定校验数据。
第三发送器550，用于向源极驱动芯片发送包含有中断标识的链路稳定校验数据，使得源极驱动芯片停止接收链路稳定校验数据。
示例的，中断标识为K1码或K4码。
示例的，目标数据为显示数据或配置数据。
综上所述，本公开的一个实施例提供的数据传输电路，由于时序控制器能够向源极驱动芯片发送链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，所以提高了数据传输的可靠性和稳定性。
本公开的一个实施例提供了另一种数据传输电路，用于如图1所示应用环境中的任一源极驱动芯片200，如图6a所示，该数据传输电路600包括：接收器610，用于接收时序控制器在时钟校准后发送的预设的链路稳定校验数据。
判断器620，用于判断接收到的链路稳定校验数据是否正确。
生成器630，用于在接收到的链路稳定校验数据正确时，生成反馈信息，并向时序控制器发送反馈信息，使得时序控制器基于反馈信息向源极驱动芯片发送目标数据。
综上所述，本公开的一个实施例提供的数据传输电路，源极驱动芯片接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，所以提高了数据传输的可靠性和稳定性。
示例的，链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，多个字节的数据码包括起始标识和数据位，起始标识用于指示数据传输开始，数据位携带有验证数据，数据位中设置有扰码标识，扰码标识的位置用于指示源极驱动芯片的端口和端口对应的LFSR的初始化时间点，LFSR用于目标数据的加扰。
示例的，多个字节的数据码为40个字节的数据码，起始标识为4个字节的K2码，扰码标识为4个字节的K3码，数据位携带的验证数据包括8个数据单元，每个数据单元包括4个字节的数据码，起始标识与扰码标识之间存在至少4个字节的数据码。
示例的，接收器610具体用于：持续1微秒接收时序控制器发送的n次链路稳定校验数据，n大于或等于5。
进一步的，如图6b所示，该数据传输电路600还可以包括：第一处理器640，用于在接收到时序控制器发送的包含有中断标识的链路稳定校验数据时，停止接收链路稳定校验数据，包含有中断标识的链路稳定校验数据是时序控制器在接收到传输中断指令时生成的。
进一步的，如图6b所示，该数据传输电路600还可以包括：第二处理器650，用于在接收到的链路稳定校验数据不正确时，重复执行相位校准操作，直至接收到正确的链路稳定校验数据。
示例的，判断器620，具体用于：对接收到的链路稳定校验数据进行解码，得到解码数据，解码数据包括扰码标识，判断解码数据与多个字节的数据码是否相同，当解码数据与多个字节的数据码相同时，确定接收到的链路稳定校验数据正确，当解码数据与多个字节的数据码不相同时，确定接收到的链路稳定校验数据不正确。
示例的，判断器620，还用于：根据扰码标识在解码数据中的位置，确定源极驱动芯片的端口和端口对应的LFSR的初始化时间点，根据初始化时间点为端口初始化LFSR。
综上所述，本公开的一个实施例提供的数据传输电路，源极驱动芯片接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，当源极驱动芯片接收到的链路稳定模式数据正确时，表明链路的数据传输状态较好，源极驱动芯片向时序控制器发送反馈信息，使得时序控制器能够在链路的数据传输状态较好的情况下再向源极驱动芯片发送数据，所以提高了数据传输的可靠性和稳定性。
本公开的一个实施例还提供了一种显示装置，该显示装置包括时序控制器和源极驱动芯片。
其中，时序控制器包括图5a或图5b所示的数据传输电路，源极驱动芯片包括图6a或图6b所示的数据传输电路。
该显示装置可以为液晶面板、电子纸、有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的一个实施例还提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在计算机上运行时，使得计算机执行图2或图4a所示的数据传输方法。
本公开的一个实施例还提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在计算机上运行时，使得计算机执行图3或图4a所示的数据传输方法。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和器件的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (32)

  1. 一种数据传输方法，用于时序控制器，所述方法包括：
    在时钟校准后，向源极驱动芯片发送预设的链路稳定校验数据，
    接收所述源极驱动芯片发送的反馈信息，所述反馈信息是所述源极驱动芯片在判断接收到的链路稳定校验数据正确时生成的，
    基于反馈信息向所述源极驱动芯片发送目标数据。
  2. 根据权利要求1所述的方法，其中，所述向源极驱动芯片发送预设的链路稳定校验数据，包括：
    在所述时序控制器要进入低功耗唤醒状态时，向所述源极驱动芯片发送所述链路稳定校验数据，所述低功耗唤醒状态为所述时序控制器由无需传输数据的低功耗状态重新进入数据传输状态的过渡状态。
  3. 根据权利要求1所述的方法，其中，
    所述链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，
    所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
  4. 根据权利要求3所述的方法，其中，所述多个字节的数据码为40个字节的数据码，
    所述起始标识为4个字节的K2码，
    所述扰码标识为4个字节的K3码，
    所述数据位携带的验证数据包括8个数据单元，每个所述数据单元包括4个字节的数据码，所述起始标识与所述扰码标识之间存在至少4个字节的数据码。
  5. 根据权利要求1所述的方法，其中，所述向源极驱动芯片发送预设的链路稳定校验数据，包括：
    持续1微秒向所述源极驱动芯片发送n次所述链路稳定校验数据，所述n大于或等于5。
  6. 根据权利要求1所述的方法，其中，在所述向源极驱动芯片发送预设的链路稳定校验数据之后，所述方法还包括：
    响应于接收到传输中断指令，生成包含有中断标识的链路稳定校验数据，
    向所述源极驱动芯片发送包含有所述中断标识的链路稳定校验数据，以指示所述源极驱动芯片停止接收链路稳定校验数据。
  7. 根据权利要求6所述的方法，其中，
    所述中断标识为K1码或K4码。
  8. 根据权利要求1所述的方法，其中，
    所述目标数据为显示数据或配置数据。
  9. 一种数据传输方法，用于源极驱动芯片，所述方法包括：
    接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，
    判断接收到的链路稳定校验数据是否正确，
    响应于判断出接收到的链路稳定校验数据正确，生成反馈信息，并向所述时序控制器发送所述反馈信息，使得所述时序控制器基于所述反馈信息向所述源极驱动芯片发送目标数据。
  10. 根据权利要求9所述的方法，其中，
    所述链路稳定校验数据由多个字节的数据码采8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，
    所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
  11. 根据权利要求10所述的方法，其中，所述多个字节的数据码为40个字节的数据码，
    所述起始标识为4个字节的K2码，
    所述扰码标识为4个字节的K3码，
    所述数据位携带的验证数据包括8个数据单元，每个所述数据单元包括4个字节的数据码，所述起始标识与所述扰码标识之间存在至少4个字节的数据码。
  12. 根据权利要求9所述的方法，其中，所述接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，包括：
    持续1微秒接收所述时序控制器发送的n次所述链路稳定校验数据，所述n大于或等于5。
  13. 根据权利要求9所述的方法，其中，在所述接收时序控制器在时钟校准后发送的预设的链路稳定校验数据之后，所述方法还包括：
    响应于接收到所述时序控制器发送的包含有中断标识的链路稳定校验数据，停止接收链路稳定校验数据，所述包含有中断标识的链路稳定校验数据是所述时序控制器在接收到传输中断指令时生成的。
  14. 根据权利要求9所述的方法，其中，在所述判断接收到的链路稳定校验数据是否正确之后，所述方法还包括：
    响应于接收到的链路稳定校验数据不正确，重复执行相位校准操作，直至接收到正确的链路稳定校验数据。
  15. 根据权利要求10所述的方法，其中，所述判断接收到的链路稳定校验数据是否正确，包括：
    对接收到的链路稳定校验数据进行解码，得到解码数据，所述解码数据包括所述扰码标识，
    判断所述解码数据与所述多个字节的数据码是否相同，
    响应于所述解码数据与所述多个字节的数据码相同，确定接收到的链路稳定校验数据正确，
    响应于所述解码数据与所述多个字节的数据码不相同，确定接收到的链路稳定校验数据不正确。
  16. 根据权利要求15所述的方法，其中，在所述确定接收到的链路稳定校验数据正确之后，所述方法还包括：
    根据所述扰码标识在所述解码数据中的位置，确定所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，
    根据所述初始化时间点为所述端口初始化所述LFSR。
  17. 一种数据传输电路，用于时序控制器，所述数据传输电路包括：
    第一发送器，用于在时钟校准后，向源极驱动芯片发送预设的链路稳定校验数据，
    接收器，用于接收所述源极驱动芯片发送的反馈信息，所述反馈信息是所述源极驱动芯片在判断接收到的链路稳定校验数据正确时生成的，
    第二发送器，用于基于反馈信息向所述源极驱动芯片发送目标数据。
  18. 根据权利要求17所述的数据传输电路，其中，所述第一发送 器，具体用于：
    在所述时序控制器要进入低功耗唤醒状态时，向所述源极驱动芯片发送所述链路稳定校验数据，所述低功耗唤醒状态为所述时序控制器由无需传输数据的低功耗状态重新进入数据传输状态的过渡状态。
  19. 根据权利要求17所述的数据传输电路，其中，
    所述链路稳定校验数据由多个字节的数据码采用8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，
    所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有扰码标识，所述扰码标识的位置用于指示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
  20. 根据权利要求19所述的数据传输电路，其中，所述多个字节的数据码为40个字节的数据码，
    所述起始标识为4个字节的K2码，
    所述扰码标识为4个字节的K3码，
    所述数据位携带的验证数据包括8个数据单元，每个所述数据单元包括4个字节的数据码，所述起始标识与所述扰码标识之间存在至少4个字节的数据码。
  21. 根据权利要求17所述的数据传输电路，其中，所述第一发送器，具体用于：
    持续1微秒向所述源极驱动芯片发送n次所述链路稳定校验数据，所述n大于或等于5。
  22. 根据权利要求17所述的数据传输电路，其中，所述数据传输电路还包括：
    生成器，用于在接收到传输中断指令时，生成包含有中断标识的链路稳定校验数据，
    第三发送器，用于向所述源极驱动芯片发送包含有所述中断标识的链路稳定校验数据，以指示所述源极驱动芯片停止接收链路稳定校验数据。
  23. 根据权利要求22所述的数据传输电路，其中，
    所述中断标识为K1码或K4码。
  24. 根据权利要求17所述的数据传输电路，其中，
    所述目标数据为显示数据或配置数据。
  25. 一种数据传输电路，用于源极驱动芯片，所述数据传输电路包括：
    接收器，用于接收时序控制器在时钟校准后发送的预设的链路稳定校验数据，
    判断器，用于判断接收到的链路稳定校验数据是否正确，
    生成器，响应于判断出接收到的链路稳定校验数据正确，生成反馈信息，并向所述时序控制器发送所述反馈信息，使得所述时序控制器基于所述反馈信息向所述源极驱动芯片发送目标数据。
  26. 根据权利要求25所述的数据传输电路，其中，所述数据传输电路还包括：
    第一处理器，用于在接收到所述时序控制器发送的包含有中断标识的链路稳定校验数据时，停止接收链路稳定校验数据，所述包含有中断标识的链路稳定校验数据是所述时序控制器在接收到传输中断指令时生成的。
  27. 根据权利要求25所述的数据传输电路，其中，所述数据传输电路还包括：
    第二处理器，用于在接收到的链路稳定校验数据不正确时，重复执行相位校准操作，直至接收到正确的链路稳定校验数据。
  28. 根据权利要求25所述的数据传输电路，其中，所述判断器，具体用于：
    对接收到的链路稳定校验数据进行解码，得到解码数据，所述解码数据包括扰码标识，
    判断所述解码数据与所述多个字节的数据码是否相同，
    响应于所述解码数据与所述多个字节的数据码相同，确定接收到的链路稳定校验数据正确，
    响应于所述解码数据与所述多个字节的数据码不相同，确定接收到的链路稳定校验数据不正确，其中
    所述链路稳定校验数据由多个字节的数据码采8b/10b编码方式编码得到，所述多个字节的数据码包括起始标识和数据位，
    所述起始标识用于指示数据传输开始，所述数据位携带有验证数据，所述数据位中设置有所述扰码标识，所述扰码标识的位置用于指 示所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，所述LFSR用于所述目标数据的加扰。
  29. 根据权利要求28所述的数据传输电路，其中，所述判断器，还用于：
    根据所述扰码标识在所述解码数据中的位置，确定所述源极驱动芯片的端口和所述端口对应的线性反馈寄存器LFSR的初始化时间点，
    根据所述初始化时间点为所述端口初始化所述LFSR。
  30. 一种显示装置，包括时序控制器和源极驱动芯片，
    所述时序控制器包括权利要求17至24任一所述的数据传输电路，
    所述源极驱动芯片包括权利要求25至32任一所述的数据传输电路。
  31. 一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在计算机上运行时，使得计算机执行权利要求1至8任一所述的数据传输方法。
  32. 一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在计算机上运行时，使得计算机执行权利要求9至16任一所述的数据传输方法。
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