WO2018214952A1

WO2018214952A1 - Voltage sampling circuit and circuit system

Info

Publication number: WO2018214952A1
Application number: PCT/CN2018/088364
Authority: WO
Inventors: 樊珊珊; 杨运东; 王方淳
Original assignee: 中兴通讯股份有限公司
Priority date: 2017-05-25
Filing date: 2018-05-25
Publication date: 2018-11-29
Also published as: CN108964418A; CN108964418B

Abstract

Provided are a voltage sampling circuit and a circuit system. The voltage sampling circuit comprises a differential sampling circuit for sampling a bus circuit, wherein a blocking unit is arranged in the differential sampling circuit.

Description

Voltage sampling circuit and circuit system

Technical field

The present disclosure relates to the field of communications, and in particular to a voltage sampling circuit and a circuit system.

Background technique

In the related art, switching power supplies are currently developing toward high power density, high efficiency, and low cost. In order to increase the power density of the power supply, a smaller package of the same performance device can be selected, and the switching frequency can be increased to reduce the volume of the magnetic device such as a transformer and an inductor. Achieving high efficiency requires reducing the switching losses and conduction losses of the switching transistor, which can be achieved by selecting new components and suitable topologies. Achieving low cost requires cost reduction through topology and device selection while meeting high power density and high efficiency. In addition, the topology also determines the range of choices for the device used.

The multi-way totem pole bridgeless power factor correction (PFC) series input structure can utilize the low on-voltage characteristics of the low-voltage device to achieve higher efficiency and contribute to the improvement of power density. In the PFC circuit, the bus (BUS) voltage value directly participates in the loop calculation, which determines the stability of the BUS voltage. Therefore, the sampling circuit of the BUS voltage is crucial for the loop regulation of the entire system. Although the structure of the multi-way totem pole bridgeless PFC series input can reduce the withstand voltage level of the switching device, improve the efficiency, and reduce the input ripple, the individual BUS capacitors are connected in series through the switching tube, so that the sampling of the total BUS voltage becomes difficult. Therefore, it is necessary to separately sample the voltage of each BUS capacitor and then participate in the loop calculation by software summation as the total BUS voltage.

At present, the commonly used voltage sampling circuit includes a resistor divider sampling circuit and a differential sampling circuit.

The differential sampling circuit processes the difference between the two input signals to effectively eliminate common mode interference. For the structure of multiple PFC series input, since the BUS capacitors are not common, a differential sampling circuit is needed. However, the structure of the multi-channel PFC series input is complicated, and each BUS voltage requires a differential sampling circuit, which causes a loop to be formed through the sampling circuit, so that each BUS is not evenly pressed. BUS uneven voltage can cause loop control to be unstable, and even cause a single BUS voltage to be too high, causing damage to the device or abnormal shutdown of the system.

There is no effective solution to the problem of BUS uneven voltage in the sampling circuit in the related art.

Summary of the invention

The embodiments of the present disclosure provide a voltage sampling circuit and a circuit system to solve at least the problem of BUS uneven voltage in the sampling circuit in the related art.

According to an aspect of the present disclosure, there is provided a voltage sampling circuit including a differential sampling circuit for sampling a BUS circuit, wherein a blocking unit is disposed in the differential sampling circuit.

In accordance with another aspect of the present disclosure, an electrical circuit system is provided, including a voltage sampling circuit in accordance with the present disclosure.

DRAWINGS

The drawings described herein are provided to provide a further understanding of the present disclosure, which is a part of the present disclosure, and the description of the present disclosure and the description thereof are not intended to limit the disclosure. In the drawing:

1 is a schematic diagram of a voltage sampling circuit in accordance with an embodiment of the present disclosure;

2 is a block diagram showing the structure of a multi-way series BUS voltage sampling circuit with a blocking function according to an embodiment of the present disclosure;

3 is a schematic diagram of a multiple serial BUS voltage sampling circuit that utilizes a diode to implement a blocking function, in accordance with an embodiment of the present disclosure;

4 is a schematic diagram of a multiple serial BUS voltage sampling circuit that implements a blocking function using a MOS transistor in accordance with an embodiment of the present disclosure.

detailed description

A voltage sampling circuit is provided in the present application, which can be applied to voltage sampling of a multi-channel PFC serial input bus circuit, that is, there are multiple BUS circuits, and each BUS circuit can utilize the voltage sampling provided by the embodiment of the present disclosure. The circuit performs voltage sampling.

1 is a schematic diagram of a voltage sampling circuit in accordance with an embodiment of the present disclosure.

As shown in FIG. 1, the voltage sampling circuit according to an embodiment of the present disclosure may include four parts: a high-impedance isolation circuit S1, a differential sampling circuit S2 having a blocking function, a filter circuit S3, and a control unit S4.

In the differential sampling circuit S2 having the blocking function, a differential sampling circuit for voltage sampling the BUS circuit is shown. A blocking unit is provided in the differential sampling circuit S2. As shown in FIG. 1, a blocking unit is provided at a position where the differential sampling circuit S2 is connected to the power source and a position connected to the ground.

By setting a blocking unit at a position where the differential sampling circuit is connected to the power source and to the ground, the problem of BUS uneven voltage in the sampling circuit in the related art is solved, and the charging circuit caused by the sampling circuit is blocked. It ensures the voltage stability of each BUS position.

As shown in FIG. 1, an operational amplifier is included in the differential sampling circuit S2, and a blocking unit is not provided at the operational amplifier. It should be noted that in the differential sampling circuit that performs voltage sampling on the BUS circuit, no blocking unit is provided at the position of the power source and the ground connected to the operational amplifier, that is, in the order of current flow, before the operational amplifier A blocking unit is provided in the differential sampling circuit.

According to an embodiment of the present disclosure, the blocking unit is for blocking a charging loop caused by the voltage sampling circuit.

As shown in FIG. 1, the number of blocking units in the differential sampling circuit is three, that is, a blocking unit is provided at a position where it is connected to the power source and a position where it is connected to the ground at two places.

According to an embodiment of the present disclosure, the blocking unit includes one of a diode, a MOS transistor, and a relay. It should be noted that electronic components capable of functioning as blocking functions can be used as blocking units in the voltage sampling circuit according to the present disclosure, and are included in the protection scope of the present disclosure.

A voltage sampling circuit in accordance with an embodiment of the present disclosure may be applied to voltage sampling of a multi-channel PFC series input bus circuit.

As shown in FIG. 1, the differential sampling circuit S2 is connected to the BUS capacitor of the BUS circuit through the high-impedance isolation circuit S1. In the high-resistance isolation circuit S1, an equal number of resistors are respectively disposed on both sides of the positive and negative sides of the BUS capacitor. Further, the output current of the differential sampling circuit S2 is transmitted to the control unit S4 through the filter circuit S3.

The embodiments of the present disclosure are further described in detail below.

Embodiments of the present disclosure provide a voltage sampling circuit that can be used for a bus circuit having a topology similar to a multi-channel PFC series input and various floating structures to effectively eliminate common mode interference without causing individual BUS uneven voltages . By adding a blocking unit to the conventional differential sampling circuit, the charging circuit caused by the sampling circuit can be blocked while accurately and efficiently sampling the voltage of the BUS.

When voltage sampling is performed on the multi-channel PFC series input bus circuit, the power portion and the control portion are isolated by the high-resistance isolation circuit; the common-mode interference signal is suppressed by the differential sampling circuit, that is, the isolated signal is differentially sampled. The circuit filters out the common mode interference and obtains the corresponding proportional and biased BUS voltage signal; the charging circuit caused by the blocking unit is cut off by adding the blocking unit; then, the sampling signal is output from the operational amplifier of the differential sampling circuit and then fed to the control through the filtering circuit. A unit (for example, a CPU) performs loop calculations by restoring the true BUS voltage.

For the charging circuit caused by the sampling circuit, the blocking unit is added, that is, the blocking device or the blocking circuit is appropriately connected in the BUS voltage sampling circuit of the first and last units, and the multiple BUS voltages are cut off. The boosting circuit formed by the sampling circuit effectively prevents the BUS voltage of the first unit and the last unit from being excessively high and the problem of multi-channel BUS unevenness. It should be noted that one unit can be regarded as a BUS circuit, that is, the technical solution of the present disclosure can be applied to a circuit system in which a plurality of BUS circuits exist.

The voltage sampling circuit in accordance with the present disclosure substantially provides a simple floating voltage sampling circuit. The topology to which the voltage sampling circuit of the present disclosure is applicable is not limited to a multi-channel PFC series circuit, and other multi-channel series floating structures having a participating main power loop are also applicable to the voltage sampling circuit according to the present disclosure.

2 is a block diagram showing the structure of a multi-way series BUS voltage sampling circuit with a blocking function according to an embodiment of the present disclosure.

As shown in FIG. 2, the voltage sampling circuit according to an embodiment of the present disclosure includes a high resistance isolation circuit, a differential sampling circuit with a blocking function, a filter circuit, and a control unit. The control unit can include a digital signal processor for analog to digital conversion and loop calculations.

For bus circuits with multiple PFC series circuits or similar topologies, the voltage sampling circuit with blocking unit is a simple and effective sampling circuit. The four hardware units of the sampling circuit shown in Figure 2 can isolate and sample the single BUS voltage, and filter the sampled voltage signal to the CPU for loop calculation.

Referring to Figures 1 and 2, the high resistance isolation circuit S1 provides an input resistance and provides the function of isolating the power portion from the control portion. Therefore, resistors R1 to R4 (see Figure 1) require resistors with a large resistance, typically several hundred KΩ to several MΩ.

The basic principle of the differential sampling circuit S2 having the blocking unit is substantially the same as that of the differential sampling circuit in the related art, that is, the non-inverting input terminal and the inverting input terminal follow the principle of differential resistance balancing. Therefore, the resistance values of the input resistors R1, R3, and R5 and R2, R4, and R6 in the high-resistance isolation circuit S1 and the differential sampling circuit S2 should be respectively in one-to-one correspondence. Resistors R7 and R9 provide a DC bias for the differential sampling circuit S2, and the resistance of the resistor R9 and the feedback resistor R10 are equal, and the resistances of the resistors R7 and R8 are equal. By adjusting the resistances of the resistors R7 and R8, the bias voltage of the differential sampling circuit S2 can be adjusted without affecting the sampling ratio. By adjusting the resistance values of the input resistors R1, R3, R5 and R2, R4, R6, the sampling ratio can be adjusted without affecting the DC offset of the differential sampling circuit S2.

Unlike the differential sampling circuit of the related art, three blocking units are provided to prevent the AC input from forming a charging circuit through the sampling circuits of the first unit and the last unit. The power supply and the ground in each sampling circuit are the same network. Without adding a blocking unit, the AC input will charge the sampling circuit of the first unit and the last unit through the power and ground in the sampling circuit. The loop makes the bus capacitance of these two units higher than the bus capacitance of other units, causing multi-channel bus non-uniform voltage problems. A blocking unit, such as a diode (as shown in FIG. 3), is added at a position where the differential sampling circuit is connected to the power source and a position connected to the ground, thereby blocking the charging current path by using the forward conduction characteristic of the diode. Does not affect the normal operation of the sampling circuit. The diode used as the blocking unit should try to select a Schottky diode with a very small voltage drop. In addition, the blocking unit may also be a switching device such as a MOS transistor (as shown in FIG. 4), a relay, or the like that can function as a blocking function.

Continuing to refer to FIG. 1 and FIG. 2, the sampled BUS voltage signal needs to pass through the filter circuit S3 to eliminate the spike glitch, so that the voltage signal reaching the control unit S4 (for example, the CPU) can be relatively clean, which is advantageous for sampling accuracy. If an RC filter circuit is used, the values of the resistor and capacitor are determined according to the ripple frequency of the BUS voltage. The cutoff frequency of the RC filter circuit is greater than the ripple frequency of the BUS voltage. In addition, other filtering circuits may be selected to filter the sampling signal as needed.

The signal outputted by the filter circuit can be directly sent to the analog-to-digital conversion port in the control unit S4 to convert the analog signal into a digital signal, and then the actual BUS voltage is restored in the control unit S4 and compared with the BUS voltage of other units. After adding, the total BUS voltage is obtained for loop calculation and the Pulse Width Modulation (PWM) waveform is controlled.

The voltage sampling circuit of the present disclosure provides an easy to use and low cost solution for high power and high efficiency switching power supply voltage sampling. The use of such a voltage sampling circuit can improve the accuracy of the control loop and solve the problem of uneven voltage of the multi-channel serial input bus circuit.

The above description is only an embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Various changes and modifications of the present disclosure are possible to those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

A voltage sampling circuit includes a differential sampling circuit for sampling a bus circuit,

Wherein, a blocking unit is provided in the differential sampling circuit.
The voltage sampling circuit according to claim 1, wherein said differential sampling circuit comprises an operational amplifier, and said blocking unit is not provided at said operational amplifier.
The voltage sampling circuit of claim 1 wherein said blocking unit is operative to block a charging loop caused by said voltage sampling circuit.
The voltage sampling circuit according to claim 1, wherein said blocking unit is provided at a position where said differential sampling circuit is connected to a power source and a position connected to the ground.
The voltage sampling circuit according to claim 1, wherein the number of blocking units in the differential sampling circuit is three.
The voltage sampling circuit of claim 1 wherein said blocking unit comprises one of:

Diodes, MOS tubes, relays.
The voltage sampling circuit of claim 1 wherein said voltage sampling circuit is applied to voltage sampling of a multi-channel power factor correction series input bus circuit.
The voltage sampling circuit of claim 1 further comprising a high impedance isolation circuit,

Wherein the differential sampling circuit is connected to a bus capacitor of the bus circuit through the high resistance isolation circuit, and

Wherein, in the high resistance isolation circuit, an equal number of resistors are respectively disposed on both sides of the bus capacitor.
The voltage sampling circuit according to claim 1, further comprising a filter circuit and a control unit,

The output current of the differential sampling circuit is transmitted to the control unit through the filter circuit.
A circuit system comprising the voltage sampling circuit of any of claims 1-9.