CN108964418B

CN108964418B - Voltage sampling circuit and circuit system

Info

Publication number: CN108964418B
Application number: CN201710381301.7A
Authority: CN
Inventors: 樊珊珊; 杨运东; 王方淳
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2017-05-25
Filing date: 2017-05-25
Publication date: 2021-08-17
Anticipated expiration: 2037-05-25
Also published as: WO2018214952A1; CN108964418A

Abstract

The invention provides a voltage sampling circuit and a circuit system, wherein the voltage sampling circuit comprises: and the differential sampling circuit is used for sampling the BUS circuit, wherein the joints of the differential sampling circuit and other BUS circuits are provided with blocking units on one side of the differential sampling circuit. By adopting the technical scheme, the problem that the BUSs in the differential sampling circuit in the related technology are not voltage-sharing is solved, the charging loop caused by the sampling circuit is blocked, and the voltage stability of the positions of the BUSs is ensured.

Description

Voltage sampling circuit and circuit system

Technical Field

The invention relates to the field of communication, in particular to a voltage sampling circuit and a circuit system.

Background

In the related art, the switching power supply is currently developed toward the goals of high power density, high efficiency, and low cost. The power density of the power supply is improved, the size of magnetic devices such as a transformer and an inductor can be reduced by selecting devices with the same performance and smaller packages and improving the switching frequency. The high efficiency then needs to reduce switching tube switching loss and conduction loss, and the accessible selects for use new components and parts and suitable topological structure to realize. The low cost requires a reduction in cost through the choice of topology and device while satisfying high power density and high efficiency, and of course, the choice of topology also determines the choice of devices used. The structure that the input of the multi-path totem-pole bridgeless PFC is connected in series can realize higher efficiency by utilizing the characteristic of small on-resistance of a low-voltage device and is beneficial to the improvement of power density.

The BUS voltage value in the PFC circuit directly participates in loop calculation and determines the stability of the BUS voltage, so that the sampling circuit of the BUS voltage is of great importance to the loop regulation of the whole system. Although the structure of the multi-path totem-pole bridgeless PFC input series connection can reduce the voltage-resistant grade of a switching device, improve the efficiency and reduce the input ripple, the various BUS capacitors are connected in series through a switching tube, so that the voltage sampling of the total BUS becomes difficult. Therefore, the voltage of each BUS capacitor needs to be separately sampled and then summed by software to be the total BUS voltage to participate in the loop calculation.

The current voltage sampling circuit is commonly used in a resistance voltage division sampling circuit and a differential sampling circuit.

The resistance voltage division sampling circuit divides the voltage to be sampled through the two resistors and then sends the sampling signal into the CPU for processing through the voltage follower and the filter circuit.

The differential sampling circuit processes the difference value of two input signals, and can effectively eliminate common-mode interference. For the PFC structure of multichannel series connection, because each BUS electric capacity is not earthed, need use differential sampling circuit, but the PFC structure of multichannel series connection input is complicated, and every way BUS voltage all needs differential sampling circuit, can lead to the circuit to form the return circuit through sampling circuit and make each way BUS voltage-sharing not. The BUS is not balanced, so that the loop control is unstable, and even the single-path BUS is in overvoltage damage to devices or abnormal shutdown of the system is caused.

Aiming at the problem that buses in different paths are not uniform in voltage in a differential sampling circuit in the related technology, no effective solution is available at present.

Disclosure of Invention

The embodiment of the invention provides a voltage sampling circuit and a circuit system, which at least solve the problem that buses in a differential sampling circuit in the related art are not voltage-sharing.

According to an embodiment of the present invention, there is provided a voltage sampling circuit including: and the differential sampling circuit is used for sampling the BUS circuit, wherein the joints of the differential sampling circuit and other BUS circuits are provided with blocking units on one side of the differential sampling circuit.

Optionally, at the junction of the differential sampling circuit and another BUS circuit, a blocking unit is disposed on one side of the differential sampling circuit, including: the blocking unit is not arranged at the position of an operational amplifier in the differential sampling circuit.

Optionally, the blocking unit is configured to prevent a current at a low voltage from flowing back to a high voltage in the differential sampling circuit.

Optionally, at the junction of the differential sampling circuit and another BUS circuit, a blocking unit is disposed on one side of the differential sampling circuit, including: the blocking unit is arranged at the joint of the differential sampling circuit and a power supply VCC and/or the joint of the differential sampling circuit and GND.

Optionally, the number of the blocking units in the differential sampling circuit is three.

Optionally, the blocking unit comprises one of: diode, MOS pipe, relay.

Optionally, the voltage sampling circuit is applied to a multi-path PFC series input circuit.

Optionally, the differential sampling circuit is connected to a BUS capacitor of the BUS circuit through a high-resistance isolation circuit, wherein equal numbers of resistors are respectively arranged on the high-resistance isolation circuit corresponding to positive and negative sides of the BUS capacitor.

Optionally, the output current of the differential sampling circuit is connected to the control unit of the BUS circuit through a filter.

According to another embodiment of the present invention, there is provided a circuit system including a plurality of the voltage sampling circuits described in any one of the above embodiments.

According to the invention, in the differential sampling circuit of the BUS circuit, the blocking unit is arranged at the position where the differential sampling circuit is connected with other BUS circuits, including the position connected with VCC or GND.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of a voltage sampling circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a multiple series BUS voltage sampling circuit with an interrupt function, in accordance with an embodiment;

FIG. 3 is a diagram of a multiple series BUS voltage sampling circuit with diode blocking according to an embodiment;

fig. 4 is a diagram of a multi-path serial BUS voltage sampling circuit with MOS tube blocking according to an embodiment.

Detailed Description

Example one

The application file provides a voltage sampling circuit, can be applied to the voltage sampling to multichannel PFC series connection input BUS circuit BUS, has multichannel BUS circuit promptly, and every BUS circuit all can set up according to the voltage sampling circuit who records in this embodiment.

In this embodiment, a voltage sampling circuit is provided, and fig. 1 is a schematic diagram of a voltage sampling circuit according to an embodiment of the present invention, as shown in fig. 1, the process includes the following steps: the voltage sampling circuit can comprise four parts:

s1, a high-resistance isolation circuit; s2, a differential sampling circuit with a disconnection unit; s3, a filter circuit; s4, a control unit.

In the section S2, a differential sampling circuit for sampling a BUS circuit is shown, where a blocking unit is disposed on one side of the differential sampling circuit at a connection between the differential sampling circuit and another BUS circuit. It is added that the connection of the differential sampling circuit and other BUS circuits includes: the position of connecting the power, the position of ground connection, at these positions, through setting up the isolation that blocks the unit and realize other BUS circuits.

Optionally, the blocking unit is not disposed at an operational amplifier in the differential sampling circuit. It is to be added that, in the differential sampling circuit of the BUS circuit, no blocking unit is provided at VCC and GND connected at the operational amplifier, and the blocking unit is provided only in the differential sampling circuit before the operational amplifier in order of the current flow.

Optionally, the blocking unit is configured to prevent a current at a low voltage from flowing back to a high voltage in the differential sampling circuit. It is added that the blocking unit in the circuit blocks in the direction of backflow from the low voltage to the high voltage, and the high voltage flows normally to the low voltage without blocking.

Optionally, the blocking unit comprises one of: diodes, MOS transistors, relays, etc. It should be added that all electronic components that function as blocking functions are within the scope of protection of the present document.

The following detailed description is given in conjunction with preferred embodiments of the present invention.

The preferred embodiment aims to provide a voltage sampling method which can be used for similar topologies such as multi-path PFC series input and various floating structures, and can effectively eliminate common-mode interference and avoid the non-voltage-sharing of various BUSs by the sampling method, and can block a charging loop caused by a sampling circuit when accurately and effectively sampling the BUS voltage by only additionally adding a plurality of blocking units on a traditional differential sampling circuit.

The preferred embodiment adopts the following technical scheme:

a method for sampling BUS voltage of a multi-path Power Factor Correction (PFC) serial input BUS circuit. The method mainly comprises the steps of isolating the BUS voltage of a power circuit through a high resistance, inhibiting a common mode interference signal through a differential sampling circuit, cutting off a charging loop caused by the sampling circuit through adding a blocking unit, and sending the sampling signal to a CPU (central processing unit) through a filter circuit after coming out of an operational amplifier for loop calculation. The main contents of the preferred embodiment include:

1. the differential sampling circuit comprises a high-resistance isolation circuit and a signal conditioning circuit. The BUS voltage is isolated from the power part and the control part through a series of resistors, the isolated signals are filtered and subjected to common-mode interference through a differential sampling circuit, BUS voltage signals with corresponding proportions and offset are obtained and sent to the CPU, and then real BUS voltage is restored for loop calculation.

2. The charging loop blocking circuit caused by the sampling circuit properly connects the blocking units such as diodes in series in the BUS voltage sampling circuits of the first cell and the last cell, and cuts off the boosting loop formed by the multiple BUS voltage sampling circuits, thereby effectively preventing the BUS voltages of the first cell and the last cell from being too high and preventing the multiple BUSs from not equalizing voltage. It should be added that one Cell can be regarded as a BUS circuit, that is, the technical scheme of the present application document can be applied to a circuit system with a plurality of BUS circuits.

The preferred embodiment provides a simple floating ground voltage sampling circuit. The topology applicable to the preferred embodiment is not limited to the multi-path PFC series circuit, and other voltage sampling circuits with multi-path series floating structure participating in the main power loop are also applicable.

The following are specific embodiments of the invention

Fig. 2 is a block diagram of a multi-path serial BUS voltage sampling circuit with an interrupt function according to a specific embodiment, and as shown in fig. 2, the voltage sampling circuit includes four parts, a high-resistance isolation circuit, a differential sampling circuit with an interrupt function, a filter circuit, and a control unit, where the control unit includes a DSP analog-to-digital converter for loop calculation.

For the topology with multi-path PFC series connection or similar functions, the BUS voltage sampling circuit with the blocking unit is a simple and effective sampling circuit. The circuit may be subdivided into four hardware units. The hardware circuit in figure 1 realizes the isolation and sampling of the single-path BUS voltage, and sends the sampled voltage signal to the CPU for loop calculation after filtering.

The S1 module is an input resistor, is a part of the differential sampling circuit, and also has the function of isolating the power part from the control part, so that resistors with larger resistance values, generally hundreds of K Ω to M Ω, need to be selected from R1 to R4.

The basic principle of the differential sampling circuit module S2 with the blocking unit is the same as that of a general differential sampling circuit, and the non-inverting input terminal and the inverting input terminal follow the principle of differential resistance balance. The input resistors R1, R3 and R5 are in one-to-one correspondence with the resistances of R2, R4 and R6, R7 and R9 provide direct current bias for the differential sampling circuit, R9 is equal to the feedback resistor R10, and R7 is equal to R8. The bias voltage of the sampling circuit can be adjusted without influencing the sampling proportion by adjusting the resistance values of the R7 and the R8, and the sampling proportion can be adjusted without influencing the direct current bias of the sampling circuit by adjusting the resistance values of the input resistors R1, R3, R5 and R2, R4 and R6. The addition of three blocking units is to block the charging loop formed by the BUS sampling circuits of the first cell and the last cell by the ac input. VCC and GND in the sampling circuit are the same network, and when a blocking unit is not added, alternating current input can enable the first cell and the last cell to form a charging loop through VCC and GND in the sampling circuit, so that the charging of BUS capacitors of the two cells is higher than that of other cells, and the problem of multipath uneven voltage is caused. Blocking units, such as diodes (fig. 3 is a diagram of a multi-path serial BUS voltage sampling circuit with a diode blocking function according to the specific embodiment), are added at VCC and GND in the sampling circuit, and the path of the charging current is blocked by utilizing the forward conduction characteristic of the diodes, and meanwhile, the normal operation of the sampling circuit is not influenced. The diode is selected from Schottky diodes with very small conduction voltage drop as much as possible. The blocking unit may also be a MOS transistor (fig. 4 is a multi-path serial BUS voltage sampling circuit diagram with MOS transistor blocking function according to the specific embodiment), a relay, or other switching devices that can perform the blocking function.

The sampled BUS voltage signal needs to be filtered by the filter circuit S3 to eliminate spike burrs, so that the voltage signal reaching the CPU is cleaner, and the sampling accuracy is facilitated. If an RC filter circuit is adopted, the selection of the RC value is determined according to the BUS voltage ripple frequency, and the cut-off frequency is larger than the ripple frequency. Other filter circuits can be selected as required to filter the sampling signal.

The signal output by the filter circuit can be directly sent to an analog-to-digital conversion port of a CPU in the control unit S4 to convert the analog signal into a digital signal, and then the actual BUS voltage is calculated and restored in the CPU, and is added to the BUS voltages of other cells for loop calculation, thereby controlling pulse Width Modulation (PWM for short) wave transmission.

By adopting the technical scheme, a simple and easy-to-use scheme with low cost is provided for sampling the voltage of the high-power high-efficiency switching power supply. The sampling circuit has good effects of improving the accuracy of a control loop and solving the problem of uneven voltage of multi-path series connection.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

Example two

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A voltage sampling circuit, comprising: the differential sampling circuit is used for sampling the BUS circuit, wherein blocking units are arranged on one side of the differential sampling circuit at the connection positions of the differential sampling circuit and other BUS circuits;

when a plurality of BUS circuits are provided, the BUS circuits are connected in series, and the differential sampling circuits corresponding to the BUS circuits have the same structure;

the junction of difference sampling circuit and other BUS circuits all is in difference sampling circuit one side is provided with blocks the unit, includes:

the blocking unit is not arranged at the position of an operational amplifier in the differential sampling circuit;

the blocking unit is used for preventing current at a low voltage position in the differential sampling circuit from flowing back to a high voltage position.

2. The circuit of claim 1, wherein at the connection of the differential sampling circuit and other BUS circuits, a blocking unit is provided at one side of the differential sampling circuit, comprising:

the blocking unit is arranged at the joint of the differential sampling circuit and a power supply VCC and/or the joint of the differential sampling circuit and GND.

3. The circuit of claim 1, wherein the number of blocking units in the differential sampling circuit is three.

4. The circuit of claim 1, wherein the blocking unit comprises one of:

diode, MOS pipe, relay.

5. The circuit of claim 1, wherein the voltage sampling circuit is applied to a multi-path PFC series input circuit.

6. The circuit of claim 1, wherein the differential sampling circuit is connected to a BUS capacitor of the BUS circuit through a high impedance isolation circuit, wherein an equal number of resistors are respectively disposed on the high impedance isolation circuit corresponding to positive and negative sides of the BUS capacitor.

7. The circuit of claim 1, wherein the output current of the differential sampling circuit is connected to the control unit of the BUS circuit through a filter.

8. A circuit system comprising a plurality of voltage sampling circuits as claimed in any one of claims 1 to 7.