WO2018214870A1 - 一种异质结太阳能电池的制备方法及异质结太阳能电池 - Google Patents

一种异质结太阳能电池的制备方法及异质结太阳能电池 Download PDF

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WO2018214870A1
WO2018214870A1 PCT/CN2018/087814 CN2018087814W WO2018214870A1 WO 2018214870 A1 WO2018214870 A1 WO 2018214870A1 CN 2018087814 W CN2018087814 W CN 2018087814W WO 2018214870 A1 WO2018214870 A1 WO 2018214870A1
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type doped
doped layer
layer
substrate
equal
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French (fr)
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陈贤刚
杨苗
郁操
张津燕
徐希翔
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君泰创新（北京）科技有限公司
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Priority to CN201880001497.5A priority Critical patent/CN109463010A/zh
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Definitions

  • the invention relates to the field of new energy, and particularly relates to a method for preparing a heterojunction solar cell and a heterojunction solar cell.
  • the PN structure of a conventional HIT heterojunction cell is a-Si:H(p) (p-doped layer)/a-Si (intrinsic i)/c-Si (single crystal silicon)/a-Si (intrinsic) i) / a-Si: H (n) (n-type doped layer), to enhance the built-in electric field of the PN junction can be achieved by increasing the doping concentration of the doped layer, but also increasing the concentration of the doped layer
  • the impurity is diffused into the intrinsic layer, and the passivation effect of the intrinsic layer is reduced, and the conversion efficiency of the battery is also reduced.
  • the invention provides a preparation method of a heterojunction solar cell, which solves the problem that the intrinsic layer passivation effect is poor and the battery conversion efficiency is reduced in the prior art when the doping concentration is high.
  • the invention provides a preparation method of a heterojunction solar cell, comprising:
  • n-type doped layer and a p-type doped layer on the intrinsic layer on both sides of the substrate, the n-type doped layer and/or the p-type doped layer being at least two layers, and The doping concentration of each of the n-type doped layer and/or the p-type doped layer in the longitudinal direction away from the substrate is increasing;
  • a transparent conductive layer and an electrode layer are sequentially formed on the n-type doped layer and the p-type doped layer, respectively.
  • the layers of the n-type doped layer and/or the p-type doped layer are tapered in thickness away from the longitudinal direction of the substrate.
  • depositing an n-type doped layer on the intrinsic layer on the substrate comprises:
  • a gas flow volume ratio range of H 2 /SiH 4 /PH 3 4 to 10/2/2 to 3;
  • the range is greater than or equal to 0.3 mbar, less than or equal to 2.0 mbar;
  • the RF power range is greater than or equal to 500 W, less than or equal to 2000 W;
  • the thickness ranges from greater than 3 nm, less than or equal to 5 nm;
  • the gas pressure ranges from 0.3 mbar to greater than or equal to 2.0 mbar;
  • the RF power range is greater than or equal to 500 W and less than or equal to 2000 W;
  • the thickness ranges from greater than or equal to 1 nm to less than or equal to 3 nm.
  • each of the n-type doped layers is deposited after evacuation.
  • the deposition conditions for depositing the p-type doped layer on the intrinsic layer on the substrate are:
  • the deposition thickness ranges from 4 nm or more to 10 nm or less.
  • the intrinsic layer is deposited by using VHF-plasma enhanced chemical vapor deposition.
  • the deposition conditions of the intrinsic layer are:
  • the providing the substrate comprises:
  • the surface of the substrate is subjected to a pretreatment of texturing and/or cleaning.
  • the present invention also provides a heterojunction solar cell comprising: a substrate, an intrinsic layer, an n-type doped layer, a p-type doped layer and an electrode layer, the intrinsic layer being disposed on both sides of the substrate.
  • the n-type doped layer and the p-type doped layer are respectively disposed on the intrinsic layer on both sides of the substrate, and the electrode layers are respectively disposed on the n-type doping on both sides of the substrate.
  • the hetero layer and the p-doped layer On the hetero layer and the p-doped layer;
  • the n-type doped layer and/or the p-type doped layer are provided at least in two layers, and each of the n-type doped layer and/or the p-type doped layer is in a longitudinal direction away from the substrate.
  • the doping concentration of the layer is increasing.
  • the layers of the n-type doped layer and/or the p-type doped layer are tapered in thickness in a longitudinal direction away from the substrate.
  • the intrinsic layer disposed on the substrate in the n-type doping layer comprises:
  • a third n-type doped layer is disposed on the second n-type doped layer.
  • the thickness of the first n-type doped layer ranges from greater than 5 nm to less than or equal to 10 nm; the thickness of the second n-type doped layer ranges from greater than 3 nm to less than or equal to 5 nm, and the third n-type doping
  • the thickness of the impurity layer ranges from 1 nm or more to 3 nm or less.
  • the intrinsic layer disposed on the substrate in the p-type doped layer comprises:
  • the p-type doped layer has a thickness ranging from 4 nm or more to 10 nm or less.
  • the thickness of the intrinsic layer ranges from 5 nm or more to 15 nm or less.
  • the present invention has the following advantages:
  • the invention provides a method for preparing a heterojunction solar cell by depositing an n-type doped layer and a p-type doped layer on an intrinsic layer on both sides of the substrate, the n-type doped layer and And/or the p-type doped layer is at least two layers, and the doping concentration of each layer of the n-type doped layer and/or the p-type doped layer is increasing in a longitudinal direction away from the substrate
  • it can achieve high concentration doping of heterojunction solar energy, which can ensure that the first intrinsic layer is not affected by impurity infiltration, and form an n/n+/n++ electric field whose electric field direction is consistent with the pn junction to increase pn.
  • the built-in electric field of the junction achieves the purpose of improving the conversion efficiency of the battery; on the other hand, to avoid the excessive interface state density, the cell sheet is inefficient, and the p-type and n-type doped layers cannot be in contact with each other, the present invention
  • the deposition doping in the longitudinal direction of the substrate does not require an additional masking process or a process of removing a portion of the doped layer after doping, that is, when deposition doping is performed on one side of the substrate, Masking or occluding the other side of the substrate, and performing the doping after the doping is completed In addition to the doping and the like, it is only necessary to deposit the other side after deposition on one side, thereby improving production efficiency.
  • FIG. 1 is a flow chart of an embodiment of a method for preparing a heterojunction solar cell according to the present invention
  • FIG. 2 is a schematic structural view of an embodiment of a heterojunction solar cell provided by the present invention.
  • FIG. 3 is another schematic structural view of an embodiment of a heterojunction solar cell provided by the present invention.
  • FIG. 4 is another schematic structural view of an embodiment of a heterojunction solar cell provided by the present invention.
  • FIG. 1 is a flow chart of an embodiment of a method for fabricating a heterojunction solar cell according to the present invention.
  • the invention provides a preparation method of a heterojunction solar cell, comprising:
  • Step S101 providing a substrate
  • the substrate of the step S101 may be an n-type single silicon wafer.
  • the performance of the battery may be affected. Pretreatment of the surface of the substrate by texturing and/or cleaning.
  • the surface of the substrate is separately subjected to cleaning and texturing treatment before proceeding to the next step.
  • the cleaning process can remove oil stains, metal impurities, and the like on the surface of the substrate.
  • impurities that may exist on the surface of the silicon wafer include: organic substances such as grease, rosin, wax, epoxy resin, and polyethylene glycol; Either metal, metal ions and some inorganic compounds; or other dust particles (silicon, silicon carbide).
  • the manner of cleaning may include: physical cleaning and chemical cleaning.
  • the physical cleaning includes:
  • Brushing or scrubbing removes particulate contamination and most of the film sticking to the silicon wafer.
  • High-pressure cleaning The surface of the silicon wafer is sprayed with liquid, and the pressure of the nozzle is up to several hundred atmospheres. High-pressure cleaning relies on spraying, and the silicon wafer is less prone to scratches and damage. However, high-pressure jets can generate static electricity by adjusting the distance, angle, or antistatic agent of the nozzle to the wafer.
  • Ultrasonic cleaning ultrasonic sound energy is introduced into the solution, and the pollution on the silicon wafer is washed away by cavitation. However, it is more difficult to remove particles smaller than 1 micron from a patterned silicon wafer, and the frequency is increased to the ultra-high frequency band, and the cleaning effect is better.
  • the chemical cleaning is to remove impurities that are invisible to atoms and ions, and there are many methods, such as solvent extraction, pickling (sulfuric acid, nitric acid, aqua regia, various mixed acids, etc.) and plasma methods.
  • Commonly used chemical cleaning agents include high-purity water, organic solvent, hydrogen peroxide, concentrated acid, strong alkali and high-purity neutral detergent.
  • the hydrogen peroxide cleaning method has better effect and less environmental pollution.
  • the specific implementation process of the cleaning process can be determined according to the condition of the surface of the substrate, for example, the manner of cleaning, the type of cleaning agent used, the cleaning time, the mixed liquid used for the texturing, and the texturing Time and so on can be determined according to the actual conditions of the actual substrate.
  • the cleaned silicon wafer needs to be dried to prevent re-contamination of the silicon wafer and to create an imprint on the surface of the wafer.
  • it can be dried by spin drying or by hot air or hot nitrogen, or by applying a volatile liquid such as isopropyl alcohol on the surface of the silicon wafer, and drying the surface of the silicon wafer by the rapid exertion of the liquid; Or directly air dry.
  • the texturing can roughen the surface of the substrate to form a pyramidal suede, increasing the absorption of sunlight by the substrate.
  • the texturing process can utilize the anisotropic etching of silicon in a low concentration alkali solution to form a pyramid structure on the surface of the silicon wafer.
  • the texturing process usually uses a mixed solution of NaOH, Na 2 SiO 3 or the like at 75 to 90 ° C for 25 to 35 minutes.
  • the specific realization process of the texturing process can be determined according to the condition of the surface of the substrate, for example, a mixed liquid used for texturing, a flocking time, and the like.
  • Step S102 depositing an intrinsic layer on each side of the substrate
  • step S102 may be that the intrinsic layer is deposited on the substrate by using a high frequency-plasma enhanced chemical vapor deposition (VHF-PECVD) method, and 40 MHz high frequency-plasma enhanced chemical vapor deposition may be used. .
  • VHF-PECVD high frequency-plasma enhanced chemical vapor deposition
  • the specific conditions of deposition can be:
  • the flow volume ratio H 2 / SiH 4 4/ 1; pressure range greater than or equal to 0.3 mbar, less than Equal to 2.0 mbar, in the present embodiment, the preferred air pressure value is 0.5 mbar; the radio frequency power range is 200 W or more, 2000 W or less. In this embodiment, the preferred RF power value is 400 W, and the deposition thickness range is greater than or equal to 5 nm, 15 nm or less, in the present embodiment, a preferred thickness value is 10 nm.
  • the flow volume range is greater than or equal to 0, less than or equal to 10, and the flow volume of silane (SiH 4 ) is 1.
  • a first intrinsic layer and a second intrinsic layer are respectively deposited on both sides of the substrate, that is, the first The smear layer and the second intrinsic layer are located on both sides of the substrate in the longitudinal direction.
  • Step S103 depositing an n-type doped layer and a p-type doped layer on the intrinsic layer on both sides of the substrate, the n-type doped layer and/or the p-type doped layer being at least two layers And the doping concentration of each of the n-type doped layer and/or the p-type doped layer in a longitudinal direction away from the substrate is increasing;
  • the first side and the second side are defined on both sides of the substrate, the first intrinsic layer is deposited on the first side of the substrate, and the second intrinsic layer is deposited on the second side of the substrate.
  • a doped layer is deposited on the second intrinsic layer.
  • the specific implementation of the step S103 is that at least two p-type doped layers and/or at least two p-type doped layers are respectively deposited on the intrinsic layers on both sides of the substrate, that is, Depositing the n-type doped layer on the first intrinsic layer in a longitudinal direction, depositing the p-type doped layer on the second intrinsic layer, and having at least two layers of an n-type doped layer And/or, the p-type doped layer is at least two layers.
  • three layers of the n-type doped layer are deposited on the first intrinsic layer, and one layer of the p-type doped layer is deposited on the second intrinsic layer, as follows:
  • the gas pressure range is 0.3 mbar or more and 2.0 mbar or less. In the present embodiment, the preferred gas pressure value is 0.8 mbar; the radio frequency power range is 500 W or more and 2000 W or less. In this embodiment, it is preferred.
  • the RF power value is 1000 W; the deposition thickness ranges from more than 5 nm to less than or equal to 10 nm, and in the present embodiment, the preferred deposition thickness value is 6 nm.
  • the gas pressure range is 0.3 mbar or more and 2.0 mbar or less.
  • the preferred gas pressure value is 0.8 mbar;
  • the radio frequency power range is 800 W or more and 1200 W or less. In this embodiment, it is preferred.
  • the RF power value is 1000 W; the deposition thickness ranges from more than 3 nm to less than or equal to 5 nm, and in the present embodiment, the preferred deposition thickness value is 4 nm.
  • the gas pressure range is greater than or equal to 0.6 mbar, less than or equal to 1.0 mbar, in the present embodiment, the preferred gas pressure value is 0.8 mbar;
  • the radio frequency power range is greater than or equal to 800 W, less than or equal to 1200 W, in this embodiment, preferably The RF power value is 1000 W;
  • the deposition thickness ranges from 1 nm or more and 3 nm or less. In the present embodiment, the preferred deposition thickness value is 2 nm.
  • each size of the gas flow volume that is introduced into the reaction chamber can be controlled.
  • the doping concentration of the n-type doped layer is controlled by adjusting the flow volumes of hydrogen (H 2 ) and phosphine (PH 3 ) flowing into the
  • the ratio of the flow volume of the introduced gas is gradually increasing. That is, the doping concentration of the first n-type doping layer is smaller than the doping concentration of the second n-type doping layer, and the doping concentration of the second n-type doping layer is smaller than the third n-type The doping concentration of the doped layer, ie gradient doping.
  • control of the doping concentration of each n-type doping layer is achieved by adjusting the gas flow volume ratio, and it is understood that the control of the doping concentration of each n-type doping layer is also
  • the doping concentration of each n-type doped layer can be controlled by adjusting the concentration of the gas mass percentage into the reaction chamber, that is, when depositing each layer of the n-type doped layer in the longitudinal direction, the gas mass percentage concentration is It can be ascending.
  • the deposition thickness of the n-type doped layer of each layer is decreasing in the longitudinal direction away from the substrate.
  • a shape that is, a thickness of the first n-type doped layer is greater than a thickness of the second n-type doped layer, and a thickness of the second n-type doped layer is greater than that of the third n-type doped layer Thickness; for example, in the embodiment, the first n-type doped layer has a deposition thickness of 6 nm, the second n-type doped layer has a deposition thickness of 4 nm, and the third n-type doped layer has a deposition thickness It is 2 nm.
  • the reaction chamber is evacuated to ensure that there is no residual gas in the reaction chamber to avoid affecting the subsequent deposition reaction process.
  • the substrate is The p-doped layer is deposited facing the second intrinsic layer.
  • Depositing conditions for depositing the p-type doped layer on the second intrinsic layer are:
  • the range is 800 W or more and 1200 W or less, and in the present embodiment, 1000 W is preferable; the deposition thickness ranges from 4 nm or more to 10 nm or less, and in the present embodiment, 8 nm is preferable.
  • a multi-layer n-type doped layer is formed on one side, and the advantages thereof are:
  • the first intrinsic layer can be protected from impurities.
  • the influence of infiltration forms an n/n+/n++ electric field whose electric field direction is consistent with the pn junction, so as to increase the built-in electric field of the pn junction, thereby achieving the purpose of improving the conversion efficiency of the battery;
  • the present invention does not require an additional mask by performing deposition doping in the longitudinal direction of the substrate. a process of removing a partially doped layer after the process or doping, that is, when performing deposition doping on one side of the substrate, it is not necessary to mask or block the other side of the substrate, and After the completion of the impurity, the steps of removing the doping and the like are performed, and only the deposition of one side is required, and then the other side is deposited, thereby improving the production efficiency.
  • the method for preparing a heterojunction solar cell may sequentially deposit a plurality of n-type doped layers on the first intrinsic layer according to different requirements, in the second intrinsic layer.
  • the deposition conditions of the first intrinsic layer and the second intrinsic layer are the same, the structure is the same, and the distinction between the first and the second is only convenient for description, and is not intended to limit the order of deposition of the two.
  • the deposition process can be performed after one side deposition and then the other side deposition.
  • the number of layers deposited is determined according to actual needs, and the deposition mode of the multilayer doping layer (multilayer n-doped layer and/or multilayer p-doping). Layer) can also be set according to specific needs.
  • Step S104 sequentially forming a transparent conductive layer and an electrode layer on the n-type doped layer and the p-type doped layer, respectively.
  • a transparent conductive layer and an electrode layer are sequentially formed on the n-type doped layer, and a transparent conductive layer and an electrode layer are sequentially formed on the p-type doped layer.
  • the specific implementation process of the step S104 may be that a transparent conductive layer is sequentially formed on the n-type doped layer and the p-type doped layer, respectively, by physical vapor deposition (PVD: Physical Vapor Deposition).
  • PVD Physical Vapor Deposition
  • the physical vapor deposition method includes: a vacuum evaporation coating, a sputtering coating, and an ion plating film; the vacuum evaporation coating is to heat and evaporate the source material; the sputtering coating is bombarding the source target with particles having a certain energy, from the target The source material atom is splashed on; the ion plating film irradiates the target with a laser, and the target material is evaporated and plasmaized by a thermal effect.
  • a transparent conductive layer (TCO: Transparent Conductive Oxide) is sputter-coated, and the sputtering deposition method has the advantages that the sputter coating is not restricted by the target, the purity is high, the compactness is good, and the combination is good. Good sex.
  • the transparent conductive layer is deposited on the third n-type doped layer, and the transparent conductive layer is deposited on the p-type doped layer.
  • An electrode layer is formed on the transparent conductive layer after depositing the transparent conductive layer, and the electrode layer can be realized by a screen printing process.
  • reducing interface recombination is beneficial to the collection and transportation of photogenerated carriers and improves the conversion efficiency of the cell.
  • the high concentration doping introduces too much impurity into the intrinsic layer, thereby reducing the passivation effect of the intrinsic layer.
  • the surface of the intrinsic layer (or the side close to the intrinsic layer) is doped with a low concentration to prevent impurities of the n-type doping layer from penetrating into the intrinsic layer, ensuring the passivation effect of the intrinsic layer and lowering the battery.
  • the n-type film layer in contact with the transparent conductive layer is heavily doped to reduce the contact resistance between the n-type doped layer and the transparent conductive layer, and improve the transport capability of the carrier. In turn, the battery conversion efficiency is improved.
  • FIG. 2 is a schematic structural diagram of an embodiment of a heterojunction solar cell according to the present invention.
  • the heterojunction solar cell provided by the present invention includes:
  • the intrinsic layer 202 is disposed on two sides of the substrate 201, and the n-type doped layer 203 and the p-type doped layer 204 are respectively disposed on the intrinsic layer 202 on both sides of the substrate 201.
  • the electrode layers 206 are respectively disposed on the n-type doping layer 203 and the p-type doping layer 204 on both sides of the substrate 201;
  • the n-type doped layer 203 and/or the p-type doped layer 204 are provided at least in two layers, and in the longitudinal direction away from the substrate 201, the n-type doped layer 203 and/or p-type doping The doping concentration of each layer in the hybrid layer 204 is increasing.
  • the description is made by providing a plurality of n-type doping layers 203 on the intrinsic layer 202, namely:
  • a third n-type doped layer 2033 is disposed on the second n-type doped layer 2032.
  • the intrinsic layer 202 is limited in name, that is, the two sides in the longitudinal direction of the substrate 201 are the first intrinsic layer 2021 and the second Layer 2022.
  • a first n-type doped layer 2031 is disposed on the first intrinsic layer 2021, and a second n-type doped layer 2032 is disposed on the first n-type doped layer 2031, where the second n-type doping is performed
  • a third n-type doped layer 2033 is disposed on the impurity layer 2032.
  • the thickness of the first n-type doped layer 2031 ranges from more than 5 nm to less than or equal to 10 nm. In the present embodiment, a preferred deposition thickness value is 6 nm.
  • the thickness of the second n-type doped layer 2032 ranges from more than 3 nm to less than or equal to 5 nm. In the present embodiment, a preferred deposition thickness value is 4 nm.
  • the thickness of the third n-type doped layer 2033 ranges from 1 nm or more to 3 nm or less. In the present embodiment, a preferred deposition thickness value is 2 nm.
  • a p-type doping layer 204 is disposed on the second intrinsic layer 2022, and the p-type doping layer 204 has a thickness ranging from 10 nm or more to 6 nm or less. In the embodiment, the preferred deposition thickness value is 8nm.
  • the first intrinsic layer 2021 and the second intrinsic layer 2022 have a thickness ranging from 5 nm or more and 15 nm or less. In the present embodiment, a preferred deposition thickness value is 10 nm.

Abstract

提供一种异质结太阳能电池的制备方法及异质结太阳能电池，方法包括：提供基片（201）；在基片的两侧分别沉积本征层（202）；在基片两侧的本征层上分别沉积n型掺杂层（203）和p型掺杂层（204），n型掺杂层和/或p型掺杂层至少为两层，且n型掺杂层和/或p型掺杂层的各层在远离基片的纵向方向上的掺杂浓度呈递增状；在n型掺杂层和p型掺杂层上分别依次形成透明导电层（205）和电极层（206）。从而提高电池转换效率以及生产效率。

Description

一种异质结太阳能电池的制备方法及异质结太阳能电池
本申请基于申请号为201710379489.1、申请日为2017年5月25日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及新能源领域，具体涉及一种异质结太阳能电池的制备方法及异质结太阳能电池。
背景技术
随着技术的快速发展，晶体硅太阳电池的转换效率逐年提高。当前，我国正在大力推广分布式太阳能光伏发电，由于屋顶资源有限，需求高转换效率的太阳电池组件。正是由于高效单晶异质结电池具有高效率、低能耗、工艺流程简单、温度系数小等诸多优点，未来几年内将得到大力发展，其效率的提升尤为重要。
常规HIT异质结电池的PN结构为a-Si:H(p)(p型掺杂层)/a-Si(本征i)/c-Si(单晶硅)/a-Si(本征i)/a-Si:H(n)(n型掺杂层)，为增强PN结的内建电场可以通过提高掺杂层的掺杂浓度实现，但是对掺杂层提高浓度的同时也会促使杂质扩散进本征层内，而降低本征层的钝化效果，进而电池的转换效率也随之降低。
如何提供一种即能够保证高掺杂浓度的同时，又能避免杂质扩散至本征层内导致电池转换效率降低的太阳能电池的制备方法及太阳能电池成为本领域技术人员需要解决的技术问题。
发明内容
本发明提供一种异质结太阳能电池的制备方法，以解决现有技术中在掺杂浓度高的情况下导致本征层钝化效果差，电池转换效率受到降低的问题。
本发明提供一种异质结太阳能电池的制备方法，包括：
提供基片；
在所述基片的两侧分别沉积本征层；
在所述基片两侧的所述本征层上分别沉积n型掺杂层和p型掺杂层，所述n型掺杂层和/或p型掺杂层至少为两层，且所述n型掺杂层和/或所述p型掺杂层的各层在远离所述基片的纵向方向上的掺杂浓度呈递增状；
在所述n型掺杂层和所述p型掺杂层上分别依次形成透明导电层和电极层。
优选的，所述n型掺杂层和/或p型掺杂层的各层在远离所述基片纵向方向上的厚度呈递减状。
优选的，在所述基片上的所述本征层上沉积n型掺杂层包括：
在所述本征层上沉积第一n型掺杂层，沉积条件为：气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/1～2；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；厚度范围为大于5nm，小于等于10nm；
在所述第一n型掺杂层上沉积第二n型掺杂层，沉积条件为：气体流量体积比的范围H 2/SiH 4/PH 3＝4～10/2/2～3；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；厚度范围为大于3nm，小于等于5nm；
在所述第二n型掺杂层上沉积第三n型掺杂层，沉积条件为：气体流量体积比的范围是H 2/SiH 4/PH 3＝4～10/2/3～4；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；厚度范围为大于等于1nm，小于等于3nm。
优选的，在沉积每一所述n型掺杂层是在抽真空后进行。
优选的，在所述基片上的所述本征层上沉积p型掺杂层的沉积条件为：
气体流量体积比为H 2/SiH 4/B 2H 6＝4～10/2/1～4；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；沉积厚度范围为大于等于4nm，小于等于10nm。
优选的，所述本征层采用的沉积方式是：采用甚高频-等离子体增强化学气相沉积。
优选的，所述本征层的沉积条件为：
气体流量体积比为H 2/SiH 4＝0～10/1；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于200W，小于等于2000W；沉积厚度范围为大于等于5nm，小于等于15nm。
优选的，所述提供基片包括：
对所述基片的表面进行制绒和/或清洗的预处理。
本发明还提供一种异质结太阳能电池，包括：基片，本征层、n型掺杂层、p型掺杂层和电极层，所述本征层设置于所述基片的两侧，所述n型掺杂层和p型掺杂层分别设置于所述基片两侧的所述本征层上，所述电极层分别设置于所述基片两侧的所述n型掺杂层和p型掺杂层上；
所述n型掺杂层和/或p型掺杂层至少设置为两层，且在远离所述基片的纵向方向上，所述n型掺杂层和/或p型掺杂层中各层的掺杂浓度呈递增状。
优选的，所述n型掺杂层和/或p型掺杂层的各层在远离所述基片的纵向方向上的厚度呈递减状。
优选的，在所述n型掺杂层设置于所述基片的所述本征层包括：
在靠近所述本征层的一侧设置第一n型掺杂层；
在所述第一n型掺杂层上设置第二n型掺杂层；
在所述第二n型掺杂层上设置第三n型掺杂层。
优选的，所述第一n型掺杂层的厚度范围为大于5nm，小于等于10nm；所述第二n型掺杂层的厚度范围为大于3nm，小于等于5nm，所述第三n型掺杂层的厚度范围为大于等于1nm，小于等于3nm。
优选的，在所述p型掺杂层设置于所述基片的所述本征层包括：
所述p型掺杂层的厚度范围为大于等于4nm，小于等于10nm。
优选的，所述本征层的厚度范围为大于等于5nm，小于等于15nm。
与现有技术相比，本发明具有以下优点：
本发明提供的一种异质结太阳能电池的制备方法，通过在所述基片两侧的本征层上分别沉积n型掺杂层和p型掺杂层，所述n型掺杂层和/或p型掺杂层至少为两层，且所述n型掺杂层和/或所述p型掺杂层的各层在远离所述基片的纵向方向上的掺杂浓度呈递增状，一方面能够实现异质结太阳能的高浓度掺杂，能够保证所述第一本征层不受到杂质渗入的影响，形成一个电场方向与pn结一致的n/n+/n++电场，以增加pn结的内建电场，达到提升电池转换效率的目的；另一方面为避免过高的界面态密度而导致电池片低效，p型和n型掺杂层不能彼此接触，本发明通过在所述基片的纵向方向上进行沉积掺杂无需额外的掩膜过程或者掺杂后增加去除部分掺杂层的过程，即：在对所述基片的一侧进行沉积掺杂时，无需对所述基片的另一侧进行掩膜或遮挡，以及在掺杂完成后进行去 除掺杂等工序，仅需在一侧沉积完毕后再沉积另一侧即可，进而提高生产效率。
附图说明
图1是本发明提供的一种异质结太阳能电池的制备方法实施例的流程图；
图2是本发明提供的一种异质结太阳能电池实施例的结构示意图；
图3是本发明提供的一种异质结太阳能电池实施例的另一结构示意图；
图4是本发明提供的一种异质结太阳能电池实施例的另一结构示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施的限制。
请参考图1所示，图1是本发明提供的一种异质结太阳能电池的制备方法实施例的流程图。
本发明提供一种异质结太阳能电池的制备方法，包括：
步骤S101：提供基片；
所述步骤S101的基片可以是一个n型单硅片，为提高异质结太阳能电池的性能，由于所述基片上可能存在金属杂质和/或油污会对电池的性能造成影响，因此，可以对所述基片表面进行制绒和/或清洗的预处理。
在本实施例中，对所述基片表面分别进行清洗和制绒处理后再进入下一步骤。其中，清洗工序能够去除所述基片表面的油污、金属杂质等，通常情况下，所述硅片表面可能存在的杂质包括：油脂、松香、蜡、环氧树脂、聚乙二醇等有机物；或者是金属、金属离子及一些无机化合物；或者是尘埃及其他颗粒(硅、碳化硅)等。
所述清洗的方式可以包括：物理清洗和化学清洗。所述物理清洗包括：
1、刷洗或擦洗：可除去颗粒污染和大多数粘在硅片上的薄膜。
2、高压清洗：是用液体喷射硅片表面，喷嘴的压力高达几百个大气压。高压清洗靠喷射作用，硅片不易产生划痕和损伤。但高压喷射会产生静电作用，靠调节喷嘴到硅片的距离、角度或加入防静电剂加以避免。
3、超声波清洗：超声波声能传入溶液，靠气蚀作用洗掉硅片上的污染。但是，从有图形的硅片上除去小于1微米颗粒则比较困难，将频率提高到超高频频段，清洗效果更好。
所述化学清洗是为除去原子、离子不可见的污染，方法较多，有溶剂萃取、酸洗(硫酸、硝酸、王水、各种混合酸等)和等离子体法等。
常用的化学清洗剂有高纯水、有机溶剂、双氧水、浓酸、强碱以及高纯中性洗涤剂等，其中双氧水体清洗方法效果较好，环境污染小。一般方法是将硅片先用成分比为H 2SO 4:H 2O 2＝5:1或4:1的酸性液清洗。清洗液的强氧化性会将有机物分解而除去；用超纯水冲洗后，再用成分比为H 2O:H 2O 2:NH 4OH＝5:2:1或5:1:1或7:2:1的碱性清洗液清洗，由于H 2O 2的氧化作用和NH4OH的络合作用，许多金属离子形成稳定的可溶性络合物而溶于水；然后使用成分比为H 2O:H 2O 2:HCL＝7:2:1或5:2:1的酸性清洗液，由于H 2O 2的氧化作用和盐酸的溶解，以及氯离子的络合性，许多金属生成溶于水的络离子，从而达到清洗的目的。
可以理解的是，所述清洗处理的具体实现过程可以根据所述基片表面的情况来确定，例如：采用清洗的方式、清洗剂的使用类型、清洗时间、制绒使用的混合液、制绒时间等等都可以根据实际基片的自身条件来确定。
对清洗后的硅片需要进行烘干，防止硅片再次污染以及在硅片表面产生清洗所留下的印记。通常可以通过旋转烘干或通过热空气或热氮气是硅片烘干，或者在硅片表面涂抹易挥发的液体，例如：异丙醇等，通过液体的快速发挥对硅片表面进行干燥处理；或者直接进行风干。
所述制绒可以使基片表面粗糙形成金字塔形的绒面，增加基片对太阳光的吸收。
所述制绒处理可以利用硅在低浓度碱液中的各向异性腐蚀，进而在硅片表面形成金字塔结构。通常情况下，制绒工艺常用NaOH、Na 2SiO 3等混合溶液在75～90℃反应25～35min。
可以理解的是，所述制绒处理具体实现过程可以根据所述基片表面的情况来确定，例如：制绒使用的混合液，制绒时间等等。
步骤S102：在所述基片的两侧分别沉积本征层；
所述步骤S102的具体实现过程可以是，在所述基片上通过采用高频-等离子体增强化学气相沉积(VHF-PECVD)方法沉积本征层，可以采用40MHz高频-等离子体增强化学气相沉积。
沉积具体条件可以是：
采用气体流量体积比的范围为H 2/SiH 4＝0～10/1，在本实施例中，优选流量体 积比为H 2/SiH 4＝4/1；气压范围为大于等于0.3mbar，小于等于2.0mbar，在本实施例中，优选的气压值是0.5mbar；射频功率范围为大于等于200W，小于等于2000W，在本实施例中，优选的射频功率值是400W，沉积厚度范围为大于等于5nm，小于等于15nm，在本实施例中，优选的厚度值是10nm。
需要说明的是，所述气体流量体积比的范围为H 2/SiH 4＝0～10/1，是指向反应腔室内通入氢气和硅烷的流量体积比范围，所述氢气(H 2)的流量体积范围是大于等于0，小于等于10，硅烷(SiH 4)的流量体积是1。
为更清楚的说明所述本征层的沉积，在本实施例中，在所述基片的两侧分别沉积第一本征层和第二本征层，也就是说，所述第一本征层和所述第二本征层在纵向方向上位于所述基片的两侧。
步骤S103：在所述基片两侧的所述本征层上分别沉积n型掺杂层和p型掺杂层，所述n型掺杂层和/或p型掺杂层至少为两层，且所述n型掺杂层和/或所述p型掺杂层的各层在远离所述基片的纵向方向上的掺杂浓度呈递增状；
在本实施例中，定义基片两侧为第一侧面和第二侧面，在基片第一侧面沉积第一本征层，在基片第二侧面沉积第二本征层。在所述基片两侧的所述本征层上分别沉积n型掺杂层和p型掺杂层，也就是说，纵向方向上，在所述第一本征层上沉积所述n型掺杂层，在所述第二本征层上沉积所述p型掺杂层。
所述步骤S103的具体实现过程是，在所述基片两侧的所述本征层上分别沉积至少两层n型掺杂层和/或至少两层p型掺杂层，也就是说，纵向方向上在所述第一本征层上沉积所述n型掺杂层，在所述第二本征层上沉积所述p型掺杂层，且，n型掺杂层至少为两层，和/或，p型掺杂层至少为两层。
在本实施例中，在所述第一本征层上沉积三层所述n型掺杂层，在所述第二本征层上沉积一层所述p型掺杂层，具体如下：
在所述第一本征层上沉积第一n型掺杂层，具体沉积方式如下：
采用气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/1～2，在本实施例中，优选的气体流量体积比为H 2/SiH 4/PH 3＝6/2/1；气压范围为大于等于0.3mbar，小于等于2.0mbar，在本实施例中，优选的气压值为0.8mbar；射频功率范围为大于等于500W，小于等于2000W，在本实施例中，优选的射频功率值为1000W；沉积厚度范围为大于5nm，小于等于10nm，在本实施例中，优选的沉积厚度值为6nm。
需要说明的是，所述气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/1～2是指， 所述氢气(H 2)的流量体积范围为大于等于4，小于等于10；所述硅烷(SiH 4)的流量体积为2；所述磷烷(PH 3)的流量体积范围为大于等于1，小于等于2；
在所述第一n型掺杂层上沉积第二n型掺杂层，具体沉积方式如下：
采用气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/2～3，在本实施例中，优选的气体流量体积比为H 2/SiH 4/PH 3＝5/2/2；气压范围为大于等于0.3mbar，小于等于2.0mbar，在本实施例中，优选的气压值为0.8mbar；射频功率范围为大于等于800W，小于等于1200W，在本实施例中，优选的射频功率值为1000W；沉积厚度范围为大于3nm，小于等于5nm，在本实施例中，优选的沉积厚度值为4nm。
需要说明的是，所述气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/2～3是指，所述氢气(H 2)的流量体积范围为大于等于4，小于等于10；所述硅烷(SiH 4)的流量体积为2；所述磷烷(PH 3)的流量体积范围为大于等于2，小于等于3；
在所述第二n型掺杂层上沉积第三n型掺杂层，具体沉积方式如下：
采用气体流量体积比的范围是H 2/SiH 4/PH 3＝4～10/2/3～4，在本实施例中优选的气体流量体积比为H 2/SiH 4/PH 3＝4/2/3；气压范围为大于等于0.6mbar，小于等于1.0mbar，在本实施例中，优选的气压值为0.8mbar；射频功率范围为大于等于800W，小于等于1200W，在本实施例中，优选的射频功率值为1000W；沉积厚度范围为大于等于1nm，小于等于3nm，在本实施例中，优选的沉积厚度值为2nm。
需要说明的是，所述气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/3～4是指，所述氢气(H 2)的流量体积范围为大于等于4，小于等于10；所述硅烷(SiH 4)的流量体积为2；所述磷烷(PH 3)的流量体积范围为大于等于3，小于等于4；
可以理解的是，在沉积所述第一n型掺杂层、第二n型掺杂层和第三n型掺杂层可以通过控制向反应腔室内通入的气体流量体积的大小，实现每一n型掺杂层不同的浓度，例如：在沉积所述第一n型掺杂层时，通入所述反应腔室内的气体流量体积比是H 2/SiH 4/PH 3＝6/2/1；在沉积所述第二n型掺杂层时，通入所述反应腔室内的气体流量体积比是H 2/SiH 4/PH 3＝5/2/2；在沉积所述第三n型掺杂层时，通入所述反应腔室内的气体流量体积比是H 2/SiH 4/PH 3＝4/2/3；也就是，主要在所述硅烷通入量一定的情况下，通过调节通入所述反应腔室内的氢(H 2)和磷烷(PH 3)流量体积控制n型掺杂层的掺杂浓度。
在本实施例中，沉积所述第一n型掺杂层、第二n型掺杂层和第三n型掺 杂层的过程中，所述通入气体流量体积的比值是逐渐递增的，即：所述第一n型掺杂层的掺杂浓度小于所述第二n型掺杂层的掺杂浓度，所述第二n型掺杂层的掺杂浓度小于所述第三n型掺杂层的掺杂浓度，即梯度掺杂。
在本实施例中是通过调节通入所述气体流量体积比来实现对各个n型掺杂层掺杂浓度的控制，可以理解的是，对于各个n型掺杂层的掺杂浓度的控制还可以通过调节通入所述反应腔室内气体质量百分比浓度，控制各个n型掺杂层的掺杂浓度，即：在纵向方向上沉积各层n型掺杂层时，所述气体质量百分比浓度呈递增状即可。
本实施中，为保证异质结太阳能电池的整体结构在增加掺杂层后，减小其空间占用量，各层n型掺杂层的沉积厚度在远离所述基片的纵向方向上呈递减状，即：所述第一n型掺杂层的厚度大于所述第二n型掺杂层的厚度，所述第二n型掺杂层的厚度大于所述第三n型掺杂层的厚度；例如：实施例中，所述第一n型掺杂层的沉积厚度为6nm，所述第二n型掺杂层的沉积厚度为4nm，所述第三n型掺杂层的沉积厚度为2nm。
需要说明的是，本实施中沉积第一n型掺杂层、第二n型掺杂层和第三n型掺杂层的过程中，在向所述反应腔室内通入反应气体前，对所述反应腔室进行抽真空处理，从而确保反应腔室内无残留气体，以避免影响后续的沉积反应过程。
在本实施例中，当所述第一n型掺杂层、第二n型掺杂层和第三n型掺杂层在所述第一本征层上沉积完毕后，将所述基片翻面对所述第二本征层沉积所述p型掺杂层。
在所述第二本征层上沉积所述p型掺杂层的沉积条件是：
采用气体流量体积比是H 2/SiH 4/B 2H 6＝6/2/1；气压范围为大于等于0.6mbar，小于等于1.0mbar，在本实施例中，优选的是0.8mbar；射频功率范围为大于等于800W，小于等于1200W，在本实施例中，优选的是1000W；沉积厚度范围为大于等于4nm，小于等于10nm，在本实施例中，优选的是8nm。
在本实施例中是单侧形成多层n型掺杂层，其优势在于：
1、通过在第一本征层上纵向依次沉积多层n型掺杂层且掺杂浓度呈递增状实现异质结太阳能的高浓度掺杂，能够保证所述第一本征层不受到杂质渗入的影响，形成一个电场方向与pn结一致的n/n+/n++电场，以增加pn结的内建电场，达到提升电池转换效率的目的；
2、为避免过高的界面态密度而导致电池片低效，p型和n型掺杂层不能彼此接触,本发明通过在所述基片的纵向方向上进行沉积掺杂无需额外的掩膜过程或者掺杂后增加去除部分掺杂层的过程，即：在对所述基片的一侧进行沉积掺杂时，无需对所述基片的另一侧进行掩膜或遮挡，以及在掺杂完成后进行去除掺杂等工序，仅需在一侧沉积完毕后再沉积另一侧即可，进而提高生产效率。
需要说明的是，本发明提供的异质结太阳能电池的制备方法可以根据不同的需求在所述第一本征层上分别依次沉积多层n型掺杂层，在所述第二本征层上沉积一层p型掺杂层，如图2所示；或者在所述第二本征层上分别依次沉积多层p型掺杂层，在所述第一本征层上沉积一层n型掺杂层，如图3所示；或者在所述第一本征层上依次沉积多层n型掺杂层，在所述第二本征层上依次沉积多层p型掺杂层，如图4所示。
所述第一本征层和所述第二本征层沉积条件相同，结构相同，用第一和第二加以区分仅为描述方便而已，并不是限定二者沉积的先后顺序。
沉积过程可以先进行一侧沉积之后再进行另一侧沉积，具体沉积的层数根据实际需要确定，以及多层掺杂层的沉积方式(多层n掺杂层和/或多层p掺杂层)也可以根据具体需要设定。
以上本实施中的举例仅为说明本发明异质结太阳能电池的制备过程，并不限制具体沉积过程中的各参数、方式等。
步骤S104：在所述n型掺杂层和所述p型掺杂层上分别依次形成透明导电层和电极层。
也就是说，在所述n型掺杂层上依次形成透明导电层和电极层，在所述p型掺杂层上依次形成透明导电层和电极层。
所述步骤S104的具体实现过程可以是，通过物理气相沉积法(PVD：Physical Vapor Deposition)在所述n型掺杂层和所述p型掺杂层上分别依次形成透明导电层。
所述物理气相沉积法包括：真空蒸发镀膜、溅射镀膜和离子镀膜；所述真空蒸发镀膜是使源物质加热蒸发；所述溅射镀膜是用具有一定能量的粒子轰击源物质靶，从靶上溅出源物质原子；所述离子镀膜是用激光照射靶，利用热效应使靶材物质蒸发并等离子体化。
在本实施例中，采用溅射镀膜溅射透明导电层(TCO：Transparent Conductive Oxide)，采用溅射镀膜沉积方法的好处在于，溅射镀膜不受靶材限制，纯度高， 致密性好以及结合性好。
本实施中，在所述第三n型掺杂层上沉积所述透明导电层，在所述p型掺杂层上沉积所述透明导电层。
在沉积透明导电层后在所述透明导电层上形成电极层，所述电极层可以通过丝网印刷工艺实现。
对于异质结电池，降低界面复合，有利于光生载流子的收集和运输，提高电池片的转换效率。对于高浓度的n型掺杂，虽然能增加pn结的内建电场，但是高浓度掺杂会引入过多的杂质进入本征层，从而降低本征层的钝化效果，本实施例中，在接触本征层的面(或者是说靠近本征层的一侧)采用低浓度掺杂，杜绝n型掺杂层的杂质渗入本征层，保证了本征层的钝化效果，降低电池的表面复合；与此同时，在低浓度掺杂层上再进行梯度重掺杂，也就是说，在由靠近本征层直至远离本征层的纵向方向上逐渐增加掺杂浓度，有效增加了pn结内建电场；另一方面与透明导电层(TCO)接触的n型膜层经过重掺杂有利于降低n型掺杂层与透明导电层的接触电阻，提高载流子的运输能力，进而提高电池转换效率。
以上是对本发明提供的一种异质结太阳能电池的制备方法实施例进行的详细描述，下面结合上述对方法的描述介绍本发明提供的一种异质结太阳能电池的具体结构，具体如下：
请参考图2所示，图2是本发明提供的一种异质结太阳能电池实施例的结构示意图，本发明提供的异质结太阳能电池包括：
基片201，本征层202、n型掺杂层203、p型掺杂层204、透明导电层205和电极层206。
所述本征层202设置于所述基片201的两侧，所述n型掺杂层203和p型掺杂层204分别设置于所述基片201两侧的所述本征层202上，所述电极层206分别设置于所述基片201两侧的所述n型掺杂层203和p型掺杂层204上；
所述n型掺杂层203和/或p型掺杂层204至少设置为两层，且在远离所述基片201的纵向方向上，所述n型掺杂层203和/或p型掺杂层204中各层的掺杂浓度呈递增状。
在本实施例中，通过在本征层202上设置多层n型掺杂层203来进行说明，即：
在靠近所述本征层202的一侧设置第一n型掺杂层2031；
在所述第一n型掺杂层2031上设置第二n型掺杂层2032；
在所述第二n型掺杂层2032上设置第三n型掺杂层2033。
为更清楚的了解本实施中电池的结构，对所述本征层202进行名称上的限定，即：所述基片201纵向方向上的两侧分别为第一本征层2021和第二本征层2022。
在所述第一本征层2021上设置第一n型掺杂层2031，在所述第一n型掺杂层2031上设置第二n型掺杂层2032，在所述第二n型掺杂层2032上设置第三n型掺杂层2033。
所述第一n型掺杂层2031的厚度范围为大于5nm，小于等于10nm，在本实施例中，优选的沉积厚度值为6nm。
所述第二n型掺杂层2032的厚度范围为大于3nm，小于等于5nm，在本实施例中，优选的沉积厚度值为4nm。
所述第三n型掺杂层2033的厚度范围为大于等于1nm，小于等于3nm，在本实施例中，优选的沉积厚度值为2nm。
在所述第二本征层2022上设置p型掺杂层204，所述p型掺杂层204的厚度范围为大于等于10nm，小于等于6nm，在本实施例中，优选的沉积厚度值为8nm。
所述第一本征层2021和所述第二本征层2022的厚度范围为大于等于5nm，小于等于15nm，在本实施例中，优选的沉积厚度值为10nm。
本发明虽然以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修改，因此本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims (14)

  1. 一种异质结太阳能电池的制备方法，其特征在于，包括：
    提供基片；
    在所述基片的两侧分别沉积本征层；
    在所述基片两侧的所述本征层上分别沉积n型掺杂层和p型掺杂层，所述n型掺杂层和/或p型掺杂层至少为两层，且所述n型掺杂层和/或所述p型掺杂层的各层在远离所述基片的纵向方向上的掺杂浓度呈递增状；
    在所述n型掺杂层和所述p型掺杂层上分别依次形成透明导电层和电极层。
  2. 根据权利要求1所述的异质结太阳能电池的制备方法，其特征在于：所述n型掺杂层和/或p型掺杂层的各层在远离所述基片纵向方向上的厚度呈递减状。
  3. 根据权利要求2所述的异质结太阳能电池的制备方法，其特征在于，在所述基片上的所述本征层上沉积n型掺杂层包括：
    在所述本征层上沉积第一n型掺杂层，沉积条件为：气体流量体积比范围为H 2/SiH 4/PH 3＝4～10/2/1～2；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；厚度范围为大于5nm，小于等于10nm；
    在所述第一n型掺杂层上沉积第二n型掺杂层，沉积条件为：气体流量体积比的范围H 2/SiH 4/PH 3＝4～10/2/2～3；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；厚度范围为大于3nm，小于等于5nm；
    在所述第二n型掺杂层上沉积第三n型掺杂层，沉积条件为：气体流量体积比的范围是H 2/SiH 4/PH 3＝4～10/2/3～4；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W；厚度范围为大于等于1nm，小于等于3nm。
  4. 根据权利要求3所述的异质结太阳能电池的制备方法，其特征在于：在沉积每一所述n型掺杂层是在抽真空后进行。
  5. 根据权利要求2所述的异质结太阳能电池的制备方法，其特征在于：在所述基片上的所述本征层上沉积p型掺杂层的沉积条件为：
    气体流量体积比为H 2/SiH 4/B 2H 6＝4～10/2/1～4；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于500W，小于等于2000W； 沉积厚度范围为大于等于4nm，小于等于10nm。
  6. 根据权利要求1所述的异质结太阳能电池的制备方法，其特征在于，所述本征层采用的沉积方式是：采用甚高频-等离子体增强化学气相沉积。
  7. 根据权利要求6所述的异质结太阳能电池的制备方法，其特征在于，所述本征层的沉积条件为：
    气体流量体积比为H 2/SiH 4＝0～10/1；气压范围为大于等于0.3mbar，小于等于2.0mbar；射频功率范围为大于等于200W，小于等于2000W；沉积厚度范围为大于等于5nm，小于等于15nm。
  8. 根据权利要求1所述的异质结太阳能电池的制备方法，其特征在于，所述提供基片包括：
    对所述基片的表面进行制绒和/或清洗的预处理。
  9. 一种异质结太阳能电池，其特征在于，包括：基片，本征层、n型掺杂层、p型掺杂层和电极层，所述本征层设置于所述基片的两侧，所述n型掺杂层和p型掺杂层分别设置于所述基片两侧的所述本征层上，所述电极层分别设置于所述基片两侧的所述n型掺杂层和p型掺杂层上；
    所述n型掺杂层和/或p型掺杂层至少设置为两层，且在远离所述基片的纵向方向上，所述n型掺杂层和/或p型掺杂层中各层的掺杂浓度呈递增状。
  10. 根据权利要求9所述的异质结太阳能电池，其特征在于，所述n型掺杂层和/或p型掺杂层的各层在远离所述基片的纵向方向上的厚度呈递减状。
  11. 根据权利要求10所述的异质结太阳能电池，其特征在于，在所述n型掺杂层设置于所述基片的所述本征层包括：
    在靠近所述本征层的一侧设置第一n型掺杂层；
    在所述第一n型掺杂层上设置第二n型掺杂层；
    在所述第二n型掺杂层上设置第三n型掺杂层。
  12. 根据权利要求11所述的异质结太阳能电池，其特征在于，所述第一n型掺杂层的厚度范围为大于5nm，小于等于10nm；所述第二n型掺杂层的厚度范围为大于3nm，小于等于5nm，所述第三n型掺杂层的厚度范围为大于等于1nm，小于等于3nm。
  13. 根据权利要求11所述的异质结太阳能电池，其特征在于，在所述p型掺杂层设置于所述基片的所述本征层包括：
    所述p型掺杂层的厚度范围为大于等于4nm，小于等于10nm。
  14. 根据权利要求9所述的异质结太阳能电池，其特征在于，所述本征层的厚度范围为大于等于5nm，小于等于15nm。
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