WO2018214533A1 - 显示装置以及像素电路及其控制方法 - Google Patents

显示装置以及像素电路及其控制方法 Download PDF

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Publication number
WO2018214533A1
WO2018214533A1 PCT/CN2018/072598 CN2018072598W WO2018214533A1 WO 2018214533 A1 WO2018214533 A1 WO 2018214533A1 CN 2018072598 W CN2018072598 W CN 2018072598W WO 2018214533 A1 WO2018214533 A1 WO 2018214533A1
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Prior art keywords
transistor
signal
pixel circuit
driving
gate
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2018/072598
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English (en)
French (fr)
Inventor
冯宇
刘利宾
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US16/096,102 priority Critical patent/US11127342B2/en
Publication of WO2018214533A1 publication Critical patent/WO2018214533A1/zh
Anticipated expiration legal-status Critical
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • the present disclosure relates to the field of liquid crystal display technology, and in particular to a display device and a pixel circuit and a control method thereof.
  • an active matrix organic light emitting display device uses a self-luminous organic light emitting diode (OLED) to display an image
  • OLED organic light emitting diode
  • Each of the pixels includes an organic light emitting diode and a pixel circuit for driving the organic light emitting diode.
  • Pixel circuits typically include a switching transistor, a drive transistor, and a storage capacitor.
  • a pixel circuit for driving LED light emission including:
  • resetting the charging module configured to charge the capacitor after resetting a capacitance between a gate of the driving transistor connected to the pixel circuit and the anode of the LED;
  • a driving module including the driving transistor, for driving the LED to emit light when the driving transistor receives the data signal;
  • the driving transistor for driving the light emitting diode to emit light uses an oxide TFT, and the other transistors in the pixel circuit are low temperature polysilicon LTPS TFT.
  • the driving module specifically includes: an input port of the illuminating indication signal, and the capacitor, the driving transistor transistor T3 and the transistor transistor T4 connected in series between the device operating voltage VDD and the anode of the LED;
  • the gate of the transistor T4 is connected to the input port of the light-emitting indication signal, and the gate of the transistor T3 is used to receive the data signal sent by the write module.
  • the driving module further includes a capacitor connected between the device operating voltage VDD and the anode of the LED.
  • the write module specifically includes: an input port of a third timing signal, an input port of a data signal, and a transistor transistor T2;
  • the gate of the transistor T2 is connected to the input port of the third timing signal, and the source and the drain of the transistor T2 are connected in series between the input port of the data signal and the gate of the driving transistor.
  • the reset charging module specifically includes: an input port of the first and second timing signals, and a transistor transistor T1, a transistor T5, and a transistor T6;
  • the gate of the transistor T5 is connected to the input port of the second timing signal, and the source and the drain of the transistor T5 are connected in series between the reference voltage and the gate of the transistor T3; the source of the transistor T1 And a drain, and a source and a drain of the transistor T6 are connected in series between the reference voltage and a positive electrode of the light emitting diode; the gates of the transistor T1 and the transistor T6 are both connected to an input port of the first timing signal
  • the connection point of the transistor T5 and the transistor T6 is connected to the gate of the transistor T3.
  • the reset charging module specifically includes: an input port of the first and second timing signals, and a transistor transistor T205 and a transistor T201;
  • the source and the drain of the transistor T205, and the source and the drain of the transistor T201 are connected in series between the reference voltage and the anode of the LED; the gates of the transistor T201 and the transistor T205 are respectively connected to The input ports of the first and second timing signals, the connection point of the transistor T205 and the transistor T201 are connected to the gate of the transistor T3.
  • the present disclosure also provides a method for controlling a pixel circuit, including:
  • the reset charging module that controls the pixel circuit in a first period of time resets a capacitance between a cathode of the LED and a gate of a driving transistor of the pixel circuit;
  • Driving a driving module of the pixel circuit to drive the LED to emit light through the driving transistor during a fourth period of time
  • the driving transistor is an oxide TFT for driving the LED to emit light
  • the other transistors in the pixel circuit are all LTPS TFTs.
  • the driving module that controls the pixel circuit in the fourth period of time to drive the LED to emit light through the driving transistor comprises:
  • the driving module specifically includes: the capacitor, and the driving transistor transistor T3 and the transistor transistor T4 connected in series between the device operating voltage VDD and the anode of the LED;
  • the gate of the transistor T4 is connected to the input end of the illumination indication signal, and the gate of the transistor T3 is used to receive the data signal sent by the write module.
  • the writing module that controls the pixel circuit in the third period of time writes a data signal to the gate of the driving transistor, which specifically includes:
  • the writing module specifically includes: a transistor T2;
  • the gate of the transistor T2 is connected to the input end of the third timing signal, and the source and the drain of the transistor T2 are connected in series between the input end of the data signal and the gate of the driving transistor.
  • the reset charging module controlling the pixel circuit in the first time period resets a capacitance between a positive electrode of the LED and a gate of the driving transistor of the pixel circuit; in the second time period Controlling the reset charging module to charge the capacitor, specifically:
  • the reset charging module specifically includes: a transistor T1, a transistor T5, and a transistor T6;
  • the gate of the transistor T5 is connected to the input end of the second timing signal, and the source and the drain of the transistor T5 are connected in series between the input end of the reference voltage and the gate of the transistor T3; the transistor T1 a source and a drain, and a source and a drain of the transistor T6 are connected in series between the input end of the reference voltage and a positive terminal of the light emitting diode; the gates of the transistor T1 and the transistor T6 are connected to the At the input of a timing signal, a connection point of the transistor T5 and the transistor T6 is connected to a gate of the transistor T3.
  • the reset charging module that controls the pixel circuit in a first period of time resets a capacitance between a cathode of the LED and a gate of a driving transistor of the pixel circuit; and controls the second period of time
  • the reset charging module charges the capacitor, and specifically includes:
  • the reset charging module specifically includes: a transistor T205 and a transistor T201;
  • the source and the drain of the transistor T205, and the source and the drain of the transistor T201 are connected in series between the input terminal of the reference voltage and the anode of the light emitting diode; the gate of the transistor T201 and the transistor T205 Connected to the input terminals of the first and second timing signals, respectively, the connection point of the transistor T205 and the transistor T201 is connected to the gate of the transistor T3.
  • the present disclosure also provides a display device including the above-described pixel circuit.
  • FIG. 1 is a block diagram showing the principle of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a flow chart of a pixel circuit control method according to an embodiment of the present disclosure
  • FIG. 3 is an internal structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of signals input to a pixel circuit according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a pixel circuit control method according to an embodiment of the present disclosure
  • FIG. 6 is an internal structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of signals input to a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a pixel circuit control method according to an embodiment of the present disclosure.
  • FIG. 9 is an internal structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of signals input to a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a pixel circuit control method according to an embodiment of the present disclosure.
  • the inventors of the present disclosure have found that the conventional pixel circuit has a problem that the hysteresis characteristic and the leakage current of the DTFT cannot fully satisfy the requirement of the display picture quality, so that the residual image phenomenon or the low contrast is caused on the display screen.
  • the inventors of the present disclosure have analyzed the existing pixel circuits, and the LTPS (Low Temperature Poly-silicon) TFT has the advantages of high electron mobility and high response speed of TFT (Thin Film Transistor).
  • Current circuits composed of LTPS TFTs are commonly used in pixel circuits.
  • the inventors of the present disclosure have found in practical applications that the LTPS TFT has the disadvantage of poor hysteresis characteristics, resulting in significant image phenomenon of the existing pixel circuit; and the DTFT (driving thin film transistor) leakage current of the LTPS TFT is large, resulting in There is a pixel circuit with low contrast.
  • an Oxide (oxide) TFT has a better hysteresis characteristic and a DTFT leakage current is small.
  • the circuit response speed is relatively slow, and it is difficult to satisfy the display device.
  • the main idea of the present disclosure is to use an Oxide TFT as a driving transistor for driving a light emitting diode in a pixel circuit, and other transistors in the pixel circuit adopt an LTPS TFT.
  • the Oxide TFT serves as a driving transistor for driving the light emitting diode, which has better hysteresis characteristics and a small DTFT leakage current, thereby improving the afterimage phenomenon of the light emitting diode and the problem of low contrast;
  • other transistors in the pixel circuit Both adopt LTPS TFTs, which have the advantages of high electron mobility and fast response speed of TFT.
  • the overall response of the pixel circuit still has due to the faster response of other transistors. The faster level can also meet the requirements of the display device high PPI (Pixels Per Inch).
  • the current pixel circuit generally has a function of transistor threshold voltage compensation in order to solve the problem of color unevenness, it is no longer a simple driving circuit structure, and therefore, the overall structure of the circuit cannot simply drive the driving transistor in the pixel circuit. Switching from LTPS TFT to Oxide TFT requires a corresponding change to the existing pixel circuit structure.
  • FIG. 1 a block diagram of a pixel circuit for driving LED light emission, as shown in FIG. 1 , includes a reset charging module 101 , a writing module 102 , and a driving module 103 . .
  • the driving module 103 includes a driving transistor T3 for driving the light emitting diode D1 to emit light, and the driving transistor is an Oxide TFT; driving the light emitting diode D1, driving the source and the drain of the transistor T3, and the positive and negative electrodes of the light emitting diode D1. It is connected in series between the device operating voltage VDD (device operating voltage) and VSS (common ground voltage).
  • the gate of the driving transistor T3 is used to drive the light emitting diode D1 to emit light according to the received signal.
  • the driving module 103 may further include a capacitor C1 connected between the gate of the driving transistor T3 and the anode of the LED D1 in the pixel circuit.
  • the charging module 101 is connected to the driving module 103, specifically connected to the gate of the driving transistor T3 in the driving module 103, and is also connected to the anode of the LED D1.
  • the reset charging module 101 is configured to charge the capacitor C1 after resetting the capacitor C1 between the gate of the driving transistor T3 connected to the pixel circuit and the anode of the LED D1. Specifically, the reset charging module 101 resets the capacitance C1 across the gate of the driving transistor T3 and the anode of the LED D1 during a first period of time; the capacitor C1 is in a second period of time. Charge it.
  • the write module 102 is connected to the drive module 103 and is specifically connected to the gate of the drive transistor T3 of the drive module 103.
  • the write module 102 is configured to write a data signal to the gate of the drive transistor T3. Specifically, the write module 102 writes a data signal to the gate of the drive transistor T3 for a third period of time.
  • the driving module 103 is configured to drive the LED D1 to emit light when the driving transistor T3 receives the data signal. Specifically, the driving module 103 drives the light emitting diode D1 to emit light through the driving transistor in a fourth period of time.
  • the first time period precedes the second time period
  • the second time period precedes the third time period
  • the third time period precedes the fourth time period.
  • the driving transistor T3 uses an oxide TFT, and the other transistors use an LTPS TFT.
  • the flow of the control method of the above pixel circuit, as shown in FIG. 2, includes the following steps:
  • Step S201 The reset charging module 101 that controls the pixel circuit in the first time period resets the capacitance C1 between the anode connected to the LED D1 and the gate of the driving transistor T3 of the pixel circuit.
  • Step S202 Control the reset charging module 101 to charge the capacitor C1 between the anode connected to the LED D1 and the gate of the driving transistor T3 of the pixel circuit in the second period.
  • Step S203 controlling the write module 102 of the pixel circuit to write a data signal to the gate of the driving transistor T3 during the third time period.
  • Step S204 The driving module 103 that controls the pixel circuit in the fourth period of time drives the LED D1 to emit light through the driving transistor T3.
  • FIG. 3 A pixel circuit according to an embodiment of the present disclosure is shown in FIG. 3, wherein the driving module is specifically configured to drive the light emitting diode through the driving transistor T3 according to an effective signal of the light emitting indication signal EM that arrives in the fourth time period. D1 glows.
  • the driving module in the pixel circuit may include an input port of an illumination indication signal, that is, an input port of the illumination indication signal of the pixel circuit, connected to the illumination indication signal line; and the driving module
  • the capacitor C1 is further connected to the driving transistor T3 and the transistor T4 connected between the device operating voltage VDD and the anode of the LED D1.
  • the cathode of the light emitting diode D1 is connected to the common ground terminal voltage VSS.
  • connection point of the capacitor C1 and the driving transistor T3 is referred to as N1 point
  • connection point of the capacitor C1 and the anode of the light emitting diode D1 is referred to as N2 point.
  • the driving module in the pixel circuit may further include a capacitor C2 across the device operating voltage VDD and the anode of the LED D1 to help stabilize the N2 point. Potential.
  • the write module in the pixel circuit is specifically configured to write the data signal V d to the gate of the driving transistor T3 according to the valid signal of the third timing signal S 3 arriving at the third time period; The valid signal of the data signal V d arrives in the third time period.
  • the pixel circuit may include a module written in a third timing signal S input port 3, i.e., the third timing signal input port of the pixel circuit S 3 is connected to the third timing signal Line (not shown).
  • the writing module may further include an input port of a data signal V d, i.e., the input data signal V d port of the pixel circuit connected to the data signal line (not shown).
  • the write module may further include a transistor T2; wherein a gate of the transistor T2 is connected to an input port of the third timing signal, and a source and a drain of the transistor T2 are connected in series with the data signal V d and the input port between the gate of the driving transistor T3.
  • the reset charging module in the pixel circuit of the embodiment of the present disclosure is specifically configured to reset the capacitor C1 according to the valid signal of the first timing signal S 1 that arrives in the first time period, and reach the second according to the second time period.
  • the effective signal of the timing signal S 2 charges the capacitor C1.
  • the reset charging module in the pixel circuit may include an input port of the first timing signal S 1 and an input port of the second timing signal S 2 as the first timing signals of the pixel circuits, respectively.
  • the input port and the input port of the second timing signal are respectively connected to the first timing signal line and the second timing signal line.
  • Reset charging module may further comprise: transistor T1, a transistor T5 and a transistor T6; wherein the gate of the transistor T5 is connected to the second input port timing signal S 2, the source and the drain of the transistor T5 is connected in series with the reference voltage Vref Between the gates of the transistor T3; the source and the drain of the transistor T1 and the source and the drain of the transistor T6 are connected in series between the reference voltage Vref and the anode of the light-emitting diode D1; the gate of the transistor T1 and the gate of the transistor T6 are connected to the first input port timing signal S 1 is connected to a gate connection point of the transistors T5 and T6 and the transistor T3.
  • the input ports of the first, second, and third timing signals S 1 , S 2 , and S 3 of the pixel circuit of the first embodiment of the present disclosure are respectively connected to the first, second, and third timing signal lines, and the input port of the illumination indication signal EM is connected to the illumination indication.
  • a signal line, a data signal V d is connected to the input port of the data signal line.
  • the pixel circuit is controlled to drive the light emission of the light-emitting diode D1 by controlling the signal timings of the first, second, and third timing signal lines, the light-emitting indication signal line, and the data signal line.
  • the transistor T3 is an N-type TFT, and the other transistors are P-type TFTs; accordingly, in the technical solution according to an embodiment of the present disclosure, the first, second, and third The timing signals S 1 , S 2 , S 3 , and the effective signals of the illumination indication signal EM are all low level signals, and the effective signal of the data signal V d is a high level signal, and the specific timing is as shown in FIG. 4 .
  • a control method of a pixel circuit includes the following steps:
  • Step S501 first time period a first control output signals S 1 timing signal is active, so that the charge reset module resets the valid signal of the first capacitor C1 in accordance with the timing of the signals S 1.
  • the low-level signal outputting the first timing signal S 1 is controlled as the effective signal of the first timing signal S 1 in the first period, and the second and third timing signals S 2 , S 3 and the data signal V d are both It is an invalid signal; at this time, the transistor T1 and the transistor T6 are turned on, and the voltages at the points N1 and N2 are reset, thereby realizing resetting of the capacitor C1 or resetting C1 and C2.
  • Step S502 Control the output of the valid signal of the second timing signal S 2 during the second time period, so that the reset charging module charges the capacitor C1 according to the valid signal of the second timing signal S 2 .
  • the low-level signal outputting the second timing signal S 2 is controlled as the effective signal of the second timing signal S 2 in the second period, and the first and third timing signals S 1 , S3 and the data signal V d are both Invalid signal; at this time, the transistor T1 and the transistor T6 are turned off, and the transistor T5 is turned on; the voltage at the N1 point is equal to Vref, and the voltage at the N2 point is equal to Vref-Vth, and the capacitor C1 is charged.
  • Vth is the threshold voltage of the driving transistor T3.
  • Step S503 third time period in the active control signal to output a third timing signal and a data signal S 3 V d so that the write module to the gate of the driving transistor T3 based on the effective write signal S 3 of the third timing signal The valid signal of the data signal V d .
  • the low-level signal outputting the third timing signal S 3 is controlled as the effective signal of the third timing signal S 3 during the third period, and the high-level signal of the output data signal V d is controlled as the effective of the data signal V d .
  • the first and second timing signals S 1 , S 2 and the illumination indication signal EM are all invalid signals; at this time, the transistor T2 is turned on, and the high-level effective signal of the data signal V d is written to the driving transistor transistor T3. gate; point voltage V N1 N1 is equal to the high-level data signal V d, V a voltage value of the node N2 N2 equation 1 as follows:
  • C1 and C2 respectively represent capacitance values of the capacitors C1 and C2, and ⁇ V N1 represents a change value of the point voltage V N1 of the third period N1.
  • Step S504 Control the output of the effective signal of the illumination indication signal EM in the fourth period of time, so that the driving module drives the LED D1 to emit light through the driving transistor T3 according to the effective signal of the illumination indication signal EM.
  • the low-level signal outputting the illumination indication signal EM is controlled as the effective signal of the illumination indication signal EM in the fourth period; and the first, second, and third timing signals S 1 , S 2 , and S 3 are all invalid signals.
  • the transistor T4 is turned on, and the driving transistor T3 is maintained in a state where the gate of the driving transistor T3 is maintained at the high level by the voltage of the capacitor C1, thereby driving the light-emitting diode D1 to emit light.
  • the voltage at the N2 point is equal to the positive voltage VEL at the time when the light-emitting diode D1 is turned on, and the voltage V N1 at the point N1 is as follows:
  • V N1 Vdata+VEL-Vref+Vth-C1*(Vdata-Vref)/(C1+C2) (Equation 2)
  • the circuit structure of the driving module and the writing module in the pixel circuit is the same as the circuit structure of the driving module and the writing module in the pixel circuit of FIG. 3 , respectively. I won't go into details here.
  • the reset charging module in the pixel circuit is specifically configured to reset the capacitor C1 according to the valid signals of the first and second timing signals S 1 , S 2 that arrive at the first time period, according to The effective signal of the second timing signal S 2 continuing for the second period of time charges the capacitor C1.
  • the reset charging module in the pixel circuit provided by the second embodiment of the present disclosure includes: an input port that can include the first and second timing signals S 1 , S 2 , respectively, as the first and second timing signals S 1 of the pixel circuit,
  • the input ports of S 2 are respectively connected to the first and second timing signal lines.
  • the reset charging module in the pixel circuit may further include: a transistor T205 and a transistor T201; wherein a source and a drain of the transistor T205, and a source and a drain of the transistor T201 are connected in series Between the reference voltage Vref and the anode of the LED D1; the gates of the transistor T201 and the transistor T205 are respectively connected to the input ports of the first and second timing signals S 1 , S 2 , the transistor T205 and the transistor T201 The connection point is connected to the gate of the transistor T3.
  • the input ports of the first, second, and third timing signals S 1 , S 2 , and S 3 of the pixel circuit according to an embodiment of the present disclosure are respectively connected to the first, second, and third timing signal lines, and the input port of the light-emitting indication signal EM is connected.
  • emission instruction signal line, a data signal V d is connected to the input port of the data signal line.
  • the pixel circuit is controlled to drive the light emission of the light-emitting diode D1 by controlling the signal timings of the first, second, and third timing signal lines, the light-emitting indication signal line, and the data signal line.
  • the transistor T3 is an N-type TFT
  • the transistor T1, the transistor T2, the transistor T4, and the transistor T205 are all P-type TFTs; accordingly, in accordance with an embodiment of the present disclosure,
  • the first, second and third timing signals S 1 , S 2 , S 3 and the effective signal of the illumination indication signal EM are all low level signals
  • the effective signal of the data signal V d is a high level signal
  • a control method of a pixel circuit includes the following steps:
  • Step S801 Control the output of the valid signals of the first and second timing signals S 1 , S 2 in the first time period, so that the reset charging module performs the capacitor C1 according to the effective signals of the first and second timing signals S 1 , S 2 . Reset.
  • the low-level signal outputting the first timing signal S 1 is controlled as the effective signal of the first timing signal S 1 in the first period
  • the low-level signal outputting the second timing signal S 2 is controlled as the second timing signal.
  • the effective signal of S 2 , and the third timing signal S 3 and the data signal V d are all invalid signals; at this time, the transistor T201 and the transistor T205 are turned on, and the voltages of the N1 and N2 points are reset, thereby realizing resetting of the capacitor C1, or to the C1.
  • C2 reset is the connection point of the capacitor C1 and the gate of the driving transistor T3, and the point N2 is the connection point of the capacitor C1 and the anode of the light-emitting diode D1.
  • Step S802 Continuing the valid signal of the second timing signal S 2 in the second time period, so that the reset charging module charges the capacitor C1 according to the valid signal of the second timing signal S 2 .
  • the output second timing signal S 2 continues to continue the active signal of the low level, and the first and third timing signals S 1 , S 3 and the data signal V d are invalid signals;
  • the transistor T201 is turned off, the transistor T205 is turned on; the voltage at the N1 point is equal to Vref, and the voltage at the N2 point is equal to Vref-Vth, and the capacitor C1 is charged.
  • Step S803 third time period in the active control signal to output a third timing signal and a data signal S 3 V d so that the write module to the gate of the driving transistor T3 based on the effective write signal S 3 of the third timing signal The valid signal of the data signal V d .
  • step S503 in FIG. I will not repeat them here.
  • Step S804 Control the output of the effective signal of the illumination indication signal EM in the fourth period of time, so that the driving module drives the LED D1 to emit light through the driving transistor T3 according to the effective signal of the illumination indication signal EM.
  • the circuit structure of the driving module and the writing module in the pixel circuit according to an embodiment of the present disclosure is respectively related to the driving module and the writing in the pixel circuit of one embodiment of the present disclosure in FIG. 3 .
  • the circuit structure of the incoming module is the same and will not be described here.
  • the reset charging module in the pixel circuit is specifically configured to reset the capacitor C1 according to the valid signals of the first and second timing signals S 1 , S 2 that arrive at the first time period, according to The effective signal of the second timing signal S 2 continuing for the second period of time charges the capacitor C1.
  • the reset charging module in the pixel circuit may include input ports of the first and second timing signals S 1 , S 2 as the first and second timing signals S 1 of the pixel circuit, respectively.
  • the input ports of S 2 are respectively connected to the first and second timing signal lines.
  • the reset charging module in the pixel circuit may further include: a transistor T205 and a transistor T201; wherein a source and a drain of the transistor T205, and a source and a drain of the transistor T201 are connected in series Between the reference voltage Vref and the anode of the LED D1; the gates of the transistor T201 and the transistor T205 are respectively connected to the input ports of the first and second timing signals S 1 , S 2 , the transistor T205 and the transistor T201 The connection point is connected to the gate of the transistor T3.
  • the transistor T205 in the pixel circuit of FIG. 9 is an N-type TFT; that is, in the pixel circuit according to an embodiment of the present disclosure shown in FIG. 9, the transistor T3 and the transistor T205 For the N-type TFT, the other transistor T201, the transistor T2, and the transistor T4 are P-type TFTs; correspondingly, according to the technical solution of one embodiment of the present disclosure, the first and third timing signals S 1 , S 3 and the illumination indication signal
  • the effective signal of the EM is a low level signal
  • the effective signal of the second timing signal S 2 is a high level signal
  • the effective signal of the data signal V d is a high level signal
  • the specific timing is as shown in FIG. 10 .
  • the input ports of the first, second, and third timing signals S 1 , S 2 , and S 3 of the pixel circuit according to an embodiment of the present disclosure are respectively connected to the first, second, and third timing signal lines, and the input port of the light-emitting indication signal EM is connected.
  • emission instruction signal line, a data signal V d is connected to the input port of the data signal line.
  • the pixel circuit is controlled to drive the light emission of the light-emitting diode D1 by controlling the signal timings of the first, second, and third timing signal lines, the light-emitting indication signal line, and the data signal line.
  • a control method of a pixel circuit includes the following steps:
  • Step S1101 Control outputting the valid signals of the first and second timing signals S 1 , S 2 in the first time period, so that the reset charging module pairs the capacitor according to the effective signals of the first and second timing signals S 1 , S 2 C1 is reset.
  • the low-level signal outputting the first timing signal S 1 is controlled as the effective signal of the first timing signal S 1 in the first period
  • the high-level signal outputting the second timing signal S 2 is controlled as the second timing signal.
  • the effective signal of S 2 , and the third timing signal S 3 and the data signal V d are all invalid signals; at this time, the transistor T201 and the transistor T205 are turned on, and the voltages of the N1 and N2 points are reset, thereby realizing resetting of the capacitor C1, or to the C1.
  • the point N1 is the connection point of the capacitor C1 and the gate of the driving transistor T3
  • the point N2 is the connection point of the capacitor C1 and the anode of the light-emitting diode D1.
  • Step S1102 The effective signal of the second timing signal S 2 is continued for the second time period, so that the reset charging module charges the capacitor C1 according to the valid signal of the second timing signal S 2 .
  • the second timing signal S 2 is controlled to continue to continue the high-level effective signal, and the first and third timing signals S 1 , S 3 and the data signal V d are invalid signals;
  • the transistor T201 is turned off, the transistor T205 is turned on; the voltage at the N1 point is equal to Vref, and the voltage at the N2 point is equal to Vref-Vth, and the capacitor C1 is charged.
  • Step S1103 Control the output of the third timing signal S 3 and the valid signal of the data signal V d in the third period, so that the writing module writes to the gate of the driving transistor T3 according to the effective signal of the third timing signal S 3 .
  • the valid signal of the data signal V d is the valid signal of the data signal V d .
  • step S503 in FIG. 5 Since the write module of the write module in FIG. 9 is the same as the write module of FIG. 3, this step is the same as step S503 in FIG. 5, and details are not described herein again.
  • Step S1104 Control the output of the effective signal of the illumination indication signal EM in the fourth period of time, so that the driving module drives the LED D1 to emit light through the driving transistor T3 according to the effective signal of the illumination indication signal EM.
  • step S504 in FIG. 5 Since the driving module of the driving module in FIG. 9 is the same as the driving module of FIG. 3, this step is the same as step S504 in FIG. 5, and details are not described herein again.
  • the reference voltage Vref, the device operating voltage VDD, and the common ground terminal voltage VSS described in the above embodiments are respectively supplied from a reference voltage line, a device operating voltage line, and a common ground terminal voltage line.
  • the pixel circuit according to the embodiment of the present disclosure shown in FIGS. 6 and 9 reduces the use of one transistor compared to the pixel circuit according to one embodiment of the present disclosure shown in FIG. 3, reducing the cost and reducing the circuit area. To help improve circuit integration.
  • an Oxide TFT is employed as the driving transistor T3 for driving the light emitting diode D1 in the pixel circuit, and other transistors in the pixel circuit are LTPS TFTs.
  • the Oxide TFT as the driving transistor T3 for driving the light emitting diode D1 has the advantages of better hysteresis characteristics and small DTFT leakage current, thereby improving the afterimage phenomenon of the light emitting diode D1 and the problem of low contrast; on the other hand, in the pixel circuit Other transistors use LTPS TFTs, which have the advantages of high electron mobility and fast TFT response speed.
  • the overall response of the pixel circuit is due to the faster response of other transistors. It still has a relatively fast level, so that it can also meet the high PPI requirements of the display device.

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Abstract

一种显示装置以及像素电路及其控制方法，电路包括：复位充电模块（101），用于对跨接于像素电路的驱动晶体管（T3）的栅极与发光二极管（D1）正极之间的电容（C1）进行复位后，对电容（C1）充电；写入模块（102），用于向驱动晶体管（T3）的栅极写入数据信号（V d）；驱动模块（103），其包括驱动晶体管（T3），用于在驱动晶体管（T3）接收数据信号（V d）时驱动发光二极管（D1）发光；其中，用以驱动发光二极管（D1）发光的驱动晶体管（T3）采用氧化物TFT，像素电路中的其它晶体管采用LTPS TFT；可以改善像素电路的磁滞特性、减小漏电流，从而改善显示画面的残像问题，以及对比度低的问题。

Description

显示装置以及像素电路及其控制方法
相关申请交叉引用
本公开要求申请日为2017年5月26日、发明名称为“显示装置以及像素电路及其控制方法”、申请号为201710382557.X的中国发明专利申请的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及液晶显示技术领域，特别是指一种显示装置以及像素电路及其控制方法。
背景技术
在各种类型的平板显示装置中，由于有源矩阵有机发光显示装置(AMOLED)使用自发光的有机发光二极管(OLED)来显示图像，通常具有响应时间短、使用低功耗进行驱动，相对更好的亮度和颜色纯度的特性，所以有机发光显示装置已经成为下一代显示装置的焦点。
对于大型有源矩阵有机发光显示装置，包括位于扫描线和数据线的交叉区域的多个像素。每个像素包括有机发光二极管和用于驱动所述有机发光二极管的像素电路。像素电路通常包括开关晶体管，驱动晶体管和存储电容器。
发明内容
根据本公开的一个实施例，提供一种像素电路，用于驱动发光二极管发光，其包括：
复位充电模块，用于对跨接于所述像素电路的驱动晶体管的栅极与所述发光二极管正极之间的电容进行复位后，对所述电容充电；
写入模块，用于向所述驱动晶体管的栅极写入数据信号；
驱动模块，其包括所述驱动晶体管，用于在所述驱动晶体管接收所述数据信号时驱动所述发光二极管发光；
其中，用以驱动所述发光二极管发光的驱动晶体管采用氧化物TFT，所述像素电路中的其它晶体管采用低温多晶硅LTPS TFT。
较佳地，所述驱动模块具体包括：发光指示信号的输入端口，以及所述电容、串接于 器件工作电压VDD与所述发光二极管正极之间的所述驱动晶体管晶体管T3和晶体管晶体管T4；
其中，晶体管T4的栅极连接于所述发光指示信号的输入端口，所述晶体管T3的栅极用于接收所述写入模块发送的数据信号。
进一步，所述驱动模块还包括一个跨接于器件工作电压VDD与所述发光二极管正极之间的电容。
较佳地，所述写入模块具体包括：第三时序信号的输入端口、数据信号的输入端口以及晶体管晶体管T2；
其中，晶体管T2的栅极连接于第三时序信号的输入端口，晶体管T2的源极和漏极串接所述数据信号的输入端口与所述驱动晶体管的栅极之间。
较佳地，所述复位充电模块具体包括：第一、二时序信号的输入端口，以及晶体管晶体管T1、晶体管T5和晶体管T6；
其中，所述晶体管T5的栅极连接于第二时序信号的输入端口，晶体管T5的源极和漏极串接于参考电压与所述晶体管T3的栅极之间；所述晶体管T1的源极和漏极，以及晶体管T6的源极和漏极串接于所述参考电压与所述发光二极管的正极之间；所述晶体管T1和晶体管T6的栅极均连接于第一时序信号的输入端口，所述晶体管T5和晶体管T6的连接点与所述晶体管T3的栅极相连。
或者，所述复位充电模块具体包括：第一、二时序信号的输入端口，以及晶体管晶体管T205和晶体管T201；
其中，所述晶体管T205的源极和漏极，以及晶体管T201的源极和漏极串接于参考电压与所述发光二极管的正极之间；所述晶体管T201、晶体管T205的栅极分别连接于第一、二时序信号的输入端口，所述晶体管T205和晶体管T201的连接点与所述晶体管T3的栅极相连。
本公开还提供一种像素电路的控制方法，包括：
在第一时间段控制所述像素电路的复位充电模块对跨接于发光二极管正极与所述像素电路的驱动晶体管的栅极之间的电容进行复位；
在第二时间段控制所述复位充电模块对所述电容进行充电；
在第三时间段控制所述像素电路的写入模块向所述驱动晶体管的栅极写入数据信号；
在第四时间段控制所述像素电路的驱动模块通过所述驱动晶体管驱动所述发光二极管 发光；
其中，所述驱动晶体管为所述像素电路用于驱动所述发光二极管发光的氧化物TFT，所述像素电路中的其它晶体管均采用LTPS TFT。
较佳地，所述在第四时间段控制所述像素电路的驱动模块通过所述驱动晶体管驱动所述发光二极管发光，具体包括：
在第四时间段控制输出发光指示信号的有效信号，使得所述驱动模块根据所述发光指示信号的有效信号，通过所述驱动晶体管驱动所述发光二极管发光；
其中，所述驱动模块具体包括：所述电容，以及串接于器件工作电压VDD与所述发光二极管正极之间的所述驱动晶体管晶体管T3和晶体管晶体管T4；
其中，晶体管T4的栅极连接于所述发光指示信号的输入端，所述晶体管T3的栅极用于接收所述写入模块发送的数据信号。
较佳地，所述在第三时间段控制所述像素电路的写入模块向所述驱动晶体管的栅极写入数据信号，具体包括：
在第三时间段控制输出第三时序信号以及数据信号的有效信号，使得所述写入模块根据第三时序信号的有效信号向所述驱动晶体管的栅极写入数据信号的有效信号；其中，
所述写入模块具体包括：晶体管T2；
其中，晶体管T2的栅极连接于第三时序信号的输入端，晶体管T2的源极和漏极串接所述数据信号的输入端与所述驱动晶体管的栅极之间。
较佳地，所述在第一时间段控制所述像素电路的复位充电模块对跨接于发光二极管正极与所述像素电路的驱动晶体管的栅极之间的电容进行复位；在第二时间段控制所述复位充电模块对所述电容进行充电，具体包括：
在第一时间段控制输出第一时序信号的有效信号，使得所述复位充电模块根据第一时序信号的有效信号对所述电容进行复位；
在第二时间段控制输出第二时序信号的有效信号，使得所述复位充电模块根据第二时序信号的有效信号对所述电容充电；其中，
所述复位充电模块具体包括：晶体管T1、晶体管T5和晶体管T6；
其中，所述晶体管T5的栅极连接于第二时序信号的输入端，晶体管T5的源极和漏极串接于参考电压的输入端与所述晶体管T3的栅极之间；所述晶体管T1的源极和漏极，以及晶体管T6的源极和漏极串接于所述参考电压的输入端与所述发光二极管的正极之间；所 述晶体管T1和晶体管T6的栅极均连接于第一时序信号的输入端，所述晶体管T5和晶体管T6的连接点与所述晶体管T3的栅极相连。
或者，所述在第一时间段控制所述像素电路的复位充电模块对跨接于发光二极管正极与所述像素电路的驱动晶体管的栅极之间的电容进行复位；在第二时间段控制所述复位充电模块对所述电容进行充电，具体包括：
在第一时间段控制输出第一、二时序信号的有效信号，使得所述复位充电模块根据第一、二时序信号的有效信号对所述电容进行复位；
在第二时间段延续第二时序信号的有效信号，使得所述复位充电模块根据第二时序信号的有效信号对所述电容进行充电；其中，
复位充电模块具体包括：晶体管T205和晶体管T201；
其中，所述晶体管T205的源极和漏极，以及晶体管T201的源极和漏极串接于参考电压的输入端与所述发光二极管的正极之间；所述晶体管T201、晶体管T205的栅极分别连接于第一、二时序信号的输入端，所述晶体管T205和晶体管T201的连接点与所述晶体管T3的栅极相连。
本公开还提供一种显示装置，包括上述的像素电路。
附图说明
图1为本公开的一个实施例的像素电路原理框图图；
图2为本公开的一个实施例的像素电路控制方法流程图；
图3为本公开的一个实施例的像素电路内部结构图；
图4为本公开的一个实施例的输入到像素电路各信号的时序图；
图5为本公开的一个实施例的像素电路控制方法流程图；
图6为本公开的一个实施例的像素电路内部结构图；
图7为本公开的一个实施例的输入到像素电路各信号的时序图；
图8为本公开的一个实施例的像素电路控制方法流程图；
图9为本公开的一个实施例的像素电路内部结构图；
图10为本公开的一个实施例的输入到像素电路各信号的时序图；
图11为本公开的一个实施例的像素电路控制方法流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能解释为对本公开的限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
需要说明的是，本公开实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便，不应理解为对本公开实施例的限定，后续实施例对此不再一一说明。
在实际应用中，本公开的发明人发现，现有的像素电路具有如下问题：DTFT的磁滞特性和漏电流不能完全满足显示画面质量的需求，使得显示画面出现残像现象或对比度低的问题。
本公开的发明人对现有像素电路进行分析，由于LTPS(Low Temperature Poly-silicon，低温多晶硅)TFT具有电子迁移率高，TFT(Thin Film Transistor，薄膜晶体管)响应速度较快等优点，因此，目前像素电路中通常采用由LTPS TFT构成的电路。然而，本公开的发明人在实际应用中发现：LTPS TFT具有磁滞特性差的缺点，从而导致现有像素电路残像现象明显；而LTPS TFT的DTFT(驱动薄膜晶体管)漏电流较大，导致现有像素电路画面对比度低。
本公开的发明人考虑到，Oxide(氧化物)TFT虽然具有较佳磁滞特性，DTFT漏电流小，但是，如果采用由Oxide TFT构成像素电路，则电路响应速度会比较慢，难以满足显示装置高PPI(Pixels Per Inch，每英寸的像素数目)的要求。
基于上述分析，本公开的主要思路为，采用Oxide TFT作为像素电路中用以驱动发光二极管的驱动晶体管，而像素电路中的其它晶体管采用LTPS TFT。这样，一方面Oxide TFT作为驱动发光二极管的驱动晶体管具有较佳磁滞特性，DTFT漏电流小的优点，从而改善发光二极管的残像现象，以及对比度低的问题；另一方面，像素电路中其它晶体管均采用LTPS TFT，具有电子迁移率高，TFT响应速度较快的优点，虽然，像素电路中具有一个响应速度 较慢的Oxide TFT，但由于其它晶体管响应较快，因此，像素电路整体响应仍然具有较快的水平，从而也可以满足显示装置高PPI(Pixels Per Inch，每英寸的像素数目)的要求。
另外，考虑到目前的像素电路为了解决色不均的问题而通常具有晶体管阈值电压补偿的功能，不再是简单的驱动电路结构，因此，电路的整体结构不能简单地将像素电路中的驱动晶体管由LTPS TFT换为Oxide TFT，还需对现有像素电路结构进行相应的改动。
下面结合附图详细介绍本公开的一个实施例的技术方案。
基于上述的思路，本公开的一个实施例提供的一种用于驱动发光二极管发光的像素电路的原理框图，如图1所示，包括：复位充电模块101、写入模块102，以及驱动模块103。
其中，驱动模块103中包括用以驱动发光二极管D1发光的驱动晶体管T3，该驱动晶体管采用Oxide TFT；为驱动发光二极管D1，驱动晶体管T3的源极、漏极，以及发光二极管D1的正极、负极串连于器件工作电压VDD(器件工作电压)与VSS(公共接地端电压)之间。驱动晶体管T3的栅极用于根据接收的信号驱动发光二极管D1发光。驱动模块103中还可以包括跨接于所述像素电路中的驱动晶体管T3的栅极与所述发光二极管D1的正极之间的电容C1。
复位充电模块101，其连接于驱动模块103，具体连接于驱动模块103中的驱动晶体管T3的栅极，还连接于发光二极管D1正极。复位充电模块101用于对跨接于所述像素电路中的驱动晶体管T3的栅极与所述发光二极管D1正极之间的电容C1进行复位后，对所述电容C1充电。具体地，复位充电模块101在第一时间段对跨接于所述驱动晶体管T3的栅极与所述发光二极管D1的正极之间的电容C1进行复位；在第二时间段对所述电容C1进行充电。
写入模块102，其连接于驱动模块103，具体连接于驱动模块103的驱动晶体管T3的栅极。写入模块102用于向所述驱动晶体管T3的栅极写入数据信号。具体地，写入模块102在第三时间段向所述驱动晶体管T3的栅极写入数据信号。
驱动模块103用于在所述驱动晶体管T3接收所述数据信号时驱动所述发光二极管D1发光。具体地，驱动模块103在第四时间段通过所述驱动晶体管驱动所述发光二极管D1发光。
其中，第一时间段先于第二时间段，第二时间段先于第三时间段，第三时间段先于第四时间段。
本公开提供的像素电路中，驱动晶体管T3采用氧化物TFT，其它晶体管均采用LTPS TFT。
上述像素电路的控制方法流程，如图2所示，包括如下步骤：
步骤S201：在第一时间段控制所述像素电路的复位充电模块101对跨接于发光二极管D1的正极与所述像素电路的驱动晶体管T3的栅极之间的电容C1进行复位。
步骤S202：在第二时间段控制所述复位充电模块101对跨接于发光二极管D1的正极与所述像素电路的驱动晶体管T3的栅极之间的电容C1进行充电。
步骤S203：在第三时间段控制所述像素电路的写入模块102向所述驱动晶体管T3的栅极写入数据信号。
步骤S204：在第四时间段控制所述像素电路的驱动模块103通过所述驱动晶体管T3驱动所述发光二极管D1发光。
基于上述原理，本公开提供了几个具体的实施例电路。
根据本公开的一个实施例提供的像素电路如图3所示，其中的驱动模块具体用于根据第四时间段到达的发光指示信号EM的有效信号，通过所述驱动晶体管T3驱动所述发光二极管D1发光。
具体地，根据本公开的一个实施例的像素电路中驱动模块可以包括一个发光指示信号的输入端口，该输入端口亦即像素电路的发光指示信号的输入端口，连接于发光指示信号线；驱动模块中还可包括：电容C1、串接于器件工作电压VDD与所述发光二极管D1的正极之间的所述驱动晶体管T3和晶体管T4。发光二极管D1的负极连接于公共接地端电压VSS。
为便于描述，本文将电容C1与驱动晶体管T3的栅极连接点称为N1点，将电容C1与发光二极管D1的正极的连接点称为N2点。
更优地，根据本公开的一个实施例的像素电路中的驱动模块还可包括一个跨接于器件工作电压VDD与所述发光二极管D1的正极之间的电容C2，以有助于稳定N2点的电位。
根据本公开的一个实施例的像素电路中的写入模块具体用于根据第三时间段到达的第三时序信号S 3的有效信号向所述驱动晶体管T3的栅极写入数据信号V d；其中，所述数据信号V d的有效信号在第三时间段到达。
具体地，根据本公开的一个实施例的像素电路中的写入模块可以包括一个第三时序信号S 3的输入端口，即像素电路的第三时序信号S 3的输入端口连接于第三时序信号线(未示出)。
在根据本公开的一个实施例中，写入模块还可以包括一个数据信号V d的输入端口，即 像素电路的数据信号V d的输入端口连接于数据信号线(未示出)。
在根据本公开的一个实施例中，写入模块还可以包括晶体管T2；其中，晶体管T2的栅极连接于第三时序信号的输入端口，晶体管T2的源极和漏极串接所述数据信号V d的输入端口与所述驱动晶体管T3的栅极之间。
本公开的一个实施例的像素电路中的复位充电模块具体用于根据第一时间段到达的第一时序信号S 1的有效信号对所述电容C1进行复位，根据第二时间段到达的第二时序信号S 2的有效信号对所述电容C1进行充电。
具体地，根据本公开的一个实施例的像素电路中的复位充电模块可以包括第一时序信号S 1的输入端口和第二时序信号S 2的输入端口，分别作为像素电路的第一时序信号的输入端口和第二时序信号的输入端口，并分别连接于第一时序信号线和第二时序信号线。
复位充电模块还可以包括：晶体管T1、晶体管T5和晶体管T6；其中，晶体管T5的栅极连接于第二时序信号S 2的输入端口，晶体管T5的源极和漏极串接于参考电压Vref与晶体管T3的栅极之间；晶体管T1的源极和漏极以及晶体管T6的源极和漏极都串接于参考电压Vref与所述发光二极管D1的正极之间；所述晶体管T1的栅极和晶体管T6的栅极均连接于第一时序信号S 1的输入端口，所述晶体管T5和晶体管T6的连接点与所述晶体管T3的栅极相连。
本公开实施例一的像素电路的第一、二、三时序信号S 1、S 2、S 3的输入端口分别连接第一、二、三时序信号线，发光指示信号EM的输入端口连接发光指示信号线，数据信号V d的输入端口连接数据信号线。通过控制第一、二、三时序信号线、发光指示信号线、数据信号线上的信号时序，控制像素电路驱动发光二极管D1的发光。
在根据本公开的一个实施例的像素电路中，晶体管T3为N型TFT，其它晶体管则为P型TFT；相应地，在根据本公开的一个实施例的技术方案中，第一、二、三时序信号S 1、S 2、S 3，以及发光指示信号EM的有效信号均为低电平信号，数据信号V d的有效信号为高电平信号，具体时序如图4所示。
根据本公开的一个实施例的像素电路的控制方法，流程如图5所示，包括如下步骤：
步骤S501：在第一时间段控制输出第一时序信号S 1的有效信号，使得所述复位充电模块根据第一时序信号S 1的有效信号对电容C1进行复位。
具体地，在第一时间段控制输出第一时序信号S 1的低电平信号作为第一时序信号S 1的有效信号，而第二、三时序信号S 2、S 3、数据信号V d均为无效信号；此时，晶体管T1、 晶体管T6打开，N1和N2点的电压复位，从而实现对电容C1复位，或者对C1和C2复位。
步骤S502：在第二时间段控制输出第二时序信号S 2的有效信号，使得复位充电模块根据第二时序信号S 2的有效信号对电容C1充电。
具体地，在第二时间段控制输出第二时序信号S 2的低电平信号作为第二时序信号S 2的有效信号，而第一、三时序信号S 1、S3、数据信号V d均为无效信号；此时，晶体管T1、晶体管T6关闭，晶体管T5打开；N1点电压等于Vref，N2点电压等于Vref-Vth，对电容C1实现充电。其中，Vth为驱动晶体管T3的阈值电压。
步骤S503：在第三时间段控制输出第三时序信号S 3以及数据信号V d的有效信号，使得写入模块根据第三时序信号S 3的有效信号向所述驱动晶体管T3的栅极写入数据信号V d的有效信号。
具体地，在第三时间段控制输出第三时序信号S 3的低电平信号作为第三时序信号S 3的有效信号，控制输出数据信号V d的高电平信号作为数据信号V d的有效信号；而第一、二时序信号S 1、S 2、发光指示信号EM均为无效信号；此时，晶体管T2打开，将数据信号V d的高电平有效信号写入到驱动晶体管晶体管T3的栅极；N1点的电压V N1等于数据信号V d的高电平，N2点的电压值V N2如下公式1：
V N2＝(Vref-Vth)+C1*ΔV N1/(C1+C2)＝(Vref-Vth)+C1*(Vref-Vth)/(C1+C2)(公式1)
其中，C1、C2分别表示电容C1、C2的容值，ΔV N1表示第三时间段N1点电压V N1的变化值。
步骤S504：在第四时间段控制输出发光指示信号EM的有效信号，使得驱动模块根据所述发光指示信号EM的有效信号，通过驱动晶体管T3驱动所述发光二极管D1发光。
具体地，在第四时间段控制输出发光指示信号EM的低电平信号作为发光指示信号EM的有效信号；而第一、二、三时序信号S 1、S 2、S 3均为无效信号。此时，晶体管T4打开，而驱动晶体管T3因电容C1的电压保持作用其栅极也维持高电平也处于打开状态，从而驱动发光二极管D1发光。此时，N2点的电压等于发光二极管D1导通时的正极电压VEL，N1点的电压V N1如下公式2：
V N1＝Vdata+VEL-Vref+Vth-C1*(Vdata-Vref)/(C1+C2)           (公式2)
如图6所示，根据本公开的一个实施例提供的像素电路中的驱动模块、写入模块的电 路结构，分别与图3的像素电路中的驱动模块、写入模块的电路结构相同，此处不再赘述。
根据本公开的一个实施例提供的像素电路中的复位充电模块具体用于根据第一时间段到达的第一、二时序信号S 1、S 2的有效信号对所述电容C1进行复位，根据在第二时间段延续的第二时序信号S 2的有效信号对所述电容C1进行充电。
具体地，本公开实施例二提供的像素电路中的复位充电模块包括：可以包括第一、二时序信号S 1、S 2的输入端口，分别作为像素电路的第一、二时序信号S 1、S 2的输入端口，并分别连接于第一、二时序信号线。
根据本公开的一个实施例提供的像素电路中的复位充电模块还可以包括：晶体管T205和晶体管T201；其中，所述晶体管T205的源极和漏极，以及晶体管T201的源极和漏极串接于参考电压Vref与所述发光二极管D1的正极之间；所述晶体管T201和晶体管T205的栅极分别连接于第一、二时序信号S 1、S 2的输入端口，所述晶体管T205和晶体管T201的连接点与所述晶体管T3的栅极相连。
根据本公开的一个实施例的像素电路的第一、二、三时序信号S 1、S 2、S 3的输入端口分别连接第一、二、三时序信号线，发光指示信号EM的输入端口连接发光指示信号线，数据信号V d的输入端口连接数据信号线。通过控制第一、二、三时序信号线、发光指示信号线、数据信号线上的信号时序，控制像素电路驱动发光二极管D1的发光。
在根据本公开的一个实施例的像素电路中，晶体管T3为N型TFT，晶体管T1、晶体管T2、晶体管T4、晶体管T205则均为P型TFT；相应地，在根据本公开的一个实施例的技术方案中，第一、二、三时序信号S 1、S 2、S 3以及发光指示信号EM的有效信号均为低电平信号，数据信号V d的有效信号为高电平信号，具体时序如图7所示。
根据本公开的一个实施例的像素电路的控制方法，流程如图8所示，包括如下步骤：
步骤S801：在第一时间段控制输出第一、二时序信号S 1、S 2的有效信号，使得所述复位充电模块根据第一、二时序信号S 1、S 2的有效信号对电容C1进行复位。
具体地，在第一时间段控制输出第一时序信号S 1的低电平信号作为第一时序信号S 1的有效信号，控制输出第二时序信号S 2的低电平信号作为第二时序信号S 2的有效信号，而第三时序信号S 3、数据信号V d均为无效信号；此时，晶体管T201、晶体管T205打开，N1和N2点电压复位，从而实现对电容C1复位，或者对C1和C2复位。其中，N1点为电容C1与驱动晶体管T3的栅极连接点，N2点为电容C1与发光二极管D1的正极的连接点。
步骤S802：在第二时间段延续第二时序信号S 2的有效信号，使得所述复位充电模块根 据第二时序信号S 2的有效信号对电容C1进行充电。
具体地，在第二时间段控制输出第二时序信号S 2继续延续低电平的有效信号，而第一、三时序信号S 1、S 3、数据信号V d均为无效信号；此时，晶体管T201关闭，晶体管T205打开；N1点电压等于Vref，N2点电压等于Vref-Vth，对电容C1实现充电。
步骤S803：在第三时间段控制输出第三时序信号S 3以及数据信号V d的有效信号，使得写入模块根据第三时序信号S 3的有效信号向所述驱动晶体管T3的栅极写入数据信号V d的有效信号。
由于图6中的根据本公开的该实施例的写入模块与图3中的根据本公开的一个实施例的写入模块的电路结构相同，因此，本步骤与图5中的步骤S503相同，此处不再赘述。
步骤S804：在第四时间段控制输出发光指示信号EM的有效信号，使得驱动模块根据所述发光指示信号EM的有效信号，通过驱动晶体管T3驱动所述发光二极管D1发光。
由于图6中的根据本公开的一个实施例的驱动模块与图3中的根据本公开的一个实施例的驱动模块的电路结构相同，因此，本步骤与图5中的步骤S504相同，此处不再赘述。
如图9所示，根据本公开的一个实施例提供的像素电路中的驱动模块、写入模块的电路结构，分别与图3中的本公开的一个实施例的像素电路中的驱动模块、写入模块的电路结构相同，此处不再赘述。
根据本公开的一个实施例提供的像素电路中的复位充电模块具体用于根据第一时间段到达的第一、二时序信号S 1、S 2的有效信号对所述电容C1进行复位，根据在第二时间段延续的第二时序信号S 2的有效信号对所述电容C1充电。
具体地，根据本公开的一个实施例提供的像素电路中的复位充电模块可以包括第一、二时序信号S 1、S 2的输入端口，分别作为像素电路的第一、二时序信号S 1、S 2的输入端口，并分别连接于第一、二时序信号线。
根据本公开的一个实施例提供的像素电路中的复位充电模块还可以包括：晶体管T205和晶体管T201；其中，所述晶体管T205的源极和漏极，以及晶体管T201的源极和漏极串接于参考电压Vref与所述发光二极管D1的正极之间；所述晶体管T201、晶体管T205的栅极分别连接于第一、二时序信号S 1、S 2的输入端口，所述晶体管T205和晶体管T201的连接点与所述晶体管T3的栅极相连。
不同于图6所示的像素电路，图9的像素电路中的晶体管T205为N型TFT；也就是说， 图9所示的根据本公开的一个实施例的像素电路中，晶体管T3与晶体管T205为N型TFT，其它晶体管T201、晶体管T2、晶体管T4则为P型TFT；相应地，根据本公开的一个实施例的技术方案中，第一、三时序信号S 1、S 3以及发光指示信号EM的有效信号均为低电平信号，第二时序信号S 2的有效信号为高电平信号，数据信号V d的有效信号为高电平信号，具体时序如图10所示。
根据本公开的一个实施例的像素电路的第一、二、三时序信号S 1、S 2、S 3的输入端口分别连接第一、二、三时序信号线，发光指示信号EM的输入端口连接发光指示信号线，数据信号V d的输入端口连接数据信号线。通过控制第一、二、三时序信号线、发光指示信号线、数据信号线上的信号时序，控制像素电路驱动发光二极管D1的发光。
根据本公开的一个实施例的像素电路的控制方法，流程如图11所示，包括如下步骤：
步骤S1101：在第一时间段控制输出第一、二时序信号S 1、S 2的有效信号，使得所述复位充电模块根据第一、二时序信号S 1、S 2的有效信号对所述电容C1进行复位。
具体地，在第一时间段控制输出第一时序信号S 1的低电平信号作为第一时序信号S 1的有效信号，控制输出第二时序信号S 2的高电平信号作为第二时序信号S 2的有效信号，而第三时序信号S 3、数据信号V d均为无效信号；此时，晶体管T201、晶体管T205打开，N1和N2点电压复位，从而实现对电容C1复位，或者对C1和C2复位。其中，N1点为电容C1与驱动晶体管T3的栅极连接点，N2点为电容C1与发光二极管D1的正极的连接点。
步骤S1102：在第二时间段延续第二时序信号S 2的有效信号，使得所述复位充电模块根据第二时序信号S 2的有效信号对所述电容C1进行充电。
具体地，在第二时间段控制输出第二时序信号S 2继续延续高电平的有效信号，而第一、三时序信号S 1、S 3、数据信号V d均为无效信号；此时，晶体管T201关闭，晶体管T205打开；N1点电压等于Vref，N2点电压等于Vref-Vth，对电容C1实现充电。
步骤S1103：在第三时间段控制输出第三时序信号S 3以及数据信号V d的有效信号，使得写入模块根据第三时序信号S 3的有效信号向所述驱动晶体管T3的栅极写入数据信号V d的有效信号。
由于图9中的根据本公开的一个实施例的写入模块与图3中的写入模块的电路结构相同，因此，本步骤与图5中的步骤S503相同，此处不再赘述。
步骤S1104：在第四时间段控制输出发光指示信号EM的有效信号，使得驱动模块根据所述发光指示信号EM的有效信号，通过驱动晶体管T3驱动所述发光二极管D1发光。
由于图9中的根据本公开的一个实施例的驱动模块与图3中的驱动模块的电路结构相同，因此，本步骤与图5中的步骤S504相同，此处不再赘述。
上述各实施例中所述的参考电压Vref、器件工作电压VDD、公共接地端电压VSS，分别由参考电压线、器件工作电压线、公共接地端电压线供给。
图6和图9中所示的根据本公开的实施例的像素电路相比于图3所示的根据本公开的一个实施例的像素电路减少使用了一个晶体管，降低了成本，减小电路面积，利于提高电路集成度。
在根据本公开实施例的技术方案中，采用OxideTFT作为像素电路中用以驱动发光二极管D1的驱动晶体管T3，而像素电路中的其它晶体管采用LTPS TFT。这样，一方面OxideTFT作为驱动发光二极管D1的驱动晶体管T3具有较佳磁滞特性，DTFT漏电流小的优点，从而改善发光二极管D1的残像现象，以及对比度低的问题；另一方面，像素电路中其它晶体管均采用LTPS TFT，具有电子迁移率高，TFT响应速度较快的优点，虽然，像素电路中具有一个响应速度较慢的Oxide TFT，但由于其它晶体管响应较快，因此，像素电路整体响应仍然具有较快的水平，从而也可以满足显示装置高PPI的要求。
本技术领域技术人员可以理解，本公开中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本公开中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本公开中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本公开的范围(包括权利要求)被限于这些例子；在本公开的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本公开的不同方面的许多其它变化，为了简明它们没有在细节中提供。因此，凡在本公开的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种像素电路，用于驱动发光二极管发光，其包括：
    复位充电模块，用于对跨接于所述像素电路的驱动晶体管的栅极与所述发光二极管正极之间的电容进行复位以及对所述电容充电；
    写入模块，用于向所述驱动晶体管的栅极写入数据信号；
    驱动模块，其包括所述驱动晶体管，用于根据所述驱动晶体管的栅极接收的所述数据信号驱动所述发光二极管发光；
    其中，所述驱动晶体管为氧化物薄膜晶体管，所述像素电路中的其它晶体管采用低温多晶硅薄膜晶体管。
  2. 根据权利要求1所述的像素电路，其特征在于，所述驱动模块还包括：发光指示信号的输入端口、所述电容、串接于器件工作电压VDD与所述发光二极管的正极之间的所述驱动晶体管(T3)和第四晶体管(T4)；
    其中，第四晶体管(T4)的栅极连接于所述发光指示信号的输入端口，所述驱动晶体管(T3)的栅极用于接收所述写入模块发送的数据信号。
  3. 根据权利要求2所述的像素电路，其特征在于，所述驱动模块还包括一个跨接于所述器件工作电压VDD与所述发光二极管的正极之间的电容。
  4. 根据权利要求2或3所述的像素电路，其特征在于，所述写入模块包括：第三时序信号的输入端口、数据信号的输入端口以及第二晶体管T2；
    其中，第二晶体管T2的栅极连接于第三时序信号的输入端口，第二晶体管T2的源极和漏极串接在所述数据信号的输入端口与所述驱动晶体管的栅极之间。
  5. 根据权利要求4所述的像素电路，其特征在于，所述复位充电模块包括：第一、二时序信号的输入端口，第一晶体管(T1)、第五晶体管(T5)和第六晶体管(T6)；
    其中，所述第五晶体管(T5)的栅极连接于第二时序信号的输入端口，第五晶体管(T5)的源极和漏极串接于参考电压与所述驱动晶体管(T3)的栅极之间；所述第一晶体管(T1) 的源极和漏极，以及第六晶体管(T6)的源极和漏极串接于所述参考电压与所述发光二极管的正极之间；所述第一晶体管(T1)和第六晶体管(T6)的栅极均连接于第一时序信号的输入端口，所述第五晶体管(T5)和第六晶体管(T6)的连接点与所述驱动晶体管(T3)的栅极相连。
  6. 根据权利要求4所述的像素电路，其特征在于，所述复位充电模块包括：第一、二时序信号的输入端口，以及第五晶体管(T205)和第1晶体管(T201)；
    其中，所述第五晶体管(T205)的源极和漏极，以及第一晶体管(T201)的源极和漏极串接于参考电压与所述发光二极管的正极之间；所述第一晶体管(T201)、第五晶体管(T205)的栅极分别连接于第一、二时序信号的输入端口，所述第五晶体管(T205)和第一晶体管(T201)的连接点与所述驱动晶体管(T3)的栅极相连。
  7. 根据权利要求6所述的像素电路，其特征在于，所述第一晶体管(T1)、第二晶体管(T2)、第四晶体管(T4)、第五晶体管(T205)均为P型TFT；以及
    第一、二、三时序信号，以及发光指示信号的有效信号均为低电平信号。
  8. 根据权利要求6所述的像素电路，其特征在于，所述第一晶体管(T1)、第二晶体管(T2)、第四晶体管(T4)均为P型TFT，第五晶体管(T205)为N型TFT；以及
    第一、三时序信号，以及发光指示信号的有效信号均为低电平信号；第二时序信号的有效信号为高电平信号。
  9. 一种像素电路的控制方法，包括：
    在第一时间段控制所述像素电路的复位充电模块对跨接于发光二极管正极与所述像素电路的驱动晶体管的栅极之间的电容进行复位；
    在第二时间段控制所述复位充电模块对所述电容进行充电；
    在第三时间段控制所述像素电路的写入模块向所述驱动晶体管的栅极写入数据信号；
    在第四时间段控制所述像素电路的驱动模块通过所述驱动晶体管驱动所述发光二极管发光；
    其中，所述驱动晶体管为氧化物薄膜晶体管TFT，所述像素电路中的其它晶体管均采 用低温多晶硅薄膜晶体管LTPS TFT。
  10. 根据权利要求9所述的方法，其特征在于，在第四时间段控制所述像素电路的驱动模块通过所述驱动晶体管驱动所述发光二极管发光的步骤包括：
    在第四时间段控制输出发光指示信号的有效信号，使得所述驱动模块根据所述发光指示信号的有效信号，通过所述驱动晶体管驱动所述发光二极管发光；其中，
    所述驱动模块具体包括：所述电容，以及串接于器件工作电压VDD与所述发光二极管正极之间的所述驱动晶体管(T3)和第四晶体管(T4)；
    其中，第四晶体管(T4)的栅极连接于所述发光指示信号的输入端，所述驱动晶体管(T3)的栅极用于接收所述写入模块发送的数据信号。
  11. 根据权利要求10所述的方法，其特征在于，在第三时间段控制所述像素电路的写入模块向所述驱动晶体管(T3)的栅极写入数据信号的步骤包括：
    在第三时间段控制输出第三时序信号以及数据信号的有效信号，使得所述写入模块根据第三时序信号的有效信号向所述驱动晶体管(T3)的栅极写入数据信号的有效信号；其中，
    所述写入模块包括：第二晶体管(T2)；
    其中，第二晶体管(T2)的栅极连接于第三时序信号的输入端，第二晶体管(T2)的源极和漏极串接所述数据信号的输入端与所述驱动晶体管(T3)的栅极之间。
  12. 根据权利要求11所述的方法，其特征在于，在第一时间段控制所述像素电路的复位充电模块对跨接于发光二极管正极与所述像素电路的驱动晶体管(T3)的栅极之间的电容进行复位；以及在第二时间段控制所述复位充电模块对所述电容进行充电的步骤包括：
    在第一时间段控制输出第一时序信号的有效信号，使得所述复位充电模块根据第一时序信号的有效信号对所述电容进行复位；
    在第二时间段控制输出第二时序信号的有效信号，使得所述复位充电模块根据第二时序信号的有效信号对所述电容充电；其中，
    所述复位充电模块包括：第一晶体管(T1)、第二晶体管(T5)和第六晶体管(T6)；
    其中，所述第五晶体管(T5)的栅极连接于第二时序信号的输入端，第五晶体管(T5) 的源极和漏极串接于参考电压的输入端与所述驱动晶体管(T3)的栅极之间；所述第一晶体管(T1)的源极和漏极，以及第六晶体管(T6)的源极和漏极串接于所述参考电压的输入端与所述发光二极管的正极之间；所述第一晶体管(T1)和第六晶体管(T6)的栅极均连接于第一时序信号的输入端，所述第五晶体管(T5)和第六晶体管(T6)的连接点与所述驱动晶体管(T3)的栅极相连。
  13. 根据权利要求11所述的方法，其特征在于，在第一时间段控制所述像素电路的复位充电模块对跨接于发光二极管正极与所述像素电路的驱动晶体管的栅极之间的电容进行复位；以及在第二时间段控制所述复位充电模块对所述电容进行充电的步骤包括：
    在第一时间段控制输出第一、二时序信号的有效信号，使得所述复位充电模块根据第一、二时序信号的有效信号对所述电容进行复位；
    在第二时间段延续第二时序信号的有效信号，使得所述复位充电模块根据第二时序信号的有效信号对所述电容进行充电；其中，
    复位充电模块具体包括：第五晶体管(T205)和第一晶体管(T201)；
    其中，所述第五晶体管(T205)的源极和漏极，以及第一晶体管(T201)的源极和漏极串接于参考电压的输入端与所述发光二极管的正极之间；所述第一晶体管(T201)、第五晶体管(T205)的栅极分别连接于第一、二时序信号的输入端，所述第五晶体管(T205)和第一晶体管(T201)的连接点与所述驱动晶体管(T3)的栅极相连。
  14. 根据权利要求13所述的方法，其特征在于，所述第一、二、三时序信号，以及发光指示信号的有效信号均为低电平信号，以及第一晶体管(T201)、晶体管第二T2、第四晶体管(T4)、第五晶体管(T205)均为P型TFT；或者
    所述第一、三时序信号、发光指示信号的有效信号均为低电平信号；第二时序信号的有效信号为高电平信号，以及第一晶体管(T201)、第二晶体管(T2)、第四晶体管(T4)均为P型TFT，第五晶体管(T205)为N型TFT。
  15. 一种显示装置，其特征在于，包括：如权利要求1-8任一所述的像素电路。
PCT/CN2018/072598 2017-05-26 2018-01-15 显示装置以及像素电路及其控制方法 Ceased WO2018214533A1 (zh)

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