WO2018209909A1 - 像素驱动电路、显示装置和驱动方法 - Google Patents

像素驱动电路、显示装置和驱动方法 Download PDF

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Publication number
WO2018209909A1
WO2018209909A1 PCT/CN2017/110793 CN2017110793W WO2018209909A1 WO 2018209909 A1 WO2018209909 A1 WO 2018209909A1 CN 2017110793 W CN2017110793 W CN 2017110793W WO 2018209909 A1 WO2018209909 A1 WO 2018209909A1
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Prior art keywords
thin film
film transistor
circuit
sub
node
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PCT/CN2017/110793
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English (en)
French (fr)
Inventor
胡祖权
王锡平
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/061,593 priority Critical patent/US11211005B2/en
Publication of WO2018209909A1 publication Critical patent/WO2018209909A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • Embodiments of the present disclosure relate to a pixel driving circuit, a display device, and a driving method.
  • AMOLED active matrix organic light emitting diode
  • FIG. 1 shows a structure of a pixel driving circuit including a first thin film transistor 51, a second thin film transistor 52, a third thin film transistor 53, a fourth thin film transistor 54, a storage capacitor 55, and a first power supply Vdd.
  • the second power source Vss, the data line I_oled, the control line G_N, and the control signal line S1 works as follows:
  • the control line G_N is at a high level, the second thin film transistor 52 and the third thin film transistor 53 are turned on, and the signal current on the data line I_oled is written to the first via the second thin film transistor 52 and the third thin film transistor 53.
  • the gate of the thin film transistor 51 while the signal current charges the storage capacitor 55 through the source and drain of the first thin film transistor 1. Since the control signal line S1 is at a low level, so that the fourth thin film transistor 54 is turned off, the first power source Vdd and the second power source Vss cannot form a loop, and thus the organic light emitting diode (OLED) 56 does not emit light. At this time, the node A is short-circuited with the drain of the first thin film transistor 51.
  • the signal current flows through the drain and source of the first thin film transistor 51 to the second power source Vss.
  • the control line G_N is at a low level, and the second thin film transistor 52 and the third thin film transistor 53 are turned off.
  • the first thin film transistor 51 is in a saturated on state, and the control signal line S1 is At a high level, the fourth thin film transistor 54 is turned on, the first power source Vdd forms a loop with the second power source Vss, and the signal current is completely reproduced as a driving signal current, which is supplied to the OLED 56 to drive its light.
  • the fourth thin film transistor 54 in the light emitting phase, is connected in series in a loop formed by the first power source Vdd and the second power source Vss, and the fourth thin film transistor 54 has a resistance R when linearly turned on, so that when the OLED 56 continues to emit light,
  • the fourth thin film transistor 54 consumes I 2 R, where I is the signal current, and for each OLED pixel, there is a resistor R present, resulting in loss of power of the entire OLED display panel.
  • the OLED display panel is provided with the control signal line S1 to control the fourth thin film transistor 54, so that the number of signal lines is increased, resulting in complicated OLED display panel routing and reduced production yield.
  • the embodiments of the present disclosure provide a pixel driving circuit, a display device, and a driving method to solve the problems of high power consumption of the conventional pixel driving circuit, complicated wiring of the OLED display panel, and low production yield.
  • Embodiments of the present disclosure provide a pixel driving circuit including: a control sub-circuit, a charging sub-circuit, a driving sub-circuit, and an illuminating sub-circuit.
  • the control sub-circuit is connected to the data line and the control line, and the control sub-circuit is connected to the driving sub-circuit through the first node and the second node; the charging sub-circuit passes through the first node and the third node
  • the driving sub-circuit is connected; one end of the illuminating sub-circuit is connected to the driving sub-circuit, and the other end of the illuminating sub-circuit is connected to a first power source or a second power source; the driving sub-circuit includes a first thin film transistor
  • the control sub-circuit charges the charging sub-circuit by controlling the first thin film transistor through the first node and the third node, and the charging sub-circuit passes the first node as the driver
  • the circuit provides a voltage, and the drive subcircuit drives
  • the charging sub-circuit includes a storage capacitor, one end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the third node.
  • the third node is connected to the second power source.
  • a gate of a first thin film transistor of the driving sub-circuit is connected to the first node, and a source of the first thin film transistor and the third a node is connected; a drain of the first thin film transistor is connected to the second node.
  • the illuminating sub-circuit includes a light emitting device, and a cathode of the illuminating device is connected to the second node, an anode of the illuminating device and the first power source connection.
  • the control sub-circuit includes: a second thin film transistor and a third thin film transistor; a gate of the second thin film transistor and the third thin a gate of the film transistor is connected and connected to the control line; a drain of the second thin film transistor is connected to the data line; a source of the second thin film transistor, a drain of the third thin film transistor, and a drain The first node is connected; the source of the third thin film transistor is connected to the second node.
  • control sub-circuit further includes a fourth thin film transistor, a gate of the fourth thin film transistor, and a gate of the second thin film transistor, the first The gates of the three thin film transistors are connected; the source of the fourth thin film transistor is connected to the second node, and the drain of the fourth thin film transistor is connected to the first power source.
  • the control sub-circuit includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor; a gate of the second thin film transistor, the third a gate of the thin film transistor is connected to a gate of the fourth thin film transistor and connected to the control line; a drain of the second thin film transistor is connected to the data line; a source of the second thin film transistor a drain of the third thin film transistor is connected to the first node; a source of the third thin film transistor is connected to the second node; the second node is connected to the first power source; A drain of the thin film transistor is connected to the third node, and a source of the fourth thin film transistor is connected to the second power source.
  • the illuminating sub-circuit includes a light emitting device, and an anode of the illuminating device is connected to the third node, a cathode of the illuminating device and the second power source connection.
  • the embodiment of the present disclosure further provides a display device, including the pixel driving circuit provided by any embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a driving method of a pixel driving circuit
  • the pixel driving circuit includes a control sub-circuit, a charging sub-circuit, a driving sub-circuit, and a lighting sub-circuit
  • the driving method includes: passing the control sub-circuit Controlling the driving sub-circuit to charge the charging sub-circuit; supplying a voltage to the driving sub-circuit through the charging sub-circuit to drive the illuminating sub-circuit to emit light.
  • the control sub-circuit includes a second thin film transistor and a third thin film transistor
  • the driving sub-circuit includes a first thin film transistor
  • the charging sub-circuit includes a storage capacitor.
  • Controlling the driving sub-circuit to charge the charging sub-circuit by the control sub-circuit includes: the control line providing a high level, such that the second thin film transistor and the third thin film transistor are turned on; The line provides a signal current that charges the storage capacitor through the gate and source of the first thin film transistor.
  • the charging sub-circuit is Driving the sub-circuit to supply a voltage to drive the illuminating sub-circuit to emit light includes: the control line providing a low level, such that the second thin film transistor and the third thin film transistor are turned off; The gate of the thin film transistor is supplied with a high level such that the first thin film transistor is turned on; the first power supply provides a high level to drive the light emitting sub-circuit to emit light.
  • the control sub-circuit includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor
  • the driving sub-circuit includes a first thin film transistor
  • the charger The circuit includes a storage capacitor
  • controlling the driving sub-circuit to charge the charging sub-circuit by the control sub-circuit includes: the control line providing a high level, so that the second thin film transistor, the third thin film transistor And the fourth thin film transistor is turned on; the data line provides a signal current, and the signal current charges the storage capacitor through a gate and a source of the first thin film transistor.
  • supplying a voltage to the driving sub-circuit by the charging sub-circuit to drive the illuminating sub-circuit to emit light includes: the control line providing a low level, so that The second thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned off; a high level is provided to a gate of the first thin film transistor by the storage capacitor, so that the first thin film transistor is turned on; The first power source provides a high level to drive the illuminating sub-circuit to emit light.
  • the pixel driving circuit of the embodiment of the present disclosure includes a control sub-circuit, a charging sub-circuit, a driving sub-circuit, and a lighting sub-circuit.
  • the control sub-circuit is connected to the data line and the control line, and the control sub-circuit passes through the first node, the second node, and the driver.
  • the circuit is connected, the charging sub-circuit is connected to the driving sub-circuit through the first node and the third node, the driving sub-circuit is connected to one end of the illuminating sub-circuit, and the other end of the illuminating sub-circuit is connected to the first power source or the second power source, and the driving sub-circuit
  • the first thin film transistor is included, and the control sub-circuit controls the first thin film transistor to charge the charging sub-circuit through the first node and the third node, the charging sub-circuit supplies a voltage to the driving sub-circuit through the first node, and the driving sub-circuit drives the illuminating sub-circuit Glowing.
  • the driving sub-circuit of the embodiment of the present disclosure includes only the first thin film transistor, thereby facilitating reduction of power supply load and power consumption reduction; in addition, since only the control line and the data line are needed, it is not necessary to add other signal control lines, and the circuit structure wiring is simpler. It is advantageous to simplify the manufacturing process and improve the yield.
  • 1 is a schematic structural view of a pixel driving circuit
  • FIG. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a driving method of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 7 is a signal timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the pixel driving circuit of the embodiment of the present disclosure includes: a control sub-circuit 10, a charging sub-circuit 30, a driving sub-circuit 20, and a illuminating sub-circuit 40, a control sub-circuit 10 and a data line I_oled and a control line G_N.
  • the control sub-circuit 10 is connected to the driving sub-circuit 20 through the first node 1 and the second node 2
  • the charging sub-circuit 30 is connected to the driving sub-circuit 20 through the first node 1 and the third node 3, and drives the sub-circuit 20 and the light-emitting unit.
  • One end of the sub-circuit 40 is connected, and the other end of the illuminating sub-circuit 40 is connected to the first power source Vdd or the second power source Vss, and the driving sub-circuit 20 includes a first thin film transistor.
  • the working principle of the pixel driving circuit of the embodiment of the present disclosure is that the control sub-circuit 10 controls the first thin film transistor of the driving sub-circuit 20 to charge the charging sub-circuit 30 through the first node 1 and the third node 3, and the charging sub-circuit 30 passes The first node 1 supplies voltage to the driving sub-circuit 20, and drives the sub-circuit 20 is used to drive the illuminating sub-circuit 40 to emit light.
  • FIG. 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the control sub-circuit 10 includes the second thin film transistor 12 and the third thin film transistor 13, the gate of the second thin film transistor 12, and the third thin film transistor 13
  • the gate is connected to the control line G_N
  • the drain of the second thin film transistor 12 is connected to the data line I_oled
  • the source of the second thin film transistor 12 and the drain of the third thin film transistor 13 are connected to the first node 1
  • third The source of the thin film transistor 13 is connected to the second node 2.
  • the charging sub-circuit 30 includes a storage capacitor 15. One end of the storage capacitor 15 is connected to the first node 1, the other end of the storage capacitor 15 is connected to the third node 3, and the third node 3 is connected to the second power source Vss.
  • the driving sub-circuit 20 includes a first thin film transistor 11, a gate of the first thin film transistor 11 is connected to the first node 1, a source of the first thin film transistor 11 is connected to the third node 3, and a drain of the first thin film transistor 11 is The second node 2 is connected.
  • the illuminating sub-circuit 40 includes a light emitting device 16, the cathode of which is connected to the second node 2, and the anode of the illuminating device 16 is connected to the first power source Vdd.
  • the light emitting device 16 can be an organic light emitting diode.
  • the first power source Vdd is at a high level with respect to the second power source Vss. That is, the level of the first power source Vdd is higher than the level of the second power source Vss.
  • the first thin film transistor 11, the second thin film transistor 12, and the third thin film transistor 13 may be N-type thin film transistors.
  • the first thin film transistor 11, the second thin film transistor 12, and the third thin film transistor 13 may be P-type thin film transistors.
  • the control line G_N supplies a high level, so that the second thin film transistor 12 and the third thin film transistor 13 are turned on, the data line I_oled provides a signal current, and the signal current passes.
  • the third thin film transistor 13 is turned on, so that the first node 1 and the second node 2 are short-circuited, due to the self-regulation of the first thin film transistor 11,
  • the signal current charges the storage capacitor 15 via the drain and the source of the first thin film transistor 11. Further, the signal current flows through the drain and source of the first thin film transistor 11 to the second power source Vss.
  • the first power source Vdd does not provide a level signal, that is, the first power source Vdd is suspended so that the first power source Vdd, the first thin film transistor 11, the light emitting device 16, and the second power source Vss cannot form a loop, and the light emitting device 16 does not emit light.
  • the control line G_N is supplied with a low level, so that the second thin film transistor 12 and the third thin film transistor 13 are turned off, and the storage capacitor 15 is the first thin due to the charge retention of the storage capacitor 15.
  • the gate of the film transistor 11 is supplied with a high level so that the first thin film transistor 11 remains turned on, and the drain and the source of the first thin film transistor 11 are turned on.
  • the current flowing through the light emitting device 16 is the first thin film transistor.
  • the turn-on current of 11 (ie, the signal current during the write phase).
  • the first power source Vdd supplies a high level, the first power source Vdd, the first thin film transistor 11, the light emitting device 16, and the second power source Vss form a loop, and the light emitting device 16 emits light.
  • the driving sub-circuit of the embodiment of the present disclosure includes only the first thin film transistor, thereby facilitating reduction of power load and power consumption.
  • the circuit structure since only the control line G_N and the data line I_oled, there is no need to add other signal control lines, the circuit structure The wiring is simpler, which simplifies the manufacturing process and improves the yield.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure.
  • the control sub-circuit 10 of the pixel driving circuit of the embodiment shown in FIG. 4 further includes a fourth thin film transistor 14, a fourth film, as compared with the pixel driving circuit of the embodiment shown in FIG.
  • the gate of the transistor 14 is connected to the gate of the second thin film transistor 12 and the gate of the third thin film transistor 13, the source of the fourth thin film transistor 14 is connected to the second node 2, and the drain of the fourth thin film transistor 14 is A power supply Vdd connection.
  • the first thin film transistor 11, the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 may be an N-type thin film transistor or a P-type thin film transistor.
  • the control line G_N is supplied with a high level, so that the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 are turned on, and the fourth thin film transistor is turned on.
  • the data line I_oled provides a signal current
  • the signal current passes through the second thin film transistor 12 and is written to the gate of the first thin film transistor 11, and the third thin film transistor 13 is turned on, thereby Short-circuiting between the node 1 and the second node 2, due to the self-adjusting action of the first thin film transistor 11, and the first power source Vdd is suspended, the signal current charges the storage capacitor 15 via the drain and the source of the first thin film transistor 11; Current can flow into the second power source Vss through the drain and source of the first thin film transistor 11.
  • the control line G_N is supplied with a low level, so that the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 are turned off; the storage capacitor 15 is the first thin film transistor 11 due to the charge retention of the storage capacitor 15.
  • the gate of the first thin film transistor 11 is turned on, and the drain and the source of the first thin film transistor 11 are turned on.
  • the current flowing through the light emitting device 16 is the opening of the first thin film transistor 11.
  • Current ie the signal current during the write phase).
  • the first power source Vdd supplies a high level, the first power source Vdd, the first thin film transistor 11, the light emitting device 16, and the second power source Vss form a loop, and the light emitting device 16 emits light.
  • the driving sub-circuit of the embodiment of the present disclosure includes only the first thin film transistor, thereby reducing the power load and reducing the power consumption.
  • the control line and the data line are needed, no other signal control lines need to be added, and the circuit structure is wired. It is simpler, which simplifies the manufacturing process and improves the yield.
  • control sub-circuit increases the fourth thin film transistor, improves the stability of the circuit, facilitates stable illumination of the light-emitting device, and ensures display brightness uniformity of the display.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure.
  • the control sub-circuit 10 includes the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14.
  • the gate of the second thin film transistor 12, the gate of the third thin film transistor 13 and the gate of the fourth thin film transistor 14 are connected, and the control line G_N is connected, and the drain of the second thin film transistor 12 is connected to the data line I_oled, the second film.
  • the source of the transistor 12 and the drain of the third thin film transistor 13 are connected to the first node 1.
  • the source of the third thin film transistor 13 is connected to the second node 2, and the second node 2 is connected to the first power source Vdd.
  • the drain of the transistor 14 is connected to the third node 3, and the source of the fourth thin film transistor 14 is connected to the second power source Vss.
  • the illuminating sub-circuit 40 includes the illuminating device 16, the anode of the illuminating device 16 is connected to the third node 3, and the cathode of the illuminating device 16 is connected to the second power source Vss.
  • the light emitting device 16 can be an organic light emitting diode.
  • the charging sub-circuit 30 includes a storage capacitor 15, one end of the storage capacitor 15 is connected to the first node 1, and the other end of the storage capacitor 15 is connected to the third node 3.
  • the driving sub circuit 20 includes a first thin film transistor 11.
  • the gate of the first thin film transistor 11 is connected to the first node 1
  • the source of the first thin film transistor 11 is connected to the third node 3
  • the drain of the first thin film transistor 11 is connected to the second node 2.
  • the first thin film transistor 11, the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 may be an N-type thin film transistor or a P-type thin film transistor.
  • the control line G_N is supplied with a high level, so that the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 are turned on, and the fourth thin film transistor is turned on.
  • the data line I_oled provides a signal current
  • the signal current passes through the second thin film transistor 12 and is written to the gate of the first thin film transistor 11, and the third thin film transistor 13 is turned on, thereby Short-circuiting between the node 1 and the second node 2, due to the self-adjusting action of the first thin film transistor 11, and the first power source Vdd is suspended, the signal current charges the storage capacitor 15 via the drain and the source of the first thin film transistor 11; Current can pass through the first film The drain, the source, and the drain and source of the transistor 11 flow into the second power source Vss.
  • the control line G_N is supplied with a low level, so that the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 are turned off; the storage capacitor 15 supplies a high level to the gate of the first thin film transistor 11, so that The first thin film transistor 11 remains turned on, and the drain and the source of the first thin film transistor 11 are turned on.
  • the current flowing through the light emitting device 16 is the turn-on current of the first thin film transistor 11 (ie, the signal current in the writing phase). ).
  • the first power source Vdd supplies a high level, the first power source Vdd, the first thin film crystal 11, the light emitting device 16, and the second power source Vss form a loop, and the light emitting device 16 emits light.
  • the driving sub-circuit of the embodiment of the present disclosure includes only the first thin film transistor, thereby facilitating reduction of power load and power consumption.
  • the circuit structure since only the control line G_N and the data line I_oled, there is no need to add other signal control lines, the circuit structure The wiring is simpler, which simplifies the manufacturing process and improves the yield.
  • the driving sub-circuit increases the fourth thin film transistor, improves the stability of the circuit, facilitates stable illumination of the light-emitting device, and ensures display brightness uniformity of the display.
  • the cathodes of all the light emitting devices on the display panel are commonly connected to the second power source Vss, and the common cathode mode is easier to ensure the product yield in terms of the manufacturing process than the common anode mode.
  • FIG. 6 is a flow chart of steps of a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of signals of a pixel driving circuit according to an embodiment of the present disclosure.
  • the driving method of the pixel circuit of the embodiment of the present disclosure is based on a pixel driving circuit including a control sub-circuit, a charging sub-circuit, a driving sub-circuit, and a light-emitting sub-circuit and a first power source, the driving Methods include:
  • Step 101 controlling, by the control sub-circuit, the driving sub-circuit to charge the charging sub-circuit
  • Step 102 Supply a voltage to the driving sub-circuit through the charging sub-circuit to drive the illuminating sub-circuit to emit light.
  • the pixel driving circuit can be divided into a non-lighting phase (writing phase) and a light emitting phase, and the writing phase is a phase of charging the charging subcircuit.
  • the signal timing of the embodiment of the present disclosure includes a scan signal timing of the control line G_N, a data signal timing of the data line I_oled, and a power signal timing of the first power supply Vdd, and the signal timing can be divided into a write phase and Luminous stage.
  • control sub-circuit 10 of the pixel driving circuit includes a second thin film crystal
  • driving sub-circuit 20 of the pixel driving circuit includes a first thin film transistor
  • the charging sub-circuit 30 of the pixel driving circuit includes a storage capacitor 15.
  • Step 101 may include the following sub-steps:
  • control line provides a high level, so that the second thin film transistor and the third thin film transistor are turned on;
  • the data line provides a signal current
  • the signal current charges the storage capacitor through a gate and a source of the first thin film transistor.
  • control sub-circuit 10 of the pixel driving circuit includes a second thin film transistor 12, a third thin film transistor 13, and a fourth thin film transistor 14, and the driving sub-circuit 20 of the pixel driving circuit includes the A thin film transistor 11, the charging sub-circuit 30 of the pixel driving circuit includes a storage capacitor 15, and step 101 may include the following sub-steps:
  • control line provides a high level, so that the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned on;
  • the data line provides a signal current
  • the signal current charges the storage capacitor through a gate and a source of the first thin film transistor.
  • the first power source Vdd does not provide a level signal, that is, the first power source Vdd is suspended.
  • control sub-circuit 10 of the pixel driving circuit includes a second thin film transistor 12 and a third thin film transistor 13, and the driving sub-circuit 20 of the pixel driving circuit includes a first thin film transistor 11 and a pixel driving circuit.
  • the charging sub-circuit 30 includes a storage capacitor 15, and step 102 can include the following sub-steps:
  • control line provides a low level, so that the second thin film transistor and the third thin film transistor are turned off;
  • the first power source provides a high level to drive the illuminating sub-circuit to emit light.
  • the control line G_N is supplied with a low level, and the second thin film transistor 12 and the third thin film transistor 13 are turned off. Due to the discharge of the storage capacitor 15, the storage capacitor 15 can be The gate of a thin film transistor 11 is supplied with a high level so that the first thin film transistor 11 is kept turned on, the drain and the source of the first thin film transistor 11 are turned on, and the turn-on current thereof flows through the first film in the writing phase.
  • the signal current of the drain and the source of the transistor 11 while the first power source Vdd supplies a high level Vd1, so that the first power source Vdd, the first thin film transistor 11, the light emitting device 16, and the second power source Vss form a loop, thereby driving the light emitting sub-circuit
  • the light emitting device 16 of 40 emits light.
  • control sub-circuit 10 of the pixel driving circuit includes a second thin film transistor 12, a third thin film transistor 13, and a fourth thin film transistor 14, and the driving sub-circuit 20 of the pixel driving circuit includes the A thin film transistor 11, the charging sub-circuit 30 of the pixel driving circuit includes a storage capacitor 15, and step 102 may include the following sub-steps:
  • control line provides a low level, and the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned off;
  • the first power source provides a high level to drive the illuminating sub-circuit to emit light.
  • the control line G_N is supplied with a low level, and the second thin film transistor 12, the third thin film transistor 13, and the fourth thin film transistor 14 are turned off, due to the discharge of the storage capacitor 15,
  • the storage capacitor 15 can supply a high level to the gate of the first thin film transistor 11 so that the first thin film transistor 11 is kept turned on, the drain and the source of the first thin film transistor 11 are turned on, and the turn-on current is written.
  • the signal current flowing through the gate and the source of the first thin film transistor 11 while the first power supply Vdd supplies the high level Vd1, so that the first power supply Vdd, the first thin film transistor 11, the light emitting device 16, and the second power supply Vss form a loop Thereby, the light emitting device 16 that drives the illuminating sub-circuit 40 emits light.
  • the driving sub-circuit of the pixel driving circuit includes only the first thin film transistor, thereby facilitating reduction of power supply load and power consumption reduction; in addition, since only the control line G_N and the data line I_oled, no need to add other signal control lines, circuit structure routing is simpler, which simplifies the manufacturing process and improves the yield, and reduces the timing signal.
  • the cathodes of all of the light emitting devices on the display panel are commonly connected to the second power source Vss, and the common cathode mode is more likely to ensure yield in terms of manufacturing process than the common anode mode.
  • An embodiment of the present disclosure also provides a display device.
  • the display device includes the pixel drive circuit of any of the above.
  • the driving sub-circuit of the pixel driving circuit only includes the first thin film transistor, thereby facilitating reduction of power load and reducing power consumption of the display device; in addition, since only the control line G_N and the data line I_oled, there is no need to add other signal control lines, the circuit
  • the structure trace is simpler, which simplifies the manufacturing process and improves the yield, and reduces the timing signal of the display device.

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Abstract

一种像素驱动电路、显示装置和驱动方法，该像素驱动电路包括控制子电路(10)、充电子电路(30)、驱动子电路(20)和发光子电路(40)；控制子电路(10)与数据线(I_oled)和控制线(G_N)连接，控制子电路(10)通过第一节点(1)、第二节点(2)与驱动子电路(20)连接，充电子电路(30)通过第一节点(1)、第三节点(3)与驱动子电路(20)连接，驱动子电路(20)与发光子电路(40)的一端连接，发光子电路(40)的另一端与第一电源(Vdd)或者第二电源(Vss)连接，驱动子电路(20)包括第一薄膜晶体管(11)，控制子电路(10)用于控制第一薄膜晶体管(11)对充电子电路(30)进行充电，充电子电路(30)用于为驱动子电路(20)提供电压以驱动发光子电路(40)发光。

Description

像素驱动电路、显示装置和驱动方法
本申请要求于2017年05月17日递交的中国专利申请第201710349239.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素驱动电路、显示装置和驱动方法。
背景技术
随着显示技术的进步，越来越多的有源矩阵有机发光二极管AMOLED(Active Matrix Organic Light Emitting Diode)显示面板进入市场，相对于传统的薄膜晶体管液晶显示面板，AMOLED具有更快的反应速度，更高的对比度，更广的视角以及更薄的模组等优点，因此，AMOLED越来越受到面板厂商的重视。
图1示出了一种像素驱动电路的结构，该像素驱动电路包括第一薄膜晶体管51、第二薄膜晶体管52、第三薄膜晶体管53、第四薄膜晶体管54、存储电容55、第一电源Vdd、第二电源Vss、数据线I_oled、控制线G_N和控制信号线S1，该像素驱动电路的工作原理如下：
在写入阶段，控制线G_N为高电平，第二薄膜晶体管52和第三薄膜晶体管53开启，数据线I_oled上的信号电流经由第二薄膜晶体管52和第三薄膜晶体管53写入到第一薄膜晶体管51的栅极，同时信号电流通过第一薄膜晶体管1的源极和漏极对存储电容55充电。由于控制信号线S1为低电平，从而第四薄膜晶体管54关闭，第一电源Vdd与第二电源Vss无法形成回路，因此有机发光二极管(OLED)56不发光。此时，节点A与第一薄膜晶体管51的漏极短接，由于第一薄膜晶体管51的自调节作用，信号电流将通过第一薄膜晶体管51的漏极、源极流入到第二电源Vss。在发光阶段，控制线G_N为低电平，第二薄膜晶体管52和第三薄膜晶体管53关闭，由于存储电容55的电荷保持作用，第一薄膜晶体管51的处于饱和开启状态，控制信号线S1为高电平，第四薄膜晶体管54开启，第一电源Vdd与第二电源Vss形成回路，信号电流被完全复制为驱动信号电流，提供给OLED 56以驱动其发光。
一方面，在发光阶段，第四薄膜晶体管54串联在第一电源Vdd与第二电源Vss形成的回路中，且第四薄膜晶体管54在线性开启时具有电阻R，从而在OLED 56持续发光时，第四薄膜晶体管54消耗的电能为I2R，其中I为信号电流，对于每个OLED像素，都有一个电阻R存在，从而造成整个OLED显示面板功率的损耗。另一方面，OLED显示面板设置有控制信号线S1以控制第四薄膜晶体管54，使得信号线数量增加，造成OLED显示面板走线复杂，生产良率降低。
发明内容
本公开实施例提供一种像素驱动电路、显示装置和驱动方法，以解决现有的像素驱动电路功耗高，OLED显示面板走线复杂，生产良率低的问题。
本公开实施例提供了一种像素驱动电路，其包括：控制子电路、充电子电路、驱动子电路和发光子电路。所述控制子电路与数据线和控制线连接，所述控制子电路通过第一节点、第二节点与所述驱动子电路连接；所述充电子电路通过所述第一节点和第三节点与所述驱动子电路连接；所述发光子电路的一端与所述驱动子电路连接，所述发光子电路的另一端与第一电源或者第二电源连接；所述驱动子电路包括第一薄膜晶体管；所述控制子电路通过所述第一节点和所述第三节点控制所述第一薄膜晶体管对所述充电子电路进行充电，所述充电子电路通过所述第一节点为所述驱动子电路提供电压，所述驱动子电路驱动所述发光子电路发光。
例如，在本公开一实施例提供的像素驱动电路中，所述充电子电路包括存储电容，所述存储电容的一端连接所述第一节点，所述存储电容的另一端连接所述第三节点，所述第三节点连接所述第二电源。
例如，在本公开一实施例提供的像素驱动电路中，所述驱动子电路的第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极与所述第三节点连接；所述第一薄膜晶体管的漏极与所述第二节点连接。
例如，在本公开一实施例提供的像素驱动电路中，所述发光子电路包括发光器件，所述发光器件的阴极与所述第二节点连接，所述发光器件的阳极与所述第一电源连接。
例如，在本公开一实施例提供的像素驱动电路中，所述控制子电路包括：第二薄膜晶体管和第三薄膜晶体管；所述第二薄膜晶体管的栅极和所述第三薄 膜晶体管的栅极相连，并连接所述控制线；所述第二薄膜晶体管的漏极连接所述数据线；所述第二薄膜晶体管的源极、所述第三薄膜晶体管的漏极与所述第一节点连接；所述第三薄膜晶体管的源极与所述第二节点连接。
例如，在本公开一实施例提供的像素驱动电路中，所述控制子电路还包括第四薄膜晶体管，所述第四薄膜晶体管的栅极和所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极相连；所述第四薄膜晶体管的源极与所述第二节点连接，所述第四薄膜晶体管的漏极与所述第一电源连接。
例如，在本公开一实施例提供的像素驱动电路中，所述控制子电路包括第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管；所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极和所述第四薄膜晶体管的栅极相连，并连接所述控制线；所述第二薄膜晶体管的漏极连接所述数据线；所述第二薄膜晶体管的源极、所述第三薄膜晶体管的漏极与所述第一节点连接；所述第三薄膜晶体管的源极与所述第二节点连接；所述第二节点与所述第一电源连接；所述第四薄膜晶体管的漏极与所述第三节点连接，所述第四薄膜晶体管的源极与所述第二电源连接。
例如，在本公开一实施例提供的像素驱动电路中，所述发光子电路包括发光器件，所述发光器件的阳极与所述第三节点连接，所述发光器件的阴极与所述第二电源连接。
本公开实施例还提供了一种显示装置，包括本公开任一实施例提供的像素驱动电路。
本公开实施例还提供了一种像素驱动电路的驱动方法，所述像素驱动电路包括控制子电路、充电子电路、驱动子电路和发光子电路，所述驱动方法包括：通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电；通过所述充电子电路为所述驱动子电路提供电压以驱动所述发光子电路发光。
例如，在本公开一实施例提供的驱动方法中，所述控制子电路包括第二薄膜晶体管和第三薄膜晶体管，所述驱动子电路包括第一薄膜晶体管，所述充电子电路包括存储电容，通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电包括：所述控制线提供高电平，使得所述第二薄膜晶体管和所述第三薄膜晶体管开启；所述数据线提供信号电流，所述信号电流通过所述第一薄膜晶体管的栅极和源极对所述存储电容充电。
例如，在本公开一实施例提供的驱动方法中，通过所述充电子电路为所述 驱动子电路提供电压以驱动所述发光子电路发光包括：所述控制线提供低电平，使得所述第二薄膜晶体管和所述第三薄膜晶体管关闭；通过所述存储电容为所述第一薄膜晶体管的栅极提供高电平，使得所述第一薄膜晶体管开启；所述第一电源提供高电平，以驱动所述发光子电路发光。
例如，在本公开一实施例提供的驱动方法中，所述控制子电路包括第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管，所述驱动子电路包括第一薄膜晶体管，所述充电子电路包括存储电容，通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电包括：所述控制线提供高电平，使得所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管开启；所述数据线提供信号电流，所述信号电流通过所述第一薄膜晶体管的栅极和源极对所述存储电容充电。
例如，在本公开一实施例提供的驱动方法中，通过所述充电子电路为所述驱动子电路提供电压以驱动所述发光子电路发光包括：所述控制线提供低电平，使得所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管关闭；通过所述存储电容为所述第一薄膜晶体管的栅极提供高电平，使得所述第一薄膜晶体管开启；所述第一电源提供高电平，以驱动所述发光子电路发光。
本公开实施例的像素驱动电路包括控制子电路、充电子电路、驱动子电路和发光子电路，控制子电路与数据线和控制线连接，控制子电路通过第一节点、第二节点与驱动子电路连接，充电子电路通过第一节点、第三节点与驱动子电路连接，驱动子电路与发光子电路的一端连接，发光子电路的另一端与第一电源或者第二电源连接，驱动子电路包括第一薄膜晶体管，控制子电路通过第一节点和第三节点控制第一薄膜晶体管对充电子电路进行充电，充电子电路通过第一节点为驱动子电路提供电压，驱动子电路驱动发光子电路发光。本公开实施例的驱动子电路仅包括第一薄膜晶体管，因此有利于减少电源负载、降低功耗；另外，由于只有控制线和数据线，不需要增加其它信号控制线，电路结构走线更加简单，有利简化制造工艺和提高良率。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是一种像素驱动电路的结构示意图；
图2是本公开一实施例提供的一种像素驱动电路的示意图；
图3是本公开一实施例提供的一种像素驱动电路的结构示意图；
图4是本公开另一实施例提供的一种像素驱动电路的结构示意图；
图5是本公开又一实施例提供的一种像素驱动电路的结构示意图；
图6是本公开一实施例提供的一种像素驱动电路的驱动方法的流程图；以及
图7是本公开一实施例提供的一种像素驱动电路的信号时序图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
图2为本公开一实施例提供的一种像素驱动电路的示意图。
例如，如图2所示，本公开实施例的像素驱动电路包括：控制子电路10、充电子电路30、驱动子电路20和发光子电路40，控制子电路10与数据线I_oled和控制线G_N连接，控制子电路10通过第一节点1、第二节点2与驱动子电路20连接，充电子电路30通过第一节点1、第三节点3与驱动子电路20连接，驱动子电路20与发光子电路40的一端连接，发光子电路40的另一端与第一电源Vdd或者第二电源Vss连接，驱动子电路20包括第一薄膜晶体管。
本公开实施例的像素驱动电路的工作原理为：控制子电路10通过第一节点1和第三节点3控制驱动子电路20的第一薄膜晶体管对充电子电路30进行充电，充电子电路30通过第一节点1为驱动子电路20提供电压，驱动子电路 20用于驱动发光子电路40发光。
图3为本公开一实施例提供的像素驱动电路的结构示意图。
例如，如图3所示，在本公开实施例的像素驱动电路中，控制子电路10包括第二薄膜晶体管12和第三薄膜晶体管13，第二薄膜晶体管12的栅极和第三薄膜晶体管13的栅极相连，并连接控制线G_N，第二薄膜晶体管12的漏极连接数据线I_oled，第二薄膜晶体管12的源极、第三薄膜晶体管13的漏极与第一节点1连接，第三薄膜晶体管13的源极与第二节点2连接。
充电子电路30包括存储电容15，存储电容15的一端连接第一节点1，存储电容15的另一端与第三节点3连接，第三节点3与第二电源Vss连接。
驱动子电路20包括第一薄膜晶体管11，第一薄膜晶体管11的栅极与第一节点1连接，第一薄膜晶体管11的源极与第三节点3连接，第一薄膜晶体管11的漏极与第二节点2连接。
发光子电路40包括发光器件16，发光器件16的阴极与第二节点2连接，发光器件16的阳极与第一电源Vdd连接。
例如，发光器件16可以为有机发光二极管。
本公开实施例中，第一电源Vdd相对第二电源Vss为高电平。也就是说，第一电源Vdd的电平比第二电源Vss的电平高。
例如，在本公开实施例中，第一薄膜晶体管11、第二薄膜晶体管12和第三薄膜晶体管13可以为N型薄膜晶体管。但不限于此，第一薄膜晶体管11、第二薄膜晶体管12和第三薄膜晶体管13也可以为P型薄膜晶体管。
例如，在本公开实施例的像素驱动电路中，在写入阶段，控制线G_N提供高电平，使得第二薄膜晶体管12和第三薄膜晶体管13开启，数据线I_oled提供信号电流，信号电流通过第二薄膜晶体管12后写入第一薄膜晶体管11的栅极，第三薄膜晶体管13开启，从而第一节点1与第二节点2之间短接，由于第一薄膜晶体管11的自调节作用，信号电流经由第一薄膜晶体管11漏极和源极对存储电容15充电，此外，信号电流通过第一薄膜晶体管11的漏极、源极流入到第二电源Vss。第一电源Vdd不提供电平信号，即第一电源Vdd悬空，以使得第一电源Vdd、第一薄膜晶体管11、发光器件16和第二电源Vss无法形成回路，发光器件16不发光。
在发光阶段，控制线G_N提供低电平，使得第二薄膜晶体管12和第三薄膜晶体管13关闭，由于存储电容15的电荷保持作用，存储电容15为第一薄 膜晶体管11的栅极提供高电平，使得第一薄膜晶体管11保持开启，第一薄膜晶体管11的漏极和源极导通，此时，流经发光器件16的电流即是第一薄膜晶体管11的开启电流(即写入阶段的信号电流)。第一电源Vdd提供高电平，第一电源Vdd、第一薄膜晶体管11、发光器件16和第二电源Vss形成回路，发光器件16发光。
可见，本公开实施例的驱动子电路仅包括第一薄膜晶体管，因此有利于减少电源负载、降低功耗；另外，由于只有控制线G_N和数据线I_oled，不需要增加其它信号控制线，电路结构走线更加简单，有利简化制造工艺和提高良率。
图4为本公开另一实施例提供的像素驱动电路的结构示意图。
例如，如图4所示，与图3所示的实施例的像素驱动电路相比，图4所示的实施例的像素驱动电路的控制子电路10还包括第四薄膜晶体管14，第四薄膜晶体管14的栅极和第二薄膜晶体管12的栅极、第三薄膜晶体管13的栅极相连，第四薄膜晶体管14的源极与第二节点2连接，第四薄膜晶体管14的漏极与第一电源Vdd连接。
例如，第一薄膜晶体管11、第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14可以为N型薄膜晶体管或P型薄膜晶体管。
例如，在本公开实施例的像素驱动电路中，在写入阶段，控制线G_N提供高电平，使得第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14开启，第四薄膜晶体管14短接发光器件16，发光器件16不发光，数据线I_oled提供信号电流，信号电流通过第二薄膜晶体管12后写入第一薄膜晶体管11的栅极，第三薄膜晶体管13开启，从而第一节点1与第二节点2之间短接，由于第一薄膜晶体管11的自调节作用，且第一电源Vdd悬空，信号电流经由第一薄膜晶体管11漏极和源极对存储电容15充电；信号电流可以通过第一薄膜晶体管11的漏极、源极流入到第二电源Vss。
在发光阶段，控制线G_N提供低电平，使得第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14关闭；由于存储电容15的电荷保持作用，存储电容15为第一薄膜晶体管11的栅极提供高电平，使得第一薄膜晶体管11保持开启，第一薄膜晶体管11的漏极和源极导通，此时，流经发光器件16的电流即是第一薄膜晶体管11的开启电流(即写入阶段的信号电流)。第一电源Vdd提供高电平，第一电源Vdd、第一薄膜晶体管11、发光器件16和第二电源Vss形成回路，发光器件16发光。
可见，本公开实施例的驱动子电路仅包括第一薄膜晶体管，因此有利于减少电源负载、降低功耗；另外，由于只有控制线和数据线，不需要增加其它信号控制线，电路结构走线更加简单，有利简化制造工艺和提高良率。
本公开实施例的像素驱动电路中，控制子电路增加第四薄膜晶体管，提高了电路的稳定性，有利于发光器件稳定发光，保证了显示器的显示亮度均匀性。
图5为本公开又一实施例提供的像素驱动电路的结构示意图。
例如，如图5所示，在本公开实施例的像素驱动电路中，控制子电路10包括第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14。第二薄膜晶体管12的栅极、第三薄膜晶体管13的栅极和第四薄膜晶体管14的栅极相连，并连接控制线G_N，第二薄膜晶体管12的漏极连接数据线I_oled，第二薄膜晶体管12的源极、第三薄膜晶体管13的漏极与第一节点1连接，第三薄膜晶体管13的源极与第二节点2连接，第二节点2与第一电源Vdd连接，第四薄膜晶体管14的漏极与第三节点3连接，第四薄膜晶体管14的源极与第二电源Vss连接。
例如，在本公开实施例中，发光子电路40包括发光器件16，发光器件16的阳极与第三节点3连接，发光器件16的阴极与第二电源Vss连接。
例如，发光器件16可以是有机发光二极管。
例如，在本公开实施例中，充电子电路30包括存储电容15，存储电容15的一端连接第一节点1，存储电容15的另一端连接第三节点3。
驱动子电路20包括第一薄膜晶体管11。第一薄膜晶体管11的栅极与第一节点1连接，第一薄膜晶体管11的源极与第三节点3连接，第一薄膜晶体管11的漏极与第二节点2连接。
例如，第一薄膜晶体管11、第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14可以为N型薄膜晶体管或P型薄膜晶体管。
例如，在本公开实施例的像素驱动电路中，在写入阶段，控制线G_N提供高电平，使得第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14开启，第四薄膜晶体管14短接发光器件16，发光器件16不发光，数据线I_oled提供信号电流，信号电流通过第二薄膜晶体管12后写入第一薄膜晶体管11的栅极，第三薄膜晶体管13开启，从而第一节点1与第二节点2之间短接，由于第一薄膜晶体管11的自调节作用，且第一电源Vdd悬空，信号电流经由第一薄膜晶体管11漏极和源极对存储电容15充电；信号电流可以通过第一薄膜 晶体管11的漏极、源极和第四薄膜晶体管14的漏极、源极流入到第二电源Vss。
在发光阶段，控制线G_N提供低电平，使得第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14关闭；存储电容15为第一薄膜晶体管11的栅极提供高电平，使得第一薄膜晶体管11保持开启，第一薄膜晶体管11的漏极和源极导通，此时，流经发光器件16的电流即是第一薄膜晶体管11的开启电流(即写入阶段的信号电流)。第一电源Vdd提供高电平，第一电源Vdd、第一薄膜晶体11、发光器件16和第二电源Vss形成回路，发光器件16发光。
可见，本公开实施例的驱动子电路仅包括第一薄膜晶体管，因此有利于减少电源负载、降低功耗；另外，由于只有控制线G_N和数据线I_oled，不需要增加其它信号控制线，电路结构走线更加简单，有利简化制造工艺和提高良率。
本公开实施例的像素驱动电路中，驱动子电路增加第四薄膜晶体管，提高了电路的稳定性，有利于发光器件稳定发光，保证了显示器的显示亮度均匀性。
本公开实施例的像素驱动电路中，显示面板上的所有发光器件的阴极均共同连接到第二电源Vss，公共阴极方式比公共阳极方式在制造工艺方面更容易保证产品良率。
图6为本公开一实施例提供的像素驱动电路的驱动方法的步骤流程图。
图7为本公开一实施例提供的像素驱动电路的信号时序图。
例如，如图6所示，本公开实施例的像素电路的驱动方法基于像素驱动电路，该像素驱动电路包括控制子电路、充电子电路、驱动子电路和发光子电路和第一电源，该驱动方法包括：
步骤101，通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电；以及
步骤102，通过所述充电子电路为所述驱动子电路提供电压以驱动所述发光子电路发光。
在实际应用中，像素驱动电路可以分为不发光阶段(写入阶段)和发光阶段，写入阶段为对充电子电路进行充电的阶段。
例如，如图7所示，本公开实施例的信号时序包括控制线G_N的扫描信号时序、数据线I_oled的数据信号时序和第一电源Vdd的电源信号时序，信号时序可以分为写入阶段和发光阶段。
在图3所示的实施例中，像素驱动电路的控制子电路10包括第二薄膜晶 体管12和第三薄膜晶体管13，像素驱动电路的驱动子电路20包括第一薄膜晶体管11，像素驱动电路的充电子电路30包括存储电容15，则步骤101可以包括如下子步骤：
S11，所述控制线提供高电平，使得所述第二薄膜晶体管和第三薄膜晶体管开启；
S12，所述数据线提供信号电流，所述信号电流通过所述第一薄膜晶体管的栅极和源极对所述存储电容充电。
例如，在子步骤S11中，如图7所示，在写入阶段(T1)，当控制线G_N提供高电平时，如图3所示，由于第二薄膜晶体管12和第三薄膜晶体管13的栅极和控制线G_N相连，基于薄膜晶体管的特性，第二薄膜晶体管12和第三薄膜晶体管13开启。
例如，在子步骤S12中，如图7所示，在写入阶段(T1)，当数据线I_oled提供信号电流时，如图3所示，由于第二薄膜晶体管12的漏极与数据线I_oled相连，信号电流通过第二薄膜晶体管12写入第一薄膜晶体管11的栅极，第三薄膜晶体管13开启，从而第一节点1与第二节点2之间短接，由于第一薄膜晶体管11的自调节作用，信号电流经由第一薄膜晶体管11漏极和源极对存储电容15充电。信号电流将通过第一薄膜晶体管11的漏极、源极流入到第二电源Vss。
例如，在子步骤S12中，如图7所示，在写入阶段(T1)，第一电源Vdd可以提供低电平Vd0(例如，Vd0＝0)。需要说明的是，在子步骤S12中，第一电源Vdd也可以不提供电平信号，即第一电源Vdd悬空。
在图4和图5所示的实施例中，像素驱动电路的控制子电路10包括第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14，像素驱动电路的驱动子电路20包括第一薄膜晶体管11，像素驱动电路的充电子电路30包括存储电容15，则步骤101可以包括如下子步骤：
S21，所述控制线提供高电平，使得所述第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管开启；
S22，所述数据线提供信号电流，所述信号电流通过所述第一薄膜晶体管的栅极和源极对所述存储电容充电。
例如，在子步骤S21中，如图7所示，在写入阶段(T1)，当控制线G_N提供高电平时，如图4和图5所示，由于第二薄膜晶体管12、第三薄膜晶体管 13的栅极、第四薄膜晶体管14的栅极和控制线G_N相连，基于薄膜晶体管的特性，第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14开启。
例如，在子步骤S22中，如图7所示，在写入阶段(T1)，当数据线I_oled提供信号电流时，如图4和图5所示，由于第二薄膜晶体管12的漏极与数据线I_oled相连，信号电流通过第二薄膜晶体管12写入第一薄膜晶体管11的栅极，第三薄膜晶体管13开启，从而第一节点1与第二节点2之间短接，由于第一薄膜晶体管11的自调节作用，信号电流经由第一薄膜晶体管11漏极和源极对存储电容15充电。信号电流将通过第一薄膜晶体管11的漏极、源极流入到第三节点3，最终信号电流流入第二电源Vss。
例如，在子步骤S22中，在写入阶段(T1)，第一电源Vdd不提供电平信号，即第一电源Vdd悬空。
在图3所示的实施例中，像素驱动电路的控制子电路10包括第二薄膜晶体管12和第三薄膜晶体管13，像素驱动电路的驱动子电路20包括第一薄膜晶体管11，像素驱动电路的充电子电路30包括存储电容15，则步骤102可以包括如下子步骤：
S31，所述控制线提供低电平，使得所述第二薄膜晶体管和第三薄膜晶体管关闭；
S32，通过所述存储电容为所述第一薄膜晶体管的栅极提供高电平，使得所述第一薄膜晶体管开启；
S33，所述第一电源提供高电平，以驱动所述发光子电路发光。
例如，如图7所示，在发光阶段(T2)，控制线G_N提供低电平，第二薄膜晶体管12和第三薄膜晶体管13关闭，由于存储电容15的放电作用，存储电容15可以为第一薄膜晶体管11的栅极提供高电平，以使得第一薄膜晶体管11保持开启状态，第一薄膜晶体管11的漏极和源极导通，其开启电流即为写入阶段流过第一薄膜晶体管11漏极和源极的信号电流，同时第一电源Vdd提供高电平Vd1，使得第一电源Vdd、第一薄膜晶体管11、发光器件16和第二电源Vss形成回路，从而驱动发光子电路40的发光器件16发光。
在图4和图5所示的实施例中，像素驱动电路的控制子电路10包括第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14，像素驱动电路的驱动子电路20包括第一薄膜晶体管11，像素驱动电路的充电子电路30包括存储电容15，则步骤102可以包括如下子步骤：
S41，所述控制线提供低电平，所述第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管关闭；
S42，通过所述存储电容为所述第一薄膜晶体管的栅极提供高电平，使得所述第一薄膜晶体管开启；
S43，所述第一电源提供高电平，以驱动所述发光子电路发光。
例如，如图7所示，在发光阶段(T2)，控制线G_N提供低电平，第二薄膜晶体管12、第三薄膜晶体管13和第四薄膜晶体管14关闭，由于存储电容15的放电作用，存储电容15可以为第一薄膜晶体管11的栅极提供高电平，以使得第一薄膜晶体管11保持开启状态，第一薄膜晶体管11的漏极和源极导通，其开启电流即为写入阶段流过第一薄膜晶体管11栅极和源极的信号电流，同时第一电源Vdd提供高电平Vd1，使得第一电源Vdd、第一薄膜晶体管11、发光器件16和第二电源Vss形成回路，从而驱动发光子电路40的发光器件16发光。
在本公开实施例的像素驱动电路的驱动方法中，该像素驱动电路的驱动子电路仅包括第一薄膜晶体管，因此有利于减少电源负载、降低功耗；另外，由于只有控制线G_N和数据线I_oled，不需要增加其它信号控制线，电路结构走线更加简单，有利简化制造工艺和提高良率，减少了时序信号。
本公开的一些实施例中，显示面板上所有发光器件的阴极均共同连接到第二电源Vss，公共阴极方式比公共阳极方式在制造工艺方面更容易保证良率。
本公开一实施例还提供了一种显示装置。该显示装置包括上述任一项所述的像素驱动电路。该像素驱动电路的驱动子电路仅包括第一薄膜晶体管，因此有利于减少电源负载、降低显示装置的功耗；另外，由于只有控制线G_N和数据线I_oled，不需要增加其它信号控制线，电路结构走线更加简单，有利简化制造工艺和提高良率，减少了显示装置的时序信号。
对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本公开并不受所描述的动作顺序的限制，因为依据本公开，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本公开所必须的。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即 可。
以上对本公开提供的一种像素驱动电路、显示装置和驱动方法，进行了详细介绍，本文中应用了具体实施例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (14)

  1. 一种像素驱动电路，包括：控制子电路、充电子电路、驱动子电路和发光子电路，其中，
    所述控制子电路与数据线和控制线连接，所述控制子电路通过第一节点、第二节点与所述驱动子电路连接；
    所述充电子电路通过所述第一节点和第三节点与所述驱动子电路连接；
    所述发光子电路的一端与所述驱动子电路连接，所述发光子电路的另一端与第一电源或者第二电源连接；
    所述驱动子电路包括第一薄膜晶体管；
    所述控制子电路通过所述第一节点和所述第三节点控制所述第一薄膜晶体管对所述充电子电路进行充电，所述充电子电路通过所述第一节点为所述驱动子电路提供电压，所述驱动子电路驱动所述发光子电路发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述充电子电路包括存储电容，所述存储电容的一端连接所述第一节点，所述存储电容的另一端连接所述第三节点，所述第三节点连接所述第二电源。
  3. 根据权利要求1或2所述的像素驱动电路，其中，所述驱动子电路的第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极与所述第三节点连接；所述第一薄膜晶体管的漏极与所述第二节点连接。
  4. 根据权利要求1-3任一项所述的像素驱动电路，其中，所述发光子电路包括发光器件，所述发光器件的阴极与所述第二节点连接，所述发光器件的阳极与所述第一电源连接。
  5. 根据权利要求1-4任一项所述的像素驱动电路，其中，所述控制子电路包括：第二薄膜晶体管和第三薄膜晶体管；
    所述第二薄膜晶体管的栅极和所述第三薄膜晶体管的栅极相连，并连接所述控制线；
    所述第二薄膜晶体管的漏极连接所述数据线；
    所述第二薄膜晶体管的源极、所述第三薄膜晶体管的漏极与所述第一节点连接；
    所述第三薄膜晶体管的源极与所述第二节点连接。
  6. 根据权利要求5所述的像素驱动电路，其中，所述控制子电路还包括 第四薄膜晶体管，
    所述第四薄膜晶体管的栅极和所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极相连；
    所述第四薄膜晶体管的源极与所述第二节点连接，所述第四薄膜晶体管的漏极与所述第一电源连接。
  7. 根据权利要求1或3所述的像素驱动电路，其中，所述控制子电路包括第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管；
    所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极和所述第四薄膜晶体管的栅极相连，并连接所述控制线；
    所述第二薄膜晶体管的漏极连接所述数据线；
    所述第二薄膜晶体管的源极、所述第三薄膜晶体管的漏极与所述第一节点连接；
    所述第三薄膜晶体管的源极与所述第二节点连接；
    所述第二节点与所述第一电源连接；
    所述第四薄膜晶体管的漏极与所述第三节点连接，所述第四薄膜晶体管的源极与所述第二电源连接。
  8. 根据权利要求7所述的像素驱动电路，其中，所述发光子电路包括发光器件，所述发光器件的阳极与所述第三节点连接，所述发光器件的阴极与所述第二电源连接。
  9. 一种显示装置，包括如权利要求1至8任一所述的像素驱动电路。
  10. 一种像素驱动电路的驱动方法，其中，所述驱动方法基于像素驱动电路，所述像素驱动电路包括控制子电路、充电子电路、驱动子电路和发光子电路和第一电源，所述驱动方法包括：
    通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电；
    通过所述充电子电路为所述驱动子电路提供电压以驱动所述发光子电路发光。
  11. 根据权利要求10所述的驱动方法，其中，所述控制子电路包括第二薄膜晶体管和第三薄膜晶体管，所述驱动子电路包括第一薄膜晶体管，所述充电子电路包括存储电容，
    通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电包括：
    所述控制线提供高电平，使得所述第二薄膜晶体管和所述第三薄膜晶体管开启；
    所述数据线提供信号电流，所述信号电流通过所述第一薄膜晶体管的栅极和源极对所述存储电容充电。
  12. 根据权利要求11所述的驱动方法，其中，通过所述充电子电路为所述驱动子电路提供电压以驱动所述发光子电路发光包括：
    所述控制线提供低电平，使得所述第二薄膜晶体管和所述第三薄膜晶体管关闭；
    通过所述存储电容为所述第一薄膜晶体管的栅极提供高电平，使得所述第一薄膜晶体管开启；
    所述第一电源提供高电平，以驱动所述发光子电路发光。
  13. 根据权利要求10所述的驱动方法，其中，所述控制子电路包括第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管，所述驱动子电路包括第一薄膜晶体管，所述充电子电路包括存储电容，
    通过所述控制子电路控制所述驱动子电路对所述充电子电路进行充电包括：
    所述控制线提供高电平，使得所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管开启；
    所述数据线提供信号电流，所述信号电流通过所述第一薄膜晶体管的栅极和源极对所述存储电容充电。
  14. 根据权利要求13所述的驱动方法，其中，通过所述充电子电路为所述驱动子电路提供电压以驱动所述发光子电路发光包括：
    所述控制线提供低电平，使得所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管关闭；
    通过所述存储电容为所述第一薄膜晶体管的栅极提供高电平，使得所述第一薄膜晶体管开启；
    所述第一电源提供高电平，以驱动所述发光子电路发光。
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