WO2018203181A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- WO2018203181A1 WO2018203181A1 PCT/IB2018/052825 IB2018052825W WO2018203181A1 WO 2018203181 A1 WO2018203181 A1 WO 2018203181A1 IB 2018052825 W IB2018052825 W IB 2018052825W WO 2018203181 A1 WO2018203181 A1 WO 2018203181A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductor
- insulator
- transistor
- oxide
- semiconductor device
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 314
- 239000004020 conductor Substances 0.000 claims abstract description 962
- 239000012212 insulator Substances 0.000 claims abstract description 784
- 229910044991 metal oxide Inorganic materials 0.000 claims description 116
- 150000004706 metal oxides Chemical class 0.000 claims description 106
- 230000010354 integration Effects 0.000 abstract description 3
- 230000006870 function Effects 0.000 description 220
- 238000000034 method Methods 0.000 description 188
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- 239000001301 oxygen Substances 0.000 description 127
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- 239000001257 hydrogen Substances 0.000 description 90
- 239000000463 material Substances 0.000 description 90
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- 239000010937 tungsten Substances 0.000 description 50
- 239000012535 impurity Substances 0.000 description 49
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 48
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Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- One embodiment of the present invention relates to a semiconductor device.
- a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
- a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
- a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may have a semiconductor device. .
- one embodiment of the present invention is not limited to the above technical field.
- One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
- one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
- a technology for forming a transistor using a semiconductor thin film has attracted attention.
- the transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device).
- IC integrated circuit
- image display device also simply referred to as a display device.
- a silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.
- Patent Documents 1 and 2 For example, a technique for manufacturing a display device using a transistor including zinc oxide or an In—Ga—Zn oxide in a channel formation region as an oxide semiconductor is disclosed (see Patent Documents 1 and 2). ).
- Patent Document 3 a technique for manufacturing an integrated circuit of a memory device using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3).
- arithmetic devices and the like have been manufactured using transistors including oxide semiconductors.
- transistors are becoming smaller in size.
- process rules for manufacturing transistors are also decreasing year by year, such as 45 nm, 32 nm, and 22 nm. Accordingly, a transistor including an oxide semiconductor is required to have a fine structure and good electrical characteristics as designed.
- An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device in which variation in electrical characteristics in a substrate surface is small. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. Another object of one embodiment of the present invention is to provide a highly productive semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.
- One embodiment of the present invention includes a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, the first conductor, And an oxide having a region in contact with a side surface of the second conductor, a second insulator on the oxide, and a third conductor on the second insulator,
- the second insulator has a region facing the side surfaces of the first conductor, the first insulator, and the second conductor through the oxide
- the third conductor includes the oxide
- the semiconductor device includes a first conductor, a first insulator, and a region facing a side surface of the second conductor via a second insulator.
- the first conductor, the first insulator, and the second conductor are covered with a third insulator, and the third insulator has an opening, an oxide, The second insulator and the third conductor may be formed so as to fill the opening.
- the oxide has a region in contact with the upper surface of the second conductor, and the second insulator has a region overlapping with the upper surface of the second conductor through the oxide.
- the third conductor may have a region overlapping with the upper surface of the second conductor with the oxide and the second insulator interposed therebetween.
- the film thickness of the first insulator may be 1 nm or more and 100 nm or less.
- the oxide may contain a metal oxide.
- a semiconductor device that can be miniaturized or highly integrated can be provided.
- a semiconductor device having favorable electrical characteristics can be provided.
- a semiconductor device with low off-state current can be provided.
- a semiconductor device with high on-state current can be provided.
- a semiconductor device in which variation in electric characteristics in a substrate surface is small can be provided.
- a highly reliable semiconductor device can be provided.
- a semiconductor device with reduced power consumption can be provided.
- a semiconductor device with high design freedom can be provided.
- a highly productive semiconductor device can be provided.
- a novel semiconductor device can be provided.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a structure example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
- 4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
- 6A and 6B are a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention and a timing chart illustrating an operation example of the semiconductor device.
- 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention.
- FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention.
- 10A and 10B are a flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component.
- FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
- the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.
- the drawing schematically shows an ideal example, and is not limited to the shape or value shown in the drawing.
- a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding.
- the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.
- the hatch pattern is the same, and there is a case where no reference numeral is given.
- a top view also referred to as a “plan view”
- a perspective view a perspective view, and the like
- some components may be omitted in order to facilitate understanding of the invention.
- description of some hidden lines may be omitted.
- the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
- the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
- parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
- substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
- Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
- substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
- a transistor is an element having at least three terminals including a gate, a drain, and a source.
- a channel formation region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and between the source and the drain through the channel formation region. It is possible to pass a current through.
- a channel formation region refers to a region through which a current mainly flows.
- the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
- the channel length in a transistor means, for example, a source (in a region where a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed) A distance between a source region or source electrode) and a drain (drain region or drain electrode).
- the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
- a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as the composition, and a silicon nitride oxide film has a nitrogen content as compared to oxygen as a composition. Refers to membranes with a lot of
- a metal oxide is a metal oxide in a broad expression.
- Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
- oxide semiconductors also referred to as oxide semiconductors or simply OS.
- the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short.
- OS FET or an OS transistor it can be said to be a transistor including a metal oxide or an oxide semiconductor.
- metal oxides having nitrogen may be collectively referred to as metal oxides.
- a metal oxide containing nitrogen may be referred to as a metal oxynitride.
- CAAC C-Axis Aligned Crystal
- CAC Cloud-Aligned Composite
- a CAC-OS or a CAC-metal oxide has a conductive function in part of a material, an insulating function in part of the material, and a semiconductor in the whole material.
- the conductive function is a function of flowing electrons (or holes) serving as carriers
- the insulating function is This is a function of preventing electrons (or holes) from flowing.
- a function of switching (a function of turning on / off) can be imparted to the CAC-OS or the CAC-metal oxide by causing the conductive function and the insulating function to act complementarily.
- CAC-OS or CAC-metal oxide includes a conductive region and an insulating region.
- the conductive region has the above-described conductive function
- the insulating region has the above-described insulating function.
- the conductive region and the insulating region may be separated at the nanoparticle level.
- the conductive region and the insulating region may be unevenly distributed in the material, respectively.
- the conductive region may be observed with the periphery blurred and connected in a cloud shape.
- the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
- CAC-OS or CAC-metal oxide is composed of components having different band gaps.
- CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
- the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
- the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
- CAC-OS or CAC-metal oxide can also be called a matrix composite (metal matrix composite) or a metal matrix composite (metal matrix composite).
- film and “layer” can be interchanged.
- conductive layer may be changed to the term “conductive film”.
- insulating film may be changed to the term “insulating layer”.
- the term “insulator” can be referred to as an insulating film or an insulating layer.
- the term “conductor” can be referred to as a conductive film or a conductive layer.
- the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
- the transistors described in this specification and the like are field-effect transistors unless otherwise specified.
- the transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.
- FIG. 1A is a top view of a semiconductor device having a transistor 10.
- FIG. 1B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG.
- FIG. 1C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG.
- the portion indicated by the one-dot chain line of A1-A2 and the portion indicated by the one-dot chain line of A3-A4 are orthogonal to each other.
- some elements are omitted for clarity.
- the semiconductor device of one embodiment of the present invention includes a transistor 10 and an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as an interlayer film over a substrate (not illustrated). 176, an insulator 178, and an insulator 180.
- the conductor 185 and the conductor 200 which are electrically connected to the transistor 10 and function as wirings, and the conductor 190 and the conductor 195 which function as plugs are included.
- the conductor 185 is formed in an opening provided in the insulator 105.
- the height of the upper surface of the conductor 185 and the height of the upper surface of the insulator 105 are preferably approximately the same.
- the conductor 185 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto.
- the conductor 185 may have a stacked structure of two or more layers.
- the conductor 190 is formed in an opening provided in the insulator 110.
- the bottom surface of the conductor 190 is provided so as to have a region in contact with the top surface of the conductor 185.
- the height of the upper surface of the conductor 190 and the height of the upper surface of the insulator 110 are preferably approximately the same.
- the conductor 190 is illustrated as a single layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto.
- the conductor 190 is in contact with the inner wall of the opening provided in the insulator 110 to form a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen, and the conductor 190 is formed over the conductor.
- a laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed may be used.
- the conductor 195 is formed in an opening reaching the upper surface of the conductor 140 provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180.
- the height of the upper surface of the conductor 195 and the height of the upper surface of the insulator 180 are preferably approximately the same.
- the conductor 195 is illustrated as a single layer structure; however, one embodiment of the present invention is not limited thereto, for example, the conductor 195 includes an insulator 175, an insulator 176, and an insulator.
- a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen is formed in contact with the inner wall of the opening provided in the body 178 and the insulator 180, and the conductor is formed on the conductor. It may be a laminated structure of two or more layers in which a conductor made of a material having higher conductivity is formed.
- the conductor 200 is formed on the insulator 180 so as to have a region in contact with the upper surface of the conductor 195. Note that although the conductor 200 is illustrated as a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto. For example, the conductor 200 may have a stacked structure of two or more layers.
- the transistor 10 includes a conductor 120 and an oxide 150 which are disposed over the insulator 110, an insulator 130 which is disposed over the conductor 120, and the insulator 130. It has a conductor 140 disposed on top, an insulator 160 disposed on the oxide 150, and a conductor 170 disposed on the insulator 160.
- the oxide 150 is provided so as to have a region in contact with the side surfaces of the conductor 120, the insulator 130, and the conductor 140.
- the insulator 160 is provided to have a region facing the side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 interposed therebetween.
- the conductor 170 is provided so as to have a region facing the side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 and the insulator 160 interposed therebetween.
- an insulator 175 is provided on the conductor 120, the insulator 130, and the conductor 140 so as to cover them.
- the insulator 175 is provided with an opening in which the side surface of the conductor 120, the insulator 130, and the conductor 140 partially overlaps with the inner wall, and the oxide 150 is provided along the inner wall of the opening.
- An insulator 160 is provided above, and a conductor 170 is provided on the insulator 160 so as to embed the opening.
- the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175.
- FIG. 1B illustrates the oxide 150 as a single layer structure, one embodiment of the present invention is not limited thereto.
- the oxide 150 may have a stacked structure including two or more layers.
- the conductor 120 functions as one of a source electrode and a drain electrode
- the conductor 140 functions as the other of the source electrode and the drain electrode.
- the overlapping region has a function as a channel formation region
- the insulator 160 has a function as a gate insulator
- the conductor 170 has a function as a gate electrode.
- the transistor 10 includes the conductive layer functioning as one of the source electrode and the drain electrode (conductor 120) and the insulating layer having a region in contact with the oxide functioning as a channel formation region ( The insulator 130) and a conductive layer (conductor 140) functioning as the other of the source electrode and the drain electrode are stacked in order from the bottom. That is, in the transistor 10, the direction (channel length direction) in which carriers (electrons or holes) flow is substantially perpendicular to the substrate surface. With the transistor 10 having this structure, the channel length of the transistor 10 is defined by the thickness of the insulator 130 sandwiched between the source electrode and the drain electrode.
- the channel length of the transistor 10 can be controlled by the film thickness when the insulator 130 is formed.
- the channel length of the transistor 10 can be arbitrarily controlled in the range of 1 nm to 100 nm. Therefore, a plurality of fine transistors can be manufactured with higher accuracy in the substrate surface than in the case where the channel length is formed by a lithography method or the like.
- the oxide 150 having a function as a channel formation region is preferably a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor).
- a transistor in which a metal oxide is used for a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, so that a semiconductor device with low power consumption can be provided.
- a metal oxide can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
- a transistor using a metal oxide for a channel formation region electrical characteristics are likely to fluctuate due to impurities or oxygen vacancies in the metal oxide, and reliability may deteriorate.
- hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed.
- oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor in which a metal oxide containing oxygen vacancies is used for a channel formation region is likely to be normally on. For this reason, it is preferable that the oxygen deficiency in a metal oxide is reduced as much as possible.
- the insulator 160 in contact with the oxide 150 preferably contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition.
- excess oxygen included in the insulator 160 diffuses into the channel formation region included in the oxide 150, whereby oxygen vacancies in the channel formation region can be reduced.
- the transistor 10 is preferably covered with an insulator having a barrier property to prevent entry of impurities such as water or hydrogen.
- An insulator having a barrier property is a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. (The above impurities are difficult to transmit.)
- An insulator using an insulating material it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
- the transistor 10 is provided over the insulator 102 having a barrier property. Further, an insulator 178 having a barrier property is provided over the transistor 10. With the structure in which the insulator 102 and the insulator 178 are arranged above and below the transistor 10, the transistor 10 can be sandwiched between insulators having a barrier property. With this structure, impurities such as hydrogen and water can be prevented from entering the transistor 10 from the lower layer of the insulator 102 and the upper layer of the insulator 178. Alternatively, diffusion of oxygen contained in the insulator 130 and the insulator 160 to the lower layer of the insulator 102 and the upper layer of the insulator 178 can be suppressed. Accordingly, oxygen contained in the insulator 130 and the insulator 160 can be efficiently supplied to the channel formation region included in the oxide 150.
- the insulator 102 and the insulator 178 preferably function as barrier films that prevent impurities such as water or hydrogen from entering the transistor 10 from the outside of the insulator. Therefore, the insulator 102 and the insulator 178 suppress diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom. It is preferable to use an insulating material having a function of preventing the above impurities from being transmitted. Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits).
- oxygen for example, oxygen atoms and oxygen molecules
- the insulator 102 and the insulator 178 it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 102 and the insulator 178.
- impurities such as hydrogen and water can be prevented from diffusing inside (on the transistor 10 side) from the insulator.
- oxygen contained in the insulator 130 or the like can be prevented from diffusing outside the insulator 102 and the insulator 178.
- an insulator such as aluminum oxide, hafnium oxide, or silicon nitride can be used in a single layer or a stacked layer.
- the insulator 100, the insulator 105, the insulator 110, the insulator 175, the insulator 176, and the insulator 180 functioning as interlayer films preferably have a lower dielectric constant than the insulator 102 and the insulator 178.
- parasitic capacitance generated between wirings can be reduced.
- PZT lead zirconate titanate
- SrTiO 3 strontium titanate
- BST Ba, Sr TiO 3
- the concentration of impurities such as hydrogen and water in the film is preferably reduced as much as possible.
- the insulator 130 physically and electrically separates the conductor 120 functioning as one of the source electrode and the drain electrode from the conductor 140 functioning as the other of the source electrode and the drain electrode. It has a function.
- the thickness of the insulator 130 is preferably greater than or equal to 1 nm and less than or equal to 100 nm.
- the side surface of the insulator 130 is in contact with the channel formation region of the transistor 10 included in the oxide 150. Therefore, the insulator 130 is preferably formed using an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region is formed in the insulator 130. By providing such an insulator containing excess oxygen in contact with the oxide 150, oxygen vacancies in the channel formation region of the oxide 150 can be reduced and the reliability of the transistor 10 can be improved.
- an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
- the oxide from which oxygen is released by heating is an oxygen desorption amount of 1.0 ⁇ 10 14 atoms / cm 2 or more, preferably 3 or more in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis.
- the oxide film has a thickness of 0.0 ⁇ 10 15 atoms / cm 2 or more.
- the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.
- the insulator 130 preferably contains as much oxygen as possible, but preferably does not contain hydrogen or water as much as possible. This is because, for the transistor 10, hydrogen, water, or the like can be a factor that fluctuates electrical characteristics. Therefore, the concentration of hydrogen, water, or the like that can be an impurity for the transistor 10 is reduced as much as possible not only in the oxide 150 functioning as a channel formation region but also in the insulator 130 in contact with the oxide 150. preferable.
- a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
- an oxide semiconductor one having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.
- the oxide 150 may have a stacked structure of two or more layers using oxides having different atomic ratios of metal atoms.
- the metal oxide used for the oxide 150b includes The atomic ratio of the element M is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 150a.
- the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 150a.
- the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 150b.
- the oxide 150a mainly functions as a channel formation region of the transistor 10.
- defect levels are more likely to be formed at the interface between the insulator 160 made of a different material and the oxide 150b than at the interface between the oxide 150a and the oxide 150b made of materials having similar compositions.
- the defect level can be a trap level that causes fluctuations in electrical characteristics of the transistor 10 or deterioration of reliability.
- the defect level is changed to the oxide 150a by including the oxide 150b over the oxide 150a. Can be separated from.
- the transistor 10 can provide good electrical characteristics and reliability.
- the oxide 150b over the oxide 150a, it is possible to suppress the diffusion of impurities from above the oxide 150b into the channel formation region included in the oxide 150a.
- a transistor using a metal oxide for a channel formation region has a very small leakage current in a non-conduction state, and thus can provide a semiconductor device with low power consumption.
- a metal oxide can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
- the oxide 150 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) It is preferable to use a metal oxide such as one or more selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 150, an In—Ga oxide or an In—Zn oxide may be used as the oxide 150.
- the conductor 120 and the conductor 140 have a function as a source electrode or a drain electrode of the transistor 10. As shown in FIGS. 1B and 1C, the conductor 120 and the conductor 140 are provided above and below with the insulator 130 interposed therebetween.
- a conductor such as tantalum nitride, tungsten, or titanium nitride can be used. Note that in FIG. 1, the conductor 120 and the conductor 140 are illustrated as a single layer structure, but may be a stacked structure including two or more layers.
- a metal such as tungsten is used for the first layer (second layer) of the conductor 120 (conductor 140), and the conductor 120 (conductor)
- a conductor having a function of suppressing permeation of oxygen such as titanium nitride or tantalum nitride, may be used for the second layer (first layer) 140).
- an insulator having a function of suppressing permeation of oxygen such as aluminum oxide may be formed over the conductor 120 (under the conductor 140).
- a conductor such as tantalum nitride, tungsten, or titanium nitride may be used as the conductor 120 and the conductor 140, and an insulator such as aluminum oxide may be stacked over the conductor 120 (under the conductor 140).
- aluminum oxide having excess oxygen can be formed.
- the excess oxygen can be supplied to the insulator 130.
- oxygen supplied to the insulator 130 may be supplied to the oxide 150 in some cases.
- the conductor 120 or the conductor 140 may react with the oxide 150.
- a region in which carriers are increased due to n-type formation may be formed at the interface between the oxide 150 and the conductor 120 or the conductor 140. This region may contribute to increasing the drain current of the transistor 10.
- the insulator 160 functions as a gate insulator of the transistor 10.
- the insulator 160 is preferably disposed in contact with the upper surface of the oxide 150.
- the insulator 160 is preferably formed using an insulator from which oxygen is released by heating.
- the insulator 160 has an oxygen desorption amount of 1.0 ⁇ 10 14 atoms / cm 2 or more, preferably 3 in terms of oxygen atom in temperature-programmed desorption gas spectroscopy analysis (TDS analysis). It is preferable that the oxide film be 0.0 ⁇ 10 15 atoms / cm 2 or more.
- the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.
- the insulator 160 By providing an insulator from which oxygen is released by heating as the insulator 160 in contact with the upper surface of the oxide 150, oxygen can be efficiently supplied to the channel formation region of the oxide 150. Similarly to the insulator 130, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 160 be reduced.
- the thickness of the insulator 160 is preferably greater than or equal to 1 nm and less than or equal to 20 nm. Note that in FIG. 1, the insulator 160 is illustrated as a single layer structure, but a stacked structure including two or more layers may be used.
- the conductor 170 has a function as a gate electrode of the transistor 10.
- a metal such as tungsten can be used. Note that in FIG. 1, the conductor 170 is shown as a single layer structure, but a laminated structure of two or more layers may be used.
- the conductor 170 has a three-layer structure
- a conductive oxide is used for the first layer of the conductor 170
- titanium nitride is used for the second layer of the conductor 170
- the third layer of the conductor 170 is used. It is preferable to use a metal such as tungsten.
- the first layer of the conductor 170 is disposed along the upper surface of the insulator 160
- the second layer of the conductor 170 is the conductor 170.
- the third layer of the conductor 170 is disposed along the upper surface of the first layer so as to fill the remaining space where the conductor 170 is provided.
- the height of the top surface of the first layer of the conductor 170, the second layer of the conductor 170, and the third layer of the conductor 170 is preferably approximately the same as the height of the top surface of the insulator 175.
- Examples of the conductive oxide that can be used for the first layer of the conductor 170 include a metal oxide that can be used as the oxide 150.
- oxygen is less mixed from the lower side of the first layer of the conductor 170 into the second layer and the third layer of the conductor 170. Therefore, it is possible to suppress an increase in the electric resistance value of the second layer and the third layer of the conductor 170.
- the conductive oxide that can be used for the first layer of the conductor 170 is formed by a sputtering method, whereby oxygen is added to the insulator 160 and oxygen is supplied to the oxide 150. Is possible. Accordingly, oxygen vacancies in the channel formation region included in the oxide 150 can be reduced.
- a metal nitride such as titanium nitride can be used for the second layer of the conductor 170.
- an impurity such as nitrogen may be added to the first layer of the conductor 170 to improve the conductivity of the first layer of the conductor 170.
- a metal such as tungsten can be used for the third layer of the conductor 170. By using a low resistivity material such as tungsten, the electrical resistance value of the conductor 170 can be reduced.
- the conductor 170 has a two-layer structure
- a structure in which a metal nitride such as titanium nitride is stacked on the first layer and a metal such as tungsten is stacked on the second layer may be used.
- an insulator having a function of suppressing oxygen permeation may be formed between the insulator 175 and the insulator 176.
- an insulator such as aluminum oxide may be formed as the insulator.
- the conductor 170 functioning as a gate electrode includes an opening provided in the insulator 175 so that the conductor 120, the insulator 130, and the conductor 140 have regions that partially overlap with side surfaces of the conductor 120. 150 and the insulator 160 (see FIGS. 1A and 1B).
- the smaller the gate electrode formation size the higher the alignment accuracy of the mask is required.
- the mask for forming the gate electrode the mask No alignment is required. Therefore, a fine gate electrode can be formed with high accuracy compared to the case where a mask is used for forming the gate electrode, and the productivity is excellent.
- the conductor 120 has a function as one of the source electrode and the drain electrode
- the conductor 140 has a function as the other of the source electrode and the drain electrode.
- the region overlapping with the insulator 130 of 150 has a function as a channel formation region
- the insulator 160 has a function as a gate insulator
- the conductor 170 has a function as a gate electrode. Therefore, in the transistor 10, the length of the oxide 150 in the region in contact with the insulator 130 sandwiched between the conductor 120 and the conductor 140 (that is, the thickness of the insulator 130) is equal to the channel length of the transistor 10. Equivalent to.
- the channel length can be controlled by the film thickness at the time of the formation of the insulator 130, and the channel length can be fined to several nm or less, which is difficult to manufacture by the lithography method.
- the channel length can be controlled by the film thickness at the time of film formation of the insulator 130, the accuracy of resist dimension variation and the like as in the case of forming the channel length by a lithography method is not required, and the element on the substrate surface can be easily obtained. It is possible to suppress variations in processing.
- the transistor 10 according to one embodiment of the present invention is a transistor with a high degree of design freedom, and a plurality of transistors with a small channel length can be manufactured with high accuracy in a substrate plane.
- a plurality of transistors with small processing variations can be manufactured in the substrate surface, variation in electrical characteristics between elements can be reduced as compared with a case where a channel length is formed by a lithography method.
- the transistor 10 includes the conductor 120 and the conductor 140 functioning as a source electrode or a drain electrode provided above and below with the insulator 130 interposed therebetween. It has a feature in that. A structure in which a conductor having a function as a source electrode and a conductor having a function as a drain electrode are stacked in a direction perpendicular to the substrate surface as described above with the insulator 130 interposed therebetween. The area occupied by the conductor having a function as a source electrode or a drain electrode in the substrate surface can be reduced. Thereby, miniaturization of each transistor 10 can be achieved. In addition, since each transistor 10 can be miniaturized, a semiconductor device including the transistor 10 can be highly integrated.
- a conductor which is one of a source electrode and a drain electrode, an insulator, and a conductor which is the other of the source electrode and the drain electrode are sequentially formed.
- the “type transistor structure” a plurality of transistors having extremely fine channel lengths can be manufactured with high accuracy and ease.
- a transistor with small variation in electrical characteristics between elements can be manufactured in the substrate plane.
- the transistor can be miniaturized.
- high integration of a semiconductor device including the transistor can be achieved.
- the transistor 10 according to one embodiment of the present invention a metal oxide can be used for the oxide 150 having a channel formation region. Therefore, for example, a short channel effect is less likely to occur compared to a transistor using Si in a channel formation region, and off-state current can be significantly reduced. That is, the transistor 10 according to one embodiment of the present invention can have favorable electrical characteristics even when miniaturization is advanced. Note that details of the metal oxide will be described later in ⁇ Components of Semiconductor Device>.
- the conductor 190 includes a conductor 120 (conductor 140) that functions as one (the other) of the source electrode and the drain electrode of the transistor 10 and a conductor 185 (conductor) that functions as a wiring. 200) has a function as a plug to be connected.
- the conductor 190 (conductor 195) is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
- the conductor 190 (conductor 195) may have a stacked structure, for example, provided in the insulator 110 (insulator 175, insulator 176, insulator 178, and insulator 180).
- a structure may be adopted in which titanium, titanium nitride, or the like is formed in contact with the inner wall of the opening and the upper surface (bottom surface) of the conductor 185 (conductor 200), and the above-described conductive material is provided on the inside.
- the conductor 190 (conductor 195) has a stacked structure, an inner wall of an opening provided in the insulator 110 (insulator 175, insulator 176, insulator 178, and insulator 180), and a conductor 185 ( As the conductor in contact with the upper surface (bottom surface) of the conductor 200), it is preferable to use a conductive material having a function of suppressing permeation of impurities such as hydrogen and water.
- a conductive material having a function of suppressing permeation of impurities such as hydrogen and water.
- tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used.
- a conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer.
- impurities such as hydrogen and water from the lower layer (upper layer) than the insulator 110 (insulator 180) are prevented from entering the oxide 150 through the conductor 190 (conductor 195). be able to.
- the conductor 185 (conductor 200) having a function as a wiring
- a conductive material mainly containing tungsten, copper, or aluminum is preferably used.
- the conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material.
- a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and ease over a substrate. Can do.
- a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane.
- a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured.
- a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured.
- the fine transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated.
- the semiconductor device can be manufactured with high yield.
- FIG. 2A is a top view of the semiconductor device having the transistor 11.
- FIG. 2B is a cross-sectional view taken along the dashed-dotted line B1-B2 in FIG.
- FIG. 2C is a cross-sectional view taken along the dashed-dotted line B3-B4 in FIG.
- the part shown with the dashed-dotted line of B1-B2 and the part shown with the dashed-dotted line of B3-B4 are mutually orthogonal.
- some elements are omitted for clarity.
- the structure having the same function as the structure of the semiconductor device illustrated in ⁇ Structure Example 1 of Semiconductor Device> is denoted by the same reference numeral.
- portions different from the semiconductor device described in ⁇ Semiconductor device configuration example 1> will be mainly described, and for other portions, the contents described in ⁇ semiconductor device configuration example 1> are referred to. It shall be possible.
- the semiconductor device illustrated in FIGS. 2A and 2B functions as a conductor that functions as a source electrode or a drain electrode, and a plug that connects the conductor and the upper and lower wirings.
- the semiconductor device described in ⁇ Structure Example 1 of Semiconductor Device> is that a conductor or the like includes the transistor 11 provided so as to face the oxide 150, the insulator 160, and the conductor 170. (See FIG. 1).
- the semiconductor device of one embodiment of the present invention includes a transistor 11 and an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as an interlayer film over a substrate (not illustrated). 176, an insulator 178, and an insulator 180. Further, the conductor 185_1, the conductor 185_2, the conductor 200_1, and the conductor 200_2 that are electrically connected to the transistor 11 and function as wirings, and the conductor 190_1, the conductor 190_2, the conductor 195_1, which function as plugs, and A conductor 195_2 is included.
- the conductor 185_1 and the conductor 185_2, the conductor 190_1 and the conductor 190_2, the conductor 195_1 and the conductor 195_2, and the conductor 200_1 and the conductor 200_2 are the oxide 150, the insulator 160, and the conductor. 170 are provided opposite to each other with reference to 170 (see FIG. 2B).
- the conductor 185_1 (conductor 185_2) is formed in an opening provided in the insulator 105.
- the height of the upper surface of the conductor 185_1 (conductor 185_2) and the height of the upper surface of the insulator 105 are preferably approximately the same.
- the conductor 185_1 (conductor 185_2) is illustrated as a single-layer structure; however, one embodiment of the present invention is not limited thereto.
- the conductor 185_1 (conductor 185_2) may have a stacked structure of two or more layers.
- the conductor 190_1 (conductor 190_2) is formed in an opening provided in the insulator 110.
- the bottom surface of the conductor 190_1 (conductor 190_2) is provided to have a region in contact with the top surface of the conductor 185_1 (conductor 185_2).
- the height of the upper surface of the conductor 190_1 (conductor 190_2) and the height of the upper surface of the insulator 110 are preferably approximately the same. Note that although FIG. 2B illustrates the conductor 190_1 (conductor 190_2) as a single-layer structure, one embodiment of the present invention is not limited thereto.
- the conductor 190_1 (conductor 190_2) is in contact with the inner wall of the opening provided in the insulator 110 and forms a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen.
- a laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed on the conductor may be used.
- the conductor 195_1 (conductor 195_2) is formed in an opening reaching the upper surface of the insulator 175, the insulator 176, the insulator 178, and the conductor 140_1 (conductor 140_2) provided in the insulator 180.
- the height of the upper surface of the conductor 195_1 (conductor 195_2) and the height of the upper surface of the insulator 180 are preferably approximately the same. Note that in FIG.
- the conductor 195_1 (conductor 195_2) is illustrated as a single-layer structure; however, one embodiment of the present invention is not limited thereto, for example, the conductor 195_1 (conductor 195_2)
- a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen is formed in contact with the inner wall of the opening provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180.
- a stacked structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed on the conductor may be used.
- the conductor 200_1 (conductor 200_2) is formed over the insulator 180 so as to have a region in contact with the upper surface of the conductor 195_1 (conductor 195_2).
- the conductor 200_1 (conductor 200_2) is illustrated as a single-layer structure; however, one embodiment of the present invention is not limited thereto.
- the conductor 200_1 (conductor 200_2) may have a stacked structure of two or more layers.
- the transistor 11 includes a conductor 120_1, a conductor 120_2, and an oxide 150 which are disposed over the insulator 110, and an insulator 130_1 which is disposed over the conductor 120_1.
- the insulator 130_2 disposed over the conductor 120_2, the conductor 140_1 disposed over the insulator 130_1, the conductor 140_2 disposed over the insulator 130_2, and the oxide 150 And a conductor 170 disposed on the insulator 160.
- the conductor 120_1, the insulator 130_1, and the conductor 140_1 are opposite to the conductor 120_2, the insulator 130_2, and the conductor 140_2 with the oxide 150, the insulator 160, and the conductor 170 interposed therebetween.
- the oxide 150 is provided so as to have regions in contact with side surfaces of the conductor 120_1, the insulator 130_1, and the conductor 140_1 and the conductor 120_2, the insulator 130_2, and the conductor 140_2 that face each other.
- the insulator 160 includes a region facing the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) with the oxide 150 interposed therebetween.
- the conductor 170 is a region facing the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) through the oxide 150 and the insulator 160. Is provided.
- the conductor 120_1, the conductor 120_2, the insulator 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2 are covered so as to cover them.
- An insulator 175 is provided.
- the insulator 175 is provided with an opening in which the side surface of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) overlap with part of the inner wall.
- An oxide 150 is provided along the inner wall, an insulator 160 is provided on the oxide 150, and a conductor 170 is provided on the insulator 160 so as to fill the opening.
- the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175.
- FIG. 2B illustrates the oxide 150 as a single-layer structure, one embodiment of the present invention is not limited thereto.
- the oxide 150 may have a stacked structure including two or more layers.
- the conductor 120_1 functions as one of the source electrode and the drain electrode
- the conductor 140_1 functions as the other of the source electrode and the drain electrode
- the insulator 130_1 of the oxide 150 The overlapping region has a function as a channel formation region
- the insulator 160 has a function as a gate insulator
- the conductor 170 has a function as a gate electrode.
- the conductor 120_2 functions as one of the source electrode and the drain electrode
- the conductor 140_2 functions as the other of the source electrode and the drain electrode
- the region overlapping with the body 130_2 has a function as a channel formation region
- the insulator 160 has a function as a gate insulator
- the conductor 170 has a function as a gate electrode.
- the transistor 11 includes one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductor 120_1 and conductor 140_1, conductor 120_2, and conductor 120_2). It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region overlapping with the insulator 130_1 of the oxide 150 and a region overlapping with the insulator 130_2 of the oxide 150).
- the transistor 11 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including an oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source electrode or a drain electrode and the oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_2) is used.
- I can say that.
- the transistor 11 can output a drain current larger than that of the transistor 10 (see FIG. 1) included in the semiconductor device shown in ⁇ Structure Example 1 of Semiconductor Device>.
- the conductor 120_1 functioning as one of the source electrode and the drain electrode of the transistor 11 and the conductor 120_2 are electrically connected to each other through the conductor 190_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2.
- the conductor 140_1 functioning as the other of the source electrode and the drain electrode and the conductor 140_2 are electrically connected to each other through the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2.
- the transistor 11 by applying a potential at which the transistor 11 is turned on to the conductor 170 having a function as a gate electrode, the transistor 11 has the same magnitude as that of the transistor 10 when the potential is applied to the conductor 170. Double drain current can be output. Since the transistor 11 has the above-described electrical connection configuration, the transistor 11 has an occupied area smaller than the case where the two transistors 10 are simply provided, and is equivalent to the case where the two transistors 10 are provided. Current output capability can be obtained.
- the conductors 185_1 and 185_2, and the conductors 200_1 and 200_2 may not be electrically connected, and the two transistors included in the transistor 11 may be controlled independently. That is, the transistor 11 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including an oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source or drain electrode and the oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_2) is controlled independently. It is good also as composition to do.
- the same material as the conductor 185 of the transistor 10 can be used for the conductor 185_1 (conductor 185_2).
- the same material as the conductor 190 of the transistor 10 can be used for the conductor 190_2.
- the conductor 120_1 (conductor 120_2) the same material as the conductor 120 of the transistor 10 can be used for the conductor 120_1 (conductor 120_2).
- the insulator 130_1 (insulator 130_2) can be formed using the same material as the insulator 130 of the transistor 10.
- the conductor 140_1 (conductor 140_2) the same material as the conductor 140 of the transistor 10 can be used for the conductor 140_2
- conductor 195_1 (conductor 195_2)
- conductor 195_2 the same material as the conductor 195 of the transistor 10
- conductor 200_1 (conductor 200_2)
- the same material as the conductor 200 of the transistor 10 can be used.
- the structure example of the semiconductor device including the transistor 11 according to one embodiment of the present invention which is different from the semiconductor device including the transistor 10 described in ⁇ Structure Example 1 of Semiconductor Device>, is described above.
- a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be accurately and easily manufactured over a substrate surface. Can do.
- a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane.
- a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured.
- a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured.
- a transistor with high on-state current can be manufactured while being fine.
- the fine transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated.
- the semiconductor device can be manufactured with high yield.
- ⁇ Configuration Example 3 of Semiconductor Device> The semiconductor device including the transistor 10 described in ⁇ Structure Example 1 of Semiconductor Device> and a semiconductor device including the transistor 11 illustrated in ⁇ Structure Example 2 of Semiconductor Device> are different from those of one embodiment of the present invention.
- a structural example of a semiconductor device including the transistor 12 will be described with reference to FIGS.
- FIG. 3A is a top view of the semiconductor device having the transistor 12.
- FIG. 3B is a cross-sectional view taken along the dashed-dotted line C1-C2 in FIG.
- FIG. 3C is a cross-sectional view taken along the dashed-dotted line C3-C4 in FIG.
- the part shown with the dashed-dotted line of C1-C2 and the part shown with the dashed-dotted line of C3-C4 are mutually orthogonal.
- some elements are omitted for clarity.
- the structure having the same function as the structure of the semiconductor device illustrated in ⁇ Semiconductor device configuration example 1> or ⁇ Semiconductor device configuration example 2> is denoted by the same reference numeral. ing.
- parts different from the semiconductor device described in ⁇ Semiconductor device configuration example 1> or ⁇ semiconductor device configuration example 2> will be mainly described, and other parts will be described in ⁇ semiconductor device configuration>.
- the contents described in Example 1> or ⁇ Structure Example 2 of Semiconductor Device> can be referred to.
- the semiconductor device illustrated in FIG. 3 has a function as a conductor that functions as a source electrode or a drain electrode and a plug that connects the conductor and the upper and lower wirings.
- the semiconductor device shown in ⁇ Structure Example 1 of Semiconductor Device> is that a conductor or the like includes the insulator 12 and the transistor 12 provided opposite to each other with the conductor 170 interposed therebetween (see FIG. 1). .).
- the oxide 150 is provided only in a region facing the side surface of the conductor 170 with the insulator 160 interposed therebetween (oxide 150_1 and oxide 150_2), and provided in a region overlapping with the bottom surface of the conductor 170. This is different from the semiconductor device shown in ⁇ Semiconductor device configuration example 2> (see FIG. 2).
- the transistor 12 and the insulator 100, the insulator 102, the insulator 105, the insulator 110, the insulator 175, and the insulator which function as an interlayer film are provided over a substrate (not illustrated). 176, an insulator 178, and an insulator 180.
- the conductor 185_1, the conductor 185_2, the conductor 200_1, and the conductor 200_2 that are electrically connected to the transistor 12 and function as wirings, and the conductor 190_1, the conductor 190_2, the conductor 195_1, which function as plugs, and A conductor 195_2 is included.
- the conductor 185_1, the conductor 190_1, the conductor 195_1, and the conductor 200_1, and the conductor 185_2, the conductor 190_2, the conductor 195_2, and the conductor 200_2 are all formed of the insulator 160 and the conductor 170. They are provided opposite to each other (see FIG. 3B).
- the semiconductor device illustrated in FIG. 3 can be applied to the conductor 185_1 (conductor 185_2), the conductor 190_1 (conductor 190_2), the conductor 195_1 (conductor 195_2), and the conductor 200_1 (conductor 200_2).
- the contents described in ⁇ Structural Example 2 of Semiconductor Device> can be referred to.
- the transistor 12 includes the conductor 120_1, the conductor 120_2, the oxide 150_1, the oxide 150_2, and the insulator 160 which are provided over the insulator 110 and the conductor 120_1.
- a conductor 170 disposed on the insulator 160.
- the conductor 120_1 and the conductor 120_2, the insulator 130_1 and the insulator 130_2, the conductor 140_1 and the conductor 140_2, and the oxide 150_1 and the oxide 150_2 are opposite to each other with the insulator 160 and the conductor 170 interposed therebetween. Provided.
- the oxide 150_1 (the oxide 150_2) includes the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2), the conductor 120_2 (conductor 120_1),
- the insulating layer 130 ⁇ / b> _ ⁇ b> 2 (insulator 130 ⁇ / b> _ ⁇ b> 1) and the conductor 140 ⁇ / b> _ ⁇ b> 2 (conductor 140 ⁇ / b> _ ⁇ b> 1) are provided to have a region in contact with the side surface.
- the insulator 160 faces the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) through the oxide 150_1 (oxide 150_2).
- a region is provided.
- the conductor 170 includes the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) through the oxide 150_1 (oxide 150_2) and the insulator 160. Provided so as to have a region facing the side surface.
- the conductor 120_1, the conductor 120_2, the insulator 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2 are covered so as to cover them.
- An insulator 175 is provided.
- the insulator 175 is provided with an opening in which the side surface of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) overlap with part of the inner wall.
- the oxide 150_1 and the oxide 150_2 are provided along the inner wall (side surface), and cover the side surfaces of the oxide 150_1 and the oxide 150_2 facing each other and the upper surface of the insulator 110 between the oxide 150_1 and the oxide 150_2.
- the insulator 160 is provided, and the conductor 170 is provided on the insulator 160 so as to embed the opening.
- the heights of the top surfaces of the oxide 150_1, the oxide 150_2, the insulator 160, and the conductor 170 are approximately the same as the height of the top surface of the insulator 175. Is preferred.
- FIG. 3B illustrates the oxide 150_1 (oxide 150_2) as a single-layer structure, one embodiment of the present invention is not limited thereto.
- the oxide 150_1 (oxide 150_2) may have a stacked structure of two or more layers.
- the conductor 120_1 functions as one of the source electrode and the drain electrode
- the conductor 140_1 functions as the other of the source electrode and the drain electrode
- the insulator 120_1 of the oxide 150_1 The overlapping region has a function as a channel formation region
- the insulator 160 has a function as a gate insulator
- the conductor 170 has a function as a gate electrode.
- the conductor 120_2 functions as one of a source electrode and a drain electrode
- the conductor 140_2 functions as the other of the source electrode and the drain electrode
- the oxide 150_2 is insulated.
- the region overlapping with the body 130_2 has a function as a channel formation region
- the insulator 160 has a function as a gate insulator
- the conductor 170 has a function as a gate electrode.
- the transistor 12 includes one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductor 120_1 and conductor 140_1, conductor 120_2, and conductor 120_2). It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region overlapping with the insulator 130_1 of the oxide 150_1 and a region overlapping with the insulator 130_2 of the oxide 150_2).
- the transistor 12 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including the oxide 150_1 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, and an insulator 160 having a function as a gate insulator; A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source electrode or a drain electrode, and an oxide 150_2 having a function as a channel formation region (a region overlapping with the insulator 130_2). I can say that.
- the transistor 12 can output a larger drain current than the transistor 10 (see FIG. 1) included in the semiconductor device shown in ⁇ Structure Example 1 of Semiconductor Device>.
- the conductor 120_1 functioning as one of the source electrode and the drain electrode of the transistor 12 and the conductor 120_2 are electrically connected to each other through the conductor 190_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2.
- the conductor 140_1 functioning as the other of the source electrode and the drain electrode and the conductor 140_2 are electrically connected to each other through the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2.
- the transistor 12 has the same magnitude as the potential of the transistor 10 when the potential is applied to the conductor 170. Double drain current can be output. Since the transistor 12 has an electrical connection configuration as described above, the transistor 12 has an occupied area smaller than that in the case where two transistors 10 are simply provided, and is equivalent to the case where two transistors 10 are provided. Current output capability can be obtained.
- the conductors 185_1 and 185_2 and the conductors 200_1 and 200_2 may not be electrically connected, and the two transistors included in the transistor 12 may be controlled independently. That is, the transistor 12 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including the oxide 150_1 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, and an insulator 160 having a function as a gate insulator; A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source electrode or a drain electrode and the oxide 150_2 having a function as a channel formation region (a region overlapping with the insulator 130_2) is controlled independently. It is good also as composition
- the transistor 12 included in the semiconductor device illustrated in FIG. 3 is different from the transistor 11 included in the semiconductor device illustrated in FIG. 2 in the shape of an oxide having a channel formation region.
- the transistor 11 includes the conductor 120_1, the insulator 130_1, and the conductor 140_1, the side surfaces of the conductor 120_2, the insulator 130_2, and the conductor 140_2 that face each other and part of the top surface of the insulator 110.
- the transistor 12 includes an oxide 150 in contact with a side surface of the conductor 120_1, the insulator 130_1, and the conductor 140_1 that faces the conductor 120_2, the insulator 130_2, and the conductor 140_2.
- the oxide 120_2 in contact with the side surface of the conductor 120_1, the insulator 130_1, and the conductor 140_1 opposite to the conductor 120_1. That is, in the transistor 12, the oxide having a channel formation region is divided into two (oxide 150_1 and oxide 150_2) with the insulator 160 and the conductor 170 interposed therebetween. And different. An oxide having a channel formation region has conductivity. Therefore, for example, when the two transistors included in the above-described transistor 12 are controlled independently, it is possible to suppress the occurrence of leakage via an oxide between the two transistors. This makes it difficult for the other transistor to be affected by the operation (on operation, off operation) of one of the transistors constituting the transistor 12, and each operation can be reliably controlled.
- the same material as the oxide 150 of the transistor 10 can be used for the oxide 150_1 (oxide 150_2).
- the same material as the conductor 185 of the transistor 10 can be used.
- the conductor 190_1 (conductor 190_2)
- the same material as the conductor 190 of the transistor 10 can be used.
- the conductor 120_1 (conductor 120_2)
- the same material as the conductor 120 of the transistor 10 can be used.
- the insulator 130_1 (insulator 130_2) can be formed using the same material as the insulator 130 of the transistor 10.
- the conductor 140_1 (conductor 140_2) the same material as the conductor 140 of the transistor 10 can be used.
- conductor 195_1 (conductor 195_2)
- conductor 195_2 the same material as the conductor 195 of the transistor 10
- conductor 200_1 (conductor 200_2)
- the same material as the conductor 200 of the transistor 10 can be used.
- the structure and effects of the semiconductor device including the transistor 12 other than those described above are described in ⁇ Semiconductor Device Constitution Example 1> described in ⁇ Semiconductor Device Configuration Example 1> or ⁇ Semiconductor Device Configuration Example 2>.
- the structure and effects of the semiconductor device including the transistor 11 can be taken into consideration.
- the above is different from the semiconductor device including the transistor 10 described in ⁇ Structural Example 1 of Semiconductor Device> or the semiconductor device including the transistor 11 illustrated in ⁇ Structural Example 2 of the semiconductor device> according to one embodiment of the present invention.
- the structural example of the semiconductor device including the transistor 12 has been described.
- a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and ease over a substrate. Can do.
- a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane.
- a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured.
- a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured.
- a transistor with high on-state current can be manufactured while being fine.
- the fine transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated.
- a semiconductor device with high integration and low leakage between adjacent transistors can be manufactured.
- the semiconductor device can be manufactured with high yield.
- FIG. 4A is a top view of the semiconductor device having the transistor 13.
- FIG. 4B is a cross-sectional view taken along the dashed-dotted line D1-D2 in FIG.
- FIG. 4C is a cross-sectional view taken along the dashed-dotted line D3-D4 in FIG.
- the part shown with the dashed-dotted line of D1-D2 and the part shown with the dashed-dotted line of D3-D4 are mutually orthogonally crossed.
- some elements are omitted for clarity.
- the conductor 171 functioning as a gate electrode includes an oxide 151 functioning as a channel formation region and a gate insulator.
- the transistor 13 has a region that overlaps not only the side surfaces of the conductor 120, the insulator 130, and the conductor 140 but also part of the upper surface of the conductor 140 with the functioning insulator 161 interposed therebetween. It differs from the semiconductor device shown in ⁇ Structure Example 1 of Semiconductor Device> (see FIG. 1).
- the semiconductor device of one embodiment of the present invention includes the transistor 13 and the insulator 100, the insulator 102, the insulator 105, the insulator 110, the insulator 175, and the insulator which function as an interlayer film over a substrate (not illustrated). 176, an insulator 178, and an insulator 180.
- a conductor 185 and a conductor 200 which are electrically connected to the transistor 13 and function as wirings, and a conductor 190 and a conductor 195 which function as plugs are included.
- the transistor 13 includes a conductor 120 and an oxide 151 which are disposed over the insulator 110, an insulator 130 which is disposed over the conductor 120, and the insulator 130.
- the conductor 140 disposed above, the insulator 161 disposed on the oxide 151, and the conductor 171 disposed on the insulator 161 are included.
- the oxide 151 is provided so as to have a region in contact with the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and part of the top surface of the conductor 140.
- the insulator 161 is provided so as to have a region overlapping with the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and part of the top surface of the conductor 140 with the oxide 151 interposed therebetween.
- the conductor 171 has a region overlapping with the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and part of the upper surface of the conductor 140 with the oxide 151 and the insulator 161 interposed therebetween. Is provided.
- an insulator 175 is provided on the conductor 120, the insulator 130, and the conductor 140 so as to cover them.
- the insulator 175 is provided with an opening in which a part of the inner wall overlaps a side surface of the conductor 120, the insulator 130, and the conductor 140 and a part of the upper surface of the conductor 140, and extends along the inner wall of the opening.
- the oxide 151 is provided, the insulator 161 is provided over the oxide 151, and the conductor 171 is provided over the insulator 161 so as to fill the opening.
- the heights of the top surfaces of the oxide 151, the insulator 161, and the conductor 171 are preferably approximately the same as the height of the top surface of the insulator 175.
- FIG. 4B illustrates the oxide 151 as a single-layer structure, one embodiment of the present invention is not limited thereto.
- the oxide 151 may have a stacked structure including two or more layers.
- the conductor 120 functions as one of a source electrode and a drain electrode
- the conductor 140 functions as the other of the source electrode and the drain electrode.
- the overlapping region has a function as a channel formation region
- the insulator 161 has a function as a gate insulator
- the conductor 171 has a function as a gate electrode.
- the transistor 10 has only one contact surface between the oxide 150 and the insulator 130 shown in FIG. 1B, whereas the transistor 13 has a contact surface between the oxide 151 and the insulator 130.
- the transistor 10 and the transistor 13 each have a difference in the area of a region that can function as a channel formation region in the oxide (the oxide 150 or the oxide 151) (the transistor 13 is more than the transistor 10).
- the area of the oxide that can function as a channel formation region is large. Therefore, the transistor 13 can output a larger drain current than the transistor 10 while having the same element size as the transistor 10.
- the transistor 13 is different from the transistor 10 in that the conductor 171 functioning as a gate electrode has a region overlapping with a part of the upper surface of the conductor 140.
- the transistor 13 having this structure a channel formation region (a region overlapping with the insulator 130 of the oxide 151) can be surrounded by the conductor 171 as illustrated in FIG. Therefore, the transistor 13 can improve the controllability of applying the gate electric field to the channel formation region more reliably than the transistor 10. Therefore, the transistor 13 can reliably control the carrier during operation (on operation, off operation), and can realize both a larger on-current and a smaller off-current than the transistor 10.
- the oxide 151 can be formed using the same material as the oxide 150 of the transistor 10.
- the insulator 161 can be formed using the same material as the insulator 160 of the transistor 10.
- the conductor 171 the same material as the conductor 170 of the transistor 10 can be used.
- the semiconductor device including the transistor 10 described in ⁇ Structure Example 1 of Semiconductor Device> and ⁇ Structure Example 2 of Semiconductor Device> are described.
- the structure and effects of the semiconductor device including the transistor 11 or the semiconductor device including the transistor 12 described in ⁇ Structure Example 3 of Semiconductor Device> can be considered.
- the structure example of the semiconductor device including the transistor 13 according to one embodiment of the present invention is described above as a modification example of the semiconductor device including the transistor 10 described in ⁇ Structure Example 1 of Semiconductor Device>.
- a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and ease over a substrate. Can do.
- a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane.
- a transistor with high on-state current can be manufactured.
- a transistor with low off-state current can be manufactured.
- a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured.
- a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured.
- the minute transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated.
- the semiconductor device can be manufactured with high yield.
- An example of a semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device including the transistor 10, the transistor 11, the transistor 12, or the transistor 13 (see FIGS. 1 to 4) described above.
- the semiconductor device according to one embodiment of the present invention can be combined with any of the structures of the semiconductor devices described above as appropriate.
- an insulator substrate for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
- the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
- the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
- there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
- the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
- a substrate including a metal nitride examples include a substrate including a metal oxide, and the like.
- a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
- a substrate in which an element is provided may be used.
- the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
- a flexible substrate may be used as the substrate.
- a method for providing a transistor over a flexible substrate there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled and transferred to a flexible substrate.
- a separation layer is preferably provided between the non-flexible substrate and the transistor.
- the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
- the substrate has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
- a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.
- a substrate that is a flexible substrate for example, metal, alloy, resin, glass, or fiber thereof can be used.
- a substrate that is a flexible substrate is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed.
- a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used.
- the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
- aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
- insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
- the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), and the insulator 160 for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum,
- An insulator containing silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
- the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), and the insulator 160 include silicon oxide, silicon oxynitride, or silicon nitride. preferable.
- the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) is preferably reduced.
- the desorption amount of hydrogen of the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) is determined by a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)).
- TDS Thermal Desorption Spectroscopy
- the amount of desorption converted to hydrogen molecules corresponds to the area of the insulator 105, the insulator 110, or the insulator 130 (or the insulator 130_1 and the insulator 130_2). It is 2 ⁇ 10 15 molecules / cm 2 or less, preferably 1 ⁇ 10 15 molecules / cm 2 or less, more preferably 5 ⁇ 10 14 molecules / cm 2 or less.
- the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) are preferably formed using an insulator from which oxygen is released by heating.
- the insulator 105, the insulator 110, and the insulator 130 are used.
- oxygen can be effectively supplied from the insulator 130_2 to the oxide 150 (or the oxide 150_1 and the oxide 150_2).
- the insulator 160 preferably includes an insulator having a high relative dielectric constant.
- the insulator 160 includes gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, an oxide including silicon and hafnium, an oxide including silicon and hafnium. It is preferable to include a nitride or a nitride including silicon and hafnium.
- the insulator 160 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, when combined with an insulator having a high relative dielectric constant, a laminated structure having a thermally stable and high relative dielectric constant can be obtained with a film having few defects. .
- the insulator 160 is preferably disposed in contact with the upper surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2).
- the insulator 160 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 160 in contact with the top surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2), oxygen can be effectively added to the oxide 150 (or the oxide 150_1 or the oxide 150_2). Can be supplied.
- the concentration of impurities such as water or hydrogen in the insulator 160 be reduced. .
- the thickness of the insulator 160 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, and may be, for example, about 1 nm.
- the insulator 160 preferably contains oxygen.
- oxygen for example, in the temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 160 in the range of the surface temperature of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. 1 ⁇ 10 14 molecules / cm 2 or more, preferably 2 ⁇ 10 14 molecules / cm 2 or more, more preferably 4 ⁇ 10 14 molecules / cm 2 or more.
- TDS analysis temperature-programmed desorption gas spectroscopy analysis
- the insulator 175, the insulator 176, and the insulator 180 include an insulator having a low relative dielectric constant.
- the insulator 175, the insulator 176, and the insulator 180 were doped with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen. It is preferable to include silicon oxide, silicon oxide having holes, resin, or the like.
- the insulator 175, the insulator 176, and the insulator 180 are added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and nitrogen. It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon.
- the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
- the insulator 175, the insulator 176, and the insulator 180 are formed in the same manner as the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), the insulator 160, and the like. It is preferable that the concentration of impurities such as water or hydrogen is reduced.
- an insulator having a high barrier property against impurities such as hydrogen and water and oxygen is preferably used.
- hydrogen or water enters the transistor 10, the transistor 11, the transistor 12, or the transistor 13 from the lower side (upper side) of the insulator 102 (insulator 178). It can suppress that impurities, such as, mix. Further, diffusion of oxygen in the transistor 10, the transistor 11, the transistor 12, or the transistor 13 to the lower side (upper side) of the insulator 102 (insulator 178) can be suppressed.
- the insulator examples include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Is preferably used in a single layer or a stacked layer.
- the insulator includes aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, metal oxide such as tantalum oxide, silicon nitride oxide, Silicon nitride or the like may be used.
- the insulator preferably includes aluminum oxide, hafnium oxide, or the like.
- Conductor 120 (or conductor 120_1, conductor 120_2), conductor 140 (or conductor 140_1, conductor 140_2), conductor 185 (or conductor 185_1, conductor 185_2), conductor 190 (or , Conductor 190_1, conductor 190_2), conductor 195 (or conductor 195_1, conductor 195_2), conductor 200 (or conductor 200_1, conductor 200_2), and conductor 170 include aluminum, chromium A material containing at least one metal element selected from copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
- a conductive material containing a metal element and oxygen contained in a metal oxide applicable to the oxide 150 can be used as the conductor, particularly the conductor 170.
- the above-described conductive material containing a metal element and nitrogen may be used.
- a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
- indium gallium zinc oxide containing nitrogen may be used.
- hydrogen contained in the oxide 150 (or the oxide 150_1 or the oxide 150_2) may be trapped in some cases.
- hydrogen mixed from an external insulator or the like may be captured.
- a plurality of conductive layers formed of the above materials may be stacked.
- a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
- a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
- a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
- a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used as the gate electrode is preferably used.
- a conductive material containing oxygen is preferably provided on the channel formation region side.
- the conductor 185 (or the conductor 185_1, the conductor 185_2), the conductor 190 (or the conductor 190_1, the conductor 190_2), the conductor 195 (or the conductor 195_1, the conductor 195_2), and the conductor 200 (or the conductor 200_1 or the conductor 200_2) may be formed using a highly embedded conductive material such as tungsten or polysilicon.
- a conductive material with high embedding property and a conductive barrier film such as titanium, titanium nitride, or tantalum nitride may be used in combination.
- a metal oxide is preferably used as the oxide 150 (or the oxide 150_1 and the oxide 150_2).
- silicon including strained silicon
- germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used as a semiconductor material. It doesn't matter.
- a metal oxide which is preferably used for the oxide 150 (or the oxide 150_1 and the oxide 150_2) according to one embodiment of the present invention is described.
- the metal oxide preferably contains at least indium or zinc.
- indium and zinc are preferably included.
- aluminum, gallium, yttrium, tin, or the like is contained.
- One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.
- the metal oxide is InMZnO containing indium, element M and zinc.
- the element M is aluminum, gallium, yttrium, tin, or the like.
- other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
- the element M may be a combination of a plurality of the aforementioned elements.
- a transistor with high field effect mobility can be realized by using the metal oxide in a channel formation region of a transistor.
- a transistor having good reliability can be realized.
- a metal oxide can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
- a metal oxide with low carrier density is preferably used for a channel formation region of the transistor.
- the impurity concentration in the metal oxide film may be decreased and the defect level density may be decreased.
- a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
- the metal oxide has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / What is necessary is just to be cm 3 or more.
- the trap level density may be low.
- the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in a metal oxide having a high trap state density may have unstable electrical characteristics.
- Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
- the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the metal when an alkali metal or an alkaline earth metal is contained in the metal oxide, the metal may form a defect level in the metal oxide and generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
- the nitrogen in the metal oxide is preferably reduced as much as possible.
- the nitrogen concentration in the metal oxide is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less in SIMS, Preferably, it is 5 ⁇ 10 17 atoms / cm 3 or less.
- hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed.
- oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated.
- a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible.
- the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
- Stable electrical characteristics can be imparted by using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor.
- the CAC-OS is an example of a function or a material structure that can be included in the metal oxide of the transistor of one embodiment of the present invention.
- the CAC-OS is one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
- elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
- the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
- the state mixed with is also referred to as mosaic or patch.
- a CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
- X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.
- CAC-OS includes a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 there is a region which is a main component, a composite metal oxide having a structure that is mixed.
- the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
- IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O.
- ZnO ZnO
- the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
- the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
- CAC-OS relates to a material structure of metal oxide.
- CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In.
- the region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
- the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
- a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
- a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or the region InO X1 is the main component, it may be difficult to observe a clear boundary.
- the CAC-OS is a part of a nanoparticle mainly including the metal element as a main component and a part of a nanoparticle mainly including In.
- the regions observed in the above are each randomly dispersed in a mosaic pattern.
- the CAC-OS can be formed by, for example, a sputtering method under a condition that the substrate is not intentionally heated.
- a sputtering method any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas is used as a deposition gas. That's fine.
- the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas at the time of film formation is preferably as low as possible.
- CAC-OS is characterized in that no clear peak is observed when it is measured using the ⁇ / 2 ⁇ scan by the out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods.
- XRD X-ray diffraction
- the CAC-OS in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
- nc nano-crystal
- GaO X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 are unevenly distributed and mixed.
- the CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
- the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2, or InO X1 is a region which is a main component, by carriers flow, conductive metal oxide is expressed. Therefore, a region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is distributed in a cloud shape in the metal oxide, so that a transistor using the metal oxide achieves high field-effect mobility. it can.
- areas such as GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 is compared to region which is a main component, has a high area insulation. That is, a region containing GaO X3 or the like as a main component is distributed in a metal oxide, so that a transistor using the metal oxide can suppress a leakage current and realize a favorable switching operation.
- CAC-OS when CAC-OS is used for a semiconductor element such as a transistor, conductivity caused by In X2 Zn Y2 O Z2 or InO X1 and insulation caused by GaO X3 or the like act complementarily. Thus, both a high on-current and a low off-current can be realized.
- CAC-OS is optimally used for various semiconductor devices such as a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, and an electronic device.
- FIGS. 5A to 10A are top views of the semiconductor device including the transistor 10.
- (B) of each figure is sectional drawing of the site
- (C) of each figure is sectional drawing of the site
- a substrate (not shown) is prepared.
- the insulator 100 is formed on the substrate.
- the insulator 100 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD method. (Atomic Layer Deposition) method or the like can be used.
- the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
- PECVD Plasma Enhanced CVD
- TCVD Thermal CVD
- Photo CVD Photo CVD
- MCVD Metal CVD
- MOCVD Metal Organic CVD
- the plasma CVD method can obtain a high-quality film at a relatively low temperature.
- the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
- a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
- a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
- plasma damage during film formation does not occur, so that a film with few defects can be obtained.
- the ALD method is also a film forming method that can reduce plasma damage to the object to be processed.
- the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
- the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
- the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
- the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
- the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
- a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
- a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
- a silicon oxide film is formed as the insulator 100 by a CVD method.
- the insulator 100 for example, silicon oxynitride may be used in addition to silicon oxide.
- an insulator 102 is formed on the insulator 100.
- the insulator 102 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an aluminum oxide film is formed as the insulator 102 by a sputtering method.
- the insulator 102 may have a multilayer structure.
- an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method.
- an aluminum oxide film may be formed by an ALD method, and the aluminum oxide film may be formed on the aluminum oxide by a sputtering method.
- an insulator 105 is formed on the insulator 102.
- the insulator 105 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is formed as the insulator 105 by a CVD method.
- silicon oxynitride may be used in addition to silicon oxide.
- an opening reaching the insulator 102 is formed in the insulator 105.
- the openings include, for example, grooves and slits. In some cases, the opening is pointed to a region where the opening is formed.
- a wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing.
- the insulator 102 an insulator that functions as an etching stopper film when the opening is formed by etching the insulator 105 is preferably selected.
- the insulator 102 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.
- the conductor 185 includes a stacked structure including a conductor 185a (not shown) having a function of suppressing permeation of oxygen and a conductor 185b (not shown) having higher conductivity than the conductor 185a. It is preferable that
- the conductor to be the conductor 185a preferably includes a conductive material having a function of suppressing permeation of oxygen.
- a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
- a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
- the conductor to be the conductor 185a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
- a conductor to be the conductor 185b is formed over the conductor to be the conductor 185a.
- the conductor to be the conductor 185b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a low-resistance conductive material such as copper is formed as the conductor to be the conductor 185b.
- the conductor to be the conductor 185a and part of the conductor to be the conductor 185b are removed, and the insulator 105 is exposed.
- the conductor to be the conductor 185a and the conductor to be the conductor 185b remain only in the opening. Accordingly, the conductor 185 including the conductor 185a and the conductor 185b having a flat upper surface can be formed (see FIG. 5). Note that part of the insulator 105 may be removed by the CMP treatment.
- the insulator 110 is formed over the insulator 105 and the conductor 185.
- the insulator 110 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a silicon oxide film is formed as the insulator 110 by a CVD method.
- silicon oxynitride may be used in addition to silicon oxide.
- the first heat treatment may be performed.
- the first heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, for example.
- the first heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.
- the first heat treatment may be performed in a reduced pressure state.
- heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be performed.
- the first heat treatment impurities such as hydrogen and water contained in the insulator 110 and the insulator 105 can be reduced.
- plasma treatment containing oxygen may be performed in a reduced pressure state.
- an apparatus having a power source that generates high-density plasma using microwaves is preferably used.
- a power source for applying RF (Radio Frequency) may be provided on the substrate side.
- high-density plasma high-density oxygen radicals can be generated.
- oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 110 and the insulator 105. be able to.
- plasma treatment containing oxygen may be performed in order to supplement the desorbed oxygen.
- an opening reaching the conductor 185 is formed in the insulator 110.
- the opening may be formed by a wet etching method, but the dry etching method is preferable for fine processing.
- the conductor 190 has a stacked structure including a conductor 190a (not shown) having a function of suppressing permeation of oxygen and a conductor 190b (not shown) having higher conductivity than this. It is preferable.
- the conductor to be the conductor 190a preferably includes a conductive material having a function of suppressing permeation of oxygen.
- a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
- a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
- the conductor to be the conductor 190a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- tantalum nitride is formed by a sputtering method as a conductor to be the conductor 190a.
- a conductor to be the conductor 190b is formed on the conductor to be the conductor 190a.
- the conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- titanium nitride is formed by an ALD method, and tungsten is formed over the titanium nitride by a CVD method.
- the conductor to be the conductor 190a and a part of the conductor to be the conductor 190b are removed, and the insulator 110 is exposed.
- the conductor to be the conductor 190a and the conductor to be the conductor 190b remain only in the opening.
- the conductor 190 including the conductor 190a and the conductor 190b having a flat upper surface can be formed (see FIG. 5).
- part of the insulator 110 may be removed by the CMP treatment.
- a conductor 120a is formed over the insulator 110 and the conductor 190.
- the conductor 120a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a conductor such as tantalum nitride, tungsten, or titanium nitride can be used.
- tungsten may be formed, and a conductor having a function of suppressing transmission of oxygen such as titanium nitride or tantalum nitride may be formed over the tungsten. With this structure, it is possible to suppress an increase in electric resistance value due to oxidation of tungsten by oxygen mixed from above the conductor 120a.
- the conductor 120a may be a conductive oxide such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium containing titanium oxide.
- ITO indium tin oxide
- An oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, or indium gallium zinc oxide containing nitrogen is formed, and aluminum, chromium, A material containing one or more metal elements selected from copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc., or phosphorus Contains impurity elements such as Typified by polycrystalline silicon obtained, the electrical conductivity is high semiconductor may be configured for forming a silicide such as nickel silicide.
- the oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffused from the outside, which may improve the electrical characteristics and reliability of the transistor 10. Alternatively, even when titanium is used instead of the oxide, the same function may be obtained.
- tungsten is deposited as the conductor 120a by a sputtering method.
- an insulator 130a is formed on the conductor 120a.
- the insulator 130a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is formed by a CVD method as the insulator 130a.
- silicon oxynitride may be used in addition to silicon oxide.
- the second heat treatment may be performed.
- conditions for the first heat treatment can be used.
- impurities such as hydrogen and water contained in the insulator 130a can be reduced. Further, oxygen can be supplied into the insulator 130a.
- an ion implantation method in which ionized source gas is added after mass separation an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. Oxygen may be supplied.
- the insulator 130a can have excess oxygen by the heat treatment described above, the ion implantation method, or the like.
- the excess oxygen is supplied into the oxide 150 by heat treatment or the like later, so that the electrical characteristics and reliability of the transistor 10 may be improved.
- a conductor 140a is formed over the insulator 130a (see FIG. 6).
- the conductor 140a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a conductor such as tantalum nitride, tungsten, or titanium nitride can be used as the conductor 140a.
- a conductor having a function of suppressing permeation of oxygen such as titanium nitride or tantalum nitride may be formed, and tungsten may be formed over the conductor. With this structure, it is possible to suppress an increase in electric resistance value due to oxidation of tungsten by oxygen mixed from the lower side of the conductor 140a.
- the conductor 140a is a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and the like.
- a material having one or more elements, or a polycrystalline silicon containing an impurity element such as phosphorus, a semiconductor having high electrical conductivity, or a silicide such as nickel silicide is formed on the conductive layer.
- ITO Indium Tin Oxide
- indium oxide containing tungsten oxide indium oxide containing tungsten oxide
- indium zinc oxide containing tungsten oxide indium oxide containing titanium oxide
- indium tin containing titanium oxide Oxide indium zinc acid Things
- indium tin oxide added with silicon, or nitrogen may be configured for forming the indium gallium zinc oxide containing.
- the oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffused from the outside, which may improve the electrical characteristics and reliability of the transistor 10. Alternatively, even when titanium is used instead of the oxide, the same function may be obtained.
- tungsten is deposited as the conductor 140a by a sputtering method.
- the conductor 120a, the insulator 130a, and the conductor 140a are processed using a lithography method or the like, so that the conductor 120b, the insulator 130b, Then, the conductor 140b is formed (see FIG. 7).
- a dry etching method or a wet etching method can be used.
- the dry etching method is suitable because it is suitable for processing a fine shape. Part of the insulator 110 may be removed by the processing.
- a resist is exposed through a mask.
- a resist mask is formed by removing or leaving the exposed region using a developer.
- the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask.
- the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
- an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
- an electron beam or an ion beam may be used.
- the resist mask is removed by a method such as performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
- a dry etching process such as ashing
- performing a wet etching process performing a wet etching process after the dry etching process
- performing a dry etching process after the wet etching process can do.
- a hard mask made of an insulator or a conductor may be used instead of the resist mask.
- an insulating film or a conductive film to be a hard mask material is formed over the conductor 140a, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do.
- Etching of the conductor 120a, the insulator 130a, and the conductor 140a may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
- the hard mask may be removed by an etching method after the conductor 120a, the insulator 130a, and the conductor 140a are etched.
- the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
- a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
- the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
- a configuration in which a plurality of different high-frequency power supplies are applied to one of the parallel plate electrodes may be employed.
- mold electrode may be sufficient.
- a configuration in which high-frequency power sources having different frequencies are applied to the parallel plate electrodes may be used.
- a dry etching apparatus having a high-density plasma source can be used.
- an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
- impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the conductor 120b, the insulator 130b, and the conductor 140b.
- impurities include fluorine and chlorine.
- Cleaning may be performed to remove the above impurities.
- the cleaning method there are wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be combined as appropriate.
- cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
- aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
- ultrasonic cleaning using pure water or carbonated water may be performed.
- an insulator 175 is formed over the insulator 110, the conductor 120b, the insulator 130b, and the conductor 140b.
- the insulator 175 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is formed as the insulator 175 by a CVD method.
- the insulator 175 for example, silicon oxynitride may be used in addition to silicon oxide.
- the top surface of the insulator 175 is planarized by removing a part of the insulator 175 (see FIG. 8).
- the planarization can be performed by a CMP process, a dry etching process, or the like.
- the top surface of the insulator 175 is planarized by CMP treatment.
- the upper surface of the insulator 175 after the planarization treatment is preferably located above the upper surface of the conductor 140b. Note that in the case where the top surface of the insulator 175 after deposition has flatness, the above planarization treatment may not be performed.
- a third heat treatment may be performed.
- conditions for the first heat treatment can be used.
- impurities such as hydrogen and water contained in the insulator 175 can be reduced. Further, oxygen can be supplied into the insulator 175.
- the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are processed by a lithography method, so that the opening 145 reaching the upper surface of the insulator 110, the conductor 120, the insulator 130, and the conductor 140 are formed.
- Resist exposure in the lithography method may be performed using a KrF excimer laser beam, an ArF excimer laser beam, EUV light, or the like through a mask, or may be performed using an immersion technique.
- a method of directly drawing a pattern on a resist with an electron beam or an ion beam without using a mask may be used.
- the exposure using an electron beam or an ion beam is suitable for fine processing because a finer pattern can be drawn on the resist than the exposure using the above light.
- resist exposure is performed using an electron beam.
- a dry etching method or a wet etching method can be used as an etching process in the lithography method.
- the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are etched using a dry etching method.
- the opening 145 formed by the etching process preferably has an inner wall (side surface) formed substantially perpendicular to the substrate surface. As the inner wall (side surface) of the opening 145 is formed at an angle closer to perpendicular to the substrate surface, the transistor 10 can be miniaturized. Note that part of the insulator 110 may be removed by the etching treatment.
- an oxide film to be the oxide 150 is formed over the inner wall of the opening 145 and the insulator 175.
- the oxide film to be the oxide 150 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- an oxide to be the oxide 150 is formed by a sputtering method
- oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
- excess oxygen in the oxide film can be increased.
- the oxide is formed by a sputtering method
- the above-described target of In-M-Zn oxide can be used.
- the oxygen-deficient type is formed by setting the proportion of oxygen contained in the sputtering gas to 1% to 30%, preferably 5% to 20%.
- the metal oxide is formed.
- a transistor in which an oxygen-deficient metal oxide is used for a channel formation region can have a relatively high field-effect mobility.
- the oxide 150 may have a stacked structure of two or more layers.
- the oxide to be the oxide 150a is formed by sputtering using a sputtering method.
- Ga: Zn 4: 2: 4.1 [atomic ratio]
- the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5%.
- the film may be formed at 20% or less.
- the film thickness may be set to 70% or more, preferably 80% or more, more preferably 100%.
- the oxide 150 a mainly functions as a channel formation region of the transistor 10.
- oxygen contained in the oxide to be the oxide 150b can be supplied to the oxide to be the oxide 150a by a fourth heat treatment or the like.
- the fourth heat treatment is preferably performed after formation of the oxide to be the oxide 150b.
- the oxide to be the oxide 150a is formed by a sputtering method.
- the proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, more preferably. May be formed as 100%.
- the film may be formed at a ratio of oxygen of 1% to 30%, preferably 5% to 20%.
- the oxide 150b mainly functions as a channel formation region of the transistor 10. With the structure of the oxide 150, oxygen contained in the oxide to be the oxide 150a can be supplied to the oxide to be the oxide 150b by a fourth heat treatment or the like.
- the film may be formed with the ratio of oxygen contained in the sputtering gas being 70% or more, preferably 80% or more, more preferably 100%.
- the oxide 150b mainly functions as a channel formation region of the transistor 10.
- an insulator to be the insulator 160 is formed over the oxide to be the oxide 150.
- the insulator to be the insulator 160 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- silicon oxide is formed by a CVD method as an insulator to be the insulator 160.
- silicon oxynitride may be used in addition to silicon oxide.
- the fifth heat treatment it is preferable to perform the fifth heat treatment.
- conditions for the fourth heat treatment can be used.
- oxygen contained in the insulator that becomes the insulator 160 and the oxide that becomes the oxide 150c in the case where the oxide has a three-layer structure
- oxide that becomes the oxide 150 oxide
- a conductor to be the conductor 170 is formed on the insulator to be the insulator 160.
- the conductor to be the conductor 170 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a tungsten film is further formed by a CVD method. Note that in the conductor to be the conductor 170, it is preferable that the thickness of tungsten is larger than that of titanium nitride.
- Titanium nitride is preferably formed so as to be formed along the inner wall of the opening 145 through an insulator serving as the insulator 160 and to fill the remaining space in the opening 145 with tungsten.
- a conductor to be the conductor 170 in this manner, the conductor 170 having a stacked structure of titanium nitride and tungsten can be formed later.
- the conductor which becomes the conductor 170, the insulator which becomes the insulator 160, and the upper surface of the oxide which becomes the oxide 150 are polished until the upper surface of the insulator 175 is exposed, and the conductor 170, the insulator 160, Then, an oxide 150 is formed (see FIG. 10).
- the polishing can be performed by a CMP process or the like.
- the conductor 170, the insulator is formed by dry etching the conductor that becomes the conductor 170, the insulator that becomes the insulator 160, and the oxide that becomes the oxide 150 until the upper surface of the insulator 175 is exposed. 160 and the oxide 150 may be formed.
- the conductor 170, the insulator 160, and the oxide 150 are formed by CMP treatment.
- the CMP treatment the height of the top surface of the insulator 175 and the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 can be formed to be approximately the same (see FIG. 10). Note that part of the insulator 175 may be removed by the CMP treatment.
- the top surface of the insulator 175, the oxide 150, the insulator 160, and the top surface of the conductor 170 are the insulator 176, the insulator 176 is the insulator 178, the insulator 178 is the insulator 180, Each is deposited.
- the insulator 176, the insulator 178, and the insulator 180 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a silicon oxide film is formed as the insulator 176 by a CVD method
- an aluminum oxide film is formed as the insulator 178 by a sputtering method
- a silicon oxide film is formed as the insulator 180 by a CVD method.
- the insulator 176 or the insulator 180 may be formed using silicon oxynitride other than silicon oxide, for example.
- the insulator 178 other than aluminum oxide, for example, silicon nitride or hafnium oxide may be used.
- an opening reaching the conductor 140 is formed in the insulator 180, the insulator 178, the insulator 176, and the insulator 175.
- the opening may be formed by a wet etching method, but the dry etching method is preferable for fine processing.
- the conductor 195 has a stacked structure including a conductor 195a (not shown) having a function of suppressing permeation of oxygen and a conductor 195b (not shown) having a higher conductivity than the conductor 195a. It is preferable that
- the conductor to be the conductor 195a preferably includes a conductive material having a function of suppressing permeation of oxygen.
- a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
- a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
- the conductor to be the conductor 195a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- tantalum nitride is formed by a sputtering method as a conductor to be the conductor 195a.
- a conductor to be the conductor 195b is formed on the conductor to be the conductor 195a.
- the conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- titanium nitride is formed by an ALD method, and tungsten is formed over the titanium nitride by a CVD method.
- the conductor to be the conductor 195a and a part of the conductor to be the conductor 195b are removed, and the insulator 180 is exposed.
- the conductor to be the conductor 195a and the conductor to be the conductor 195b remain only in the opening. Accordingly, the conductor 195 including the conductor 195a and the conductor 195b having a flat upper surface can be formed. Note that part of the insulator 180 may be removed by the CMP treatment.
- the conductor 200 is a stacked structure including a conductor 200a (not shown) having a function of suppressing permeation of oxygen and a conductor 200b (not shown) having higher conductivity than the conductor 200a. It is preferable that
- the conductor to be the conductor 200a preferably includes a conductive material having a function of suppressing permeation of oxygen.
- a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
- a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
- the conductor to be the conductor 200a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
- a conductor to be the conductor 200b is formed on the conductor to be the conductor 200a.
- the conductor to be the conductor 200b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
- a low-resistance conductive material such as copper is formed as the conductor to be the conductor 200b.
- the conductor to be the conductor 200b and the conductor to be the conductor 200a are processed so as to have a region overlapping with the conductor 195, and the conductor 200a and the conductor 200a are formed over the insulator 180.
- a conductor 200 made of the conductor 200b can be formed. Note that part of the insulator 180 may be removed by the processing.
- a semiconductor device including the transistor 10 according to one embodiment of the present invention can be manufactured (see FIG. 1).
- a semiconductor device that can be miniaturized or highly integrated can be provided.
- a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and easily in a substrate surface.
- a semiconductor device including a transistor with favorable electrical characteristics in which a short channel effect is difficult to be realized while a channel length is fine can be manufactured.
- a semiconductor device including a minute transistor with an element size including not only a channel length but also a wiring and a plug can be manufactured.
- a semiconductor device having favorable electrical characteristics can be provided.
- a semiconductor device including a transistor with low off-state current can be provided.
- a semiconductor device including a transistor with high on-state current can be provided.
- a semiconductor device in which variation in electrical characteristics between elements is small in a substrate surface can be provided.
- a highly reliable semiconductor device can be provided.
- a semiconductor device with reduced power consumption can be provided.
- a highly productive semiconductor device can be provided.
- the memory device illustrated in FIG. 11 includes a transistor 3000, a transistor 2000, and a capacitor 1000.
- the transistor 2000 is a transistor in which a channel is formed in a semiconductor layer including a metal oxide. Since the transistor 2000 has a low off-state current, stored data can be held for a long time by using the transistor 2000 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
- the first wiring 3001 is electrically connected to the source of the transistor 3000
- the second wiring 3002 is electrically connected to the drain of the transistor 3000.
- the third wiring 3003 is electrically connected to one of a source and a drain of the transistor 2000
- the fourth wiring 3004 is electrically connected to the gate of the transistor 2000.
- the other of the gate of the transistor 3000 and the source or drain of the transistor 2000 is electrically connected to one of the electrodes of the capacitor 1000
- the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 1000. It is connected.
- the memory device shown in FIG. 11 has a characteristic that the potential of the gate of the transistor 3000 can be held, so that information can be written, held, and read as described below.
- the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is turned on, so that the transistor 2000 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 3000 and the electrode of the capacitor 1000. That is, predetermined charge is given to the gate of the transistor 3000 (writing).
- predetermined charge is given to the gate of the transistor 3000 (writing).
- the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is turned off and the transistor 2000 is turned off, so that charge is held at the node FG (holding).
- the second wiring 3002 has a charge held in the node FG.
- the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3000 is the case where a low level charge is applied to the gate of the transistor 3000 This is because it becomes lower than the apparent threshold voltage Vth_L .
- the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3000 into a conductive state.
- the potential of the fifth wiring 3005 can be set to a potential V 0 between V th_H and V th_L .
- the transistor 3000 is turned on when the potential of the fifth wiring 3005 is V 0 (> V th_H ).
- the transistor 3000 is kept off even when the potential of the fifth wiring 3005 is V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
- a memory device of one embodiment of the present invention includes a transistor 3000, a transistor 2000, and a capacitor 1000 as illustrated in FIG.
- the transistor 2000 is provided above the transistor 3000
- the capacitor 1000 is provided above the transistor 3000 and the transistor 2000.
- the transistor 3000 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b which function as a source region or a drain region.
- a conductor 316 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b which function as a source region or a drain region.
- the transistor 3000 may be either a p-channel type or an n-channel type.
- the region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 3000 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
- HEMT High Electron Mobility Transistor
- the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
- the conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
- a conductive material such as a material or a metal oxide material can be used.
- Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and in particular, tungsten is preferable from the viewpoint of heat resistance.
- transistor 3000 illustrated in FIGS. 11A and 11B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
- An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 3000.
- the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
- the insulator 322 may have a function as a planarization film that planarizes a step generated by the transistor 3000 or the like provided below the insulator 322.
- the top surface of the insulator 322 may be planarized by CMP treatment or the like to improve planarity.
- the insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 3000 to a region where the transistor 2000 is provided.
- a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
- silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element having a metal oxide such as the transistor 2000, electrical characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 2000 and the transistor 3000.
- the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
- the amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS).
- TDS temperature programmed desorption gas analysis method
- the amount of hydrogen desorbed from the insulator 324 is calculated by converting the amount of desorption converted to hydrogen atoms per area of the insulator 324 in the range of the surface temperature of the film from 50 ° C. to 500 ° C. in TDS analysis. 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
- the insulator 326 preferably has a lower dielectric constant than the insulator 324.
- the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
- the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times that of the insulator 324, and more preferably equal to or less than 0.6 times.
- a conductor 328 that is electrically connected to the capacitor 1000 or the transistor 2000, the conductor 330, and the like are embedded.
- the conductor 328 and the conductor 330 function as plugs or wirings.
- a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures.
- the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
- a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is formed in a single layer or stacked layers.
- a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
- low resistance conductive materials such as aluminum and copper. Wiring resistance can be lowered by using a low-resistance conductive material.
- a wiring layer may be provided over the insulator 326 and the conductor 330.
- an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
- a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
- the conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
- the insulator 350 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
- the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
- the conductor 356 having a barrier property against hydrogen is preferably formed in the opening of the insulator 350 having a barrier property against hydrogen.
- tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 3000 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
- a wiring layer may be provided over the insulator 354 and the conductor 356.
- the insulator 360, the insulator 362, and the insulator 364 are sequentially stacked.
- a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
- the conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
- an insulator having a barrier property against hydrogen is preferably used as the insulator 360.
- the conductor 366 preferably includes a conductor having a barrier property against hydrogen.
- the conductor 366 having a barrier property against hydrogen is preferably formed in the opening of the insulator 360 having a barrier property against hydrogen.
- a wiring layer may be provided over the insulator 364 and the conductor 366.
- an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked.
- a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374.
- the conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
- the insulator 370 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
- the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
- the conductor 376 having a barrier property against hydrogen is preferably formed in the opening of the insulator 370 having a barrier property against hydrogen.
- a wiring layer may be provided over the insulator 374 and the conductor 376.
- the insulator 380, the insulator 382, and the insulator 384 are sequentially stacked.
- a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
- the conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
- an insulator having a barrier property against hydrogen is preferably used as the insulator 380.
- the conductor 386 preferably includes a conductor having a barrier property against hydrogen.
- the conductor 386 having a barrier property against hydrogen is preferably formed in the opening portion of the insulator 380 having a barrier property against hydrogen.
- the insulator 210, the insulator 100, the insulator 102, and the insulator 105 are sequentially stacked over the insulator 384 and the conductor 386. Any of the insulator 210, the insulator 100, the insulator 102, and the insulator 105 is preferably formed using a film having a barrier property against oxygen or hydrogen.
- the insulator 210 and the insulator 102 are preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 3000 is provided to a region where the transistor 2000 is provided. . Therefore, a material similar to that of the insulator 324 can be used.
- silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
- silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element having a metal oxide such as the transistor 2000, electrical characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 2000 and the transistor 3000.
- the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
- the insulator 210 and the insulator 102 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
- aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000.
- the same material as the insulator 320 can be used.
- a material having a relatively low dielectric constant for the insulator parasitic capacitance generated between wirings can be reduced.
- silicon oxide, silicon oxynitride, or the like can be used as the insulator 100 and the insulator 105.
- the insulator 210, the insulator 100, the insulator 102, and the insulator 105 are embedded with a conductor 218, a conductor (conductor 185) that is electrically connected to the transistor 2000, and the like.
- the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 1000 or the transistor 3000.
- the conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.
- the insulator 210 and the conductor 218 in a region in contact with the insulator 102 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
- the transistor 3000 and the transistor 2000 can be reliably separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.
- a transistor 2000 is provided above the insulator 105 with an insulator 110 interposed therebetween. Note that as the structure of the transistor 2000, a transistor included in the semiconductor device described in the above embodiment may be used.
- the transistor 2000 illustrated in FIGS. 11A and 11B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
- An insulator 175, an insulator 176, and an insulator 178 are provided above the transistor 2000.
- the insulator 178 is preferably a film having a barrier property against oxygen or hydrogen. Therefore, the insulator 178 can be formed using a material similar to that of the insulator 102.
- the insulator 178 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
- aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000.
- an insulator 180 is provided on the insulator 178.
- the insulator 180 can be formed using a material similar to that of the insulator 320.
- a material having a relatively low dielectric constant for the insulator parasitic capacitance generated between wirings can be reduced.
- the insulator 180 silicon oxide, silicon oxynitride, or the like can be used.
- a conductor 246, a conductor 248, and the like are embedded in the insulator 110, the insulator 175, the insulator 176, the insulator 178, and the insulator 180.
- the conductor 246 and the conductor 248 have a function as a plug or a wiring electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000.
- the conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.
- a capacitor element 1000 is provided above the transistor 2000.
- the capacitor 1000 includes a conductor 1100, a conductor 1200, and an insulator 1300.
- the conductor 112 may be provided over the conductor 246 and the conductor 248.
- the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000.
- the conductor 1100 functions as an electrode of the capacitor 1000. Note that the conductor 112 and the conductor 1100 can be formed at the same time.
- the conductor 112 and the conductor 1100 include a metal containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride containing any of the above elements as a component (nitriding) (Tantalum, titanium nitride, molybdenum nitride, tungsten nitride) or the like can be used.
- indium tin oxide indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.
- FIG. 11 illustrates a structure in which the conductor 112 and the conductor 1100 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used.
- a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
- an insulator 1300 is provided as a dielectric of the capacitor 1000 over the conductor 112 and the conductor 1100.
- the insulator 1300 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like. What is necessary is just to use, and it can provide by lamination
- a material with high withstand voltage such as silicon oxynitride may be used.
- silicon oxynitride a material with high withstand voltage
- the dielectric breakdown resistance of the capacitive element 1000 is improved, and electrostatic breakdown of the capacitive element 1000 can be suppressed.
- a conductor 1200 is provided on the insulator 1300 so as to overlap with the conductor 1100.
- the conductor 1200 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.
- An insulator 1500 is provided over the conductor 1200 and the insulator 1300.
- the insulator 1500 can be provided using a material similar to that of the insulator 320.
- the insulator 1500 may function as a planarization film that covers the concave and convex shapes below the insulator 1500.
- the above is the description of the structure example of the memory device to which the semiconductor device according to one embodiment of the present invention is applied.
- a transistor including a metal oxide variation in electrical characteristics can be suppressed and reliability can be improved.
- a transistor including a metal oxide with high on-state current can be provided.
- a transistor including a metal oxide with low off-state current can be provided.
- a semiconductor device with reduced power consumption can be provided.
- NOSRAM Nonvolatile Oxide Semiconductor RAM
- 2T type, 3T type a memory device using an OS transistor such as NOSRAM
- OS memory a memory device using an OS transistor such as NOSRAM
- OS memory a memory device using an OS transistor for a memory cell (hereinafter referred to as “OS memory”) is applied.
- the OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
- FIG. 12 shows a configuration example of NOSRAM.
- a NOSRAM 1600 illustrated in FIG. 12 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670.
- the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
- the memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a plurality of bit lines BL, and a plurality of source lines SL.
- the word line WWL is a write word line
- the word line RWL is a read word line.
- one memory cell 1611 stores 3-bit (eight values) data.
- the controller 1640 comprehensively controls the entire NOSRAM 1600, and writes data WDA [31: 0] and reads data RDA [31: 0].
- the controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
- the row driver 1650 has a function of selecting a row to be accessed.
- the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
- the column driver 1660 drives the source line SL and the bit line BL.
- the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
- the DAC 1663 converts 3-bit digital data into analog voltage.
- the DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
- the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL.
- the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
- the selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672.
- the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
- FIG. 13A is a circuit diagram illustrating a structural example of the memory cell 1611.
- the memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, the word line RWL, the bit line BL, and the source line SL.
- the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61.
- the OS transistor MO61 is a write transistor.
- the transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor.
- the capacitive element C61 is a holding capacitor for holding the voltage of the node SN.
- the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
- the NOSRAM 1600 can hold data for a long time.
- the bit line is a common bit line for writing and reading.
- a writing bit line WBL and a reading bit line RBL may be provided. Good.
- FIGS. 13C to 13E show other configuration examples of the memory cell.
- FIGS. 13C to 13E show an example in which a write bit line and a read bit line are provided. As shown in FIG. 13A, a bit line shared by writing and reading is used. May be provided.
- a memory cell 1612 shown in FIG. 13C is a modified example of the memory cell 1611 in which a read transistor is changed to an n-channel transistor (MN61).
- the transistor MN61 may be an OS transistor or a Si transistor.
- a memory cell 1613 shown in FIG. 13D is a 3T type gain cell, and is electrically connected to the word line WWL, the word line RWL, the bit line WBL, the bit line RBL, the source line SL, and the wiring PCL.
- the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
- the OS transistor MO62 is a write transistor.
- the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
- a memory cell 1614 shown in FIG. 13E is a modified example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (MN62 and MN63).
- the transistors MN62 and MN63 may be OS transistors or Si transistors.
- the OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a bottom gate or a transistor with a bottom gate.
- the NOSRAM 1600 Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no limitation on the number of rewrites in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
- the transistor 2000 is used as the OS transistor MO61 and the OS transistor MO62
- the transistor 3000 is used as the transistor MP61 and the transistor MN62.
- the area occupied by the transistor in a top view can be reduced, so that the memory device according to this embodiment can be further highly integrated.
- the storage capacity per unit area of the storage device according to this embodiment can be increased.
- DOSRAM is described as an example of a memory device to which an OS transistor is applied according to one embodiment of the present invention, with reference to FIGS.
- DOSRAM registered trademark
- amic Oxide Semiconductor RAM is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells.
- OS memory is applied to DOSRAM as well as NOSRAM.
- FIG. 14 shows a configuration example of the DOSRAM.
- a DOSRAM 1400 illustrated in FIG. 14 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
- the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
- the column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417.
- the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
- the MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and a global bit line GBLR.
- the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
- the global bit line GBLL and the global bit line GBLR are stacked on the memory cell array 1422.
- a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
- the memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> to 1425 ⁇ N-1>.
- FIG. 15A illustrates a configuration example of the local memory cell array 1425.
- the local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a plurality of bit lines BLR.
- the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
- FIG. 15B shows a circuit configuration example of the memory cell 1445.
- the memory cell 1445 includes a transistor MW1, a capacitor CS1, and a terminal B1.
- the transistor MW1 has a function of controlling charging / discharging of the capacitor CS1.
- the gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitor CS1.
- the second terminal of the capacitive element CS1 is electrically connected to the terminal B1.
- a constant potential for example, a low power supply potential
- the transistor MW1 may be a transistor having a bottom gate.
- the transistor MW1 is a transistor having a bottom gate, for example, the bottom gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1.
- the sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> to 1426 ⁇ N-1>.
- the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
- a bit line pair is electrically connected to the sense amplifier 1446.
- the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference between the bit line pair, and a function of holding this potential difference.
- the switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
- bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier.
- a global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier.
- a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
- bit line BLL and the bit line BLR form one bit line pair.
- Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
- bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
- the controller 1405 has a function of controlling the overall operation of the DOSRAM 1400.
- the controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.
- the row circuit 1410 has a function of driving the MC-SA array 1420.
- the decoder 1411 has a function of decoding an address signal.
- the word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
- the column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
- the column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column.
- the switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413.
- the plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
- the column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0].
- the data signal WDA [31: 0] is a write data signal
- the data signal RDA [31: 0] is a read data signal.
- the global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR).
- the global sense amplifier 1447 has a function of amplifying a potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Data is written to and read from the global bit line pair (GBLL, GBLR) by an input / output circuit 1417.
- Data is written to the global bit line pair by the input / output circuit 1417.
- Data of the global bit line pair is held by the global sense amplifier array 1416.
- the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address.
- the local sense amplifier array 1426 amplifies and holds the written data.
- the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
- One row of the local memory cell array 1425 is designated by the address signal.
- the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line.
- the local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data.
- the switch array 1444 writes the data in the column specified by the address among the data held in the local sense amplifier array 1426 to the global bit line pair.
- the global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.
- the DOSRAM 1400 In order to rewrite data by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of rewrites in principle, and can write and read data with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
- the transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is much longer than that of a DRAM using a Si transistor. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the power consumption of the display controller IC and the source driver IC can be reduced by using the DOSRAM 1400 as a frame memory.
- the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reason, the load that is driven when accessing the DOSRAM 1400 is reduced, so that the energy consumption of the display controller IC and the source driver IC can be reduced.
- a field programmable gate array (FPGA) is described as an example of a semiconductor device to which a transistor using a metal oxide in a channel formation region (OS transistor) according to one embodiment of the present invention is applied.
- OS transistor channel formation region
- an OS memory is applied to the configuration memory and the register.
- OS-FPGA Such FPGA is referred to as “OS-FPGA”.
- the OS memory is a memory having at least a capacitive element and an OS transistor that controls charging / discharging of the capacitive element. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
- FIG. 16A shows a configuration example of the OS-FPGA.
- the OS-FPGA 3110 shown in FIG. 16A is capable of NOFF (normally off) computing that performs context switching by a multi-context structure and fine-grain power gating for each PLE.
- the OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.
- the programmable area 3115 has two input / output blocks (IOB) 3117 and a core (Core) 3119.
- the IOB 3117 has a plurality of programmable input / output circuits.
- the core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130.
- the LAB 3120 includes a plurality of PLE 3121s.
- FIG. 16B shows an example in which the LAB 3120 is composed of five PLE 3121s.
- the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array.
- the LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.
- SB3131 will be described with reference to FIGS. 17 (A) to 17 (C).
- Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG.
- data and datab are configuration data, and data and datab have a complementary logic relationship.
- the number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal.
- the signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.
- the SB 3131 includes a PRS (programmable routing switch) 3133 [0] and a PRS 3133 [1].
- the PRS 3133 [0] and the PRS 3133 [1] have a configuration memory (CM) that can store complementary data.
- CM configuration memory
- PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.
- FIG. 17B illustrates a circuit configuration example of PRS3133 [0].
- PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration.
- PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal.
- the signal context [0] and the signal word [0] are input to the PRS 3133 [0]
- the signal context [1] and the signal word [1] are input to the PRS 3133 [1].
- the PRS 3133 [0] becomes active.
- PRS3133 [0] has CM3135 and Si transistor M31.
- the Si transistor M31 is a pass transistor controlled by the CM 3135.
- the CM 3135 includes a memory circuit 3137 and a memory circuit 3137B.
- the memory circuit 3137 and the memory circuit 3137B have the same circuit configuration.
- the memory circuit 3137 includes a capacitor C31, an OS transistor MO31, and an OS transistor MO32.
- the memory circuit 3137B includes a capacitor CB31, an OS transistor MOB31, and an OS transistor MOB32.
- the OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 may have a bottom gate.
- the bottom gates may be electrically connected to power supply lines that supply a fixed potential. .
- the gate of the Si transistor M31 is the node N31
- the gate of the OS transistor MO32 is the node N32
- the gate of the OS transistor MOB32 is the node NB32.
- the nodes N32 and NB32 are charge holding nodes of the CM 3135.
- the OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0].
- the OS transistor MOB32 controls the conduction state between the node N31 and the low potential power supply line VSS.
- the logic of data held in the memory circuit 3137 and the memory circuit 3137B has a complementary relationship. Therefore, either the OS transistor MO32 or the OS transistor MOB32 becomes conductive.
- the PRS 3133 [0] While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.
- the PRS 3133 [0] is active.
- the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
- the OS transistor MO32 of the memory circuit 3137 is a source follower, and therefore the gate potential of the Si transistor M31 is increased by boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
- the CM 3135 also has a multiplexer function.
- FIG. 18 shows a configuration example of the PLE 3121.
- the PLE 3121 includes an LUT (look-up table) block 3123, a register block 3124, a selector 3125, and a CM 3126.
- the LUT block (LUT block) 3123 is configured to select and output data according to input inA-inD.
- the selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.
- the PLE 3121 is electrically connected to the power line for the potential VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
- the register block 3124 is composed of a nonvolatile register.
- the nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as “OS-FF”) including an OS memory.
- the register block 3124 includes OS-FF 3140 [1] and OS-FF 3140 [2].
- the signal user_res, the signal load, and the signal store are input to the OS-FF 3140 [1] and the OS-FF 3140 [2].
- the clock signal CLK1 is input to the OS-FF 3140 [1]
- the clock signal CLK2 is input to the OS-FF 3140 [2].
- FIG. 19A illustrates a configuration example of the OS-FF 3140.
- the OS-FF 3140 includes an FF 3141 and a shadow register 3142.
- the FF 3141 includes a node CK, a node R, a node D, a node Q, and a node QB.
- a clock signal is input to the node CK.
- a signal user_res is input to the node R.
- the signal user_res is a reset signal.
- Node D is a data input node
- node Q is a data output node.
- the node Q and the node QB have a complementary logic relationship.
- the shadow register 3142 functions as a backup circuit for the FF 3141.
- the shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
- the shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, an Si transistor M37, an Si transistor MB37, a memory circuit 3143, and a memory circuit 3143B.
- the memory circuit 3143 and the memory circuit 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133.
- the memory circuit 3143 includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36.
- the memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36.
- the node N36 and the node NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes.
- the nodes N37 and NB37 are the gates of the Si transistor M37 and the Si transistor MB37.
- the OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 may have a bottom gate.
- the bottom gates may be electrically connected to power supply lines that supply fixed potentials. .
- the power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.
- the power consumption of the OS-FPGA 3110 can be effectively reduced.
- An error that can occur in a memory circuit is a soft error due to the incidence of radiation.
- a soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair.
- An OS memory using an OS transistor has high soft error resistance. Therefore, the OS-FPGA 3110 with high reliability can be provided by installing the OS memory.
- a semiconductor device 5400 illustrated in FIG. 20 includes a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422.
- the power management unit 5421 includes a power controller (Power Controller) 5402 and a power switch (Power Switch) 5403.
- the peripheral circuit 5422 includes a cache 5404 having a cache memory, a bus interface (BUS I / F) 5405, and a debug interface (Debug I / F) 5406.
- the CPU core 5401 includes a data bus 5423, a control unit (Control Unit) 5407, a PC (Program Counter) 5408, a pipeline register (Pipeline Register) 5409, a pipeline register 5410, an ALU (Arithmetic logic unit) 5411, and a register file ( (Register File) 5412. Data exchange between the CPU core 5401 and the peripheral circuit 5422 such as the cache 5404 is performed via the data bus 5423.
- Control Unit Control Unit
- PC Program Counter
- Pipeline Register Pipeline Register
- ALU Arimetic logic unit
- register file (Register File) 5412.
- Data exchange between the CPU core 5401 and the peripheral circuit 5422 such as the cache 5404 is performed via the data bus 5423.
- the semiconductor device can be applied to many logic circuits including the power controller 5402 and the control device 5407.
- the present invention can be applied to all logic circuits that can be configured using standard cells.
- a small semiconductor device 5400 can be provided.
- a semiconductor device 5400 that can reduce power consumption can be provided.
- a semiconductor device 5400 that can increase the operation speed can be provided.
- a semiconductor device 5400 that can reduce fluctuations in power supply voltage can be provided.
- a p-channel Si transistor and a transistor including the metal oxide described in the above embodiment (preferably, an oxide containing In, Ga, and Zn) in a channel formation region are used for a semiconductor device (cell).
- a semiconductor device (cell) By applying the semiconductor device (cell) to the semiconductor device 5400, a small semiconductor device 5400 can be provided.
- a semiconductor device 5400 that can reduce power consumption can be provided.
- a semiconductor device 5400 that can increase the operation speed can be provided. In particular, manufacturing costs can be reduced by using only p-channel Si transistors.
- the control device 5407 controls the operations of the PC 5408, the pipeline register 5409, the pipeline register 5410, the ALU 5411, the register file 5412, the cache 5404, the bus interface 5405, the debug interface 5406, and the power controller 5402 so that the input is performed.
- a function of decoding and executing an instruction included in a program such as an executed application.
- the ALU 5411 has a function of performing various arithmetic processes such as four arithmetic operations and logical operations.
- the cache 5404 has a function of temporarily storing frequently used data.
- the PC 5408 is a register having a function of storing an address of an instruction to be executed next.
- the cache 5404 is provided with a cache controller that controls the operation of the cache memory.
- Pipeline register 5409 is a register having a function of temporarily storing instruction data.
- the register file 5412 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 5411, and the like.
- the pipeline register 5410 is a register having a function of temporarily storing data used for the arithmetic processing of the ALU 5411 or data obtained as a result of the arithmetic processing of the ALU 5411.
- the bus interface 5405 has a function as a data path between the semiconductor device 5400 and various devices outside the semiconductor device 5400.
- the debug interface 5406 has a function as a signal path for inputting an instruction for controlling debugging to the semiconductor device 5400.
- the power switch 5403 has a function of controlling supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400.
- the various circuits belong to several power domains, and the power switches 5403 control whether the various circuits belonging to the same power domain are supplied with a power supply voltage.
- the power controller 5402 has a function of controlling the operation of the power switch 5403.
- the semiconductor device 5400 having the above structure can perform power gating.
- the flow of power gating operation will be described with an example.
- the CPU core 5401 sets the timing of stopping the supply of the power supply voltage in the register of the power controller 5402.
- an instruction to start power gating is sent from the CPU core 5401 to the power controller 5402.
- various registers and the cache 5404 included in the semiconductor device 5400 start data saving.
- supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 is stopped by the power switch 5403.
- an interrupt signal is input to the power controller 5402
- supply of power supply voltage to various circuits included in the semiconductor device 5400 is started.
- a counter may be provided in the power controller 5402 so that the timing at which the supply of the power supply voltage is started is determined using the counter regardless of the input of the interrupt signal.
- the various registers and the cache 5404 start data restoration.
- the execution of the instruction in the control device 5407 is resumed.
- Such power gating can be performed in the entire processor or in one or a plurality of logic circuits constituting the processor. Further, power supply can be stopped even in a short time. For this reason, power consumption can be reduced with fine granularity spatially or temporally.
- a flip-flop circuit or SRAM cell that can be backed up preferably includes a transistor including a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region.
- a flip-flop circuit or an SRAM cell that can be backed up can hold information without power supply for a long time.
- a flip-flop circuit or an SRAM cell that can be backed up may be able to save and restore data in a short time.
- the semiconductor device 5500 shown in FIG. 21 is an example of a flip-flop circuit that can be backed up.
- the semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, a third memory circuit 5503, and a reading circuit 5504.
- a potential difference between the potential V1 and the potential V2 is supplied to the semiconductor device 5500 as a power supply voltage.
- One of the potential V1 and the potential V2 is at a high level, and the other is at a low level.
- a configuration example of the semiconductor device 5500 will be described by using as an example the case where the potential V1 is low level and the potential V2 is high level.
- the first memory circuit 5501 has a function of holding data when a signal D including data is input in a period in which the power supply voltage is supplied to the semiconductor device 5500. In the period when the power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 5501 outputs a signal Q including retained data. On the other hand, the first memory circuit 5501 cannot hold data in a period in which the power supply voltage is not supplied to the semiconductor device 5500. That is, the first memory circuit 5501 can be called a volatile memory circuit.
- the second memory circuit 5502 has a function of reading and storing (or saving) data held in the first memory circuit 5501.
- the third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502.
- the reading circuit 5504 has a function of reading data stored in the second memory circuit 5502 or the third memory circuit 5503 and storing (or returning) the data in the first memory circuit 5501.
- the third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502 even during a period in which the power supply voltage is not supplied to the semiconductor device 5500. Have.
- the second memory circuit 5502 includes a transistor 5512 and a capacitor 5519.
- the third memory circuit 5503 includes a transistor 5513, a transistor 5515, and a capacitor 5520.
- the reading circuit 5504 includes a transistor 5510, a transistor 5518, a transistor 5509, and a transistor 5517.
- the transistor 5512 has a function of charging and discharging the capacitor 5519 with electric charge corresponding to data stored in the first memory circuit 5501.
- the transistor 5512 can charge and discharge the capacitor 5519 with charge according to data stored in the first memory circuit 5501 at high speed.
- the transistor 5512 preferably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in a channel formation region.
- the transistor 5513 is selected to be in a conductive state or a non-conductive state in accordance with the charge held in the capacitor 5519.
- the transistor 5515 has a function of charging and discharging the capacitor 5520 with a charge corresponding to the potential of the wiring 5544 when the transistor 5513 is in a conductive state.
- the transistor 5515 preferably has extremely low off-state current.
- the transistor 5515 preferably includes a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region.
- One of the source and the drain of the transistor 5512 is connected to the first memory circuit 5501.
- the other of the source and the drain of the transistor 5512 is connected to one electrode of the capacitor 5519, the gate of the transistor 5513, and the gate of the transistor 5518.
- the other electrode of the capacitor 5519 is connected to the wiring 5542.
- One of a source and a drain of the transistor 5513 is connected to the wiring 5544.
- the other of the source and the drain of the transistor 5513 is connected to one of the source and the drain of the transistor 5515.
- the other of the source and the drain of the transistor 5515 is connected to one electrode of the capacitor 5520 and the gate of the transistor 5510.
- the other electrode of the capacitor 5520 is connected to the wiring 5543.
- One of a source and a drain of the transistor 5510 is connected to the wiring 5541.
- the other of the source and the drain of the transistor 5510 is connected to one of the source and the drain of the transistor 5518.
- the other of the source and the drain of the transistor 5518 is connected to one of the source and the drain of the transistor 5509.
- the other of the source and the drain of the transistor 5509 is connected to one of the source and the drain of the transistor 5517 and the first memory circuit 5501.
- the other of the source and the drain of the transistor 5517 is connected to the wiring 5540.
- the gate of the transistor 5509 is connected to the gate of the transistor 5517; however, the gate of the transistor 5509 is not necessarily connected to the gate of the transistor 5517.
- the transistor illustrated in the above embodiment can be used as the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can hold information without supplying power for a long time. Since the switching characteristics of the transistor 5515 are favorable, the semiconductor device 5500 can perform high-speed backup and recovery.
- FIG. 22A shows a top view of the substrate 711 before the dicing process is performed.
- a semiconductor substrate also referred to as a “semiconductor wafer”
- a plurality of circuit regions 712 are provided on the substrate 711.
- the circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.
- the plurality of circuit regions 712 are each surrounded by a separation region 713.
- a separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711.
- FIG. 22B shows an enlarged view of the chip 715.
- a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713.
- ESD Electro-Static Discharge
- the dicing process is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, preventing charging, and the like.
- the amount of pure water used can be reduced.
- the productivity of the semiconductor device can be increased.
- Electrodes An example of an electronic component using the chip 715 will be described with reference to FIGS. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.
- the electronic component is completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).
- a “back surface grinding step” of grinding the back surface of the substrate 711 (a surface where the semiconductor device or the like is not formed) is performed (step S721). ).
- the electronic component can be downsized.
- a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722).
- a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723).
- a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.
- a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724).
- a silver wire, a gold wire, etc. can be used for a metal fine wire.
- wire bonding for example, ball bonding or wedge bonding can be used.
- the wire-bonded chip 715 is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725).
- a sealing process molding process
- the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and the electrical characteristics are degraded by moisture, dust, etc. ( (Decrease in reliability) can be reduced.
- a “lead plating process” for plating the leads of the lead frame is performed (step S726).
- the plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably.
- a “molding process” for cutting and molding the lead is performed (step S727).
- a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728).
- An electronic component is completed through an “inspection step” (step S729) for checking the appearance shape and the presence / absence of operation failure.
- FIG. 23B shows a schematic perspective view of the completed electronic component.
- FIG. 23B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component.
- An electronic component 750 illustrated in FIG. 23B includes a lead 755 and a chip 715.
- the electronic component 750 may have a plurality of chips 715.
- the 23B is mounted on a printed board 752, for example.
- a plurality of such electronic components 750 are combined and electrically connected to each other on the printed circuit board 752, whereby a substrate (mounting substrate 754) on which the electronic components are mounted is completed.
- the completed mounting board 754 is used for an electronic device or the like.
- FIG. 24 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
- FIG. 24A is an external view showing an example of an automobile.
- the automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.
- the automobile 2980 includes an antenna, a battery, and the like.
- An information terminal 2910 illustrated in FIG. 24B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like.
- the display portion 2912 includes a display panel using a flexible substrate and a touch screen.
- the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911.
- the information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
- a laptop personal computer 2920 shown in FIG. 24C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.
- the laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
- a video camera 2940 illustrated in FIG. 24D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like.
- the operation switch 2944 and the lens 2945 are provided in the housing 2941
- the display portion 2944 is provided in the housing 2942.
- the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941.
- the housing 2941 and the housing 2942 are connected to each other by a connection portion 2946.
- the angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946.
- the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.
- FIG. 24E illustrates an example of a bangle type information terminal.
- the information terminal 2950 includes a housing 2951, a display portion 2952, and the like.
- the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951.
- the display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.
- FIG. 24F shows an example of a wristwatch type information terminal.
- the information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like.
- the information terminal 2960 includes an antenna, a battery, and the like inside the housing 2961.
- the information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.
- the display surface of the display unit 2962 is curved, and display can be performed along the curved display surface.
- the display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like.
- an application can be started by touching an icon 2967 displayed on the display unit 2962.
- the operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and cancellation, and power saving mode execution and cancellation. .
- the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.
- the information terminal 2960 can execute short-range wireless communication with a communication standard. For example, a hands-free call can be made by communicating with a headset capable of wireless communication.
- the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector.
- charging can be performed through the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.
- a memory device using the semiconductor device of one embodiment of the present invention can hold the above-described control information of an electronic device, a control program, and the like for a long time.
- a highly reliable electronic device can be realized.
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Abstract
Provided is a semiconductor device enabling smaller device size and higher integration. The semiconductor device comprises: a first conductor; a first insulator on the first conductor; a second conductor on the first insulator; an oxide comprising an area that contacts the side surface of the second conductor, the first insulator and the first conductor; a second insulator on the oxide; and a third conductor on the second insulator, wherein the second insulator comprises an area that faces, with the oxide lying there-between, the side surface of the second conductor, the first insulator and the first conductor, and the third conductor comprises an area that faces, with the oxide and the second insulator lying there-between, the side surface of the second conductor, the first insulator and the first conductor.
Description
本発明の一態様は、半導体装置に関する。
One embodiment of the present invention relates to a semiconductor device.
なお、本明細書等において半導体装置とは、半導体特性を利用することで機能し得る装置全般を指す。トランジスタなどの半導体素子をはじめ、半導体回路、演算装置、記憶装置は、半導体装置の一態様である。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、及び電子機器などは、半導体装置を有するといえる場合がある。
Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may have a semiconductor device. .
なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様は、物、方法、又は、製造方法に関するものである。又は、本発明の一態様は、プロセス、マシン、マニュファクチャ、又は、組成物（コンポジション・オブ・マター）に関するものである。
Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
半導体薄膜を用いてトランジスタを構成する技術が注目されている。当該トランジスタは、集積回路（ＩＣ）や画像表示装置（単に表示装置とも表記する。）等の電子デバイスに広く応用されている。トランジスタに適用可能な半導体薄膜としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。
A technology for forming a transistor using a semiconductor thin film has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.
例えば、酸化物半導体として、酸化亜鉛、又はＩｎ−Ｇａ−Ｚｎ酸化物をチャネル形成領域に有するトランジスタを用いて、表示装置を作製する技術が開示されている（特許文献１及び特許文献２参照。）。
For example, a technique for manufacturing a display device using a transistor including zinc oxide or an In—Ga—Zn oxide in a channel formation region as an oxide semiconductor is disclosed (see Patent Documents 1 and 2). ).
さらに近年、酸化物半導体を有するトランジスタを用いて、記憶装置の集積回路を作製する技術が公開されている（特許文献３参照。）。また、記憶装置だけでなく、演算装置等も、酸化物半導体を有するトランジスタによって作製されてきている。
In recent years, a technique for manufacturing an integrated circuit of a memory device using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3). In addition to memory devices, arithmetic devices and the like have been manufactured using transistors including oxide semiconductors.
ところで、電子機器の高性能化、小型化、軽量化に伴い、集積回路は高集積化され、トランジスタのサイズは微細化している。これに従って、トランジスタ作製のプロセスルールも、４５ｎｍ、３２ｎｍ、２２ｎｍと年々小さくなっている。これに伴い、酸化物半導体を有するトランジスタも、微細な構造において、設計通り良好な電気特性を有するものが求められている。
By the way, as electronic devices become more sophisticated, smaller, and lighter, integrated circuits are highly integrated and transistors are becoming smaller in size. In accordance with this, process rules for manufacturing transistors are also decreasing year by year, such as 45 nm, 32 nm, and 22 nm. Accordingly, a transistor including an oxide semiconductor is required to have a fine structure and good electrical characteristics as designed.
本発明の一態様は、微細化又は高集積化が可能な半導体装置を提供することを課題の一つとする。又は、本発明の一態様は、良好な電気特性を有する半導体装置を提供することを課題の一つとする。又は、本発明の一態様は、オフ電流の小さい半導体装置を提供することを課題の一とする。又は、本発明の一態様は、オン電流の大きい半導体装置を提供することを課題の一とする。又は、本発明の一態様は、基板面内の電気特性ばらつきが小さい半導体装置を提供することを課題の一とする。又は、本発明の一態様は、信頼性の高い半導体装置を提供することを課題の一つとする。又は、本発明の一態様は、消費電力が低減された半導体装置を提供することを課題の一つとする。又は、本発明の一態様は、設計自由度が高い半導体装置を提供することを課題の一とする。又は、本発明の一態様は、生産性の高い半導体装置を提供することを課題の一つとする。又は、本発明の一態様は、新規な半導体装置を提供することを課題の一とする。
An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device in which variation in electrical characteristics in a substrate surface is small. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. Another object of one embodiment of the present invention is to provide a highly productive semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.
なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。
Note that the description of these issues does not disturb the existence of other issues. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.
本発明の一態様は、第１の導電体と、第１の導電体上の第１の絶縁体と、第１の絶縁体上の第２の導電体と、第１の導電体、第１の絶縁体、及び第２の導電体の側面と接する領域を有する酸化物と、酸化物上の第２の絶縁体と、第２の絶縁体上の第３の導電体と、を有し、第２の絶縁体は、酸化物を介して、第１の導電体、第１の絶縁体、及び第２の導電体の側面と向かい合う領域を有し、第３の導電体は、酸化物及び第２の絶縁体を介して、第１の導電体、第１の絶縁体、及び第２の導電体の側面と向かい合う領域を有する、半導体装置である。
One embodiment of the present invention includes a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, the first conductor, And an oxide having a region in contact with a side surface of the second conductor, a second insulator on the oxide, and a third conductor on the second insulator, The second insulator has a region facing the side surfaces of the first conductor, the first insulator, and the second conductor through the oxide, and the third conductor includes the oxide and The semiconductor device includes a first conductor, a first insulator, and a region facing a side surface of the second conductor via a second insulator.
また、上記態様において、第１の導電体、第１の絶縁体、及び第２の導電体は、第３の絶縁体で覆われ、第３の絶縁体は開口を有し、酸化物、第２の絶縁体、及び第３の導電体は、開口を埋め込むように形成されていてもよい。
In the above embodiment, the first conductor, the first insulator, and the second conductor are covered with a third insulator, and the third insulator has an opening, an oxide, The second insulator and the third conductor may be formed so as to fill the opening.
また、上記態様において、酸化物は、第２の導電体の上面と接する領域を有し、第２の絶縁体は、酸化物を介して、第２の導電体の上面と重なる領域を有し、第３の導電体は、酸化物及び第２の絶縁体を介して、第２の導電体の上面と重なる領域を有していてもよい。
In the above embodiment, the oxide has a region in contact with the upper surface of the second conductor, and the second insulator has a region overlapping with the upper surface of the second conductor through the oxide. The third conductor may have a region overlapping with the upper surface of the second conductor with the oxide and the second insulator interposed therebetween.
また、上記態様において、第１の絶縁体の膜厚は、１ｎｍ以上１００ｎｍ以下であってもよい。
In the above aspect, the film thickness of the first insulator may be 1 nm or more and 100 nm or less.
また、上記態様において、酸化物は、金属酸化物を含んでいてもよい。
In the above embodiment, the oxide may contain a metal oxide.
本発明の一態様により、微細化又は高集積化が可能な半導体装置を提供することができる。又は、本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。又は、本発明の一態様により、オフ電流の小さい半導体装置を提供することができる。又は、本発明の一態様により、オン電流の大きい半導体装置を提供することができる。又は、本発明の一態様により、基板面内の電気特性ばらつきが小さい半導体装置を提供することができる。又は、本発明の一態様により、信頼性の高い半導体装置を提供することができる。又は、本発明の一態様により、消費電力が低減された半導体装置を提供することができる。又は、本発明の一態様により、設計自由度が高い半導体装置を提供することができる。又は、本発明の一態様により、生産性の高い半導体装置を提供することができる。又は、本発明の一態様により、新規な半導体装置を提供することができる。
According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device in which variation in electric characteristics in a substrate surface is small can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high design freedom can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.
なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。
Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.
以下、実施の形態について図面を参照しながら説明する。ただし、実施の形態は多くの異なる態様で実施することが可能であり、趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは、当業者であれば容易に理解される。したがって、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。
Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms, and that the forms and details can be variously changed without departing from the spirit and scope thereof. The Therefore, the present invention should not be construed as being limited to the description of the following embodiments.
また、図面において、大きさ、層の厚さ、又は領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。なお、図面は、理想的な例を模式的に示したものであり、図面に示す形状又は値などに限定されない。例えば、実際の製造工程において、エッチングなどの処理により層やレジストマスクなどが意図せずに目減りすることがあるが、理解を容易とするために省略して示すことがある。また、図面において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する場合がある。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。
In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawing schematically shows an ideal example, and is not limited to the shape or value shown in the drawing. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.
また、特に上面図（「平面図」ともいう。）や斜視図などにおいて、発明の理解を容易とするため、一部の構成要素の記載を省略する場合がある。また、一部の隠れ線などの記載を省略する場合がある。
In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may be omitted in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.
また、本明細書等において、第１、第２等として付される序数詞は便宜上用いるものであり、工程順又は積層順を示すものではない。そのため、例えば、「第１の」を「第２の」又は「第３の」などと適宜置き換えて説明することができる。また、本明細書等に記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。
In the present specification and the like, the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
また、本明細書等において、「上に」、「下に」などの配置を示す語句は、構成同士の位置関係を、図面を参照して説明するために、便宜上用いている。また、構成同士の位置関係は、各構成を描写する方向に応じて適宜変化するものである。したがって、明細書で説明した語句に限定されず、状況に応じて適切に言い換えることができる。
In addition, in this specification and the like, terms indicating arrangements such as “above” and “below” are used for convenience in order to explain the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.
また、本明細書等において、「平行」とは、二つの直線が−１０°以上１０°以下の角度で配置されている状態をいう。したがって、−５°以上５°以下の場合も含まれる。また、「略平行」とは、二つの直線が−３０°以上３０°以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０°以上１００°以下の角度で配置されている状態をいう。したがって、８５°以上９５°以下の場合も含まれる。また、「略垂直」とは、二つの直線が６０°以上１２０°以下の角度で配置されている状態をいう。
In addition, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
また、本明細書等において、トランジスタとは、ゲートと、ドレインと、ソースとを含む少なくとも三つの端子を有する素子である。そして、ドレイン（ドレイン端子、ドレイン領域又はドレイン電極）とソース（ソース端子、ソース領域又はソース電極）の間にチャネル形成領域を有しており、チャネル形成領域を介して、ソースとドレインとの間に電流を流すことができるものである。なお、本明細書等において、チャネル形成領域とは、電流が主として流れる領域をいう。
In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. In addition, a channel formation region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and between the source and the drain through the channel formation region. It is possible to pass a current through. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.
また、ソースやドレインの機能は、異なる極性のトランジスタを採用する場合や、回路動作において電流の方向が変化する場合などには入れ替わることがある。このため、本明細書等においては、ソースやドレインの用語は、入れ替えて用いることができる場合がある。
Also, the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
なお、トランジスタにおけるチャネル長とは、例えば、半導体（又はトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、又はチャネルが形成される領域における、ソース（ソース領域又はソース電極）とドレイン（ドレイン領域又はドレイン電極）との間の距離をいう。なお、一つのトランジスタにおいて、チャネル長が全ての領域で同じ値をとるとは限らない。すなわち、一つのトランジスタのチャネル長は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル長は、チャネルの形成される領域における、いずれか一の値、最大値、最小値又は平均値とする。
Note that the channel length in a transistor means, for example, a source (in a region where a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed) A distance between a source region or source electrode) and a drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
また、本明細書等において、酸化窒化シリコン膜とは、その組成として、窒素よりも酸素の含有量が多い膜を指し、窒化酸化シリコン膜とは、その組成として、酸素よりも窒素の含有量が多い膜を指す。
In this specification and the like, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as the composition, and a silicon nitride oxide film has a nitrogen content as compared to oxygen as a composition. Refers to membranes with a lot of
また、本明細書等において、金属酸化物（ｍｅｔａｌ ｏｘｉｄｅ）とは、広い表現での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む。）、酸化物半導体（Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ又は単にＯＳともいう。）などに分類される。例えば、トランジスタのチャネル形成領域に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。つまり、金属酸化物が増幅作用、整流作用、及びスイッチング作用の少なくとも１つを有する場合、当該金属酸化物を、金属酸化物半導体（ｍｅｔａｌ ｏｘｉｄｅ ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、略してＯＳと呼ぶことができる。また、ＯＳ ＦＥＴあるいはＯＳトランジスタと記載する場合においては、金属酸化物又は酸化物半導体を有するトランジスタと換言することができる。
In addition, in this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS). For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. In addition, in the case of describing an OS FET or an OS transistor, it can be said to be a transistor including a metal oxide or an oxide semiconductor.
また、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。
In addition, in this specification and the like, metal oxides having nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.
また、本明細書等において、ＣＡＡＣ（Ｃ−Ａｘｉｓ Ａｌｉｇｎｅｄ Ｃｒｙｓｔａｌ）、及びＣＡＣ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ Ｃｏｍｐｏｓｉｔｅ）と記載する場合がある。なお、ＣＡＡＣは結晶構造の一例を表し、ＣＡＣは機能、又は材料の構成の一例を表す。
Also, in this specification and the like, there are cases where they are described as CAAC (C-Axis Aligned Crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.
また、本明細書等において、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅとは、材料の一部では導電性の機能を有し、材料の一部では絶縁性の機能を有し、材料の全体では半導体としての機能を有する。なお、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅを、トランジスタのチャネル形成領域に用いる場合、導電性の機能は、キャリアとなる電子（又は正孔）を流す機能であり、絶縁性の機能は、キャリアとなる電子（又は正孔）を流さない機能である。導電性の機能と、絶縁性の機能とを、それぞれ相補的に作用させることで、スイッチングさせる機能（Ｏｎ／Ｏｆｆさせる機能）をＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅに付与することができる。ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅにおいて、それぞれの機能を分離させることで、双方の機能を最大限に高めることができる。
In this specification and the like, a CAC-OS or a CAC-metal oxide has a conductive function in part of a material, an insulating function in part of the material, and a semiconductor in the whole material. As a function. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is This is a function of preventing electrons (or holes) from flowing. A function of switching (a function of turning on / off) can be imparted to the CAC-OS or the CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.
また、本明細書等において、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅは、導電性領域、及び絶縁性領域を有する。導電性領域は、上述の導電性の機能を有し、絶縁性領域は、上述の絶縁性の機能を有する。また、材料中において、導電性領域と、絶縁性領域とは、ナノ粒子レベルで分離している場合がある。また、導電性領域と、絶縁性領域とは、それぞれ材料中に偏在する場合がある。また、導電性領域は、周辺がぼけてクラウド状に連結して観察される場合がある。
In this specification and the like, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.
また、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅにおいて、導電性領域と、絶縁性領域とは、それぞれ０．５ｎｍ以上１０ｎｍ以下、好ましくは０．５ｎｍ以上３ｎｍ以下のサイズで材料中に分散している場合がある。
In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
また、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅは、異なるバンドギャップを有する成分により構成される。例えば、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅは、絶縁性領域に起因するワイドギャップを有する成分と、導電性領域に起因するナローギャップを有する成分と、により構成される。当該構成の場合、キャリアを流す際に、ナローギャップを有する成分において、主にキャリアが流れる。また、ナローギャップを有する成分が、ワイドギャップを有する成分に相補的に作用し、ナローギャップを有する成分に連動してワイドギャップを有する成分にもキャリアが流れる。このため、上記ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅをトランジスタのチャネル形成領域に用いる場合、トランジスタのオン状態において高い電流駆動力、つまり大きなオン電流、及び高い電界効果移動度を得ることができる。
Also, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
すなわち、ＣＡＣ−ＯＳ又はＣＡＣ−ｍｅｔａｌ ｏｘｉｄｅは、マトリックス複合材（ｍａｔｒｉｘ ｃｏｍｐｏｓｉｔｅ）、又は金属マトリックス複合材（ｍｅｔａｌ ｍａｔｒｉｘ ｃｏｍｐｏｓｉｔｅ）と呼称することもできる。
That is, CAC-OS or CAC-metal oxide can also be called a matrix composite (metal matrix composite) or a metal matrix composite (metal matrix composite).
また、本明細書等において、「膜」という用語と、「層」という用語とは、互いに入れ替えることが可能である。例えば、「導電層」という用語を、「導電膜」という用語に変更することが可能な場合がある。又は、例えば、「絶縁膜」という用語を、「絶縁層」という用語に変更することが可能な場合がある。
In addition, in this specification and the like, the terms “film” and “layer” can be interchanged. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer”.
また、本明細書等において、「絶縁体」という用語を、絶縁膜又は絶縁層と言い換えることができる。また、「導電体」という用語を、導電膜又は導電層と言い換えることができる。また、「半導体」という用語を、半導体膜又は半導体層と言い換えることができる。
In this specification and the like, the term “insulator” can be referred to as an insulating film or an insulating layer. In addition, the term “conductor” can be referred to as a conductive film or a conductive layer. The term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
また、本明細書等に示すトランジスタは、明示されている場合を除き、電界効果トランジスタとする。また、本明細書等に示すトランジスタは、明示されている場合を除き、ｎチャネル型のトランジスタとする。よって、その閾値電圧（「Ｖｔｈ」ともいう。）は、明示されている場合を除き、０Ｖよりも大きいものとする。
Further, the transistors described in this specification and the like are field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.
（実施の形態１）
＜半導体装置の構成例１＞
以下では、本発明の一態様に係るトランジスタ１０を有する半導体装置の構成例について、図１を用いて説明する。 (Embodiment 1)
<Configuration Example 1 of Semiconductor Device>
A structure example of a semiconductor device including thetransistor 10 according to one embodiment of the present invention is described below with reference to FIGS.
＜半導体装置の構成例１＞
以下では、本発明の一態様に係るトランジスタ１０を有する半導体装置の構成例について、図１を用いて説明する。 (Embodiment 1)
<Configuration Example 1 of Semiconductor Device>
A structure example of a semiconductor device including the
図１（Ａ）は、トランジスタ１０を有する半導体装置の上面図である。また、図１（Ｂ）は、図１（Ａ）にＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図１（Ｃ）は、図１（Ａ）にＡ３−Ａ４の一点鎖線で示す部位の断面図である。ここで、Ａ１−Ａ２の一点鎖線で示す部位と、Ａ３−Ａ４の一点鎖線で示す部位とは、互いに直交している。図１（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。
FIG. 1A is a top view of a semiconductor device having a transistor 10. FIG. 1B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. FIG. 1C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. Here, the portion indicated by the one-dot chain line of A1-A2 and the portion indicated by the one-dot chain line of A3-A4 are orthogonal to each other. In the top view of FIG. 1A, some elements are omitted for clarity.
本発明の一態様の半導体装置は、基板（図示しない。）上に、トランジスタ１０と、層間膜として機能する絶縁体１００、絶縁体１０２、絶縁体１０５、絶縁体１１０、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０と、を有する。また、トランジスタ１０と電気的に接続し、配線として機能する導電体１８５、及び導電体２００、並びにプラグとして機能する導電体１９０、及び導電体１９５を有する。
The semiconductor device of one embodiment of the present invention includes a transistor 10 and an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as an interlayer film over a substrate (not illustrated). 176, an insulator 178, and an insulator 180. In addition, the conductor 185 and the conductor 200 which are electrically connected to the transistor 10 and function as wirings, and the conductor 190 and the conductor 195 which function as plugs are included.
導電体１８５は、絶縁体１０５に設けられた開口内に形成される。ここで、導電体１８５の上面の高さと、絶縁体１０５の上面の高さは、同程度であることが好ましい。なお、図１（Ｂ）では、導電体１８５を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、導電体１８５は、２層以上の積層構造であってもよい。
The conductor 185 is formed in an opening provided in the insulator 105. Here, the height of the upper surface of the conductor 185 and the height of the upper surface of the insulator 105 are preferably approximately the same. Note that although the conductor 185 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto. For example, the conductor 185 may have a stacked structure of two or more layers.
導電体１９０は、絶縁体１１０に設けられた開口内に形成される。導電体１９０の底面は、導電体１８５の上面と接する領域を有するように設けられる。ここで、導電体１９０の上面の高さと、絶縁体１１０の上面の高さは、同程度であることが好ましい。なお、図１（Ｂ）では、導電体１９０を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、導電体１９０は、絶縁体１１０に設けられた開口の内壁に接して、水素や水などの不純物、及び酸素の透過を抑制する材料からなる導電体を形成し、当該導電体上に、当該導電体よりも導電率の高い材料からなる導電体を形成した２層以上の積層構造であってもよい。
The conductor 190 is formed in an opening provided in the insulator 110. The bottom surface of the conductor 190 is provided so as to have a region in contact with the top surface of the conductor 185. Here, the height of the upper surface of the conductor 190 and the height of the upper surface of the insulator 110 are preferably approximately the same. Note that although the conductor 190 is illustrated as a single layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto. For example, the conductor 190 is in contact with the inner wall of the opening provided in the insulator 110 to form a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen, and the conductor 190 is formed over the conductor. A laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed may be used.
導電体１９５は、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０に設けられた、導電体１４０の上面に達する開口内に形成される。ここで、導電体１９５の上面の高さと、絶縁体１８０の上面の高さは、同程度であることが好ましい。なお、図１（Ｂ）では、導電体１９５を単層構造として示しているが、本発明の一態様はこれに限られない、例えば、導電体１９５は、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０に設けられた開口の内壁に接して、水素や水などの不純物、及び酸素の透過を抑制する材料からなる導電体を形成し、当該導電体上に、当該導電体よりも導電率の高い材料からなる導電体を形成した２層以上の積層構造であってもよい。
The conductor 195 is formed in an opening reaching the upper surface of the conductor 140 provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180. Here, the height of the upper surface of the conductor 195 and the height of the upper surface of the insulator 180 are preferably approximately the same. Note that in FIG. 1B, the conductor 195 is illustrated as a single layer structure; however, one embodiment of the present invention is not limited thereto, for example, the conductor 195 includes an insulator 175, an insulator 176, and an insulator. A conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen is formed in contact with the inner wall of the opening provided in the body 178 and the insulator 180, and the conductor is formed on the conductor. It may be a laminated structure of two or more layers in which a conductor made of a material having higher conductivity is formed.
導電体２００は、導電体１９５の上面と接する領域を有するように、絶縁体１８０上に形成される。なお、図１（Ｂ）では、導電体２００を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、導電体２００は、２層以上の積層構造であってもよい。
The conductor 200 is formed on the insulator 180 so as to have a region in contact with the upper surface of the conductor 195. Note that although the conductor 200 is illustrated as a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto. For example, the conductor 200 may have a stacked structure of two or more layers.
［トランジスタ１０］
図１（Ｂ）に示すように、トランジスタ１０は、絶縁体１１０の上に配置された導電体１２０及び酸化物１５０と、導電体１２０の上に配置された絶縁体１３０と、絶縁体１３０の上に配置された導電体１４０と、酸化物１５０の上に配置された絶縁体１６０と、絶縁体１６０の上に配置された導電体１７０と、を有する。ここで、酸化物１５０は、導電体１２０、絶縁体１３０、及び導電体１４０の側面と接する領域を有するように設けられる。また、絶縁体１６０は、酸化物１５０を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と向かい合う領域を有するように設けられる。また、導電体１７０は、酸化物１５０及び絶縁体１６０を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と向かい合う領域を有するように設けられる。 [Transistor 10]
As illustrated in FIG. 1B, thetransistor 10 includes a conductor 120 and an oxide 150 which are disposed over the insulator 110, an insulator 130 which is disposed over the conductor 120, and the insulator 130. It has a conductor 140 disposed on top, an insulator 160 disposed on the oxide 150, and a conductor 170 disposed on the insulator 160. Here, the oxide 150 is provided so as to have a region in contact with the side surfaces of the conductor 120, the insulator 130, and the conductor 140. The insulator 160 is provided to have a region facing the side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 interposed therebetween. The conductor 170 is provided so as to have a region facing the side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 and the insulator 160 interposed therebetween.
図１（Ｂ）に示すように、トランジスタ１０は、絶縁体１１０の上に配置された導電体１２０及び酸化物１５０と、導電体１２０の上に配置された絶縁体１３０と、絶縁体１３０の上に配置された導電体１４０と、酸化物１５０の上に配置された絶縁体１６０と、絶縁体１６０の上に配置された導電体１７０と、を有する。ここで、酸化物１５０は、導電体１２０、絶縁体１３０、及び導電体１４０の側面と接する領域を有するように設けられる。また、絶縁体１６０は、酸化物１５０を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と向かい合う領域を有するように設けられる。また、導電体１７０は、酸化物１５０及び絶縁体１６０を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と向かい合う領域を有するように設けられる。 [Transistor 10]
As illustrated in FIG. 1B, the
図１（Ｂ）及び図１（Ｃ）に示すように、導電体１２０、絶縁体１３０、及び導電体１４０の上には、これらを覆うように絶縁体１７５が設けられる。絶縁体１７５には、導電体１２０、絶縁体１３０、及び導電体１４０の側面と内壁の一部が重なる開口が設けられ、当該開口の内壁に沿って酸化物１５０が設けられ、酸化物１５０の上に絶縁体１６０が設けられ、絶縁体１６０の上に当該開口を埋め込むように導電体１７０が設けられる。ここで、図１（Ｂ）に示すように、酸化物１５０、絶縁体１６０、及び導電体１７０の最上面の高さは、絶縁体１７５の上面の高さと同程度であることが好ましい。なお、図１（Ｂ）では、酸化物１５０を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、酸化物１５０は、２層以上の積層構造であってもよい。
As shown in FIGS. 1B and 1C, an insulator 175 is provided on the conductor 120, the insulator 130, and the conductor 140 so as to cover them. The insulator 175 is provided with an opening in which the side surface of the conductor 120, the insulator 130, and the conductor 140 partially overlaps with the inner wall, and the oxide 150 is provided along the inner wall of the opening. An insulator 160 is provided above, and a conductor 170 is provided on the insulator 160 so as to embed the opening. Here, as illustrated in FIG. 1B, the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175. Note that although FIG. 1B illustrates the oxide 150 as a single layer structure, one embodiment of the present invention is not limited thereto. For example, the oxide 150 may have a stacked structure including two or more layers.
トランジスタ１０において、導電体１２０は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５０の絶縁体１３０と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６０は、ゲート絶縁体としての機能を有し、導電体１７０は、ゲート電極としての機能を有する。
In the transistor 10, the conductor 120 functions as one of a source electrode and a drain electrode, and the conductor 140 functions as the other of the source electrode and the drain electrode. The overlapping region has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode.
上述のように、本発明の一態様に係るトランジスタ１０は、ソース電極又はドレイン電極の一方として機能する導電層（導電体１２０）、チャネル形成領域として機能する酸化物と接する領域を有する絶縁層（絶縁体１３０）、及び、ソース電極又はドレイン電極の他方として機能する導電層（導電体１４０）が、下から順に積層された構成を有する。すなわち、トランジスタ１０では、キャリア（電子又は正孔）が流れる方向（チャネル長方向）が、基板面に対して略垂直な方向となる。トランジスタ１０が当該構成を有することで、トランジスタ１０のチャネル長は、ソース電極とドレイン電極の間に挟まれた絶縁体１３０の膜厚で規定される。したがって、トランジスタ１０のチャネル長を、絶縁体１３０の成膜時の膜厚で制御することが可能となる。例えば、トランジスタ１０のチャネル長を、１ｎｍ以上１００ｎｍ以下の範囲で任意に制御することが可能となる。そのため、リソグラフィー法などでチャネル長を形成する場合よりも、基板面内で精度良く複数の微細なトランジスタを作製することができる。
As described above, the transistor 10 according to one embodiment of the present invention includes the conductive layer functioning as one of the source electrode and the drain electrode (conductor 120) and the insulating layer having a region in contact with the oxide functioning as a channel formation region ( The insulator 130) and a conductive layer (conductor 140) functioning as the other of the source electrode and the drain electrode are stacked in order from the bottom. That is, in the transistor 10, the direction (channel length direction) in which carriers (electrons or holes) flow is substantially perpendicular to the substrate surface. With the transistor 10 having this structure, the channel length of the transistor 10 is defined by the thickness of the insulator 130 sandwiched between the source electrode and the drain electrode. Therefore, the channel length of the transistor 10 can be controlled by the film thickness when the insulator 130 is formed. For example, the channel length of the transistor 10 can be arbitrarily controlled in the range of 1 nm to 100 nm. Therefore, a plurality of fine transistors can be manufactured with higher accuracy in the substrate surface than in the case where the channel length is formed by a lithography method or the like.
なお、トランジスタ１０において、チャネル形成領域としての機能を有する酸化物１５０は、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう。）を用いることが好ましい。金属酸化物をチャネル形成領域に用いたトランジスタは、非導通状態において極めてリーク電流（オフ電流）が小さいため、低消費電力の半導体装置を提供できる。また、金属酸化物は、スパッタリング法などを用いて成膜できるため、高集積型の半導体装置を構成するトランジスタに用いることができる。
Note that in the transistor 10, the oxide 150 having a function as a channel formation region is preferably a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). A transistor in which a metal oxide is used for a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, so that a semiconductor device with low power consumption can be provided. A metal oxide can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
一方で、金属酸化物をチャネル形成領域に用いたトランジスタは、金属酸化物中の不純物又は酸素欠損によって電気特性が変動しやすく、信頼性が悪くなる場合がある。また、金属酸化物に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。当該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。したがって、酸素欠損が含まれている金属酸化物をチャネル形成領域に用いたトランジスタは、ノーマリーオン特性となりやすい。このため、金属酸化物中の酸素欠損はできる限り低減されていることが好ましい。
On the other hand, in a transistor using a metal oxide for a channel formation region, electrical characteristics are likely to fluctuate due to impurities or oxygen vacancies in the metal oxide, and reliability may deteriorate. In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor in which a metal oxide containing oxygen vacancies is used for a channel formation region is likely to be normally on. For this reason, it is preferable that the oxygen deficiency in a metal oxide is reduced as much as possible.
特に、酸化物１５０が有するチャネル形成領域と、ゲート絶縁体として機能する絶縁体１６０との界面に、酸素欠損が存在すると、トランジスタ１０の電気特性の変動が生じやすく、また信頼性が悪くなる場合がある。
In particular, when oxygen vacancies exist at the interface between the channel formation region of the oxide 150 and the insulator 160 functioning as a gate insulator, electrical characteristics of the transistor 10 are likely to vary and reliability may deteriorate. There is.
そこで、酸化物１５０と接する絶縁体１６０が、化学量論的組成を満たす酸素よりも多くの酸素（過剰酸素ともいう。）を含むことが好ましい。つまり、絶縁体１６０が有する過剰酸素が、酸化物１５０が有するチャネル形成領域へと拡散することで、当該チャネル形成領域中の酸素欠損を低減することができる。
Therefore, the insulator 160 in contact with the oxide 150 preferably contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. In other words, excess oxygen included in the insulator 160 diffuses into the channel formation region included in the oxide 150, whereby oxygen vacancies in the channel formation region can be reduced.
さらに、トランジスタ１０は、水又は水素などの不純物の混入を防ぐバリア性を有する絶縁体で覆われていることが好ましい。バリア性を有する絶縁体とは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい。）絶縁性材料を用いた絶縁体である。また、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい。）絶縁性材料を用いることが好ましい。
Further, the transistor 10 is preferably covered with an insulator having a barrier property to prevent entry of impurities such as water or hydrogen. An insulator having a barrier property is a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. (The above impurities are difficult to transmit.) An insulator using an insulating material. In addition, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
例えば、トランジスタ１０を、バリア性を有する絶縁体１０２上に設ける。また、トランジスタ１０上に、バリア性を有する絶縁体１７８を設ける。絶縁体１０２と、絶縁体１７８とが、トランジスタ１０の上下に配置された構造とすることで、トランジスタ１０を、バリア性を有する絶縁体で挟むことができる。当該構造により、水素、水などの不純物が、絶縁体１０２の下層から、及び、絶縁体１７８の上層から、トランジスタ１０に混入するのを抑制することができる。又は、絶縁体１３０及び絶縁体１６０に含まれる酸素が、絶縁体１０２の下層、及び、絶縁体１７８の上層へ拡散するのを抑制することができる。これにより、絶縁体１３０及び絶縁体１６０に含まれる酸素を、酸化物１５０が有するチャネル形成領域に効率良く供給することができる。
For example, the transistor 10 is provided over the insulator 102 having a barrier property. Further, an insulator 178 having a barrier property is provided over the transistor 10. With the structure in which the insulator 102 and the insulator 178 are arranged above and below the transistor 10, the transistor 10 can be sandwiched between insulators having a barrier property. With this structure, impurities such as hydrogen and water can be prevented from entering the transistor 10 from the lower layer of the insulator 102 and the upper layer of the insulator 178. Alternatively, diffusion of oxygen contained in the insulator 130 and the insulator 160 to the lower layer of the insulator 102 and the upper layer of the insulator 178 can be suppressed. Accordingly, oxygen contained in the insulator 130 and the insulator 160 can be efficiently supplied to the channel formation region included in the oxide 150.
以下では、本発明の一態様に係るトランジスタ１０を有する半導体装置の詳細な構成について説明する。
Hereinafter, a detailed structure of the semiconductor device including the transistor 10 according to one embodiment of the present invention will be described.
絶縁体１０２及び絶縁体１７８は、水又は水素などの不純物が、当該絶縁体よりも外側からトランジスタ１０に混入するのを防ぐバリア膜として機能することが好ましい。したがって、絶縁体１０２及び絶縁体１７８は、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい。）絶縁性材料を用いることが好ましい。又は、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい。）絶縁性材料を用いることが好ましい。
The insulator 102 and the insulator 178 preferably function as barrier films that prevent impurities such as water or hydrogen from entering the transistor 10 from the outside of the insulator. Therefore, the insulator 102 and the insulator 178 suppress diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom. It is preferable to use an insulating material having a function of preventing the above impurities from being transmitted. Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits).
例えば、絶縁体１０２及び絶縁体１７８として、酸化アルミニウムや窒化シリコンなどを用いることが好ましい。これにより、水素、水などの不純物が、当該絶縁体よりも内側（トランジスタ１０側）に拡散するのを抑制することができる。又は、絶縁体１３０などに含まれる酸素が、絶縁体１０２及び絶縁体１７８よりも外側に拡散するのを抑制することができる。
For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 102 and the insulator 178. Thus, impurities such as hydrogen and water can be prevented from diffusing inside (on the transistor 10 side) from the insulator. Alternatively, oxygen contained in the insulator 130 or the like can be prevented from diffusing outside the insulator 102 and the insulator 178.
また、例えば、絶縁体１０２及び絶縁体１７８としては、酸化アルミニウム、酸化ハフニウム、窒化シリコンなどの絶縁体を単層又は積層で用いることができる。
For example, as the insulator 102 and the insulator 178, an insulator such as aluminum oxide, hafnium oxide, or silicon nitride can be used in a single layer or a stacked layer.
また、層間膜として機能する絶縁体１００、絶縁体１０５、絶縁体１１０、絶縁体１７５、絶縁体１７６、及び絶縁体１８０は、絶縁体１０２及び絶縁体１７８よりも誘電率が低いことが好ましい。当該絶縁体に、比較的誘電率が低い材料を用いることで、例えば、配線間に生じる寄生容量を低減することができる。
In addition, the insulator 100, the insulator 105, the insulator 110, the insulator 175, the insulator 176, and the insulator 180 functioning as interlayer films preferably have a lower dielectric constant than the insulator 102 and the insulator 178. By using a material having a relatively low dielectric constant for the insulator, for example, parasitic capacitance generated between wirings can be reduced.
例えば、絶縁体１００、絶縁体１０５、絶縁体１１０、絶縁体１７５、絶縁体１７６、及び絶縁体１８０として、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、酸化アルミニウム、酸化ハフニウム、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）又は（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などの絶縁体を単層又は積層で用いることができる。又は、これらの絶縁体に、例えば、酸化アルミニウム、酸化ビスマス、酸化ゲルマニウム、酸化ニオブ、酸化シリコン、酸化チタン、酸化タングステン、酸化イットリウム、酸化ジルコニウムを添加してもよい。又は、これらの絶縁体を窒化処理してもよい。上記の絶縁体に酸化シリコン、酸化窒化シリコン又は窒化シリコンを積層して用いてもよい。なお、上記の各種絶縁体は、膜中における水素や水などの不純物濃度が、可能な限り低減されていることが好ましい。
For example, as the insulator 100, the insulator 105, the insulator 110, the insulator 175, the insulator 176, and the insulator 180, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide Insulators such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST) can be used in a single layer or stacked layers. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator. Note that, in the various insulators described above, the concentration of impurities such as hydrogen and water in the film is preferably reduced as much as possible.
また、トランジスタ１０において、絶縁体１３０は、ソース電極又はドレイン電極の一方として機能する導電体１２０と、ソース電極又はドレイン電極の他方として機能する導電体１４０とを、物理的かつ電気的に隔離する機能を有する。絶縁体１３０の膜厚は、１ｎｍ以上１００ｎｍ以下であることが好ましい。上述したように、絶縁体１３０の側面は、酸化物１５０が有するトランジスタ１０のチャネル形成領域と接している。そのため、絶縁体１３０は、化学量論的組成を満たす酸素よりも多くの酸素を含む酸化物絶縁体を用いることが好ましい。つまり、絶縁体１３０には、過剰酸素領域が形成されていることが好ましい。このような過剰酸素を含む絶縁体を酸化物１５０に接して設けることにより、酸化物１５０が有するチャネル形成領域の酸素欠損を低減し、トランジスタ１０の信頼性を向上させることができる。
In the transistor 10, the insulator 130 physically and electrically separates the conductor 120 functioning as one of the source electrode and the drain electrode from the conductor 140 functioning as the other of the source electrode and the drain electrode. It has a function. The thickness of the insulator 130 is preferably greater than or equal to 1 nm and less than or equal to 100 nm. As described above, the side surface of the insulator 130 is in contact with the channel formation region of the transistor 10 included in the oxide 150. Therefore, the insulator 130 is preferably formed using an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region is formed in the insulator 130. By providing such an insulator containing excess oxygen in contact with the oxide 150, oxygen vacancies in the channel formation region of the oxide 150 can be reduced and the reliability of the transistor 10 can be improved.
過剰酸素領域を有する絶縁体として、具体的には、加熱により一部の酸素が脱離する酸化物材料を用いることが好ましい。加熱により酸素が脱離する酸化物とは、ＴＤＳ（Ｔｈｅｒｍａｌ Ｄｅｓｏｒｐｔｉｏｎ Ｓｐｅｃｔｒｏｓｃｏｐｙ）分析にて、酸素原子に換算しての酸素の脱離量が１．０×１０１４ａｔｏｍｓ／ｃｍ２以上、好ましくは３．０×１０１５ａｔｏｍｓ／ｃｍ２以上である酸化物膜である。なお、上記ＴＤＳ分析時における膜の表面温度としては、１００℃以上７００℃以下の範囲が好ましい。
Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide from which oxygen is released by heating is an oxygen desorption amount of 1.0 × 10 14 atoms / cm 2 or more, preferably 3 or more in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 15 atoms / cm 2 or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.
なお、絶縁体１３０は、酸素をできるだけ含んでいたほうが良い一方で、水素や水などについては、できるだけ含んでいないことが好ましい。これは、トランジスタ１０にとって、水素や水などが電気特性を変動させる要因となり得るためである。そのため、チャネル形成領域として機能する酸化物１５０中だけでなく、酸化物１５０と接する絶縁体１３０についても、トランジスタ１０にとって不純物となり得る水素や水などの含有濃度が可能な限り低減されていることが好ましい。
Note that the insulator 130 preferably contains as much oxygen as possible, but preferably does not contain hydrogen or water as much as possible. This is because, for the transistor 10, hydrogen, water, or the like can be a factor that fluctuates electrical characteristics. Therefore, the concentration of hydrogen, water, or the like that can be an impurity for the transistor 10 is reduced as much as possible not only in the oxide 150 functioning as a channel formation region but also in the insulator 130 in contact with the oxide 150. preferable.
また、トランジスタ１０のチャネル形成領域として機能する酸化物１５０には、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう。）を用いることが好ましい。例えば、チャネル形成領域に用いる金属酸化物としては、バンドギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上のものを用いることが好ましい。このように、バンドギャップの大きい金属酸化物を用いることで、トランジスタのオフ電流を低減することができる。
For the oxide 150 functioning as a channel formation region of the transistor 10, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide used for the channel formation region, one having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.
酸化物１５０は、各金属原子の原子数比が異なる酸化物を用いた、２層以上の積層構造を有していてもよい。例えば、酸化物１５０が、酸化物１５０ａ（１層目）と、酸化物１５０ｂ（２層目）と、からなる２層構造である場合、酸化物１５０ｂに用いる金属酸化物において、構成元素中の元素Ｍの原子数比が、酸化物１５０ａに用いる金属酸化物における、構成元素中の元素Ｍの原子数比より、大きいことが好ましい。また、酸化物１５０ｂに用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物１５０ａに用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。また、酸化物１５０ａに用いる金属酸化物において、元素Ｍに対するＩｎの原子数比が、酸化物１５０ｂに用いる金属酸化物における、元素Ｍに対するＩｎの原子数比より大きいことが好ましい。
The oxide 150 may have a stacked structure of two or more layers using oxides having different atomic ratios of metal atoms. For example, when the oxide 150 has a two-layer structure including the oxide 150a (first layer) and the oxide 150b (second layer), the metal oxide used for the oxide 150b includes The atomic ratio of the element M is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 150a. In the metal oxide used for the oxide 150b, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 150a. In the metal oxide used for the oxide 150a, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 150b.
酸化物１５０が上記構成を有する場合、主として、酸化物１５０ａが、トランジスタ１０のチャネル形成領域として機能する。ここで、異なる材料からなる絶縁体１６０と酸化物１５０ｂの界面には、組成の近い材料からなる酸化物１５０ａと酸化物１５０ｂの界面よりも欠陥準位が形成されやすい。当該欠陥準位は、トランジスタ１０の電気特性変動や、信頼性悪化を引き起こすトラップ準位となり得るが、酸化物１５０ａ上に酸化物１５０ｂを有する構成とすることで、当該欠陥準位を酸化物１５０ａから離すことができる。これにより、トランジスタ１０は、良好な電気特性と信頼性を提供することができる。
In the case where the oxide 150 has the above structure, the oxide 150a mainly functions as a channel formation region of the transistor 10. Here, defect levels are more likely to be formed at the interface between the insulator 160 made of a different material and the oxide 150b than at the interface between the oxide 150a and the oxide 150b made of materials having similar compositions. The defect level can be a trap level that causes fluctuations in electrical characteristics of the transistor 10 or deterioration of reliability. However, the defect level is changed to the oxide 150a by including the oxide 150b over the oxide 150a. Can be separated from. Thus, the transistor 10 can provide good electrical characteristics and reliability.
また、酸化物１５０ａ上に酸化物１５０ｂを有することで、酸化物１５０ｂよりも上方から、酸化物１５０ａが有するチャネル形成領域に不純物が拡散するのを抑制することができる。
Further, by including the oxide 150b over the oxide 150a, it is possible to suppress the diffusion of impurities from above the oxide 150b into the channel formation region included in the oxide 150a.
上述したように、金属酸化物をチャネル形成領域に用いたトランジスタは、非導通状態において極めてリーク電流が小さいため、低消費電力の半導体装置を提供できる。また、金属酸化物は、スパッタリング法などを用いて成膜できるため、高集積型の半導体装置を構成するトランジスタに用いることができる。
As described above, a transistor using a metal oxide for a channel formation region has a very small leakage current in a non-conduction state, and thus can provide a semiconductor device with low power consumption. A metal oxide can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
例えば、酸化物１５０として、Ｉｎ−Ｍ−Ｚｎ酸化物（元素Ｍは、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種）等の金属酸化物を用いるとよい。また、酸化物１５０として、Ｉｎ−Ｇａ酸化物、Ｉｎ−Ｚｎ酸化物を用いてもよい。
For example, the oxide 150 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) It is preferable to use a metal oxide such as one or more selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 150, an In—Ga oxide or an In—Zn oxide may be used.
導電体１２０及び導電体１４０は、トランジスタ１０のソース電極又はドレイン電極としての機能を有する。図１（Ｂ）及び図１（Ｃ）に示すように、導電体１２０と、導電体１４０とは、絶縁体１３０を挟んで上下に設けられる。導電体１２０及び導電体１４０には、例えば、窒化タンタル、タングステン、窒化チタンなどの導電体を用いることができる。なお、図１では、導電体１２０及び導電体１４０を単層構造として示しているが、２層以上の積層構造であってもよい。
The conductor 120 and the conductor 140 have a function as a source electrode or a drain electrode of the transistor 10. As shown in FIGS. 1B and 1C, the conductor 120 and the conductor 140 are provided above and below with the insulator 130 interposed therebetween. For the conductor 120 and the conductor 140, for example, a conductor such as tantalum nitride, tungsten, or titanium nitride can be used. Note that in FIG. 1, the conductor 120 and the conductor 140 are illustrated as a single layer structure, but may be a stacked structure including two or more layers.
例えば、導電体１２０及び導電体１４０が２層構造である場合には、導電体１２０（導電体１４０）の１層目（２層目）にタングステンなどの金属を用い、導電体１２０（導電体１４０）の２層目（１層目）に窒化チタンや窒化タンタル等の酸素の透過を抑制する機能を有する導電体を用いてもよい。当該構成とすることで、上述したように、導電体１２０と導電体１４０とに挟まれた絶縁体１３０が過剰酸素を含む場合、絶縁体１３０から導電体１２０（導電体１４０）の１層目（２層目）への酸素の混入が低減し、導電体１２０（導電体１４０）の１層目（２層目）の電気抵抗値が増加するのを抑制することができる。
For example, when the conductor 120 and the conductor 140 have a two-layer structure, a metal such as tungsten is used for the first layer (second layer) of the conductor 120 (conductor 140), and the conductor 120 (conductor) A conductor having a function of suppressing permeation of oxygen, such as titanium nitride or tantalum nitride, may be used for the second layer (first layer) 140). With this structure, as described above, when the insulator 130 sandwiched between the conductor 120 and the conductor 140 contains excess oxygen, the first layer of the conductor 120 (conductor 140) from the insulator 130 is used. Mixing of oxygen into the (second layer) is reduced, and an increase in the electrical resistance value of the first layer (second layer) of the conductor 120 (conductor 140) can be suppressed.
また、図１では示していないが、導電体１２０上（導電体１４０下）に、酸化アルミニウム等の酸素の透過を抑制する機能を有する絶縁体を成膜する構成としてもよい。例えば、導電体１２０及び導電体１４０として、窒化タンタル、タングステン、窒化チタンなどの導電体を用い、導電体１２０上（導電体１４０下）に酸化アルミニウム等の絶縁体を積層する構造としてもよい。当該構造とすることで、絶縁体１３０から導電体１２０及び導電体１４０への酸素の混入が低減し、導電体１２０及び導電体１４０の電気抵抗値が増加するのを抑制することができる。また、導電体１２０及び導電体１４０への酸素の混入が低減する分、酸化物１５０に多くの酸素を供給することができる。なお、導電体１２０上（導電体１４０下）の酸化アルミニウムの成膜にスパッタリング法を用いると、過剰酸素を有する酸化アルミニウムを成膜することができる。当該過剰酸素は、絶縁体１３０に供給することができる場合がある。さらに、絶縁体１３０に供給された酸素は、酸化物１５０に供給することができる場合がある。
Although not shown in FIG. 1, an insulator having a function of suppressing permeation of oxygen such as aluminum oxide may be formed over the conductor 120 (under the conductor 140). For example, a conductor such as tantalum nitride, tungsten, or titanium nitride may be used as the conductor 120 and the conductor 140, and an insulator such as aluminum oxide may be stacked over the conductor 120 (under the conductor 140). With this structure, mixing of oxygen from the insulator 130 into the conductor 120 and the conductor 140 can be reduced, and increase in electrical resistance values of the conductor 120 and the conductor 140 can be suppressed. In addition, much oxygen can be supplied to the oxide 150 by the amount of oxygen mixed into the conductor 120 and the conductor 140 is reduced. Note that when a sputtering method is used to form aluminum oxide over the conductor 120 (under the conductor 140), aluminum oxide having excess oxygen can be formed. In some cases, the excess oxygen can be supplied to the insulator 130. Further, oxygen supplied to the insulator 130 may be supplied to the oxide 150 in some cases.
また、導電体１２０又は導電体１４０は、酸化物１５０と反応する場合がある。その結果、図１では示していないが、酸化物１５０と導電体１２０又は導電体１４０との界面に、ｎ型化してキャリアが増加した領域が形成される場合がある。当該領域は、トランジスタ１０のドレイン電流を増加させるのに寄与する場合がある。
In addition, the conductor 120 or the conductor 140 may react with the oxide 150. As a result, although not illustrated in FIG. 1, a region in which carriers are increased due to n-type formation may be formed at the interface between the oxide 150 and the conductor 120 or the conductor 140. This region may contribute to increasing the drain current of the transistor 10.
絶縁体１６０は、トランジスタ１０のゲート絶縁体としての機能を有する。絶縁体１６０は、酸化物１５０の上面に接して配置されることが好ましい。絶縁体１６０は、加熱により酸素が放出される絶縁体を用いて形成されることが好ましい。例えば、絶縁体１６０は、昇温脱離ガス分光法分析（ＴＤＳ分析）にて、酸素原子に換算しての酸素の脱離量が１．０×１０１４ａｔｏｍｓ／ｃｍ２以上、好ましくは３．０×１０１５ａｔｏｍｓ／ｃｍ２以上である酸化物膜であることが好ましい。なお、上記ＴＤＳ分析時における膜の表面温度としては、１００℃以上７００℃以下の範囲が好ましい。
The insulator 160 functions as a gate insulator of the transistor 10. The insulator 160 is preferably disposed in contact with the upper surface of the oxide 150. The insulator 160 is preferably formed using an insulator from which oxygen is released by heating. For example, the insulator 160 has an oxygen desorption amount of 1.0 × 10 14 atoms / cm 2 or more, preferably 3 in terms of oxygen atom in temperature-programmed desorption gas spectroscopy analysis (TDS analysis). It is preferable that the oxide film be 0.0 × 10 15 atoms / cm 2 or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.
加熱により酸素が放出される絶縁体を、絶縁体１６０として、酸化物１５０の上面に接して設けることにより、酸化物１５０が有するチャネル形成領域に効率良く酸素を供給することができる。また、絶縁体１３０と同様に、絶縁体１６０中の水又は水素などの不純物濃度が低減されていることが好ましい。絶縁体１６０の膜厚は、１ｎｍ以上２０ｎｍ以下とするのが好ましい。なお、図１では、絶縁体１６０を単層構造として示しているが、２層以上の積層構造であってもよい。
By providing an insulator from which oxygen is released by heating as the insulator 160 in contact with the upper surface of the oxide 150, oxygen can be efficiently supplied to the channel formation region of the oxide 150. Similarly to the insulator 130, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 160 be reduced. The thickness of the insulator 160 is preferably greater than or equal to 1 nm and less than or equal to 20 nm. Note that in FIG. 1, the insulator 160 is illustrated as a single layer structure, but a stacked structure including two or more layers may be used.
導電体１７０は、トランジスタ１０のゲート電極としての機能を有する。導電体１７０には、例えば、タングステンなどの金属を用いることができる。なお、図１では、導電体１７０を単層構造として示しているが、２層以上の積層構造であってもよい。
The conductor 170 has a function as a gate electrode of the transistor 10. For the conductor 170, for example, a metal such as tungsten can be used. Note that in FIG. 1, the conductor 170 is shown as a single layer structure, but a laminated structure of two or more layers may be used.
例えば、導電体１７０が３層構造である場合には、導電体１７０の１層目に導電性酸化物を用い、導電体１７０の２層目に窒化チタンを用い、導電体１７０の３層目にタングステンなどの金属を用いることが好ましい。なお、導電体１７０が上記のような３層構造を有する場合、導電体１７０の１層目は、絶縁体１６０の上面に沿って配置され、導電体１７０の２層目は、導電体１７０の１層目の上面に沿って配置され、導電体１７０の３層目は、導電体１７０が設けられる残りの空間を埋め込むように形成されることが好ましい。また、導電体１７０の１層目、導電体１７０の２層目、及び導電体１７０の３層目の最上面の高さは、絶縁体１７５の上面の高さと同程度であることが好ましい。
For example, when the conductor 170 has a three-layer structure, a conductive oxide is used for the first layer of the conductor 170, titanium nitride is used for the second layer of the conductor 170, and the third layer of the conductor 170 is used. It is preferable to use a metal such as tungsten. Note that in the case where the conductor 170 has the three-layer structure as described above, the first layer of the conductor 170 is disposed along the upper surface of the insulator 160, and the second layer of the conductor 170 is the conductor 170. It is preferable that the third layer of the conductor 170 is disposed along the upper surface of the first layer so as to fill the remaining space where the conductor 170 is provided. In addition, the height of the top surface of the first layer of the conductor 170, the second layer of the conductor 170, and the third layer of the conductor 170 is preferably approximately the same as the height of the top surface of the insulator 175.
導電体１７０の１層目に用いることができる導電性酸化物としては、例えば、酸化物１５０として用いることができる金属酸化物が挙げられる。特に、Ｉｎ−Ｇａ−Ｚｎ酸化物のうち、導電性が高い、金属の原子数比が［Ｉｎ］：［Ｇａ］：［Ｚｎ］＝４：２：３から４．１、及びその近傍値の金属酸化物を用いることが好ましい。このような金属酸化物を導電体１７０の１層目に用いることで、導電体１７０の１層目の下側から導電体１７０の２層目、３層目に酸素が混入するのを低減し、酸化によって導電体１７０の２層目、３層目の電気抵抗値が増加するのを抑制することができる。
Examples of the conductive oxide that can be used for the first layer of the conductor 170 include a metal oxide that can be used as the oxide 150. In particular, among In—Ga—Zn oxides, the metal has a high conductivity, the atomic ratio of metal is [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, and the vicinity thereof. It is preferable to use a metal oxide. By using such a metal oxide for the first layer of the conductor 170, oxygen is less mixed from the lower side of the first layer of the conductor 170 into the second layer and the third layer of the conductor 170. Therefore, it is possible to suppress an increase in the electric resistance value of the second layer and the third layer of the conductor 170.
また、導電体１７０の１層目に用いることができる上記導電性酸化物を、スパッタリング法を用いて成膜することで、絶縁体１６０に酸素を添加し、酸化物１５０に酸素を供給することが可能となる。これにより、酸化物１５０が有するチャネル形成領域の酸素欠損を低減することができる。
Further, the conductive oxide that can be used for the first layer of the conductor 170 is formed by a sputtering method, whereby oxygen is added to the insulator 160 and oxygen is supplied to the oxide 150. Is possible. Accordingly, oxygen vacancies in the channel formation region included in the oxide 150 can be reduced.
導電体１７０の２層目には、上述したように、例えば、窒化チタンなどの金属窒化物を用いることができる。導電体１７０の２層目に金属窒化物を用いることで、導電体１７０の１層目に窒素などの不純物を添加して、導電体１７０の１層目の導電性を向上させてもよい。また、導電体１７０の３層目には、例えば、タングステンなどの金属を用いることができる。タングステンなどの低抵抗率材料を用いることで、導電体１７０の電気抵抗値を下げることができる。
As described above, for example, a metal nitride such as titanium nitride can be used for the second layer of the conductor 170. By using metal nitride for the second layer of the conductor 170, an impurity such as nitrogen may be added to the first layer of the conductor 170 to improve the conductivity of the first layer of the conductor 170. For the third layer of the conductor 170, for example, a metal such as tungsten can be used. By using a low resistivity material such as tungsten, the electrical resistance value of the conductor 170 can be reduced.
また、例えば、導電体１７０が２層構造である場合には、１層目に窒化チタンなどの金属窒化物、２層目にタングステンなどの金属を積層した構造にしてもよい。
For example, when the conductor 170 has a two-layer structure, a structure in which a metal nitride such as titanium nitride is stacked on the first layer and a metal such as tungsten is stacked on the second layer may be used.
また、図１では示していないが、絶縁体１７５と絶縁体１７６との間に、酸素の透過を抑制する機能を有する絶縁体を成膜する構成としてもよい。例えば、当該絶縁体として、酸化アルミニウム等の絶縁体を成膜する構成としてもよい。当該構成とすることで、酸化アルミニウム等の絶縁体上から導電体１７０への酸素の混入が低減し、導電体１７０が酸化するのを抑制することができる。
Although not shown in FIG. 1, an insulator having a function of suppressing oxygen permeation may be formed between the insulator 175 and the insulator 176. For example, an insulator such as aluminum oxide may be formed as the insulator. With this structure, mixing of oxygen into the conductor 170 from an insulator such as aluminum oxide can be reduced, and oxidation of the conductor 170 can be suppressed.
また、ゲート電極としての機能を有する導電体１７０は、導電体１２０、絶縁体１３０、及び導電体１４０の側面と一部が重なる領域を有するように絶縁体１７５に設けられた開口を、酸化物１５０及び絶縁体１６０を介して埋め込むように形成される（図１（Ａ）及び図１（Ｂ）参照。）。ゲート電極形成にマスクを用いる場合、ゲート電極形成サイズが小さいほど当該マスクの高い位置合わせ精度が求められるが、本発明の一態様に係るトランジスタ１０では、ゲート電極形成のためのマスクや、当該マスクの位置合わせが不要である。そのため、ゲート電極形成にマスクを用いる場合に比べて、高い精度で微細なゲート電極を形成することができ、生産性に優れる。
In addition, the conductor 170 functioning as a gate electrode includes an opening provided in the insulator 175 so that the conductor 120, the insulator 130, and the conductor 140 have regions that partially overlap with side surfaces of the conductor 120. 150 and the insulator 160 (see FIGS. 1A and 1B). In the case where a mask is used for forming the gate electrode, the smaller the gate electrode formation size, the higher the alignment accuracy of the mask is required. In the transistor 10 according to one embodiment of the present invention, the mask for forming the gate electrode, the mask No alignment is required. Therefore, a fine gate electrode can be formed with high accuracy compared to the case where a mask is used for forming the gate electrode, and the productivity is excellent.
上述してきたように、トランジスタ１０において、導電体１２０は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５０の絶縁体１３０と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６０は、ゲート絶縁体としての機能を有し、導電体１７０は、ゲート電極としての機能を有する。したがって、トランジスタ１０では、導電体１２０と導電体１４０の間に挟まれた絶縁体１３０と接する領域における酸化物１５０の長さ（すなわち、絶縁体１３０の膜厚）が、トランジスタ１０のチャネル長に相当する。当該構成により、トランジスタ１０では、絶縁体１３０の成膜時の膜厚によって、チャネル長を制御することが可能であり、リソグラフィー法では作製が困難な数ｎｍ、あるいはそれ以下にまでチャネル長を微細化することができる。また、絶縁体１３０の成膜時の膜厚によってチャネル長を制御できるため、リソグラフィー法でチャネル長を形成する場合のようなレジスト寸法ばらつきの精度なども求められず、容易に基板面内における素子間の加工ばらつきを抑えることができる。すなわち、本発明の一態様に係るトランジスタ１０は、設計自由度の高いトランジスタであり、複数の微細なチャネル長のトランジスタを、基板面内で精度良く作製することができる。また、基板面内において、加工ばらつきの小さい複数のトランジスタを作製できるため、リソグラフィー法でチャネル長を形成した場合などと比べて、素子間の電気特性ばらつきを低減させることができる。
As described above, in the transistor 10, the conductor 120 has a function as one of the source electrode and the drain electrode, and the conductor 140 has a function as the other of the source electrode and the drain electrode. The region overlapping with the insulator 130 of 150 has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode. Therefore, in the transistor 10, the length of the oxide 150 in the region in contact with the insulator 130 sandwiched between the conductor 120 and the conductor 140 (that is, the thickness of the insulator 130) is equal to the channel length of the transistor 10. Equivalent to. With this structure, in the transistor 10, the channel length can be controlled by the film thickness at the time of the formation of the insulator 130, and the channel length can be fined to several nm or less, which is difficult to manufacture by the lithography method. Can be Further, since the channel length can be controlled by the film thickness at the time of film formation of the insulator 130, the accuracy of resist dimension variation and the like as in the case of forming the channel length by a lithography method is not required, and the element on the substrate surface can be easily obtained. It is possible to suppress variations in processing. In other words, the transistor 10 according to one embodiment of the present invention is a transistor with a high degree of design freedom, and a plurality of transistors with a small channel length can be manufactured with high accuracy in a substrate plane. In addition, since a plurality of transistors with small processing variations can be manufactured in the substrate surface, variation in electrical characteristics between elements can be reduced as compared with a case where a channel length is formed by a lithography method.
また、本発明の一態様に係るトランジスタ１０は、上述のチャネル長以外にも、ソース電極又はドレイン電極としての機能を有する導電体１２０及び導電体１４０が、絶縁体１３０を挟んで上下に設けられている点に特徴を有する。絶縁体１３０を介して、ソース電極としての機能を有する導電体と、ドレイン電極としての機能を有する導電体とを、上述のように基板面に対して垂直な方向に積層した構成とすることで、ソース電極又はドレイン電極としての機能を有する導電体の、基板面内での占有面積を減少させることができる。これにより、個々のトランジスタ１０の微細化を図ることができる。また、個々のトランジスタ１０の微細化を図ることができるため、当該トランジスタ１０を有する半導体装置の高集積化を図ることができる。
In addition to the channel length described above, the transistor 10 according to one embodiment of the present invention includes the conductor 120 and the conductor 140 functioning as a source electrode or a drain electrode provided above and below with the insulator 130 interposed therebetween. It has a feature in that. A structure in which a conductor having a function as a source electrode and a conductor having a function as a drain electrode are stacked in a direction perpendicular to the substrate surface as described above with the insulator 130 interposed therebetween. The area occupied by the conductor having a function as a source electrode or a drain electrode in the substrate surface can be reduced. Thereby, miniaturization of each transistor 10 can be achieved. In addition, since each transistor 10 can be miniaturized, a semiconductor device including the transistor 10 can be highly integrated.
このように、本発明の一態様に係るトランジスタ１０では、ソース電極又はドレイン電極の一方となる導電体、絶縁体、及びソース電極又はドレイン電極の他方となる導電体が順に成膜された「縦型トランジスタ構造」とすることにより、極めて微細なチャネル長を有する複数のトランジスタを、精度良くかつ容易に作製することができる。また、基板面内において、素子間の電気特性ばらつきが小さいトランジスタを作製することができる。また、トランジスタの微細化を図ることができる。また、当該トランジスタを有する半導体装置の高集積化を図ることができる。
As described above, in the transistor 10 according to one embodiment of the present invention, a conductor which is one of a source electrode and a drain electrode, an insulator, and a conductor which is the other of the source electrode and the drain electrode are sequentially formed. By using the “type transistor structure”, a plurality of transistors having extremely fine channel lengths can be manufactured with high accuracy and ease. In addition, a transistor with small variation in electrical characteristics between elements can be manufactured in the substrate plane. Further, the transistor can be miniaturized. In addition, high integration of a semiconductor device including the transistor can be achieved.
なお、トランジスタの微細化が進み、チャネル長が短くなると、トランジスタのＶｇ（ゲート電位）−Ｉｄ（ドレイン電流）特性におけるＶｔｈが低下する（マイナスシフトする。）、サブスレッショルドスイング値（Ｓ値）が増大する、オフ電流が増大するなどの不具合、いわゆる「短チャネル効果」が顕在化しやすくなる。しかしながら、上述したように、本発明の一態様に係るトランジスタ１０では、チャネル形成領域を有する酸化物１５０に金属酸化物を用いることができる。そのため、例えば、チャネル形成領域にＳｉを用いたトランジスタに比べて短チャネル効果が出にくく、オフ電流を大幅に低減することができる。すなわち、本発明の一態様に係るトランジスタ１０は、微細化を進めても、良好な電気特性を有することができる。なお、金属酸化物の詳細については、後ほど＜半導体装置の構成要素＞にて説明する。
Note that as transistor miniaturization progresses and the channel length becomes shorter, Vth in the Vg (gate potential) -Id (drain current) characteristic of the transistor decreases (minus shift), and the subthreshold swing value (S value) becomes smaller. Inconveniences such as an increase in off-current and so-called “short channel effect” are likely to be manifested. However, as described above, in the transistor 10 according to one embodiment of the present invention, a metal oxide can be used for the oxide 150 having a channel formation region. Therefore, for example, a short channel effect is less likely to occur compared to a transistor using Si in a channel formation region, and off-state current can be significantly reduced. That is, the transistor 10 according to one embodiment of the present invention can have favorable electrical characteristics even when miniaturization is advanced. Note that details of the metal oxide will be described later in <Components of Semiconductor Device>.
導電体１９０（導電体１９５）は、トランジスタ１０のソース電極又はドレイン電極の一方（他方）としての機能を有する導電体１２０（導電体１４０）と、配線としての機能を有する導電体１８５（導電体２００）とを、接続するプラグとしての機能を有する。導電体１９０（導電体１９５）は、タングステン、銅、又はアルミニウムを主成分とする導電性材料を用いることが好ましい。また、図１では示していないが、導電体１９０（導電体１９５）は積層構造としてもよく、例えば、絶縁体１１０（絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０）に設けられた開口の内壁と、導電体１８５（導電体２００）の上面（底面）とに接して、チタン、窒化チタン等を成膜し、その内側に上記導電性材料を設ける構成としてもよい。
The conductor 190 (conductor 195) includes a conductor 120 (conductor 140) that functions as one (the other) of the source electrode and the drain electrode of the transistor 10 and a conductor 185 (conductor) that functions as a wiring. 200) has a function as a plug to be connected. The conductor 190 (conductor 195) is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Although not illustrated in FIG. 1, the conductor 190 (conductor 195) may have a stacked structure, for example, provided in the insulator 110 (insulator 175, insulator 176, insulator 178, and insulator 180). A structure may be adopted in which titanium, titanium nitride, or the like is formed in contact with the inner wall of the opening and the upper surface (bottom surface) of the conductor 185 (conductor 200), and the above-described conductive material is provided on the inside.
導電体１９０（導電体１９５）を積層構造とする場合、絶縁体１１０（絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０）に設けられた開口の内壁、及び、導電体１８５（導電体２００）の上面（底面）と接する導電体としては、水素や水などの不純物の透過を抑制する機能を有する導電性材料を用いることが好ましい。例えば、タンタル、窒化タンタル、チタン、窒化チタン、ルテニウム又は酸化ルテニウムなどを用いることが好ましい。また、水又は水素などの不純物の透過を抑制する機能を有する導電性材料は、単層又は積層で用いてもよい。当該導電性材料を用いることで、絶縁体１１０（絶縁体１８０）より下層（上層）から水素や水などの不純物が、導電体１９０（導電体１９５）を通じて酸化物１５０に混入するのを抑制することができる。
In the case where the conductor 190 (conductor 195) has a stacked structure, an inner wall of an opening provided in the insulator 110 (insulator 175, insulator 176, insulator 178, and insulator 180), and a conductor 185 ( As the conductor in contact with the upper surface (bottom surface) of the conductor 200), it is preferable to use a conductive material having a function of suppressing permeation of impurities such as hydrogen and water. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. A conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from the lower layer (upper layer) than the insulator 110 (insulator 180) are prevented from entering the oxide 150 through the conductor 190 (conductor 195). be able to.
配線としての機能を有する導電体１８５（導電体２００）としては、タングステン、銅、又はアルミニウムを主成分とする導電性材料を用いることが好ましい。また、当該導電体は、積層構造としてもよく、例えば、チタン、窒化チタンと上記導電性材料との積層としてもよい。
As the conductor 185 (conductor 200) having a function as a wiring, a conductive material mainly containing tungsten, copper, or aluminum is preferably used. The conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material.
以上では、本発明の一態様に係るトランジスタ１０を有する半導体装置の構成例について説明した。上述してきたように、本発明の一態様では、リソグラフィー法では作製することが困難な数ｎｍ、あるいはそれ以下のチャネル長の複数のトランジスタを、基板面内において、精度良くかつ容易に作製することができる。また、本発明の一態様では、基板面内において、素子間の電気特性ばらつきが小さいトランジスタを作製することができる。また、本発明の一態様では、チャネル長が微細でありながら、短チャネル効果の顕在化しにくい、良好な電気特性を有するトランジスタを作製することができる。また、本発明の一態様では、チャネル長だけでなく、配線やプラグも含めた素子サイズの微細なトランジスタを作製することができる。また、本発明の一態様では、上記微細なトランジスタを作製できることで、上記トランジスタを有する半導体装置の高集積化を図ることができる。また、本発明の一態様では、上記半導体装置を、高歩留まりで作製することができる。
The structure example of the semiconductor device including the transistor 10 according to one embodiment of the present invention has been described above. As described above, according to one embodiment of the present invention, a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and ease over a substrate. Can do. In one embodiment of the present invention, a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane. In one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured. In one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured. In one embodiment of the present invention, the fine transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated. In one embodiment of the present invention, the semiconductor device can be manufactured with high yield.
＜半導体装置の構成例２＞
以下では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置とは異なる、本発明の一態様に係るトランジスタ１１を有する半導体装置の構成例について、図２を用いて説明する。 <Configuration Example 2 of Semiconductor Device>
Hereinafter, a structural example of the semiconductor device including thetransistor 11 according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 described in <Structural Example 1 of Semiconductor Device> will be described with reference to FIGS.
以下では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置とは異なる、本発明の一態様に係るトランジスタ１１を有する半導体装置の構成例について、図２を用いて説明する。 <Configuration Example 2 of Semiconductor Device>
Hereinafter, a structural example of the semiconductor device including the
図２（Ａ）は、トランジスタ１１を有する半導体装置の上面図である。また、図２（Ｂ）は、図２（Ａ）にＢ１−Ｂ２の一点鎖線で示す部位の断面図である。また、図２（Ｃ）は、図２（Ａ）にＢ３−Ｂ４の一点鎖線で示す部位の断面図である。ここで、Ｂ１−Ｂ２の一点鎖線で示す部位と、Ｂ３−Ｂ４の一点鎖線で示す部位とは、互いに直交している。図２（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。
FIG. 2A is a top view of the semiconductor device having the transistor 11. FIG. 2B is a cross-sectional view taken along the dashed-dotted line B1-B2 in FIG. FIG. 2C is a cross-sectional view taken along the dashed-dotted line B3-B4 in FIG. Here, the part shown with the dashed-dotted line of B1-B2 and the part shown with the dashed-dotted line of B3-B4 are mutually orthogonal. In the top view of FIG. 2A, some elements are omitted for clarity.
なお、図２に示す半導体装置において、＜半導体装置の構成例１＞で示した半導体装置を構成する構造と同機能を有する構造には、同符号を付記している。また、以下では、主に、＜半導体装置の構成例１＞で説明した半導体装置と異なる部分について説明を行い、それ以外の部分については、＜半導体装置の構成例１＞で説明した内容を参酌できるものとする。
Note that in the semiconductor device illustrated in FIG. 2, the structure having the same function as the structure of the semiconductor device illustrated in <Structure Example 1 of Semiconductor Device> is denoted by the same reference numeral. In the following description, portions different from the semiconductor device described in <Semiconductor device configuration example 1> will be mainly described, and for other portions, the contents described in <semiconductor device configuration example 1> are referred to. It shall be possible.
図２に示す半導体装置は、図２（Ａ）及び図２（Ｂ）に示すように、ソース電極又はドレイン電極として機能する導電体、当該導電体と上下配線を接続するプラグとしての機能を有する導電体などが、酸化物１５０、絶縁体１６０、及び導電体１７０を挟んで、対向して設けられたトランジスタ１１を有している点が、＜半導体装置の構成例１＞で示した半導体装置（図１参照。）と異なる。
2A and 2B, the semiconductor device illustrated in FIGS. 2A and 2B functions as a conductor that functions as a source electrode or a drain electrode, and a plug that connects the conductor and the upper and lower wirings. The semiconductor device described in <Structure Example 1 of Semiconductor Device> is that a conductor or the like includes the transistor 11 provided so as to face the oxide 150, the insulator 160, and the conductor 170. (See FIG. 1).
本発明の一態様の半導体装置は、基板（図示しない。）上に、トランジスタ１１と、層間膜として機能する絶縁体１００、絶縁体１０２、絶縁体１０５、絶縁体１１０、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０と、を有する。また、トランジスタ１１と電気的に接続し、配線として機能する導電体１８５＿１、導電体１８５＿２、導電体２００＿１、及び導電体２００＿２、並びにプラグとして機能する導電体１９０＿１、導電体１９０＿２、導電体１９５＿１、及び導電体１９５＿２を有する。ここで、導電体１８５＿１と導電体１８５＿２、導電体１９０＿１と導電体１９０＿２、導電体１９５＿１と導電体１９５＿２、及び導電体２００＿１と導電体２００＿２は、いずれも酸化物１５０、絶縁体１６０、及び導電体１７０を挟んで対向して設けられる（図２（Ｂ）参照。）。
The semiconductor device of one embodiment of the present invention includes a transistor 11 and an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as an interlayer film over a substrate (not illustrated). 176, an insulator 178, and an insulator 180. Further, the conductor 185_1, the conductor 185_2, the conductor 200_1, and the conductor 200_2 that are electrically connected to the transistor 11 and function as wirings, and the conductor 190_1, the conductor 190_2, the conductor 195_1, which function as plugs, and A conductor 195_2 is included. Here, the conductor 185_1 and the conductor 185_2, the conductor 190_1 and the conductor 190_2, the conductor 195_1 and the conductor 195_2, and the conductor 200_1 and the conductor 200_2 are the oxide 150, the insulator 160, and the conductor. 170 are provided opposite to each other with reference to 170 (see FIG. 2B).
導電体１８５＿１（導電体１８５＿２）は、絶縁体１０５に設けられた開口内に形成される。ここで、導電体１８５＿１（導電体１８５＿２）の上面の高さと、絶縁体１０５の上面の高さは、同程度であることが好ましい。なお、図２（Ｂ）では、導電体１８５＿１（導電体１８５＿２）を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、導電体１８５＿１（導電体１８５＿２）は、２層以上の積層構造であってもよい。
The conductor 185_1 (conductor 185_2) is formed in an opening provided in the insulator 105. Here, the height of the upper surface of the conductor 185_1 (conductor 185_2) and the height of the upper surface of the insulator 105 are preferably approximately the same. Note that in FIG. 2B, the conductor 185_1 (conductor 185_2) is illustrated as a single-layer structure; however, one embodiment of the present invention is not limited thereto. For example, the conductor 185_1 (conductor 185_2) may have a stacked structure of two or more layers.
導電体１９０＿１（導電体１９０＿２）は、絶縁体１１０に設けられた開口内に形成される。導電体１９０＿１（導電体１９０＿２）の底面は、導電体１８５＿１（導電体１８５＿２）の上面と接する領域を有するように設けられる。ここで、導電体１９０＿１（導電体１９０＿２）の上面の高さと、絶縁体１１０の上面の高さは、同程度であることが好ましい。なお、図２（Ｂ）では、導電体１９０＿１（導電体１９０＿２）を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、導電体１９０＿１（導電体１９０＿２）は、絶縁体１１０に設けられた開口の内壁に接して、水素や水などの不純物、及び酸素の透過を抑制する材料からなる導電体を形成し、当該導電体上に、当該導電体よりも導電率の高い材料からなる導電体を形成した２層以上の積層構造であってもよい。
The conductor 190_1 (conductor 190_2) is formed in an opening provided in the insulator 110. The bottom surface of the conductor 190_1 (conductor 190_2) is provided to have a region in contact with the top surface of the conductor 185_1 (conductor 185_2). Here, the height of the upper surface of the conductor 190_1 (conductor 190_2) and the height of the upper surface of the insulator 110 are preferably approximately the same. Note that although FIG. 2B illustrates the conductor 190_1 (conductor 190_2) as a single-layer structure, one embodiment of the present invention is not limited thereto. For example, the conductor 190_1 (conductor 190_2) is in contact with the inner wall of the opening provided in the insulator 110 and forms a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen. A laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed on the conductor may be used.
導電体１９５＿１（導電体１９５＿２）は、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０に設けられた導電体１４０＿１（導電体１４０＿２）の上面に達する開口内に形成される。ここで、導電体１９５＿１（導電体１９５＿２）の上面の高さと、絶縁体１８０の上面の高さは、同程度であることが好ましい。なお、図２（Ｂ）では、導電体１９５＿１（導電体１９５＿２）を単層構造として示しているが、本発明の一態様はこれに限られない、例えば、導電体１９５＿１（導電体１９５＿２）は、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０に設けられた開口の内壁に接して、水素や水などの不純物、及び酸素の透過を抑制する材料からなる導電体を形成し、当該導電体上に、当該導電体よりも導電率の高い材料からなる導電体を形成した２層以上の積層構造であってもよい。
The conductor 195_1 (conductor 195_2) is formed in an opening reaching the upper surface of the insulator 175, the insulator 176, the insulator 178, and the conductor 140_1 (conductor 140_2) provided in the insulator 180. Here, the height of the upper surface of the conductor 195_1 (conductor 195_2) and the height of the upper surface of the insulator 180 are preferably approximately the same. Note that in FIG. 2B, the conductor 195_1 (conductor 195_2) is illustrated as a single-layer structure; however, one embodiment of the present invention is not limited thereto, for example, the conductor 195_1 (conductor 195_2) In addition, a conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen is formed in contact with the inner wall of the opening provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180. A stacked structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed on the conductor may be used.
導電体２００＿１（導電体２００＿２）は、導電体１９５＿１（導電体１９５＿２）の上面と接する領域を有するように、絶縁体１８０上に形成される。なお、図２（Ｂ）では、導電体２００＿１（導電体２００＿２）を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、導電体２００＿１（導電体２００＿２）は、２層以上の積層構造であってもよい。
The conductor 200_1 (conductor 200_2) is formed over the insulator 180 so as to have a region in contact with the upper surface of the conductor 195_1 (conductor 195_2). Note that in FIG. 2B, the conductor 200_1 (conductor 200_2) is illustrated as a single-layer structure; however, one embodiment of the present invention is not limited thereto. For example, the conductor 200_1 (conductor 200_2) may have a stacked structure of two or more layers.
［トランジスタ１１］
図２（Ｂ）に示すように、トランジスタ１１は、絶縁体１１０の上に配置された導電体１２０＿１、導電体１２０＿２、及び酸化物１５０と、導電体１２０＿１の上に配置された絶縁体１３０＿１と、導電体１２０＿２の上に配置された絶縁体１３０＿２と、絶縁体１３０＿１の上に配置された導電体１４０＿１と、絶縁体１３０＿２の上に配置された導電体１４０＿２と、酸化物１５０の上に配置された絶縁体１６０と、絶縁体１６０の上に配置された導電体１７０と、を有する。ここで、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１と、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２とは、いずれも酸化物１５０、絶縁体１６０、及び導電体１７０を挟んで対向して設けられる。また、酸化物１５０は、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１と、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２の、互いに向かい合う側面と接する領域を有するように設けられる。また、絶縁体１６０は、酸化物１５０を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。また、導電体１７０は、酸化物１５０及び絶縁体１６０を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。 [Transistor 11]
As illustrated in FIG. 2B, thetransistor 11 includes a conductor 120_1, a conductor 120_2, and an oxide 150 which are disposed over the insulator 110, and an insulator 130_1 which is disposed over the conductor 120_1. , The insulator 130_2 disposed over the conductor 120_2, the conductor 140_1 disposed over the insulator 130_1, the conductor 140_2 disposed over the insulator 130_2, and the oxide 150 And a conductor 170 disposed on the insulator 160. Here, the conductor 120_1, the insulator 130_1, and the conductor 140_1 are opposite to the conductor 120_2, the insulator 130_2, and the conductor 140_2 with the oxide 150, the insulator 160, and the conductor 170 interposed therebetween. Provided. The oxide 150 is provided so as to have regions in contact with side surfaces of the conductor 120_1, the insulator 130_1, and the conductor 140_1 and the conductor 120_2, the insulator 130_2, and the conductor 140_2 that face each other. The insulator 160 includes a region facing the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) with the oxide 150 interposed therebetween. Provided. The conductor 170 is a region facing the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) through the oxide 150 and the insulator 160. Is provided.
図２（Ｂ）に示すように、トランジスタ１１は、絶縁体１１０の上に配置された導電体１２０＿１、導電体１２０＿２、及び酸化物１５０と、導電体１２０＿１の上に配置された絶縁体１３０＿１と、導電体１２０＿２の上に配置された絶縁体１３０＿２と、絶縁体１３０＿１の上に配置された導電体１４０＿１と、絶縁体１３０＿２の上に配置された導電体１４０＿２と、酸化物１５０の上に配置された絶縁体１６０と、絶縁体１６０の上に配置された導電体１７０と、を有する。ここで、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１と、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２とは、いずれも酸化物１５０、絶縁体１６０、及び導電体１７０を挟んで対向して設けられる。また、酸化物１５０は、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１と、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２の、互いに向かい合う側面と接する領域を有するように設けられる。また、絶縁体１６０は、酸化物１５０を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。また、導電体１７０は、酸化物１５０及び絶縁体１６０を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。 [Transistor 11]
As illustrated in FIG. 2B, the
図２（Ｂ）及び図２（Ｃ）に示すように、導電体１２０＿１、導電体１２０＿２、絶縁体１３０＿１、絶縁体１３０＿２、導電体１４０＿１、及び導電体１４０＿２の上には、これらを覆うように絶縁体１７５が設けられる。絶縁体１７５には、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と内壁の一部が重なる開口が設けられ、当該開口の内壁に沿って酸化物１５０が設けられ、酸化物１５０の上に絶縁体１６０が設けられ、絶縁体１６０の上に当該開口を埋め込むように導電体１７０が設けられる。ここで、図２（Ｂ）に示すように、酸化物１５０、絶縁体１６０、及び導電体１７０の最上面の高さは、絶縁体１７５の上面の高さと同程度であることが好ましい。なお、図２（Ｂ）では、酸化物１５０を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、酸化物１５０は、２層以上の積層構造であってもよい。
As shown in FIGS. 2B and 2C, the conductor 120_1, the conductor 120_2, the insulator 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2 are covered so as to cover them. An insulator 175 is provided. The insulator 175 is provided with an opening in which the side surface of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) overlap with part of the inner wall. An oxide 150 is provided along the inner wall, an insulator 160 is provided on the oxide 150, and a conductor 170 is provided on the insulator 160 so as to fill the opening. Here, as illustrated in FIG. 2B, the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175. Note that although FIG. 2B illustrates the oxide 150 as a single-layer structure, one embodiment of the present invention is not limited thereto. For example, the oxide 150 may have a stacked structure including two or more layers.
トランジスタ１１において、導電体１２０＿１は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０＿１は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５０の絶縁体１３０＿１と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６０は、ゲート絶縁体としての機能を有し、導電体１７０は、ゲート電極としての機能を有する。同様に、トランジスタ１１において、導電体１２０＿２は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０＿２は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５０の絶縁体１３０＿２と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６０は、ゲート絶縁体としての機能を有し、導電体１７０は、ゲート電極としての機能を有する。
In the transistor 11, the conductor 120_1 functions as one of the source electrode and the drain electrode, the conductor 140_1 functions as the other of the source electrode and the drain electrode, and the insulator 130_1 of the oxide 150 The overlapping region has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode. Similarly, in the transistor 11, the conductor 120_2 functions as one of the source electrode and the drain electrode, and the conductor 140_2 functions as the other of the source electrode and the drain electrode, The region overlapping with the body 130_2 has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode.
すなわち、トランジスタ１１は、１つのゲート電極（導電体１７０）と、１つのゲート絶縁体（絶縁体１６０）と、２組のソース電極又はドレイン電極（導電体１２０＿１及び導電体１４０＿１、導電体１２０＿２及び導電体１４０＿２）と、２つのチャネル形成領域（酸化物１５０の絶縁体１３０＿１と重なる領域、酸化物１５０の絶縁体１３０＿２と重なる領域）と、で構成されたトランジスタであるといえる。あるいは、トランジスタ１１は、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿１及び導電体１４０＿１と、チャネル形成領域としての機能を有する酸化物１５０（絶縁体１３０＿１と重なる領域）とからなるトランジスタと、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿２及び導電体１４０＿２と、チャネル形成領域としての機能を有する酸化物１５０（絶縁体１３０＿２と重なる領域）とからなるトランジスタと、で構成されているといえる。
That is, the transistor 11 includes one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductor 120_1 and conductor 140_1, conductor 120_2, and conductor 120_2). It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region overlapping with the insulator 130_1 of the oxide 150 and a region overlapping with the insulator 130_2 of the oxide 150). Alternatively, the transistor 11 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including an oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source electrode or a drain electrode and the oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_2) is used. I can say that.
トランジスタ１１が上記構成を有することで、トランジスタ１１は、＜半導体装置の構成例１＞で示した半導体装置が有するトランジスタ１０（図１参照。）よりも大きなドレイン電流を出力させることができる。例えば、トランジスタ１１のソース電極又はドレイン電極の一方としての機能を有する導電体１２０＿１と導電体１２０＿２とを、導電体１９０＿１、導電体１８５＿１、導電体１９０＿２、及び導電体１８５＿２を介して電気的に接続し、ソース電極又はドレイン電極の他方としての機能を有する導電体１４０＿１と導電体１４０＿２とを、導電体１９５＿１、導電体２００＿１、導電体１９５＿２、及び導電体２００＿２を介して電気的に接続した場合を考える。この場合、ゲート電極としての機能を有する導電体１７０に、トランジスタ１１がオン状態となる電位を印加することで、トランジスタ１１は、同じ大きさの電位を導電体１７０に印加した場合におけるトランジスタ１０の２倍のドレイン電流を出力させることができる。トランジスタ１１が、上述したような電気的な接続構成を有することで、トランジスタ１１は、単純にトランジスタ１０を２つ併設した場合よりも小さい占有面積で、トランジスタ１０を２つ併設した場合と同等の電流出力能力を得ることができる。
When the transistor 11 has the above structure, the transistor 11 can output a drain current larger than that of the transistor 10 (see FIG. 1) included in the semiconductor device shown in <Structure Example 1 of Semiconductor Device>. For example, the conductor 120_1 functioning as one of the source electrode and the drain electrode of the transistor 11 and the conductor 120_2 are electrically connected to each other through the conductor 190_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2. In the case where the conductor 140_1 functioning as the other of the source electrode and the drain electrode and the conductor 140_2 are electrically connected to each other through the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2. Think. In this case, by applying a potential at which the transistor 11 is turned on to the conductor 170 having a function as a gate electrode, the transistor 11 has the same magnitude as that of the transistor 10 when the potential is applied to the conductor 170. Double drain current can be output. Since the transistor 11 has the above-described electrical connection configuration, the transistor 11 has an occupied area smaller than the case where the two transistors 10 are simply provided, and is equivalent to the case where the two transistors 10 are provided. Current output capability can be obtained.
また、導電体１８５＿１と導電体１８５＿２、及び導電体２００＿１と導電体２００＿２を電気的に接続せず、トランジスタ１１を構成する２つのトランジスタを、それぞれ独立して制御する構成としてもよい。すなわち、トランジスタ１１は、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿１及び導電体１４０＿１と、チャネル形成領域としての機能を有する酸化物１５０（絶縁体１３０＿１と重なる領域）とからなるトランジスタと、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿２及び導電体１４０＿２と、チャネル形成領域としての機能を有する酸化物１５０（絶縁体１３０＿２と重なる領域）とからなるトランジスタとを、それぞれ独立して制御する構成としてもよい。
Alternatively, the conductors 185_1 and 185_2, and the conductors 200_1 and 200_2 may not be electrically connected, and the two transistors included in the transistor 11 may be controlled independently. That is, the transistor 11 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including an oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source or drain electrode and the oxide 150 having a function as a channel formation region (a region overlapping with the insulator 130_2) is controlled independently. It is good also as composition to do.
なお、トランジスタ１１において、導電体１８５＿１（導電体１８５＿２）は、トランジスタ１０の導電体１８５と同じ材料を用いることができる。また、導電体１９０＿１（導電体１９０＿２）は、トランジスタ１０の導電体１９０と同じ材料を用いることができる。また、導電体１２０＿１（導電体１２０＿２）は、トランジスタ１０の導電体１２０と同じ材料を用いることができる。また、絶縁体１３０＿１（絶縁体１３０＿２）は、トランジスタ１０の絶縁体１３０と同じ材料を用いることができる。また、導電体１４０＿１（導電体１４０＿２）は、トランジスタ１０の導電体１４０と同じ材料を用いることができる。また、導電体１９５＿１（導電体１９５＿２）は、トランジスタ１０の導電体１９５と同じ材料を用いることができる。また、導電体２００＿１（導電体２００＿２）は、トランジスタ１０の導電体２００と同じ材料を用いることができる。
Note that in the transistor 11, the same material as the conductor 185 of the transistor 10 can be used for the conductor 185_1 (conductor 185_2). For the conductor 190_1 (conductor 190_2), the same material as the conductor 190 of the transistor 10 can be used. For the conductor 120_1 (conductor 120_2), the same material as the conductor 120 of the transistor 10 can be used. The insulator 130_1 (insulator 130_2) can be formed using the same material as the insulator 130 of the transistor 10. For the conductor 140_1 (conductor 140_2), the same material as the conductor 140 of the transistor 10 can be used. For the conductor 195_1 (conductor 195_2), the same material as the conductor 195 of the transistor 10 can be used. For the conductor 200_1 (conductor 200_2), the same material as the conductor 200 of the transistor 10 can be used.
トランジスタ１１を有する半導体装置において、上で説明してきた以外の構成、効果については、＜半導体装置の構成例１＞で説明したトランジスタ１０を有する半導体装置の構成、効果を参酌することができる。
Regarding the configuration and effects of the semiconductor device having the transistor 11 other than those described above, the configuration and effects of the semiconductor device having the transistor 10 described in <Semiconductor Device Configuration Example 1> can be referred to.
以上では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置とは異なる、本発明の一態様に係るトランジスタ１１を有する半導体装置の構成例について説明した。上述してきたように、本発明の一態様では、リソグラフィー法では作製することが困難な数ｎｍ、あるいはそれ以下のチャネル長の複数のトランジスタを、基板面内において、精度良くかつ容易に作製することができる。また、本発明の一態様では、基板面内において、素子間の電気特性ばらつきが小さいトランジスタを作製することができる。また、本発明の一態様では、チャネル長が微細でありながら、短チャネル効果の顕在化しにくい、良好な電気特性を有するトランジスタを作製することができる。また、本発明の一態様では、チャネル長だけでなく、配線やプラグも含めた素子サイズの微細なトランジスタを作製することができる。また、本発明の一態様では、微細でありながら、オン電流の大きなトランジスタを作製することができる。また、本発明の一態様では、上記微細なトランジスタを作製できることで、上記トランジスタを有する半導体装置の高集積化を図ることができる。また、本発明の一態様では、上記半導体装置を、高歩留まりで作製することができる。
The structure example of the semiconductor device including the transistor 11 according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device>, is described above. As described above, according to one embodiment of the present invention, a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be accurately and easily manufactured over a substrate surface. Can do. In one embodiment of the present invention, a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane. In one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured. In one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured. Further, according to one embodiment of the present invention, a transistor with high on-state current can be manufactured while being fine. In one embodiment of the present invention, the fine transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated. In one embodiment of the present invention, the semiconductor device can be manufactured with high yield.
＜半導体装置の構成例３＞
以下では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置、及び＜半導体装置の構成例２＞で示したトランジスタ１１を有する半導体装置とは異なる、本発明の一態様に係るトランジスタ１２を有する半導体装置の構成例について、図３を用いて説明する。 <Configuration Example 3 of Semiconductor Device>
The semiconductor device including thetransistor 10 described in <Structure Example 1 of Semiconductor Device> and a semiconductor device including the transistor 11 illustrated in <Structure Example 2 of Semiconductor Device> are different from those of one embodiment of the present invention. A structural example of a semiconductor device including the transistor 12 will be described with reference to FIGS.
以下では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置、及び＜半導体装置の構成例２＞で示したトランジスタ１１を有する半導体装置とは異なる、本発明の一態様に係るトランジスタ１２を有する半導体装置の構成例について、図３を用いて説明する。 <Configuration Example 3 of Semiconductor Device>
The semiconductor device including the
図３（Ａ）は、トランジスタ１２を有する半導体装置の上面図である。また、図３（Ｂ）は、図３（Ａ）にＣ１−Ｃ２の一点鎖線で示す部位の断面図である。また、図３（Ｃ）は、図３（Ａ）にＣ３−Ｃ４の一点鎖線で示す部位の断面図である。ここで、Ｃ１−Ｃ２の一点鎖線で示す部位と、Ｃ３−Ｃ４の一点鎖線で示す部位とは、互いに直交している。図３（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。
FIG. 3A is a top view of the semiconductor device having the transistor 12. FIG. 3B is a cross-sectional view taken along the dashed-dotted line C1-C2 in FIG. FIG. 3C is a cross-sectional view taken along the dashed-dotted line C3-C4 in FIG. Here, the part shown with the dashed-dotted line of C1-C2 and the part shown with the dashed-dotted line of C3-C4 are mutually orthogonal. In the top view of FIG. 3A, some elements are omitted for clarity.
なお、図３に示す半導体装置において、＜半導体装置の構成例１＞又は＜半導体装置の構成例２＞で示した半導体装置を構成する構造と同機能を有する構造には、同符号を付記している。また、以下では、主に、＜半導体装置の構成例１＞又は＜半導体装置の構成例２＞で説明した半導体装置と異なる部分について説明を行い、それ以外の部分については、＜半導体装置の構成例１＞又は＜半導体装置の構成例２＞で説明した内容を参酌できるものとする。
Note that in the semiconductor device illustrated in FIG. 3, the structure having the same function as the structure of the semiconductor device illustrated in <Semiconductor device configuration example 1> or <Semiconductor device configuration example 2> is denoted by the same reference numeral. ing. In the following description, parts different from the semiconductor device described in <Semiconductor device configuration example 1> or <semiconductor device configuration example 2> will be mainly described, and other parts will be described in <semiconductor device configuration>. The contents described in Example 1> or <Structure Example 2 of Semiconductor Device> can be referred to.
図３に示す半導体装置は、図３（Ａ）及び図３（Ｂ）に示すように、ソース電極又はドレイン電極として機能する導電体、当該導電体と上下配線を接続するプラグとしての機能を有する導電体などが、絶縁体１６０、及び導電体１７０を挟んで、対向して設けられたトランジスタ１２を有している点が、＜半導体装置の構成例１＞で示した半導体装置（図１参照。）と異なる。また、酸化物１５０が、絶縁体１６０を介して、導電体１７０の側面と向かい合う領域にのみ設けられており（酸化物１５０＿１、酸化物１５０＿２）、導電体１７０の底面と重なる領域には設けられていない点が、＜半導体装置の構成例２＞で示した半導体装置（図２参照。）と異なる。
As shown in FIGS. 3A and 3B, the semiconductor device illustrated in FIG. 3 has a function as a conductor that functions as a source electrode or a drain electrode and a plug that connects the conductor and the upper and lower wirings. The semiconductor device shown in <Structure Example 1 of Semiconductor Device> is that a conductor or the like includes the insulator 12 and the transistor 12 provided opposite to each other with the conductor 170 interposed therebetween (see FIG. 1). .). The oxide 150 is provided only in a region facing the side surface of the conductor 170 with the insulator 160 interposed therebetween (oxide 150_1 and oxide 150_2), and provided in a region overlapping with the bottom surface of the conductor 170. This is different from the semiconductor device shown in <Semiconductor device configuration example 2> (see FIG. 2).
本発明の一態様の半導体装置は、基板（図示しない。）上に、トランジスタ１２と、層間膜として機能する絶縁体１００、絶縁体１０２、絶縁体１０５、絶縁体１１０、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０と、を有する。また、トランジスタ１２と電気的に接続し、配線として機能する導電体１８５＿１、導電体１８５＿２、導電体２００＿１、及び導電体２００＿２、並びにプラグとして機能する導電体１９０＿１、導電体１９０＿２、導電体１９５＿１、及び導電体１９５＿２を有する。ここで、導電体１８５＿１、導電体１９０＿１、導電体１９５＿１、及び導電体２００＿１と、導電体１８５＿２、導電体１９０＿２、導電体１９５＿２、及び導電体２００＿２とは、いずれも絶縁体１６０及び導電体１７０を挟んで対向して設けられる（図３（Ｂ）参照。）。
In the semiconductor device of one embodiment of the present invention, the transistor 12 and the insulator 100, the insulator 102, the insulator 105, the insulator 110, the insulator 175, and the insulator which function as an interlayer film are provided over a substrate (not illustrated). 176, an insulator 178, and an insulator 180. In addition, the conductor 185_1, the conductor 185_2, the conductor 200_1, and the conductor 200_2 that are electrically connected to the transistor 12 and function as wirings, and the conductor 190_1, the conductor 190_2, the conductor 195_1, which function as plugs, and A conductor 195_2 is included. Here, the conductor 185_1, the conductor 190_1, the conductor 195_1, and the conductor 200_1, and the conductor 185_2, the conductor 190_2, the conductor 195_2, and the conductor 200_2 are all formed of the insulator 160 and the conductor 170. They are provided opposite to each other (see FIG. 3B).
なお、図３に示す半導体装置において、導電体１８５＿１（導電体１８５＿２）、導電体１９０＿１（導電体１９０＿２）、導電体１９５＿１（導電体１９５＿２）、及び導電体２００＿１（導電体２００＿２）に適用できる構成については、＜半導体装置の構成例２＞で説明した内容を参酌することができる。
Note that the semiconductor device illustrated in FIG. 3 can be applied to the conductor 185_1 (conductor 185_2), the conductor 190_1 (conductor 190_2), the conductor 195_1 (conductor 195_2), and the conductor 200_1 (conductor 200_2). For the above, the contents described in <Structural Example 2 of Semiconductor Device> can be referred to.
［トランジスタ１２］
図３（Ｂ）に示すように、トランジスタ１２は、絶縁体１１０の上に配置された導電体１２０＿１、導電体１２０＿２、酸化物１５０＿１、酸化物１５０＿２、及び絶縁体１６０と、導電体１２０＿１の上に配置された絶縁体１３０＿１と、導電体１２０＿２の上に配置された絶縁体１３０＿２と、絶縁体１３０＿１の上に配置された導電体１４０＿１と、絶縁体１３０＿２の上に配置された導電体１４０＿２と、絶縁体１６０の上に配置された導電体１７０と、を有する。ここで、導電体１２０＿１と導電体１２０＿２、絶縁体１３０＿１と絶縁体１３０＿２、導電体１４０＿１と導電体１４０＿２、及び酸化物１５０＿１と酸化物１５０＿２は、いずれも絶縁体１６０及び導電体１７０を挟んで対向して設けられる。また、酸化物１５０＿１（酸化物１５０＿２）は、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の、導電体１２０＿２（導電体１２０＿１）、絶縁体１３０＿２（絶縁体１３０＿１）、及び導電体１４０＿２（導電体１４０＿１）と対向する側面と接する領域を有するように設けられる。また、絶縁体１６０は、酸化物１５０＿１（酸化物１５０＿２）を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。また、導電体１７０は、酸化物１５０＿１（酸化物１５０＿２）及び絶縁体１６０を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。 [Transistor 12]
As illustrated in FIG. 3B, thetransistor 12 includes the conductor 120_1, the conductor 120_2, the oxide 150_1, the oxide 150_2, and the insulator 160 which are provided over the insulator 110 and the conductor 120_1. An insulator 130_1 disposed on the conductor 120_2, an insulator 130_2 disposed on the conductor 120_2, a conductor 140_1 disposed on the insulator 130_1, and a conductor 140_2 disposed on the insulator 130_2. And a conductor 170 disposed on the insulator 160. Here, the conductor 120_1 and the conductor 120_2, the insulator 130_1 and the insulator 130_2, the conductor 140_1 and the conductor 140_2, and the oxide 150_1 and the oxide 150_2 are opposite to each other with the insulator 160 and the conductor 170 interposed therebetween. Provided. In addition, the oxide 150_1 (the oxide 150_2) includes the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2), the conductor 120_2 (conductor 120_1), The insulating layer 130 </ b> _ <b> 2 (insulator 130 </ b> _ <b> 1) and the conductor 140 </ b> _ <b> 2 (conductor 140 </ b> _ <b> 1) are provided to have a region in contact with the side surface. The insulator 160 faces the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) through the oxide 150_1 (oxide 150_2). A region is provided. The conductor 170 includes the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) through the oxide 150_1 (oxide 150_2) and the insulator 160. Provided so as to have a region facing the side surface.
図３（Ｂ）に示すように、トランジスタ１２は、絶縁体１１０の上に配置された導電体１２０＿１、導電体１２０＿２、酸化物１５０＿１、酸化物１５０＿２、及び絶縁体１６０と、導電体１２０＿１の上に配置された絶縁体１３０＿１と、導電体１２０＿２の上に配置された絶縁体１３０＿２と、絶縁体１３０＿１の上に配置された導電体１４０＿１と、絶縁体１３０＿２の上に配置された導電体１４０＿２と、絶縁体１６０の上に配置された導電体１７０と、を有する。ここで、導電体１２０＿１と導電体１２０＿２、絶縁体１３０＿１と絶縁体１３０＿２、導電体１４０＿１と導電体１４０＿２、及び酸化物１５０＿１と酸化物１５０＿２は、いずれも絶縁体１６０及び導電体１７０を挟んで対向して設けられる。また、酸化物１５０＿１（酸化物１５０＿２）は、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の、導電体１２０＿２（導電体１２０＿１）、絶縁体１３０＿２（絶縁体１３０＿１）、及び導電体１４０＿２（導電体１４０＿１）と対向する側面と接する領域を有するように設けられる。また、絶縁体１６０は、酸化物１５０＿１（酸化物１５０＿２）を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。また、導電体１７０は、酸化物１５０＿１（酸化物１５０＿２）及び絶縁体１６０を介して、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と向かい合う領域を有するように設けられる。 [Transistor 12]
As illustrated in FIG. 3B, the
図３（Ｂ）及び図３（Ｃ）に示すように、導電体１２０＿１、導電体１２０＿２、絶縁体１３０＿１、絶縁体１３０＿２、導電体１４０＿１、及び導電体１４０＿２の上には、これらを覆うように絶縁体１７５が設けられる。絶縁体１７５には、導電体１２０＿１（導電体１２０＿２）、絶縁体１３０＿１（絶縁体１３０＿２）、及び導電体１４０＿１（導電体１４０＿２）の側面と内壁の一部が重なる開口が設けられ、当該開口の内壁（側面）に沿って酸化物１５０＿１と酸化物１５０＿２が設けられ、酸化物１５０＿１と酸化物１５０＿２の互いに向かい合う側面と、酸化物１５０＿１と酸化物１５０＿２の間における絶縁体１１０の上面と、を覆うように絶縁体１６０が設けられ、絶縁体１６０の上に当該開口を埋め込むように導電体１７０が設けられる。ここで、図３（Ｂ）に示すように、酸化物１５０＿１、酸化物１５０＿２、絶縁体１６０、及び導電体１７０の最上面の高さは、絶縁体１７５の上面の高さと同程度であることが好ましい。なお、図３（Ｂ）では、酸化物１５０＿１（酸化物１５０＿２）を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、酸化物１５０＿１（酸化物１５０＿２）は、２層以上の積層構造であってもよい。
As shown in FIGS. 3B and 3C, the conductor 120_1, the conductor 120_2, the insulator 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2 are covered so as to cover them. An insulator 175 is provided. The insulator 175 is provided with an opening in which the side surface of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) overlap with part of the inner wall. The oxide 150_1 and the oxide 150_2 are provided along the inner wall (side surface), and cover the side surfaces of the oxide 150_1 and the oxide 150_2 facing each other and the upper surface of the insulator 110 between the oxide 150_1 and the oxide 150_2. The insulator 160 is provided, and the conductor 170 is provided on the insulator 160 so as to embed the opening. Here, as shown in FIG. 3B, the heights of the top surfaces of the oxide 150_1, the oxide 150_2, the insulator 160, and the conductor 170 are approximately the same as the height of the top surface of the insulator 175. Is preferred. Note that although FIG. 3B illustrates the oxide 150_1 (oxide 150_2) as a single-layer structure, one embodiment of the present invention is not limited thereto. For example, the oxide 150_1 (oxide 150_2) may have a stacked structure of two or more layers.
トランジスタ１２において、導電体１２０＿１は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０＿１は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５０＿１の絶縁体１３０＿１と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６０は、ゲート絶縁体としての機能を有し、導電体１７０は、ゲート電極としての機能を有する。同様に、トランジスタ１２において、導電体１２０＿２は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０＿２は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５０＿２の絶縁体１３０＿２と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６０は、ゲート絶縁体としての機能を有し、導電体１７０は、ゲート電極としての機能を有する。
In the transistor 12, the conductor 120_1 functions as one of the source electrode and the drain electrode, the conductor 140_1 functions as the other of the source electrode and the drain electrode, and the insulator 120_1 of the oxide 150_1 The overlapping region has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode. Similarly, in the transistor 12, the conductor 120_2 functions as one of a source electrode and a drain electrode, and the conductor 140_2 functions as the other of the source electrode and the drain electrode, and the oxide 150_2 is insulated. The region overlapping with the body 130_2 has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode.
すなわち、トランジスタ１２は、１つのゲート電極（導電体１７０）と、１つのゲート絶縁体（絶縁体１６０）と、２組のソース電極又はドレイン電極（導電体１２０＿１及び導電体１４０＿１、導電体１２０＿２及び導電体１４０＿２）と、２つのチャネル形成領域（酸化物１５０＿１の絶縁体１３０＿１と重なる領域、酸化物１５０＿２の絶縁体１３０＿２と重なる領域）と、で構成されたトランジスタであるといえる。あるいは、トランジスタ１２は、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿１及び導電体１４０＿１と、チャネル形成領域としての機能を有する酸化物１５０＿１（絶縁体１３０＿１と重なる領域）とからなるトランジスタと、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿２及び導電体１４０＿２と、チャネル形成領域としての機能を有する酸化物１５０＿２（絶縁体１３０＿２と重なる領域）とからなるトランジスタと、で構成されているといえる。
That is, the transistor 12 includes one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductor 120_1 and conductor 140_1, conductor 120_2, and conductor 120_2). It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region overlapping with the insulator 130_1 of the oxide 150_1 and a region overlapping with the insulator 130_2 of the oxide 150_2). Alternatively, the transistor 12 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including the oxide 150_1 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, and an insulator 160 having a function as a gate insulator; A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source electrode or a drain electrode, and an oxide 150_2 having a function as a channel formation region (a region overlapping with the insulator 130_2). I can say that.
トランジスタ１２が上記構成を有することで、トランジスタ１２は、＜半導体装置の構成例１＞で示した半導体装置が有するトランジスタ１０（図１参照。）よりも大きなドレイン電流を出力させることができる。例えば、トランジスタ１２のソース電極又はドレイン電極の一方としての機能を有する導電体１２０＿１と導電体１２０＿２とを、導電体１９０＿１、導電体１８５＿１、導電体１９０＿２、及び導電体１８５＿２を介して電気的に接続し、ソース電極又はドレイン電極の他方としての機能を有する導電体１４０＿１と導電体１４０＿２とを、導電体１９５＿１、導電体２００＿１、導電体１９５＿２、及び導電体２００＿２を介して電気的に接続した場合を考える。この場合、ゲート電極としての機能を有する導電体１７０に、トランジスタ１２がオン状態となる電位を印加することで、トランジスタ１２は、同じ大きさの電位を導電体１７０に印加した場合におけるトランジスタ１０の２倍のドレイン電流を出力させることができる。トランジスタ１２が、上述したような電気的な接続構成を有することで、トランジスタ１２は、単純にトランジスタ１０を２つ併設した場合よりも小さい占有面積で、トランジスタ１０を２つ併設した場合と同等の電流出力能力を得ることができる。
Since the transistor 12 has the above structure, the transistor 12 can output a larger drain current than the transistor 10 (see FIG. 1) included in the semiconductor device shown in <Structure Example 1 of Semiconductor Device>. For example, the conductor 120_1 functioning as one of the source electrode and the drain electrode of the transistor 12 and the conductor 120_2 are electrically connected to each other through the conductor 190_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2. In the case where the conductor 140_1 functioning as the other of the source electrode and the drain electrode and the conductor 140_2 are electrically connected to each other through the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2. Think. In this case, by applying a potential at which the transistor 12 is turned on to the conductor 170 having a function as a gate electrode, the transistor 12 has the same magnitude as the potential of the transistor 10 when the potential is applied to the conductor 170. Double drain current can be output. Since the transistor 12 has an electrical connection configuration as described above, the transistor 12 has an occupied area smaller than that in the case where two transistors 10 are simply provided, and is equivalent to the case where two transistors 10 are provided. Current output capability can be obtained.
また、導電体１８５＿１と導電体１８５＿２、及び導電体２００＿１と導電体２００＿２を電気的に接続せず、トランジスタ１２を構成する２つのトランジスタを、それぞれ独立して制御する構成としてもよい。すなわち、トランジスタ１２は、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿１及び導電体１４０＿１と、チャネル形成領域としての機能を有する酸化物１５０＿１（絶縁体１３０＿１と重なる領域）とからなるトランジスタと、ゲート電極としての機能を有する導電体１７０と、ゲート絶縁体としての機能を有する絶縁体１６０と、ソース電極又はドレイン電極としての機能を有する導電体１２０＿２及び導電体１４０＿２と、チャネル形成領域としての機能を有する酸化物１５０＿２（絶縁体１３０＿２と重なる領域）とからなるトランジスタとを、それぞれ独立して制御する構成としてもよい。
Alternatively, the conductors 185_1 and 185_2 and the conductors 200_1 and 200_2 may not be electrically connected, and the two transistors included in the transistor 12 may be controlled independently. That is, the transistor 12 includes a conductor 170 having a function as a gate electrode, an insulator 160 having a function as a gate insulator, a conductor 120_1 and a conductor 140_1 having a function as a source electrode or a drain electrode, A transistor including the oxide 150_1 having a function as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 having a function as a gate electrode, and an insulator 160 having a function as a gate insulator; A transistor including the conductor 120_2 and the conductor 140_2 having a function as a source electrode or a drain electrode and the oxide 150_2 having a function as a channel formation region (a region overlapping with the insulator 130_2) is controlled independently. It is good also as composition to do.
ここで、図３に示す半導体装置が有するトランジスタ１２は、図２に示す半導体装置が有するトランジスタ１１と比べて、チャネル形成領域を有する酸化物の形状が異なる。具体的には、トランジスタ１１が、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１と、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２の、互いに向かい合う側面と、絶縁体１１０の上面の一部と、に接する酸化物１５０を有するのに対し、トランジスタ１２は、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１の、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２と対向する側面に接する酸化物１５０＿１と、導電体１２０＿２、絶縁体１３０＿２、及び導電体１４０＿２の、導電体１２０＿１、絶縁体１３０＿１、及び導電体１４０＿１と対向する側面に接する酸化物１５０＿２と、を有する。すなわち、トランジスタ１２では、チャネル形成領域を有する酸化物が、絶縁体１６０及び導電体１７０を挟んで２つ（酸化物１５０＿１、酸化物１５０＿２）に分断されている点が、トランジスタ１１の酸化物１５０と異なる。チャネル形成領域を有する酸化物は、導電性を有する。そのため、例えば、上述したトランジスタ１２を構成する２つのトランジスタを、それぞれ独立して制御する場合、当該２つのトランジスタ間で、酸化物を介したリークが発生するのを抑制することができる。これにより、トランジスタ１２を構成する一方のトランジスタの動作（オン動作、オフ動作）時の影響を、他方のトランジスタが受けにくくなり、それぞれの動作を確実に制御することができる。
Here, the transistor 12 included in the semiconductor device illustrated in FIG. 3 is different from the transistor 11 included in the semiconductor device illustrated in FIG. 2 in the shape of an oxide having a channel formation region. Specifically, the transistor 11 includes the conductor 120_1, the insulator 130_1, and the conductor 140_1, the side surfaces of the conductor 120_2, the insulator 130_2, and the conductor 140_2 that face each other and part of the top surface of the insulator 110. In contrast, the transistor 12 includes an oxide 150 in contact with a side surface of the conductor 120_1, the insulator 130_1, and the conductor 140_1 that faces the conductor 120_2, the insulator 130_2, and the conductor 140_2. And the oxide 120_2 in contact with the side surface of the conductor 120_1, the insulator 130_1, and the conductor 140_1 opposite to the conductor 120_1. That is, in the transistor 12, the oxide having a channel formation region is divided into two (oxide 150_1 and oxide 150_2) with the insulator 160 and the conductor 170 interposed therebetween. And different. An oxide having a channel formation region has conductivity. Therefore, for example, when the two transistors included in the above-described transistor 12 are controlled independently, it is possible to suppress the occurrence of leakage via an oxide between the two transistors. This makes it difficult for the other transistor to be affected by the operation (on operation, off operation) of one of the transistors constituting the transistor 12, and each operation can be reliably controlled.
なお、トランジスタ１２において、酸化物１５０＿１（酸化物１５０＿２）は、トランジスタ１０の酸化物１５０と同じ材料を用いることができる。また、導電体１８５＿１（導電体１８５＿２）は、トランジスタ１０の導電体１８５と同じ材料を用いることができる。また、導電体１９０＿１（導電体１９０＿２）は、トランジスタ１０の導電体１９０と同じ材料を用いることができる。また、導電体１２０＿１（導電体１２０＿２）は、トランジスタ１０の導電体１２０と同じ材料を用いることができる。また、絶縁体１３０＿１（絶縁体１３０＿２）は、トランジスタ１０の絶縁体１３０と同じ材料を用いることができる。また、導電体１４０＿１（導電体１４０＿２）は、トランジスタ１０の導電体１４０と同じ材料を用いることができる。また、導電体１９５＿１（導電体１９５＿２）は、トランジスタ１０の導電体１９５と同じ材料を用いることができる。また、導電体２００＿１（導電体２００＿２）は、トランジスタ１０の導電体２００と同じ材料を用いることができる。
Note that in the transistor 12, the same material as the oxide 150 of the transistor 10 can be used for the oxide 150_1 (oxide 150_2). For the conductor 185_1 (conductor 185_2), the same material as the conductor 185 of the transistor 10 can be used. For the conductor 190_1 (conductor 190_2), the same material as the conductor 190 of the transistor 10 can be used. For the conductor 120_1 (conductor 120_2), the same material as the conductor 120 of the transistor 10 can be used. The insulator 130_1 (insulator 130_2) can be formed using the same material as the insulator 130 of the transistor 10. For the conductor 140_1 (conductor 140_2), the same material as the conductor 140 of the transistor 10 can be used. For the conductor 195_1 (conductor 195_2), the same material as the conductor 195 of the transistor 10 can be used. For the conductor 200_1 (conductor 200_2), the same material as the conductor 200 of the transistor 10 can be used.
トランジスタ１２を有する半導体装置において、上で説明してきた以外の構成、効果については、＜半導体装置の構成例１＞で説明したトランジスタ１０を有する半導体装置、又は＜半導体装置の構成例２＞で説明したトランジスタ１１を有する半導体装置の構成、効果を参酌することができる。
The structure and effects of the semiconductor device including the transistor 12 other than those described above are described in <Semiconductor Device Constitution Example 1> described in <Semiconductor Device Configuration Example 1> or <Semiconductor Device Configuration Example 2>. The structure and effects of the semiconductor device including the transistor 11 can be taken into consideration.
以上では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置、又は＜半導体装置の構成例２＞で示したトランジスタ１１を有する半導体装置とは異なる、本発明の一態様に係るトランジスタ１２を有する半導体装置の構成例について説明した。上述してきたように、本発明の一態様では、リソグラフィー法では作製することが困難な数ｎｍ、あるいはそれ以下のチャネル長の複数のトランジスタを、基板面内において、精度良くかつ容易に作製することができる。また、本発明の一態様では、基板面内において、素子間の電気特性ばらつきが小さいトランジスタを作製することができる。また、本発明の一態様では、チャネル長が微細でありながら、短チャネル効果の顕在化しにくい、良好な電気特性を有するトランジスタを作製することができる。また、本発明の一態様では、チャネル長だけでなく、配線やプラグも含めた素子サイズの微細なトランジスタを作製することができる。また、本発明の一態様では、微細でありながら、オン電流の大きなトランジスタを作製することができる。また、本発明の一態様では、上記微細なトランジスタを作製できることで、上記トランジスタを有する半導体装置の高集積化を図ることができる。また、本発明の一態様では、高集積でありながら、隣接するトランジスタ間のリークが小さい半導体装置を作製することができる。また、本発明の一態様では、上記半導体装置を、高歩留まりで作製することができる。
The above is different from the semiconductor device including the transistor 10 described in <Structural Example 1 of Semiconductor Device> or the semiconductor device including the transistor 11 illustrated in <Structural Example 2 of the semiconductor device> according to one embodiment of the present invention. The structural example of the semiconductor device including the transistor 12 has been described. As described above, according to one embodiment of the present invention, a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and ease over a substrate. Can do. In one embodiment of the present invention, a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane. In one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured. In one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured. Further, according to one embodiment of the present invention, a transistor with high on-state current can be manufactured while being fine. In one embodiment of the present invention, the fine transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated. According to one embodiment of the present invention, a semiconductor device with high integration and low leakage between adjacent transistors can be manufactured. In one embodiment of the present invention, the semiconductor device can be manufactured with high yield.
＜半導体装置の変形例＞
以下では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置の変形例として、本発明の一態様に係るトランジスタ１３を有する半導体装置について、図４を用いて説明する。 <Modification of semiconductor device>
Hereinafter, as a modification example of the semiconductor device including thetransistor 10 described in <Structural Example 1 of Semiconductor Device>, a semiconductor device including the transistor 13 according to one embodiment of the present invention will be described with reference to FIGS.
以下では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置の変形例として、本発明の一態様に係るトランジスタ１３を有する半導体装置について、図４を用いて説明する。 <Modification of semiconductor device>
Hereinafter, as a modification example of the semiconductor device including the
図４（Ａ）は、トランジスタ１３を有する半導体装置の上面図である。また、図４（Ｂ）は、図４（Ａ）にＤ１−Ｄ２の一点鎖線で示す部位の断面図である。また、図４（Ｃ）は、図４（Ａ）にＤ３−Ｄ４の一点鎖線で示す部位の断面図である。ここで、Ｄ１−Ｄ２の一点鎖線で示す部位と、Ｄ３−Ｄ４の一点鎖線で示す部位とは、互いに直交している。図４（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。
FIG. 4A is a top view of the semiconductor device having the transistor 13. FIG. 4B is a cross-sectional view taken along the dashed-dotted line D1-D2 in FIG. FIG. 4C is a cross-sectional view taken along the dashed-dotted line D3-D4 in FIG. Here, the part shown with the dashed-dotted line of D1-D2 and the part shown with the dashed-dotted line of D3-D4 are mutually orthogonally crossed. In the top view of FIG. 4A, some elements are omitted for clarity.
なお、図４に示す半導体装置において、＜半導体装置の構成例１＞乃至＜半導体装置の構成例３＞で示した半導体装置を構成する構造と同機能を有する構造には、同符号を付記している。また、以下では、主に、＜半導体装置の構成例１＞乃至＜半導体装置の構成例３＞で説明した半導体装置と異なる部分について説明を行い、それ以外の部分については、＜半導体装置の構成例１＞乃至＜半導体装置の構成例３＞で説明した内容を参酌できるものとする。
Note that in the semiconductor device illustrated in FIGS. 4A and 4B, structures having the same functions as those of the semiconductor device illustrated in <Structure Example 1 of Semiconductor Device> to <Structure Example 3 of the semiconductor device> are denoted by the same reference numerals. ing. In the following description, parts different from the semiconductor device described in <Structure Example 1 of Semiconductor Device> to <Structure Example 3 of Semiconductor Device> will be mainly described, and other parts will be described in <Structure of Semiconductor Device>. The contents described in Example 1> to <Structure Example 3 of Semiconductor Device> can be referred to.
図４に示す半導体装置は、図４（Ｂ）及び図４（Ｃ）に示すように、ゲート電極として機能する導電体１７１が、チャネル形成領域としての機能を有する酸化物１５１及びゲート絶縁体として機能する絶縁体１６１を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面だけでなく、導電体１４０の上面の一部とも重なる領域を有するトランジスタ１３を有している点が、＜半導体装置の構成例１＞で示した半導体装置（図１参照。）と異なる。
In the semiconductor device illustrated in FIGS. 4A and 4B, as illustrated in FIGS. 4B and 4C, the conductor 171 functioning as a gate electrode includes an oxide 151 functioning as a channel formation region and a gate insulator. The transistor 13 has a region that overlaps not only the side surfaces of the conductor 120, the insulator 130, and the conductor 140 but also part of the upper surface of the conductor 140 with the functioning insulator 161 interposed therebetween. It differs from the semiconductor device shown in <Structure Example 1 of Semiconductor Device> (see FIG. 1).
本発明の一態様の半導体装置は、基板（図示しない。）上に、トランジスタ１３と、層間膜として機能する絶縁体１００、絶縁体１０２、絶縁体１０５、絶縁体１１０、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０と、を有する。また、トランジスタ１３と電気的に接続し、配線として機能する導電体１８５、及び導電体２００、並びにプラグとして機能する導電体１９０、及び導電体１９５を有する。
The semiconductor device of one embodiment of the present invention includes the transistor 13 and the insulator 100, the insulator 102, the insulator 105, the insulator 110, the insulator 175, and the insulator which function as an interlayer film over a substrate (not illustrated). 176, an insulator 178, and an insulator 180. In addition, a conductor 185 and a conductor 200 which are electrically connected to the transistor 13 and function as wirings, and a conductor 190 and a conductor 195 which function as plugs are included.
なお、図４に示す半導体装置において、導電体１８５、導電体１９０、導電体１９５、及び導電体２００に適用できる構成については、＜半導体装置の構成例１＞で説明した内容を参酌することができる。
Note that in the semiconductor device illustrated in FIGS. 4A and 4B, the description in <Structure Example 1 of Semiconductor Device> can be referred to for structures that can be applied to the conductor 185, the conductor 190, the conductor 195, and the conductor 200. it can.
［トランジスタ１３］
図４（Ｂ）に示すように、トランジスタ１３は、絶縁体１１０の上に配置された導電体１２０及び酸化物１５１と、導電体１２０の上に配置された絶縁体１３０と、絶縁体１３０の上に配置された導電体１４０と、酸化物１５１の上に配置された絶縁体１６１と、絶縁体１６１の上に配置された導電体１７１と、を有する。ここで、酸化物１５１は、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０の上面の一部と、に接する領域を有するように設けられる。また、絶縁体１６１は、酸化物１５１を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０上面の一部と、に重なる領域を有するように設けられる。また、導電体１７１は、酸化物１５１及び絶縁体１６１を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０の上面の一部と、に重なる領域を有するように設けられる。 [Transistor 13]
4B, thetransistor 13 includes a conductor 120 and an oxide 151 which are disposed over the insulator 110, an insulator 130 which is disposed over the conductor 120, and the insulator 130. The conductor 140 disposed above, the insulator 161 disposed on the oxide 151, and the conductor 171 disposed on the insulator 161 are included. Here, the oxide 151 is provided so as to have a region in contact with the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and part of the top surface of the conductor 140. The insulator 161 is provided so as to have a region overlapping with the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and part of the top surface of the conductor 140 with the oxide 151 interposed therebetween. The conductor 171 has a region overlapping with the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and part of the upper surface of the conductor 140 with the oxide 151 and the insulator 161 interposed therebetween. Is provided.
図４（Ｂ）に示すように、トランジスタ１３は、絶縁体１１０の上に配置された導電体１２０及び酸化物１５１と、導電体１２０の上に配置された絶縁体１３０と、絶縁体１３０の上に配置された導電体１４０と、酸化物１５１の上に配置された絶縁体１６１と、絶縁体１６１の上に配置された導電体１７１と、を有する。ここで、酸化物１５１は、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０の上面の一部と、に接する領域を有するように設けられる。また、絶縁体１６１は、酸化物１５１を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０上面の一部と、に重なる領域を有するように設けられる。また、導電体１７１は、酸化物１５１及び絶縁体１６１を介して、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０の上面の一部と、に重なる領域を有するように設けられる。 [Transistor 13]
4B, the
図４（Ｂ）に示すように、導電体１２０、絶縁体１３０、及び導電体１４０の上には、これらを覆うように絶縁体１７５が設けられる。絶縁体１７５には、導電体１２０、絶縁体１３０、及び導電体１４０の側面と、導電体１４０の上面の一部と、に内壁の一部が重なる開口が設けられ、当該開口の内壁に沿って酸化物１５１が設けられ、酸化物１５１の上に絶縁体１６１が設けられ、絶縁体１６１の上に当該開口を埋め込むように導電体１７１が設けられる。ここで、図４（Ｂ）に示すように、酸化物１５１、絶縁体１６１、及び導電体１７１の最上面の高さは、絶縁体１７５の上面の高さと同程度であることが好ましい。なお、図４（Ｂ）では、酸化物１５１を単層構造として示しているが、本発明の一態様はこれに限られない。例えば、酸化物１５１は、２層以上の積層構造であってもよい。
As shown in FIG. 4B, an insulator 175 is provided on the conductor 120, the insulator 130, and the conductor 140 so as to cover them. The insulator 175 is provided with an opening in which a part of the inner wall overlaps a side surface of the conductor 120, the insulator 130, and the conductor 140 and a part of the upper surface of the conductor 140, and extends along the inner wall of the opening. The oxide 151 is provided, the insulator 161 is provided over the oxide 151, and the conductor 171 is provided over the insulator 161 so as to fill the opening. Here, as illustrated in FIG. 4B, the heights of the top surfaces of the oxide 151, the insulator 161, and the conductor 171 are preferably approximately the same as the height of the top surface of the insulator 175. Note that although FIG. 4B illustrates the oxide 151 as a single-layer structure, one embodiment of the present invention is not limited thereto. For example, the oxide 151 may have a stacked structure including two or more layers.
トランジスタ１３において、導電体１２０は、ソース電極又はドレイン電極の一方としての機能を有し、導電体１４０は、ソース電極又はドレイン電極の他方としての機能を有し、酸化物１５１の絶縁体１３０と重なる領域は、チャネル形成領域としての機能を有し、絶縁体１６１は、ゲート絶縁体としての機能を有し、導電体１７１は、ゲート電極としての機能を有する。
In the transistor 13, the conductor 120 functions as one of a source electrode and a drain electrode, and the conductor 140 functions as the other of the source electrode and the drain electrode. The overlapping region has a function as a channel formation region, the insulator 161 has a function as a gate insulator, and the conductor 171 has a function as a gate electrode.
ここで、トランジスタ１０が、酸化物１５０と絶縁体１３０の接触面を、図１（Ｂ）に示す１箇所だけ有するのに対し、トランジスタ１３は、酸化物１５１と絶縁体１３０の接触面を、図４（Ｂ）に示す１箇所と、図４（Ｃ）に示す２箇所の、計３箇所有するという違いを有する。すなわち、トランジスタ１０と、トランジスタ１３とでは、それぞれが有する酸化物（酸化物１５０又は酸化物１５１）において、チャネル形成領域として機能できる領域の面積に違いを有する（トランジスタ１３のほうが、トランジスタ１０よりも、チャネル形成領域として機能し得る酸化物の面積が大きい。）。このため、トランジスタ１３は、トランジスタ１０と素子サイズが同程度でありながら、トランジスタ１０よりも大きなドレイン電流を出力させることができる。
Here, the transistor 10 has only one contact surface between the oxide 150 and the insulator 130 shown in FIG. 1B, whereas the transistor 13 has a contact surface between the oxide 151 and the insulator 130. There is a difference in that there are a total of three places, one place shown in FIG. 4B and two places shown in FIG. That is, the transistor 10 and the transistor 13 each have a difference in the area of a region that can function as a channel formation region in the oxide (the oxide 150 or the oxide 151) (the transistor 13 is more than the transistor 10). The area of the oxide that can function as a channel formation region is large.) Therefore, the transistor 13 can output a larger drain current than the transistor 10 while having the same element size as the transistor 10.
また、トランジスタ１３は、ゲート電極として機能する導電体１７１が、導電体１４０の上面の一部と重なる領域を有することが、トランジスタ１０と異なる。トランジスタ１３が当該構造を有することで、図４（Ｃ）に示すように、チャネル形成領域（酸化物１５１の絶縁体１３０と重なる領域）を、導電体１７１で囲い込むことができる。したがって、トランジスタ１３は、トランジスタ１０と比べて、より確実にチャネル形成領域にゲート電界を印加する制御性を上げることができる。このため、トランジスタ１３は、動作（オン動作、オフ動作）時のキャリアの制御を確実に行うことができ、トランジスタ１０よりも大きなオン電流と、小さなオフ電流の双方を実現することができる。
Further, the transistor 13 is different from the transistor 10 in that the conductor 171 functioning as a gate electrode has a region overlapping with a part of the upper surface of the conductor 140. With the transistor 13 having this structure, a channel formation region (a region overlapping with the insulator 130 of the oxide 151) can be surrounded by the conductor 171 as illustrated in FIG. Therefore, the transistor 13 can improve the controllability of applying the gate electric field to the channel formation region more reliably than the transistor 10. Therefore, the transistor 13 can reliably control the carrier during operation (on operation, off operation), and can realize both a larger on-current and a smaller off-current than the transistor 10.
なお、トランジスタ１３において、酸化物１５１は、トランジスタ１０の酸化物１５０と同じ材料を用いることができる。また、絶縁体１６１は、トランジスタ１０の絶縁体１６０と同じ材料を用いることができる。また、導電体１７１は、トランジスタ１０の導電体１７０と同じ材料を用いることができる。
Note that in the transistor 13, the oxide 151 can be formed using the same material as the oxide 150 of the transistor 10. The insulator 161 can be formed using the same material as the insulator 160 of the transistor 10. For the conductor 171, the same material as the conductor 170 of the transistor 10 can be used.
トランジスタ１３を有する半導体装置において、上で説明してきた以外の構成、効果については、＜半導体装置の構成例１＞で説明したトランジスタ１０を有する半導体装置、＜半導体装置の構成例２＞で説明したトランジスタ１１を有する半導体装置、又は＜半導体装置の構成例３＞で説明したトランジスタ１２を有する半導体装置の構成、効果を参酌することができる。
Regarding the structure and effects of the semiconductor device including the transistor 13 other than those described above, the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device> and <Structure Example 2 of Semiconductor Device> are described. The structure and effects of the semiconductor device including the transistor 11 or the semiconductor device including the transistor 12 described in <Structure Example 3 of Semiconductor Device> can be considered.
以上では、＜半導体装置の構成例１＞で示したトランジスタ１０を有する半導体装置の変形例として、本発明の一態様に係るトランジスタ１３を有する半導体装置の構成例について説明した。上述してきたように、本発明の一態様では、リソグラフィー法では作製することが困難な数ｎｍ、あるいはそれ以下のチャネル長の複数のトランジスタを、基板面内において、精度良くかつ容易に作製することができる。また、本発明の一態様では、基板面内において、素子間の電気特性ばらつきが小さいトランジスタを作製することができる。また、本発明の一態様では、オン電流の大きなトランジスタを作製することができる。また、本発明の一態様では、オフ電流の小さなトランジスタを作製することができる。また、本発明の一態様では、チャネル長が微細でありながら、短チャネル効果の顕在化しにくい、良好な電気特性を有するトランジスタを作製することができる。また、本発明の一態様では、チャネル長だけでなく、配線やプラグも含めた素子サイズの微細なトランジスタを作製することができる。また、また、本発明の一態様では、上記微細なトランジスタを作製できることで、上記トランジスタを有する半導体装置の高集積化を図ることができる。また、本発明の一態様では、上記半導体装置を、高歩留まりで作製することができる。
The structure example of the semiconductor device including the transistor 13 according to one embodiment of the present invention is described above as a modification example of the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device>. As described above, according to one embodiment of the present invention, a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and ease over a substrate. Can do. In one embodiment of the present invention, a transistor with small variation in electrical characteristics between elements can be manufactured in a substrate plane. In one embodiment of the present invention, a transistor with high on-state current can be manufactured. In one embodiment of the present invention, a transistor with low off-state current can be manufactured. In one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short channel effect is difficult to be realized although a channel length is fine can be manufactured. In one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring or a plug can be manufactured. In addition, according to one embodiment of the present invention, the minute transistor can be manufactured, so that the semiconductor device including the transistor can be highly integrated. In one embodiment of the present invention, the semiconductor device can be manufactured with high yield.
本発明の一態様に係る半導体装置の一例は、上で説明してきたトランジスタ１０、トランジスタ１１、トランジスタ１２、又はトランジスタ１３を有する半導体装置（図１乃至図４参照。）に限られない。本発明の一態様に係る半導体装置は、上で説明してきた各半導体装置の構成を適宜組み合わせて用いることができる。
An example of a semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device including the transistor 10, the transistor 11, the transistor 12, or the transistor 13 (see FIGS. 1 to 4) described above. The semiconductor device according to one embodiment of the present invention can be combined with any of the structures of the semiconductor devices described above as appropriate.
＜半導体装置の構成要素＞
以下では、本発明の一態様に係るトランジスタ１０、トランジスタ１１、トランジスタ１２、又はトランジスタ１３を有する半導体装置（図１乃至図４参照。）に適用できる各構成要素について詳細に説明する。 <Constituent elements of semiconductor device>
Hereinafter, each component applicable to the semiconductor device (see FIGS. 1 to 4) including thetransistor 10, the transistor 11, the transistor 12, or the transistor 13 according to one embodiment of the present invention is described in detail.
以下では、本発明の一態様に係るトランジスタ１０、トランジスタ１１、トランジスタ１２、又はトランジスタ１３を有する半導体装置（図１乃至図４参照。）に適用できる各構成要素について詳細に説明する。 <Constituent elements of semiconductor device>
Hereinafter, each component applicable to the semiconductor device (see FIGS. 1 to 4) including the
〔基板〕
基板としては、例えば、絶縁体基板、半導体基板、又は導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、又は炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。又は、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体又は半導体が設けられた基板、半導体基板に導電体又は絶縁体が設けられた基板、導電体基板に半導体又は絶縁体が設けられた基板などがある。又は、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 〔substrate〕
As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate including a metal nitride, a substrate including a metal oxide, and the like. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
基板としては、例えば、絶縁体基板、半導体基板、又は導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、又は炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。又は、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体又は半導体が設けられた基板、半導体基板に導電体又は絶縁体が設けられた基板、導電体基板に半導体又は絶縁体が設けられた基板などがある。又は、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 〔substrate〕
As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate including a metal nitride, a substrate including a metal oxide, and the like. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
また、基板として、可撓性基板を用いてもよい。なお、可撓性基板上にトランジスタを設ける方法としては、非可撓性の基板上にトランジスタを作製した後、トランジスタを剥離し、可撓性基板である基板に転置する方法もある。その場合には、非可撓性基板とトランジスタとの間に剥離層を設けるとよい。なお、基板として、繊維を編み込んだシート、フィルム又は箔などを用いてもよい。また、基板が伸縮性を有してもよい。また、基板は、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有してもよい。又は、元の形状に戻らない性質を有してもよい。基板は、例えば、５μｍ以上７００μｍ以下、好ましくは１０μｍ以上５００μｍ以下、さらに好ましくは１５μｍ以上３００μｍ以下の厚さとなる領域を有する。基板を薄くすると、トランジスタを有する半導体装置を軽量化することができる。また、基板を薄くすることで、ガラスなどを用いた場合にも伸縮性を有する場合や、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有する場合がある。そのため、落下などによって基板上の半導体装置に加わる衝撃などを緩和することができる。すなわち、丈夫な半導体装置を提供することができる。
Further, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled and transferred to a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. In addition, you may use the sheet | seat, film, foil, etc. which braided the fiber as a board | substrate. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.
可撓性性基板である基板としては、例えば、金属、合金、樹脂、若しくはガラス、又はそれらの繊維などを用いることができる。可撓性基板である基板は、線膨張率が低いほど環境による変形が抑制されて好ましい。可撓性基板である基板としては、例えば、線膨張率が１×１０−３／Ｋ以下、５×１０−５／Ｋ以下、又は１×１０−５／Ｋ以下である材質を用いればよい。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート、アクリルなどがある。特に、アラミドは、線膨張率が低いため、可撓性基板である基板として好適である。
As the substrate which is a flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. A substrate that is a flexible substrate is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed. As the substrate that is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 −3 / K or less, 5 × 10 −5 / K or less, or 1 × 10 −5 / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
〔絶縁体〕
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 〔Insulator〕
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 〔Insulator〕
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
絶縁体１００、絶縁体１０５、絶縁体１１０、絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）、及び絶縁体１６０としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム、又はタンタルを含む絶縁体を、単層で、又は積層で用いればよい。例えば、絶縁体１００、絶縁体１０５、絶縁体１１０、絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）、及び絶縁体１６０としては、酸化シリコン、酸化窒化シリコン、又は窒化シリコンを有することが好ましい。
As the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), and the insulator 160, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, An insulator containing silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. For example, the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), and the insulator 160 include silicon oxide, silicon oxynitride, or silicon nitride. preferable.
絶縁体１０５、絶縁体１１０、及び絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）中の水、水素、又は窒素酸化物などの不純物濃度は、低減されていることが好ましい。例えば、絶縁体１０５、絶縁体１１０、及び絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）の水素の脱離量は、昇温脱離ガス分析法（ＴＤＳ（Ｔｈｅｒｍａｌ Ｄｅｓｏｒｐｔｉｏｎ Ｓｐｅｃｔｒｏｓｃｏｐｙ））において、膜の表面温度が５０℃から５００℃の範囲において、水素分子に換算した脱離量が、絶縁体１０５、絶縁体１１０、又は絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）の面積当たりに換算して、２×１０１５ｍｏｌｅｃｕｌｅｓ／ｃｍ２以下、好ましくは１×１０１５ｍｏｌｅｃｕｌｅｓ／ｃｍ２以下、より好ましくは５×１０１４ｍｏｌｅｃｕｌｅｓ／ｃｍ２以下であればよい。また、絶縁体１０５、絶縁体１１０、及び絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）は、加熱により酸素が放出される絶縁体を用いて形成することが好ましい。当該絶縁体を絶縁体１０５、絶縁体１１０、及び絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）に用いることで、絶縁体１０５、絶縁体１１０、及び絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）から、酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）に、効果的に酸素を供給することができる。
The concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) is preferably reduced. For example, the desorption amount of hydrogen of the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) is determined by a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). When the surface temperature of the film is in the range of 50 ° C. to 500 ° C., the amount of desorption converted to hydrogen molecules corresponds to the area of the insulator 105, the insulator 110, or the insulator 130 (or the insulator 130_1 and the insulator 130_2). It is 2 × 10 15 molecules / cm 2 or less, preferably 1 × 10 15 molecules / cm 2 or less, more preferably 5 × 10 14 molecules / cm 2 or less. The insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) are preferably formed using an insulator from which oxygen is released by heating. By using the insulator for the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2), the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1) are used. In addition, oxygen can be effectively supplied from the insulator 130_2 to the oxide 150 (or the oxide 150_1 and the oxide 150_2).
また、絶縁体１６０は、比誘電率の高い絶縁体を有することが好ましい。例えば、絶縁体１６０は、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、酸化アルミニウム、アルミニウム及びハフニウムを有する酸化物、アルミニウム及びハフニウムを有する酸化窒化物、シリコン及びハフニウムを有する酸化物、シリコン及びハフニウムを有する酸化窒化物、又は、シリコン及びハフニウムを有する窒化物などを有することが好ましい。又は、絶縁体１６０は、酸化シリコン又は酸化窒化シリコンと、比誘電率の高い絶縁体と、の積層構造を有することが好ましい。酸化シリコン及び酸化窒化シリコンは、熱的に安定であるため、比誘電率の高い絶縁体と組み合わせることで、欠陥の少ない膜で熱的に安定かつ比誘電率の高い積層構造とすることができる。
In addition, the insulator 160 preferably includes an insulator having a high relative dielectric constant. For example, the insulator 160 includes gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, an oxide including silicon and hafnium, an oxide including silicon and hafnium. It is preferable to include a nitride or a nitride including silicon and hafnium. Alternatively, the insulator 160 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, when combined with an insulator having a high relative dielectric constant, a laminated structure having a thermally stable and high relative dielectric constant can be obtained with a film having few defects. .
絶縁体１６０は、酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）の上面に接して配置されることが好ましい。絶縁体１６０は、加熱により酸素が放出される絶縁体を用いて形成することが好ましい。このような絶縁体１６０を酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）の上面に接して設けることにより、酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）に効果的に酸素を供給することができる。また、絶縁体１０５、絶縁体１１０、及び絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）と同様に、絶縁体１６０中の水又は水素などの不純物濃度が、低減されていることが好ましい。絶縁体１６０の膜厚は、１ｎｍ以上２０ｎｍ以下とするのが好ましく、例えば、１ｎｍ程度の膜厚にすればよい。
The insulator 160 is preferably disposed in contact with the upper surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2). The insulator 160 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 160 in contact with the top surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2), oxygen can be effectively added to the oxide 150 (or the oxide 150_1 or the oxide 150_2). Can be supplied. Further, similarly to the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2), it is preferable that the concentration of impurities such as water or hydrogen in the insulator 160 be reduced. . The thickness of the insulator 160 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, and may be, for example, about 1 nm.
絶縁体１６０は、酸素を含むことが好ましい。例えば、昇温脱離ガス分光法分析（ＴＤＳ分析）にて、１００℃以上７００℃以下又は１００℃以上５００℃以下の表面温度の範囲で、酸素分子の脱離量を絶縁体１６０の面積当たりに換算して、１×１０１４ｍｏｌｅｃｕｌｅｓ／ｃｍ２以上、好ましくは２×１０１４ｍｏｌｅｃｕｌｅｓ／ｃｍ２以上、より好ましくは４×１０１４ｍｏｌｅｃｕｌｅｓ／ｃｍ２以上であればよい。
The insulator 160 preferably contains oxygen. For example, in the temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 160 in the range of the surface temperature of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. 1 × 10 14 molecules / cm 2 or more, preferably 2 × 10 14 molecules / cm 2 or more, more preferably 4 × 10 14 molecules / cm 2 or more.
絶縁体１７５、絶縁体１７６、及び絶縁体１８０は、比誘電率の低い絶縁体を有することが好ましい。例えば、絶縁体１７５、絶縁体１７６、及び絶縁体１８０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素及び窒素を添加した酸化シリコン、空孔を有する酸化シリコン、又は樹脂などを有することが好ましい。又は、絶縁体１７５、絶縁体１７６、及び絶縁体１８０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素及び窒素を添加した酸化シリコン、又は空孔を有する酸化シリコンと、樹脂と、の積層構造を有することが好ましい。酸化シリコン及び酸化窒化シリコンは、熱的に安定であるため、樹脂と組み合わせることで、熱的に安定かつ比誘電率の低い積層構造とすることができる。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート又はアクリルなどがある。なお、絶縁体１７５、絶縁体１７６、及び絶縁体１８０は、絶縁体１０５、絶縁体１１０、絶縁体１３０（又は、絶縁体１３０＿１、絶縁体１３０＿２）、及び絶縁体１６０などと同様に、膜中の水又は水素などの不純物濃度が低減されていることが好ましい。
It is preferable that the insulator 175, the insulator 176, and the insulator 180 include an insulator having a low relative dielectric constant. For example, the insulator 175, the insulator 176, and the insulator 180 were doped with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen. It is preferable to include silicon oxide, silicon oxide having holes, resin, or the like. Alternatively, the insulator 175, the insulator 176, and the insulator 180 are added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and nitrogen. It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Note that the insulator 175, the insulator 176, and the insulator 180 are formed in the same manner as the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), the insulator 160, and the like. It is preferable that the concentration of impurities such as water or hydrogen is reduced.
また、絶縁体１０２及び絶縁体１７８には、水素や水などの不純物、及び酸素に対してバリア性の高い絶縁体を用いることが好ましい。当該絶縁体を絶縁体１０２及び絶縁体１７８に用いることで、絶縁体１０２（絶縁体１７８）の下側（上側）から、トランジスタ１０、トランジスタ１１、トランジスタ１２、又はトランジスタ１３中に、水素や水などの不純物が混入するのを抑制することができる。また、トランジスタ１０、トランジスタ１１、トランジスタ１２、又はトランジスタ１３中の酸素が、絶縁体１０２（絶縁体１７８）の下側（上側）に拡散するのを抑制することができる。当該絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム、又はタンタルを含む絶縁体を、単層又は積層で用いることが好ましい。
For the insulator 102 and the insulator 178, an insulator having a high barrier property against impurities such as hydrogen and water and oxygen is preferably used. By using the insulator for the insulator 102 and the insulator 178, hydrogen or water enters the transistor 10, the transistor 11, the transistor 12, or the transistor 13 from the lower side (upper side) of the insulator 102 (insulator 178). It can suppress that impurities, such as, mix. Further, diffusion of oxygen in the transistor 10, the transistor 11, the transistor 12, or the transistor 13 to the lower side (upper side) of the insulator 102 (insulator 178) can be suppressed. Examples of the insulator include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Is preferably used in a single layer or a stacked layer.
また、例えば、当該絶縁体としては、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、又は酸化タンタルなどの金属酸化物、窒化酸化シリコン又は窒化シリコンなどを用いればよい。なお、当該絶縁体は、酸化アルミニウム又は酸化ハフニウムなどを有することが好ましい。
For example, the insulator includes aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, metal oxide such as tantalum oxide, silicon nitride oxide, Silicon nitride or the like may be used. Note that the insulator preferably includes aluminum oxide, hafnium oxide, or the like.
〔導電体〕
導電体１２０（又は、導電体１２０＿１、導電体１２０＿２）、導電体１４０（又は、導電体１４０＿１、導電体１４０＿２）、導電体１８５（又は、導電体１８５＿１、導電体１８５＿２）、導電体１９０（又は、導電体１９０＿１、導電体１９０＿２）、導電体１９５（又は、導電体１９５＿１、導電体１９５＿２）、導電体２００（又は、導電体２００＿１、導電体２００＿２）、及び導電体１７０としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 〔conductor〕
Conductor 120 (or conductor 120_1, conductor 120_2), conductor 140 (or conductor 140_1, conductor 140_2), conductor 185 (or conductor 185_1, conductor 185_2), conductor 190 (or , Conductor 190_1, conductor 190_2), conductor 195 (or conductor 195_1, conductor 195_2), conductor 200 (or conductor 200_1, conductor 200_2), andconductor 170 include aluminum, chromium A material containing at least one metal element selected from copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
導電体１２０（又は、導電体１２０＿１、導電体１２０＿２）、導電体１４０（又は、導電体１４０＿１、導電体１４０＿２）、導電体１８５（又は、導電体１８５＿１、導電体１８５＿２）、導電体１９０（又は、導電体１９０＿１、導電体１９０＿２）、導電体１９５（又は、導電体１９５＿１、導電体１９５＿２）、導電体２００（又は、導電体２００＿１、導電体２００＿２）、及び導電体１７０としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 〔conductor〕
Conductor 120 (or conductor 120_1, conductor 120_2), conductor 140 (or conductor 140_1, conductor 140_2), conductor 185 (or conductor 185_1, conductor 185_2), conductor 190 (or , Conductor 190_1, conductor 190_2), conductor 195 (or conductor 195_1, conductor 195_2), conductor 200 (or conductor 200_1, conductor 200_2), and
また、上記導電体、特に、導電体１７０として、酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）に適用可能な金属酸化物に含まれる金属元素及び酸素を含む導電性材料を用いてもよい。また、前述した金属元素及び窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）に含まれる水素を捕獲することができる場合がある。又は、外方の絶縁体などから混入する水素を捕獲することができる場合がある。
Alternatively, a conductive material containing a metal element and oxygen contained in a metal oxide applicable to the oxide 150 (or the oxide 150_1 and the oxide 150_2) can be used as the conductor, particularly the conductor 170. Good. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide 150 (or the oxide 150_1 or the oxide 150_2) may be trapped in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.
また、上記の材料で形成される導電層を複数積層して用いてもよい。例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。
Further, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
なお、トランジスタのチャネル形成領域に酸化物を用いる場合は、ゲート電極として、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。
Note that in the case where an oxide is used for a channel formation region of the transistor, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used as the gate electrode is preferably used. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.
なお、導電体１８５（又は、導電体１８５＿１、導電体１８５＿２）、導電体１９０（又は、導電体１９０＿１、導電体１９０＿２）、導電体１９５（又は、導電体１９５＿１、導電体１９５＿２）、及び導電体２００（又は、導電体２００＿１、導電体２００＿２）としては、例えば、タングステン、ポリシリコン等の埋め込み性の高い導電性材料を用いればよい。また、埋め込み性の高い導電性材料と、チタン、窒化チタン、窒化タンタルなどの導電性バリア膜を組み合わせて用いてもよい。
Note that the conductor 185 (or the conductor 185_1, the conductor 185_2), the conductor 190 (or the conductor 190_1, the conductor 190_2), the conductor 195 (or the conductor 195_1, the conductor 195_2), and the conductor 200 (or the conductor 200_1 or the conductor 200_2) may be formed using a highly embedded conductive material such as tungsten or polysilicon. Alternatively, a conductive material with high embedding property and a conductive barrier film such as titanium, titanium nitride, or tantalum nitride may be used in combination.
〔酸化物〕
酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）としては、金属酸化物を用いることが好ましい。ただし、酸化物１５０の代わりに、半導体材料として、シリコン（歪シリコン含む。）、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ガリウムヒ素、アルミニウムガリウムヒ素、インジウムリン、窒化ガリウム、又は有機半導体などを用いても構わない場合がある。以下では、本発明の一態様に係る酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）に用いることが好ましい、金属酸化物について説明する。 [Oxide]
As the oxide 150 (or the oxide 150_1 and the oxide 150_2), a metal oxide is preferably used. However, instead of theoxide 150, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used as a semiconductor material. It doesn't matter. Hereinafter, a metal oxide which is preferably used for the oxide 150 (or the oxide 150_1 and the oxide 150_2) according to one embodiment of the present invention is described.
酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）としては、金属酸化物を用いることが好ましい。ただし、酸化物１５０の代わりに、半導体材料として、シリコン（歪シリコン含む。）、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ガリウムヒ素、アルミニウムガリウムヒ素、インジウムリン、窒化ガリウム、又は有機半導体などを用いても構わない場合がある。以下では、本発明の一態様に係る酸化物１５０（又は、酸化物１５０＿１、酸化物１５０＿２）に用いることが好ましい、金属酸化物について説明する。 [Oxide]
As the oxide 150 (or the oxide 150_1 and the oxide 150_2), a metal oxide is preferably used. However, instead of the
金属酸化物は、少なくともインジウム又は亜鉛を含むことが好ましい。特に、インジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム又はスズなどが含まれていることが好ましい。また、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種が含まれていてもよい。
The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably included. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.
ここでは、金属酸化物が、インジウム、元素Ｍ及び亜鉛を有するＩｎＭＺｎＯである場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウム、又はスズなどとする。その他の元素Ｍに適用可能な元素としては、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。
Here, consider a case where the metal oxide is InMZnO containing indium, element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Examples of other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.
上記金属酸化物をトランジスタのチャネル形成領域に用いることで、高い電界効果移動度のトランジスタを実現することができる。また、良好な信頼性を有するトランジスタを実現することができる。
A transistor with high field effect mobility can be realized by using the metal oxide in a channel formation region of a transistor. In addition, a transistor having good reliability can be realized.
金属酸化物を用いたチャネル形成領域に用いたトランジスタは、非導通状態において極めてリーク電流が小さいため、低消費電力の半導体装置を提供できる。また、金属酸化物は、スパッタリング法などを用いて成膜できるため、高集積型の半導体装置を構成するトランジスタに用いることができる。
Since a transistor used in a channel formation region using a metal oxide has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. A metal oxide can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
また、トランジスタのチャネル形成領域には、キャリア密度の低い金属酸化物を用いることが好ましい。金属酸化物膜のキャリア密度を低くするためには、金属酸化物膜中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性又は実質的に高純度真性という。例えば、金属酸化物は、キャリア密度が８×１０１１／ｃｍ３未満、好ましくは１×１０１１／ｃｍ３未満、さらに好ましくは１×１０１０／ｃｍ３未満であり、１×１０−９／ｃｍ３以上とすればよい。
In addition, a metal oxide with low carrier density is preferably used for a channel formation region of the transistor. In order to reduce the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 11 / cm 3 , preferably less than 1 × 10 11 / cm 3 , more preferably less than 1 × 10 10 / cm 3 , and 1 × 10 −9 / What is necessary is just to be cm 3 or more.
また、高純度真性又は実質的に高純度真性である金属酸化物膜は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。
In addition, since the metal oxide film having high purity intrinsic or substantially high purity intrinsic has a low defect level density, the trap level density may be low.
また、金属酸化物のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い金属酸化物にチャネル形成領域が形成されるトランジスタは、電気特性が不安定となる場合がある。
Further, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in a metal oxide having a high trap state density may have unstable electrical characteristics.
したがって、トランジスタの電気特性を安定にするためには、金属酸化物中の不純物濃度を低減することが有効である。また、金属酸化物中の不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、窒素、アルカリ金属、アルカリ土類金属、鉄、ニッケル、シリコン等がある。
Therefore, to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
ここで、金属酸化物中における各不純物の影響について説明する。
Here, the influence of each impurity in the metal oxide will be described.
金属酸化物において、第１４族元素の一つであるシリコンや炭素が含まれると、金属酸化物において欠陥準位が形成される。このため、金属酸化物におけるシリコンや炭素の濃度と、金属酸化物との界面近傍のシリコンや炭素の濃度（二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ Ｉｏｎ Ｍａｓｓ Ｓｐｅｃｔｒｏｍｅｔｒｙ）により得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とする。
In the metal oxide, when silicon or carbon, which is one of Group 14 elements, is included, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.
また、金属酸化物にアルカリ金属又はアルカリ土類金属が含まれると、当該金属が金属酸化物中に欠陥準位を形成し、キャリアを生成する場合がある。したがって、アルカリ金属又はアルカリ土類金属が含まれている金属酸化物をチャネル形成領域に用いたトランジスタは、ノーマリーオン特性となりやすい。このため、金属酸化物中のアルカリ金属又はアルカリ土類金属の濃度を低減することが好ましい。具体的には、ＳＩＭＳにより得られる金属酸化物中のアルカリ金属又はアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。
In addition, when an alkali metal or an alkaline earth metal is contained in the metal oxide, the metal may form a defect level in the metal oxide and generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less.
また、金属酸化物において、窒素が含まれると、キャリアである電子が生じ、キャリア密度が増加し、ｎ型化しやすい。この結果、窒素が含まれている金属酸化物をチャネル形成領域に用いたトランジスタは、ノーマリーオン特性となりやすい。したがって、当該金属酸化物において、窒素はできる限り低減されていることが好ましい。例えば、金属酸化物中の窒素濃度は、ＳＩＭＳにおいて、５×１０１９ａｔｏｍｓ／ｃｍ３未満、好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下とする。
Further, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Therefore, nitrogen in the metal oxide is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 19 atoms / cm 3 , preferably 5 × 10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 or less in SIMS, Preferably, it is 5 × 10 17 atoms / cm 3 or less.
また、金属酸化物に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。当該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。したがって、水素が含まれている金属酸化物をチャネル形成領域に用いたトランジスタは、ノーマリーオン特性となりやすい。このため、金属酸化物中の水素はできる限り低減されていることが好ましい。具体的には、金属酸化物において、ＳＩＭＳにより得られる水素濃度を、１×１０２０ａｔｏｍｓ／ｃｍ３未満、好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３未満、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３未満とする。
In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 20 atoms / cm 3 , preferably less than 1 × 10 19 atoms / cm 3 , more preferably 5 × 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 × 10 18 atoms / cm 3 .
不純物が十分に低減された金属酸化物をトランジスタのチャネル形成領域に用いることで、安定した電気特性を付与することができる。
Stable electrical characteristics can be imparted by using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor.
以下では、ＣＡＣ−ＯＳについて詳細に説明する。ＣＡＣ−ＯＳは、本発明の一態様に係るトランジスタの金属酸化物が有することのできる機能、又は材料構成の一例である。
Hereinafter, the CAC-OS will be described in detail. The CAC-OS is an example of a function or a material structure that can be included in the metal oxide of the transistor of one embodiment of the present invention.
ＣＡＣ−ＯＳとは、例えば、金属酸化物を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、又はその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、１つあるいはそれ以上の金属元素が偏在し、当該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、又はその近傍のサイズで混合した状態をモザイク状、又はパッチ状ともいう。
The CAC-OS is one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as mosaic or patch.
例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳ（ＣＡＣ−ＯＳの中でもＩｎ−Ｇａ−Ｚｎ酸化物を、特にＣＡＣ−ＩＧＺＯと呼称してもよい。）とは、インジウム酸化物（以下、ＩｎＯＸ１（Ｘ１は０よりも大きい実数）とする。）、又はインジウム亜鉛酸化物（以下、ＩｎＸ２ＺｎＹ２ＯＺ２（Ｘ２、Ｙ２、及びＺ２は０よりも大きい実数）とする。）と、ガリウム酸化物（以下、ＧａＯＸ３（Ｘ３は０よりも大きい実数）とする。）、又はガリウム亜鉛酸化物（以下、ＧａＸ４ＺｎＹ４ＯＺ４（Ｘ４、Ｙ４、及びＺ４は０よりも大きい実数）とする。）などと、に材料が分離することでモザイク状となり、モザイク状のＩｎＯＸ１、又はＩｎＸ２ＺｎＹ２ＯＺ２が、膜中に均一に分布した構成（以下、クラウド状ともいう。）である。
For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.
つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とが、混合している構成を有する複合金属酸化物である。なお、本明細書において、例えば、第１の領域の元素Ｍに対するＩｎの原子数比が、第２の領域の元素Ｍに対するＩｎの原子数比よりも大きいことを、第１の領域は、第２の領域と比較して、Ｉｎの濃度が高いとする。
That, CAC-OS includes a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 there is a region which is a main component, a composite metal oxide having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
なお、ＩＧＺＯは通称であり、Ｉｎ、Ｇａ、Ｚｎ、及びＯによる１つの化合物をいう場合がある。代表例として、ＩｎＧａＯ３（ＺｎＯ）ｍ１（ｍ１は自然数）、又はＩｎ（１＋ｘ０）Ｇａ（１−ｘ０）Ｏ３（ＺｎＯ）ｍ０（−１≦ｘ０≦１、ｍ０は任意数）で表される結晶性の化合物が挙げられる。
Note that IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O. As a typical example, InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.
上記結晶性の化合物は、単結晶構造、多結晶構造、又はＣＡＡＣ構造を有する。なお、ＣＡＡＣ構造とは、複数のＩＧＺＯのナノ結晶がｃ軸配向を有し、かつａ−ｂ面においては配向せずに連結した結晶構造である。
The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
一方、ＣＡＣ−ＯＳは、金属酸化物の材料構成に関する。ＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、及びＯを含む材料構成において、一部にＧａを主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。したがって、ＣＡＣ−ＯＳにおいて、結晶構造は副次的な要素である。
On the other hand, CAC-OS relates to a material structure of metal oxide. CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
なお、ＣＡＣ−ＯＳに、組成の異なる二種類以上の膜の積層構造は含まないものとする。例えば、Ｉｎを主成分とする膜と、Ｇａを主成分とする膜との２層からなる構造は、含まない。
Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
なお、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とは、明確な境界を観察することが難しい場合がある。
Incidentally, a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or the region InO X1 is the main component, it may be difficult to observe a clear boundary.
なお、ガリウムの代わりに、アルミニウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウムなどから選ばれた一種、又は複数種が含まれている場合、ＣＡＣ−ＯＳは、一部に当該金属元素を主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。
In place of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. When one kind or plural kinds are included, the CAC-OS is a part of a nanoparticle mainly including the metal element as a main component and a part of a nanoparticle mainly including In. The regions observed in the above are each randomly dispersed in a mosaic pattern.
ＣＡＣ−ＯＳは、例えば、基板を意図的に加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的には、アルゴン）、酸素ガス、及び窒素ガスの中から選ばれたいずれか１つ又は複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましく、例えば、酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とする。
The CAC-OS can be formed by, for example, a sputtering method under a condition that the substrate is not intentionally heated. In the case where the CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas is used as a deposition gas. That's fine. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas at the time of film formation is preferably as low as possible.
ＣＡＣ−ＯＳは、Ｘ線回折（ＸＲＤ：Ｘ−ｒａｙ ｄｉｆｆｒａｃｔｉｏｎ）測定法の１つであるＯｕｔ−ｏｆ−ｐｌａｎｅ法によるθ／２θスキャンを用いて測定したときに、明確なピークが観察されないという特徴を有する。すなわち、Ｘ線回折から、測定領域のａ−ｂ面方向、及びｃ軸方向の配向は見られないことがわかる。
CAC-OS is characterized in that no clear peak is observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
また、ＣＡＣ−ＯＳは、プローブ径が１ｎｍの電子線（ナノビーム電子線ともいう。）を照射することで得られる電子線回折パターンにおいて、リング状に輝度の高い領域と、当該リング領域に複数の輝点が観測される。したがって、電子線回折パターンから、ＣＡＣ−ＯＳの結晶構造が、平面方向、及び断面方向において、配向性を有さないｎｃ（ｎａｎｏ−ｃｒｙｓｔａｌ）構造を有することがわかる。
In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
また、例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳでは、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ Ｄｉｓｐｅｒｓｉｖｅ Ｘ−ｒａｙ ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて取得したＥＤＸマッピングにより、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とが、偏在し、混合している構造を有することが確認できる。
In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 are unevenly distributed and mixed.
ＣＡＣ−ＯＳは、金属元素が均一に分布したＩＧＺＯ化合物とは異なる構造であり、ＩＧＺＯ化合物と異なる性質を有する。つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３などが主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域と、に互いに相分離し、各元素を主成分とする領域がモザイク状である構造を有する。
The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
ここで、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域は、ＧａＯＸ３などが主成分である領域と比較して、導電性が高い領域である。つまり、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域を、キャリアが流れることにより、金属酸化物としての導電性が発現する。したがって、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域が、金属酸化物中にクラウド状に分布することで、当該金属酸化物を用いたトランジスタは、高い電界効果移動度を実現できる。
Here, the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2, or InO X1 is a region which is a main component, by carriers flow, conductive metal oxide is expressed. Therefore, a region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is distributed in a cloud shape in the metal oxide, so that a transistor using the metal oxide achieves high field-effect mobility. it can.
一方、ＧａＯＸ３などが主成分である領域は、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域と比較して、絶縁性が高い領域である。つまり、ＧａＯＸ３などが主成分である領域が、金属酸化物中に分布することで、当該金属酸化物を用いたトランジスタは、リーク電流を抑制し、良好なスイッチング動作を実現できる。
On the other hand, areas such as GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 is compared to region which is a main component, has a high area insulation. That is, a region containing GaO X3 or the like as a main component is distributed in a metal oxide, so that a transistor using the metal oxide can suppress a leakage current and realize a favorable switching operation.
したがって、ＣＡＣ−ＯＳをトランジスタなどの半導体素子に用いた場合、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１に起因する導電性と、ＧａＯＸ３などに起因する絶縁性とが、相補的に作用することにより、高いオン電流と低いオフ電流の双方を実現することができる。
Therefore, when CAC-OS is used for a semiconductor element such as a transistor, conductivity caused by In X2 Zn Y2 O Z2 or InO X1 and insulation caused by GaO X3 or the like act complementarily. Thus, both a high on-current and a low off-current can be realized.
また、ＣＡＣ−ＯＳを用いた半導体素子は、信頼性が高い。したがって、ＣＡＣ−ＯＳは、表示装置、発光装置、照明装置、蓄電装置、記憶装置、撮像装置、プロセッサ、電子機器などの様々な半導体装置に用いることが最適である。
In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimally used for various semiconductor devices such as a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, and an electronic device.
＜半導体装置の作製方法＞
以下では、本発明の一態様に係るトランジスタ１０を有する半導体装置の作製方法について、その一例を図５乃至図１０を用いて説明する。図５乃至図１０において、各図の（Ａ）は、トランジスタ１０を有する半導体装置の上面図である。また、各図の（Ｂ）は、各図の（Ａ）にＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、各図の（Ｃ）は、各図の（Ａ）にＡ３−Ａ４の一点鎖線で示す部位の断面図である。なお、以下で説明するトランジスタ１０を有する半導体装置の作製方法において、当該半導体装置に適用できる各構成要素（基板、絶縁体、導電体、酸化物など）の具体的な材料については、＜半導体装置の構成要素＞で説明した内容を参酌できるものとする。 <Method for Manufacturing Semiconductor Device>
Hereinafter, an example of a method for manufacturing a semiconductor device including thetransistor 10 according to one embodiment of the present invention will be described with reference to FIGS. 5A to 10A are top views of the semiconductor device including the transistor 10. Moreover, (B) of each figure is sectional drawing of the site | part shown with the dashed-dotted line of A1-A2 in (A) of each figure. Moreover, (C) of each figure is sectional drawing of the site | part shown with the dashed-dotted line of A3-A4 in (A) of each figure. Note that in a method for manufacturing a semiconductor device including the transistor 10 described below, specific materials of components (a substrate, an insulator, a conductor, an oxide, and the like) that can be applied to the semiconductor device are described below. The contents explained in <Constituent elements of> can be taken into consideration.
以下では、本発明の一態様に係るトランジスタ１０を有する半導体装置の作製方法について、その一例を図５乃至図１０を用いて説明する。図５乃至図１０において、各図の（Ａ）は、トランジスタ１０を有する半導体装置の上面図である。また、各図の（Ｂ）は、各図の（Ａ）にＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、各図の（Ｃ）は、各図の（Ａ）にＡ３−Ａ４の一点鎖線で示す部位の断面図である。なお、以下で説明するトランジスタ１０を有する半導体装置の作製方法において、当該半導体装置に適用できる各構成要素（基板、絶縁体、導電体、酸化物など）の具体的な材料については、＜半導体装置の構成要素＞で説明した内容を参酌できるものとする。 <Method for Manufacturing Semiconductor Device>
Hereinafter, an example of a method for manufacturing a semiconductor device including the
まず、基板（図示しない。）を準備する。
First, a substrate (not shown) is prepared.
次に、当該基板上に絶縁体１００を成膜する。絶縁体１００の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ Ｂｅａｍ Ｅｐｉｔａｘｙ）法、パルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ Ｌａｓｅｒ Ｄｅｐｏｓｉｔｉｏｎ）法、又はＡＬＤ（Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ）法などを用いて行うことができる。
Next, the insulator 100 is formed on the substrate. The insulator 100 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD method. (Atomic Layer Deposition) method or the like can be used.
なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ Ｅｎｈａｎｃｅｄ ＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ ＣＶＤ）法などに分類できる。さらに、用いる原料ガスによって、金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ Ｏｒｇａｎｉｃ ＣＶＤ）法に分けることができる。
In addition, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.
プラズマＣＶＤ法は、比較的低温で高品質の膜が得られる。また、熱ＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、半導体装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、半導体装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いない熱ＣＶＤ法の場合、こういったプラズマダメージが生じないため、半導体装置の歩留まりを高くすることができる。また、熱ＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。
The plasma CVD method can obtain a high-quality film at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.
また、ＡＬＤ法も、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。また、ＡＬＤ法も、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。
The ALD method is also a film forming method that can reduce plasma damage to the object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
ＣＶＤ法及びＡＬＤ法は、ターゲットなどから放出される粒子が堆積する成膜方法とは異なり、被処理物の表面における反応により膜が形成される成膜方法である。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。
The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
ＣＶＤ法及びＡＬＤ法は、原料ガスの流量比によって、得られる膜の組成を制御することができる。例えば、ＣＶＤ法及びＡＬＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。また、例えば、ＣＶＤ法及びＡＬＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合のような搬送や圧力調整にかかる時間を必要としない分、成膜にかかる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。
In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation is shortened by the time required for transport and pressure adjustment as in the case of film formation using a plurality of film formation chambers. be able to. Therefore, the productivity of the semiconductor device may be increased.
本実施の形態では、絶縁体１００として、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１００としては、酸化シリコン以外に、例えば、酸化窒化シリコンを用いてもよい。
In this embodiment mode, a silicon oxide film is formed as the insulator 100 by a CVD method. As the insulator 100, for example, silicon oxynitride may be used in addition to silicon oxide.
次に、絶縁体１００上に絶縁体１０２を成膜する。絶縁体１０２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１０２として、スパッタリング法によって酸化アルミニウムを成膜する。また、絶縁体１０２は、多層構造としてもよい。例えば、スパッタリング法によって酸化アルミニウムを成膜し、当該酸化アルミニウム上にＡＬＤ法によって酸化アルミニウムを成膜する構造としてもよい。又は、ＡＬＤ法によって酸化アルミニウムを成膜し、当該酸化アルミニウム上に、スパッタリング法によって酸化アルミニウムを成膜する構造としてもよい。
Next, an insulator 102 is formed on the insulator 100. The insulator 102 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, an aluminum oxide film is formed as the insulator 102 by a sputtering method. The insulator 102 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, an aluminum oxide film may be formed by an ALD method, and the aluminum oxide film may be formed on the aluminum oxide by a sputtering method.
次に、絶縁体１０２上に絶縁体１０５を成膜する。絶縁体１０５の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１０５として、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１０５としては、酸化シリコン以外に、例えば、酸化窒化シリコンを用いてもよい。
Next, an insulator 105 is formed on the insulator 102. The insulator 105 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 105 by a CVD method. Note that as the insulator 105, for example, silicon oxynitride may be used in addition to silicon oxide.
次に、絶縁体１０５に、絶縁体１０２に達する開口を形成する。ここで、開口とは、例えば、溝やスリットなども含まれる。また、開口が形成された領域を指して開口部とする場合がある。開口の形成にはウエットエッチング法を用いてもよいが、ドライエッチング法を用いるほうが微細加工には好ましい。また、絶縁体１０２は、絶縁体１０５をエッチングして開口を形成する際のエッチングストッパ膜として機能する絶縁体を選択することが好ましい。例えば、開口を形成する絶縁体１０５に酸化シリコン膜を用いる場合は、絶縁体１０２は窒化シリコン膜、酸化アルミニウム膜、又は酸化ハフニウム膜を用いるとよい。
Next, an opening reaching the insulator 102 is formed in the insulator 105. Here, the openings include, for example, grooves and slits. In some cases, the opening is pointed to a region where the opening is formed. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing. As the insulator 102, an insulator that functions as an etching stopper film when the opening is formed by etching the insulator 105 is preferably selected. For example, in the case where a silicon oxide film is used for the insulator 105 in which the opening is formed, the insulator 102 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.
開口の形成後に、導電体１８５となる導電体を成膜する。ここで、導電体１８５は、酸素の透過を抑制する機能を有する導電体１８５ａ（図示しない。）と、導電体１８５ａよりも導電率の高い導電体１８５ｂ（図示しない。）とからなる、積層構造とすることが好ましい。
After the opening is formed, a conductor to be the conductor 185 is formed. Here, the conductor 185 includes a stacked structure including a conductor 185a (not shown) having a function of suppressing permeation of oxygen and a conductor 185b (not shown) having higher conductivity than the conductor 185a. It is preferable that
導電体１８５ａとなる導電体は、酸素の透過を抑制する機能を有する導電性材料を含むことが好ましい。例えば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。又は、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体１８５ａとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
The conductor to be the conductor 185a preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 185a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体１８５ａとなる導電体として、スパッタリング法によって窒化タンタル、又は窒化タンタルの上に窒化チタンを積層した膜を成膜する。導電体１８５ａとなる導電体として、このような金属窒化物を用いることにより、後述する導電体１８５ｂに銅など拡散しやすい金属を用いても、当該金属が導電体１８５ａから外に拡散するのを防ぐことができる。
In this embodiment, as a conductor to be the conductor 185a, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the conductor to be the conductor 185a, even if a metal such as copper that is easy to diffuse is used for the conductor 185b described later, the metal diffuses out of the conductor 185a. Can be prevented.
次に、導電体１８５ａとなる導電体上に、導電体１８５ｂとなる導電体を成膜する。導電体１８５ｂとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、導電体１８５ｂとなる導電体として、銅などの低抵抗導電性材料を成膜する。
Next, a conductor to be the conductor 185b is formed over the conductor to be the conductor 185a. The conductor to be the conductor 185b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductor to be the conductor 185b.
次に、化学機械研磨（ＣＭＰ：Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）処理を行うことで、導電体１８５ａとなる導電体、及び、導電体１８５ｂとなる導電体の一部を除去し、絶縁体１０５を露出する。その結果、開口部のみに、導電体１８５ａとなる導電体、及び、導電体１８５ｂとなる導電体が残存する。これにより、上面が平坦な、導電体１８５ａ及び導電体１８５ｂからなる導電体１８５を形成することができる（図５参照。）。なお、当該ＣＭＰ処理により、絶縁体１０５の一部が除去される場合がある。
Next, by performing a chemical mechanical polishing (CMP) process, the conductor to be the conductor 185a and part of the conductor to be the conductor 185b are removed, and the insulator 105 is exposed. As a result, the conductor to be the conductor 185a and the conductor to be the conductor 185b remain only in the opening. Accordingly, the conductor 185 including the conductor 185a and the conductor 185b having a flat upper surface can be formed (see FIG. 5). Note that part of the insulator 105 may be removed by the CMP treatment.
次に、絶縁体１０５及び導電体１８５上に絶縁体１１０を成膜する。絶縁体１１０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１１０として、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１１０としては、酸化シリコン以外に、例えば、酸化窒化シリコンを用いてもよい。
Next, the insulator 110 is formed over the insulator 105 and the conductor 185. The insulator 110 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 110 by a CVD method. As the insulator 110, for example, silicon oxynitride may be used in addition to silicon oxide.
ここで、第１の加熱処理を行ってもよい。第１の加熱処理は、例えば、２５０℃以上６５０℃以下で行えばよい。第１の加熱処理は、窒素ガス若しくは不活性ガスの雰囲気、又は酸化性ガスを１０ｐｐｍ以上、１％以上若しくは１０％以上含む雰囲気で行うことが好ましい。第１の加熱処理は減圧状態で行ってもよい。又は、第１の加熱処理は、窒素ガス又は不活性ガスの雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上又は１０％以上含む雰囲気で加熱処理を行ってもよい。第１の加熱処理によって、絶縁体１１０及び絶縁体１０５に含まれる水素や水などの不純物を低減させることなどができる。又は、第１の加熱処理において、減圧状態で酸素を含むプラズマ処理を行ってもよい。酸素を含むプラズマ処理は、例えば、マイクロ波を用いた高密度プラズマを発生させる電源を有する装置を用いることが好ましい。又は、基板側にＲＦ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ）を印加する電源を有してもよい。高密度プラズマを用いることにより高密度の酸素ラジカルを生成することができ、基板側にＲＦを印加することで高密度プラズマによって生成された酸素ラジカルを効率良く絶縁体１１０及び絶縁体１０５内に導くことができる。又は、この装置を用いて不活性ガスを含むプラズマ処理を行った後に、脱離した酸素を補うために、酸素を含むプラズマ処理を行ってもよい。
Here, the first heat treatment may be performed. The first heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, for example. The first heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed in a reduced pressure state. Alternatively, in the first heat treatment, after heat treatment in an atmosphere of nitrogen gas or inert gas, heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be performed. By the first heat treatment, impurities such as hydrogen and water contained in the insulator 110 and the insulator 105 can be reduced. Alternatively, in the first heat treatment, plasma treatment containing oxygen may be performed in a reduced pressure state. For the plasma treatment including oxygen, for example, an apparatus having a power source that generates high-density plasma using microwaves is preferably used. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 110 and the insulator 105. be able to. Alternatively, after performing plasma treatment containing an inert gas using this apparatus, plasma treatment containing oxygen may be performed in order to supplement the desorbed oxygen.
次に、絶縁体１１０に、導電体１８５に達する開口を形成する。開口の形成はウエットエッチング法を用いてもよいが、ドライエッチング法を用いるほうが微細加工には好ましい。
Next, an opening reaching the conductor 185 is formed in the insulator 110. The opening may be formed by a wet etching method, but the dry etching method is preferable for fine processing.
開口の形成後に、導電体１９０となる導電体を成膜する。ここで、導電体１９０は、酸素の透過を抑制する機能を有する導電体１９０ａ（図示しない。）と、これよりも導電率の高い導電体１９０ｂ（図示しない。）とからなる、積層構造とすることが好ましい。
After the opening is formed, a conductor to be the conductor 190 is formed. Here, the conductor 190 has a stacked structure including a conductor 190a (not shown) having a function of suppressing permeation of oxygen and a conductor 190b (not shown) having higher conductivity than this. It is preferable.
導電体１９０ａとなる導電体は、酸素の透過を抑制する機能を有する導電性材料を含むことが好ましい。例えば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。又は、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体１９０ａとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
The conductor to be the conductor 190a preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 190a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体１９０ａとなる導電体として、スパッタリング法によって窒化タンタルを成膜する。
In this embodiment, tantalum nitride is formed by a sputtering method as a conductor to be the conductor 190a.
次に、導電体１９０ａとなる導電体上に、導電体１９０ｂとなる導電体を成膜する。当該導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
Next, a conductor to be the conductor 190b is formed on the conductor to be the conductor 190a. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体１９０ｂとなる導電体として、ＡＬＤ法によって窒化チタンを成膜し、当該窒化チタン上にＣＶＤ法によってタングステンを成膜する。
In this embodiment, as a conductor to be the conductor 190b, titanium nitride is formed by an ALD method, and tungsten is formed over the titanium nitride by a CVD method.
次に、ＣＭＰ処理を行うことで、導電体１９０ａとなる導電体、及び、導電体１９０ｂとなる導電体の一部を除去し、絶縁体１１０を露出する。その結果、開口部のみに、導電体１９０ａとなる導電体、及び、導電体１９０ｂとなる導電体が残存する。これにより、上面が平坦な、導電体１９０ａ及び導電体１９０ｂからなる導電体１９０を形成することができる（図５参照。）。なお、当該ＣＭＰ処理により、絶縁体１１０の一部が除去される場合がある。
Next, by performing a CMP process, a part of the conductor to be the conductor 190a and a part of the conductor to be the conductor 190b are removed, and the insulator 110 is exposed. As a result, the conductor to be the conductor 190a and the conductor to be the conductor 190b remain only in the opening. Thus, the conductor 190 including the conductor 190a and the conductor 190b having a flat upper surface can be formed (see FIG. 5). Note that part of the insulator 110 may be removed by the CMP treatment.
次に、絶縁体１１０及び導電体１９０上に導電体１２０ａを成膜する。導電体１２０ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。導電体１２０ａとして、例えば、窒化タンタル、タングステン、窒化チタンなどの導電体を用いることができる。又は、例えば、タングステンを成膜し、当該タングステン上に、窒化チタンや窒化タンタル等の酸素の透過を抑制する機能を有する導電体を成膜する構成としてもよい。当該構成とすることで、導電体１２０ａの上側から混入した酸素によってタングステンが酸化し、電気抵抗値が増加するのを抑制することができる。
Next, a conductor 120a is formed over the insulator 110 and the conductor 190. The conductor 120a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the conductor 120a, for example, a conductor such as tantalum nitride, tungsten, or titanium nitride can be used. Alternatively, for example, tungsten may be formed, and a conductor having a function of suppressing transmission of oxygen such as titanium nitride or tantalum nitride may be formed over the tungsten. With this structure, it is possible to suppress an increase in electric resistance value due to oxidation of tungsten by oxygen mixed from above the conductor 120a.
又は、導電体１２０ａとして、導電性を有する酸化物、例えば、インジウム錫酸化物（ＩＴＯ：Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ）、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物、又は窒素を含むインジウムガリウム亜鉛酸化物を成膜し、当該酸化物上に、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウムなどから選ばれた金属元素を１種以上含む材料、又は、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを成膜する構成としてもよい。
Alternatively, the conductor 120a may be a conductive oxide such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium containing titanium oxide. An oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, or indium gallium zinc oxide containing nitrogen is formed, and aluminum, chromium, A material containing one or more metal elements selected from copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc., or phosphorus Contains impurity elements such as Typified by polycrystalline silicon obtained, the electrical conductivity is high semiconductor may be configured for forming a silicide such as nickel silicide.
当該酸化物は、酸化物１５０中の水素を吸収、及び外方から拡散してくる水素を捕獲する機能を有する場合があり、トランジスタ１０の電気特性及び信頼性が向上することがある。又は、当該酸化物の代わりにチタンを用いても、同様の機能を有する場合がある。
The oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffused from the outside, which may improve the electrical characteristics and reliability of the transistor 10. Alternatively, even when titanium is used instead of the oxide, the same function may be obtained.
本実施の形態では、導電体１２０ａとして、スパッタリング法によってタングステンを成膜する。
In this embodiment mode, tungsten is deposited as the conductor 120a by a sputtering method.
次に、導電体１２０ａ上に絶縁体１３０ａを成膜する。絶縁体１３０ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１３０ａとして、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１３０ａとしては、酸化シリコン以外に、例えば、酸化窒化シリコンを用いてもよい。
Next, an insulator 130a is formed on the conductor 120a. The insulator 130a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed by a CVD method as the insulator 130a. Note that as the insulator 130a, for example, silicon oxynitride may be used in addition to silicon oxide.
ここで、第２の加熱処理を行ってもよい。第２の加熱処理は、第１の加熱処理の条件を用いることができる。当該加熱処理により、絶縁体１３０ａに含まれる水素や水などの不純物を低減させることができる。また、絶縁体１３０ａ中に酸素を供給することができる。
Here, the second heat treatment may be performed. For the second heat treatment, conditions for the first heat treatment can be used. By the heat treatment, impurities such as hydrogen and water contained in the insulator 130a can be reduced. Further, oxygen can be supplied into the insulator 130a.
又は、イオン化された原料ガスを質量分離して添加するイオン注入法、イオン化された原料ガスを質量分離せずに添加するイオンドーピング法、プラズマイマージョンイオンインプランテーション法などを用いて、絶縁体１３０ａ中に酸素を供給してもよい。
Alternatively, an ion implantation method in which ionized source gas is added after mass separation, an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. Oxygen may be supplied.
上述した加熱処理、又はイオン注入法などによって、絶縁体１３０ａは過剰酸素を有することができる。当該過剰酸素は、後の熱処理などによって酸化物１５０中に供給され、トランジスタ１０の電気特性及び信頼性が向上することがある。
The insulator 130a can have excess oxygen by the heat treatment described above, the ion implantation method, or the like. The excess oxygen is supplied into the oxide 150 by heat treatment or the like later, so that the electrical characteristics and reliability of the transistor 10 may be improved.
次に、絶縁体１３０ａ上に導電体１４０ａを成膜する（図６参照。）。導電体１４０ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。導電体１４０ａとして、例えば、窒化タンタル、タングステン、窒化チタンなどの導電体を用いることができる。又は、例えば、窒化チタンや窒化タンタル等の酸素の透過を抑制する機能を有する導電体を成膜し、当該導電体上にタングステンを成膜する構成としてもよい。当該構成とすることで、導電体１４０ａの下側から混入した酸素によってタングステンが酸化し、電気抵抗値が増加するのを抑制することができる。
Next, a conductor 140a is formed over the insulator 130a (see FIG. 6). The conductor 140a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a conductor such as tantalum nitride, tungsten, or titanium nitride can be used as the conductor 140a. Alternatively, for example, a conductor having a function of suppressing permeation of oxygen such as titanium nitride or tantalum nitride may be formed, and tungsten may be formed over the conductor. With this structure, it is possible to suppress an increase in electric resistance value due to oxidation of tungsten by oxygen mixed from the lower side of the conductor 140a.
又は、導電体１４０ａとして、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウムなどから選ばれた金属元素を１種以上含む材料、又は、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを成膜し、この上に、導電性を有する酸化物、例えば、インジウム錫酸化物（ＩＴＯ：Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ）、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物、又は窒素を含むインジウムガリウム亜鉛酸化物を成膜する構成としてもよい。
Alternatively, the conductor 140a is a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and the like. A material having one or more elements, or a polycrystalline silicon containing an impurity element such as phosphorus, a semiconductor having high electrical conductivity, or a silicide such as nickel silicide is formed on the conductive layer. Indium tin oxide (ITO: Indium Tin Oxide), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide Oxide, indium zinc acid Things, indium tin oxide added with silicon, or nitrogen may be configured for forming the indium gallium zinc oxide containing.
当該酸化物は、酸化物１５０中の水素を吸収、及び外方から拡散してくる水素を捕獲する機能を有する場合があり、トランジスタ１０の電気特性及び信頼性が向上することがある。又は、当該酸化物の代わりにチタンを用いても、同様の機能を有する場合がある。
The oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffused from the outside, which may improve the electrical characteristics and reliability of the transistor 10. Alternatively, even when titanium is used instead of the oxide, the same function may be obtained.
本実施の形態では、導電体１４０ａとして、スパッタリング法によってタングステンを成膜する。
In this embodiment mode, tungsten is deposited as the conductor 140a by a sputtering method.
次に、リソグラフィー法などを用いて、導電体１２０ａ、絶縁体１３０ａ、及び導電体１４０ａを加工し、導電体１９０と重なる領域を有するように、絶縁体１１０上に導電体１２０ｂ、絶縁体１３０ｂ、及び導電体１４０ｂを形成する（図７参照。）。当該形成には、ドライエッチング法やウエットエッチング法を用いることができるが、特に、ドライエッチング法は、微細形状の加工に適しており好ましい。当該加工により、絶縁体１１０の一部が除去される場合がある。
Next, the conductor 120a, the insulator 130a, and the conductor 140a are processed using a lithography method or the like, so that the conductor 120b, the insulator 130b, Then, the conductor 140b is formed (see FIG. 7). For this formation, a dry etching method or a wet etching method can be used. In particular, the dry etching method is suitable because it is suitable for processing a fine shape. Part of the insulator 110 may be removed by the processing.
なお、リソグラフィー法では、まず、マスクを介してレジストを露光する。次に、露光された領域を、現像液を用いて除去又は残存させてレジストマスクを形成する。次に、当該レジストマスクを介してエッチング処理することで、導電体、半導体又は絶縁体などを所望の形状に加工することができる。例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ（Ｅｘｔｒｅｍｅ Ｕｌｔｒａｖｉｏｌｅｔ）光などを用いてレジストを露光することで、レジストマスクを形成すればよい。また、基板と投影レンズとの間に液体（例えば、水）を満たして露光する、液浸技術を用いてもよい。また、前述した光に代えて、電子ビームやイオンビームを用いてもよい。なお、電子ビームやイオンビームを用いる場合には、レジスト上に直接描画を行うため、上述のレジスト露光用のマスクは不要となる。なお、レジストマスクは、アッシングなどのドライエッチング処理を行う、ウエットエッチング処理を行う、ドライエッチング処理後にウエットエッチング処理を行う、又はウエットエッチング処理後にドライエッチング処理を行う、などの方法で、除去することができる。
In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. In addition, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, writing is performed directly on the resist, so that the resist exposure mask described above becomes unnecessary. Note that the resist mask is removed by a method such as performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process. Can do.
また、レジストマスクの代わりに、絶縁体や導電体からなるハードマスクを用いてもよい。ハードマスクを用いる場合、導電体１４０ａ上にハードマスク材料となる絶縁膜や導電膜を形成し、その上にレジストマスクを形成し、ハードマスク材料をエッチングすることで所望の形状のハードマスクを形成することができる。導電体１２０ａ、絶縁体１３０ａ、及び導電体１４０ａのエッチングは、レジストマスクを除去してから行ってもよいし、レジストマスクを残したまま行ってもよい。後者の場合、エッチング中にレジストマスクが消失することがある。導電体１２０ａ、絶縁体１３０ａ、及び導電体１４０ａのエッチング後に、ハードマスクをエッチング法により除去してもよい。一方、ハードマスクの材料が後工程に影響が無い、あるいは後工程で利用できる場合、必ずしもハードマスクを除去する必要は無い。
Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the conductor 140a, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do. Etching of the conductor 120a, the insulator 130a, and the conductor 140a may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by an etching method after the conductor 120a, the insulator 130a, and the conductor 140a are etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
ドライエッチング装置としては、平行平板型電極を有する容量結合型プラズマ（ＣＣＰ：Ｃａｐａｃｉｔｉｖｅｌｙ Ｃｏｕｐｌｅｄ Ｐｌａｓｍａ）エッチング装置を用いることができる。平行平板型電極を有する容量結合型プラズマエッチング装置は、平行平板型電極の一方の電極に高周波電源を印加する構成でもよい。又は平行平板型電極の一方の電極に複数の異なった高周波電源を印加する構成でもよい。又は平行平板型電極それぞれに同じ周波数の高周波電源を印加する構成でもよい。又は平行平板型電極それぞれに周波数の異なる高周波電源を印加する構成でもよい。又は高密度プラズマ源を有するドライエッチング装置を用いることができる。高密度プラズマ源を有するドライエッチング装置は、例えば、誘導結合型プラズマ（ＩＣＰ：Ｉｎｄｕｃｔｉｖｅｌｙ Ｃｏｕｐｌｅｄ Ｐｌａｓｍａ）エッチング装置などを用いることができる。
As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power supplies are applied to one of the parallel plate electrodes may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Alternatively, a configuration in which high-frequency power sources having different frequencies are applied to the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.
なお、上記ドライエッチングなどの処理を行うことによって、エッチングガスなどに起因した不純物が、導電体１２０ｂ、絶縁体１３０ｂ、及び導電体１４０ｂなどの表面又は内部に付着又は拡散することがある。不純物としては、例えば、フッ素又は塩素などがある。
Note that by performing the above-described treatment such as dry etching, impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the conductor 120b, the insulator 130b, and the conductor 140b. Examples of impurities include fluorine and chlorine.
上記の不純物などを除去するために、洗浄を行ってもよい。洗浄方法としては、洗浄液などを用いたウエット洗浄、プラズマを用いたプラズマ処理、又は熱処理による洗浄などがあり、上記洗浄を適宜組み合わせて行ってもよい。
Cleaning may be performed to remove the above impurities. As the cleaning method, there are wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be combined as appropriate.
ウエット洗浄としては、シュウ酸、リン酸又はフッ化水素酸などを炭酸水又は純水で希釈した水溶液を用いて洗浄処理を行ってもよい。又は、純水又は炭酸水を用いた超音波洗浄を行ってもよい。
As the wet cleaning, cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.
次に、絶縁体１１０、導電体１２０ｂ、絶縁体１３０ｂ、及び導電体１４０ｂ上に絶縁体１７５を成膜する。絶縁体１７５の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１７５として、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１７５としては、酸化シリコン以外に、例えば、酸化窒化シリコンを用いてもよい。
Next, an insulator 175 is formed over the insulator 110, the conductor 120b, the insulator 130b, and the conductor 140b. The insulator 175 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 175 by a CVD method. Note that as the insulator 175, for example, silicon oxynitride may be used in addition to silicon oxide.
次に、絶縁体１７５の一部を除去することで、絶縁体１７５の上面を平坦化する（図８参照。）。当該平坦化は、ＣＭＰ処理やドライエッチング処理などで行うことができる。本実施の形態では、ＣＭＰ処理によって絶縁体１７５の上面を平坦化する。当該平坦化処理後の絶縁体１７５の上面は、導電体１４０ｂの上面よりも上に位置することが好ましい。なお、絶縁体１７５の成膜後の上面が平坦性を有している場合は、上記平坦化処理を行わなくてもよい場合がある。
Next, the top surface of the insulator 175 is planarized by removing a part of the insulator 175 (see FIG. 8). The planarization can be performed by a CMP process, a dry etching process, or the like. In this embodiment, the top surface of the insulator 175 is planarized by CMP treatment. The upper surface of the insulator 175 after the planarization treatment is preferably located above the upper surface of the conductor 140b. Note that in the case where the top surface of the insulator 175 after deposition has flatness, the above planarization treatment may not be performed.
ここで、第３の加熱処理を行ってもよい。第３の加熱処理は、第１の加熱処理の条件を用いることができる。当該加熱処理により、絶縁体１７５に含まれる水素や水などの不純物を低減させることができる。また、絶縁体１７５中に酸素を供給することができる。
Here, a third heat treatment may be performed. For the third heat treatment, conditions for the first heat treatment can be used. By the heat treatment, impurities such as hydrogen and water contained in the insulator 175 can be reduced. Further, oxygen can be supplied into the insulator 175.
次に、絶縁体１７５、導電体１４０ｂ、絶縁体１３０ｂ、及び導電体１２０ｂをリソグラフィー法により加工し、絶縁体１１０の上面に達する開口１４５、導電体１２０、絶縁体１３０、及び導電体１４０を形成する（図９参照。）。リソグラフィー法におけるレジスト露光は、マスクを介して、例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ光などを用いて行ってもよいし、液浸技術を用いて行ってもよい。また、マスクを介さずに、電子ビームやイオンビームでレジスト上に直接パターン描画を行う方法を用いてもよい。電子ビームやイオンビームを用いる露光は、上記の光を用いる露光よりも微細なパターンをレジスト上に描画できるため、微細加工に好適である。本実施の形態では、電子ビームを用いてレジスト露光を行う。
Next, the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are processed by a lithography method, so that the opening 145 reaching the upper surface of the insulator 110, the conductor 120, the insulator 130, and the conductor 140 are formed. (See FIG. 9). Resist exposure in the lithography method may be performed using a KrF excimer laser beam, an ArF excimer laser beam, EUV light, or the like through a mask, or may be performed using an immersion technique. Alternatively, a method of directly drawing a pattern on a resist with an electron beam or an ion beam without using a mask may be used. The exposure using an electron beam or an ion beam is suitable for fine processing because a finer pattern can be drawn on the resist than the exposure using the above light. In this embodiment mode, resist exposure is performed using an electron beam.
リソグラフィー法におけるエッチング処理としては、ドライエッチング法やウエットエッチング法を用いることができる。本実施の形態では、上述した電子ビームによるレジスト露光、及び現像後に、ドライエッチング法を用いて、絶縁体１７５、導電体１４０ｂ、絶縁体１３０ｂ、及び導電体１２０ｂのエッチングを行う。なお、当該エッチング処理によって形成される開口１４５は、その内壁（側面）が、基板面に対して略垂直に形成されることが好ましい。開口１４５の内壁（側面）が、基板面に対して垂直に近い角度で形成されるほど、トランジスタ１０の微細化を図ることができる。なお、当該エッチング処理により、絶縁体１１０の一部が除去される場合がある。
As an etching process in the lithography method, a dry etching method or a wet etching method can be used. In this embodiment, after the resist exposure using the electron beam and the development described above, the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are etched using a dry etching method. Note that the opening 145 formed by the etching process preferably has an inner wall (side surface) formed substantially perpendicular to the substrate surface. As the inner wall (side surface) of the opening 145 is formed at an angle closer to perpendicular to the substrate surface, the transistor 10 can be miniaturized. Note that part of the insulator 110 may be removed by the etching treatment.
次に、開口１４５の内壁及び絶縁体１７５上に、酸化物１５０となる酸化物を成膜する。酸化物１５０となる酸化物の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
Next, an oxide film to be the oxide 150 is formed over the inner wall of the opening 145 and the insulator 175. The oxide film to be the oxide 150 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
例えば、酸化物１５０となる酸化物をスパッタリング法によって成膜する場合は、スパッタリングガスとして酸素、又は、酸素と希ガスの混合ガスを用いる。スパッタリングガスに含まれる酸素の割合を高めることで、成膜される酸化物中の過剰酸素を増やすことができる。また、上記酸化物をスパッタリング法によって成膜する場合は、上述したＩｎ−Ｍ−Ｚｎ酸化物のターゲットを用いることができる。
For example, in the case where an oxide to be the oxide 150 is formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film can be increased. In the case where the oxide is formed by a sputtering method, the above-described target of In-M-Zn oxide can be used.
また、酸化物１５０となる酸化物をスパッタリング法によって成膜する場合、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すると、酸素欠乏型の金属酸化物が形成される。酸素欠乏型の金属酸化物をチャネル形成領域に用いたトランジスタは、比較的高い電界効果移動度が得られる。
In the case where an oxide to be the oxide 150 is formed by a sputtering method, the oxygen-deficient type is formed by setting the proportion of oxygen contained in the sputtering gas to 1% to 30%, preferably 5% to 20%. The metal oxide is formed. A transistor in which an oxygen-deficient metal oxide is used for a channel formation region can have a relatively high field-effect mobility.
本実施の形態では、酸化物１５０となる酸化物として、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて成膜する。なお、酸化物１５０となる酸化物は、成膜条件、及び原子数比を適宜選択することで、トランジスタ１０の酸化物１５０に求める特性に合わせて成膜するとよい。
In this embodiment, as the oxide to be the oxide 150, an In: Ga: Zn = 4: 2: 4.1 [atomic ratio] In—Ga—Zn oxide target is used by a sputtering method. Film. Note that the oxide to be the oxide 150 is preferably formed in accordance with characteristics required for the oxide 150 of the transistor 10 by appropriately selecting a deposition condition and an atomic ratio.
なお、上述したように、酸化物１５０は、２層以上の積層構造であってもよい。例えば、酸化物１５０が、下から酸化物１５０ａ（図示しない。）と、酸化物１５０ｂ（図示しない。）からなる２層構造である場合、酸化物１５０ａとなる酸化物は、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すればよい。そして、酸化物１５０ｂとなる酸化物は、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて、スパッタリングガスに含まれる酸素の割合を７０％以上、好ましくは８０％以上、より好ましくは１００％として成膜すればよい。酸化物１５０が当該構成である場合、主として、酸化物１５０ａが、トランジスタ１０のチャネル形成領域として機能する。酸化物１５０を当該構成とすることで、酸化物１５０ｂとなる酸化物に含まれる酸素を、第４の加熱処理などで、酸化物１５０ａとなる酸化物に供給することができる。なお、第４の加熱処理は、酸化物１５０ｂとなる酸化物の成膜後に行うことが好ましい。加熱処理の条件としては、窒素雰囲気にて４００℃の温度で１時間の処理を行った後に、連続して酸素雰囲気にて４００℃の温度で１時間の処理を行うことが好ましい。
Note that as described above, the oxide 150 may have a stacked structure of two or more layers. For example, in the case where the oxide 150 has a two-layer structure including the oxide 150a (not illustrated) and the oxide 150b (not illustrated) from the bottom, the oxide to be the oxide 150a is formed by sputtering using a sputtering method. : Ga: Zn = 4: 2: 4.1 [atomic ratio] In—Ga—Zn oxide target, the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5%. The film may be formed at 20% or less. Then, the oxide to be the oxide 150b is formed by using a In—Ga: Zn = 1: 3: 4 [atomic ratio] In—Ga—Zn oxide target by sputtering to include oxygen contained in the sputtering gas. The film thickness may be set to 70% or more, preferably 80% or more, more preferably 100%. In the case where the oxide 150 has the above structure, the oxide 150 a mainly functions as a channel formation region of the transistor 10. With the structure of the oxide 150, oxygen contained in the oxide to be the oxide 150b can be supplied to the oxide to be the oxide 150a by a fourth heat treatment or the like. Note that the fourth heat treatment is preferably performed after formation of the oxide to be the oxide 150b. As a condition for the heat treatment, it is preferable to perform the treatment for one hour at a temperature of 400 ° C. in a nitrogen atmosphere and then perform the treatment for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
または、例えば、酸化物１５０が、下から酸化物１５０ａ（図示しない。）、酸化物１５０ｂ（図示しない。）からなる２層構造である場合、酸化物１５０ａとなる酸化物は、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて、スパッタリングガスに含まれる酸素の割合を７０％以上、好ましくは８０％以上、より好ましくは１００％として成膜すればよい。そして、酸化物１５０ｂとなる酸化物は、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すればよい。酸化物１５０が当該構成である場合、主として、酸化物１５０ｂが、トランジスタ１０のチャネル形成領域として機能する。酸化物１５０を当該構成とすることで、酸化物１５０ａとなる酸化物に含まれる酸素を、第４の加熱処理などで、酸化物１５０ｂとなる酸化物に供給することができる。
Alternatively, for example, in the case where the oxide 150 has a two-layer structure including the oxide 150a (not illustrated) and the oxide 150b (not illustrated) from the bottom, the oxide to be the oxide 150a is formed by a sputtering method. Using an In—Ga—Zn oxide target with In: Ga: Zn = 1: 3: 4 [atomic ratio], the proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, more preferably. May be formed as 100%. Then, the oxide to be the oxide 150b is included in a sputtering gas by using an In—Ga—Zn oxide target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] by a sputtering method. The film may be formed at a ratio of oxygen of 1% to 30%, preferably 5% to 20%. In the case where the oxide 150 has the above structure, the oxide 150b mainly functions as a channel formation region of the transistor 10. With the structure of the oxide 150, oxygen contained in the oxide to be the oxide 150a can be supplied to the oxide to be the oxide 150b by a fourth heat treatment or the like.
また、酸化物１５０が、下から酸化物１５０ａ、酸化物１５０ｂ、及び酸化物１５０ｃ（図示しない。）からなる３層構造である場合、酸化物１５０ａとなる酸化物及び酸化物１５０ｂとなる酸化物は、上述の条件で成膜し、酸化物１５０ｃとなる酸化物は、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて、スパッタリングガスに含まれる酸素の割合を７０％以上、好ましくは８０％以上、より好ましくは１００％として成膜すればよい。上述したように、酸化物１５０ｂとなる酸化物の成膜後に、第４の加熱処理を行うことが好ましい。酸化物１５０が当該構成である場合、主として、酸化物１５０ｂが、トランジスタ１０のチャネル形成領域として機能する。酸化物１５０を当該構成とすることで、酸化物１５０ａとなる酸化物に含まれる酸素に加え、酸化物１５０ｃとなる酸化物に含まれる酸素も、後の加熱処理などで、酸化物１５０ｂとなる酸化物に供給することができる。
In the case where the oxide 150 has a three-layer structure including the oxide 150a, the oxide 150b, and the oxide 150c (not shown) from the bottom, the oxide that becomes the oxide 150a and the oxide that becomes the oxide 150b Is an In—Ga—Zn oxide target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] formed by sputtering under the above-described conditions. The film may be formed with the ratio of oxygen contained in the sputtering gas being 70% or more, preferably 80% or more, more preferably 100%. As described above, it is preferable to perform the fourth heat treatment after formation of the oxide to be the oxide 150b. In the case where the oxide 150 has the above structure, the oxide 150b mainly functions as a channel formation region of the transistor 10. With the structure of the oxide 150, in addition to oxygen contained in the oxide to be the oxide 150a, oxygen contained in the oxide to be the oxide 150c also becomes the oxide 150b in a later heat treatment or the like. The oxide can be supplied.
次に、酸化物１５０となる酸化物上に、絶縁体１６０となる絶縁体を成膜する。絶縁体１６０となる絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１６０となる絶縁体として、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１６０となる絶縁体としては、酸化シリコン以外に、例えば、酸化窒化シリコンを用いてもよい。
Next, an insulator to be the insulator 160 is formed over the oxide to be the oxide 150. The insulator to be the insulator 160 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed by a CVD method as an insulator to be the insulator 160. Note that as the insulator to be the insulator 160, for example, silicon oxynitride may be used in addition to silicon oxide.
ここで、第５の加熱処理を行うことが好ましい。第５の加熱処理は、第４の加熱処理の条件を用いることができる。当該加熱処理により、絶縁体１６０となる絶縁体（及び、酸化物が３層構造である場合は、酸化物１５０ｃとなる酸化物）に含まれる酸素を、酸化物１５０となる酸化物（酸化物が３層構造である場合は、酸化物１５０ｂとなる酸化物）に供給することができる。
Here, it is preferable to perform the fifth heat treatment. For the fifth heat treatment, conditions for the fourth heat treatment can be used. By the heat treatment, oxygen contained in the insulator that becomes the insulator 160 (and the oxide that becomes the oxide 150c in the case where the oxide has a three-layer structure) is converted into oxide that becomes the oxide 150 (oxide). Can be supplied to the oxide to be the oxide 150b.
次に、絶縁体１６０となる絶縁体上に、導電体１７０となる導電体を成膜する。導電体１７０となる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、導電体１７０となる導電体として、ＡＬＤ法によって窒化チタンを成膜した後、さらに、ＣＶＤ法によってタングステンを成膜する。なお、導電体１７０となる導電体では、窒化チタンの膜厚よりも、タングステンの膜厚のほうが厚いことが好ましい。また、窒化チタンは、絶縁体１６０となる絶縁体を介して、開口１４５の内壁に沿って成膜し、開口１４５内の残りの空間をタングステンで埋め込むように成膜することが好ましい。このように導電体１７０となる導電体を成膜することで、後に、窒化チタンとタングステンの積層構造を有する導電体１７０を形成することができる。
Next, a conductor to be the conductor 170 is formed on the insulator to be the insulator 160. The conductor to be the conductor 170 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, after a titanium nitride film is formed by an ALD method as a conductor to be the conductor 170, a tungsten film is further formed by a CVD method. Note that in the conductor to be the conductor 170, it is preferable that the thickness of tungsten is larger than that of titanium nitride. Titanium nitride is preferably formed so as to be formed along the inner wall of the opening 145 through an insulator serving as the insulator 160 and to fill the remaining space in the opening 145 with tungsten. By forming a conductor to be the conductor 170 in this manner, the conductor 170 having a stacked structure of titanium nitride and tungsten can be formed later.
次に、絶縁体１７５の上面が露出するまで導電体１７０となる導電体、絶縁体１６０となる絶縁体、及び酸化物１５０となる酸化物の上面を研磨し、導電体１７０、絶縁体１６０、及び酸化物１５０を形成する（図１０参照。）。当該研磨は、ＣＭＰ処理などによって行うことができる。また、絶縁体１７５の上面が露出するまで導電体１７０となる導電体、絶縁体１６０となる絶縁体、及び酸化物１５０となる酸化物の上面をドライエッチングすることによって、導電体１７０、絶縁体１６０、及び酸化物１５０を形成してもよい。本実施の形態では、ＣＭＰ処理によって導電体１７０、絶縁体１６０、及び酸化物１５０の形成を行う。当該ＣＭＰ処理によって、絶縁体１７５の上面の高さと、酸化物１５０、絶縁体１６０、及び導電体１７０の最上面の高さを同程度に形成することができる（図１０参照。）。なお、当該ＣＭＰ処理によって、絶縁体１７５の一部が除去される場合がある。
Next, the conductor which becomes the conductor 170, the insulator which becomes the insulator 160, and the upper surface of the oxide which becomes the oxide 150 are polished until the upper surface of the insulator 175 is exposed, and the conductor 170, the insulator 160, Then, an oxide 150 is formed (see FIG. 10). The polishing can be performed by a CMP process or the like. Further, the conductor 170, the insulator is formed by dry etching the conductor that becomes the conductor 170, the insulator that becomes the insulator 160, and the oxide that becomes the oxide 150 until the upper surface of the insulator 175 is exposed. 160 and the oxide 150 may be formed. In this embodiment, the conductor 170, the insulator 160, and the oxide 150 are formed by CMP treatment. By the CMP treatment, the height of the top surface of the insulator 175 and the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 can be formed to be approximately the same (see FIG. 10). Note that part of the insulator 175 may be removed by the CMP treatment.
次に、絶縁体１７５の上面、酸化物１５０、絶縁体１６０、及び導電体１７０の最上面に絶縁体１７６を、絶縁体１７６上に絶縁体１７８を、絶縁体１７８上に絶縁体１８０を、それぞれ成膜する。絶縁体１７６、絶縁体１７８、及び絶縁体１８０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体１７６として、ＣＶＤ法によって酸化シリコンを成膜し、絶縁体１７８として、スパッタリング法によって酸化アルミニウムを成膜し、絶縁体１８０として、ＣＶＤ法によって酸化シリコンを成膜する。なお、絶縁体１７６又は絶縁体１８０は、酸化シリコン以外では、例えば、酸化窒化シリコンを用いてもよい。また、絶縁体１７８については、酸化アルミニウム以外では、例えば、窒化シリコン、酸化ハフニウムを用いてもよい。
Next, the top surface of the insulator 175, the oxide 150, the insulator 160, and the top surface of the conductor 170 are the insulator 176, the insulator 176 is the insulator 178, the insulator 178 is the insulator 180, Each is deposited. The insulator 176, the insulator 178, and the insulator 180 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 176 by a CVD method, an aluminum oxide film is formed as the insulator 178 by a sputtering method, and a silicon oxide film is formed as the insulator 180 by a CVD method. . Note that the insulator 176 or the insulator 180 may be formed using silicon oxynitride other than silicon oxide, for example. For the insulator 178, other than aluminum oxide, for example, silicon nitride or hafnium oxide may be used.
次に、絶縁体１８０、絶縁体１７８、絶縁体１７６、及び絶縁体１７５に、導電体１４０に達する開口を形成する。開口の形成はウエットエッチング法を用いてもよいが、ドライエッチング法を用いるほうが微細加工には好ましい。
Next, an opening reaching the conductor 140 is formed in the insulator 180, the insulator 178, the insulator 176, and the insulator 175. The opening may be formed by a wet etching method, but the dry etching method is preferable for fine processing.
開口の形成後に、導電体１９５となる導電体を成膜する。ここで、導電体１９５は、酸素の透過を抑制する機能を有する導電体１９５ａ（図示しない。）と、導電体１９５ａよりも導電率の高い導電体１９５ｂ（図示しない。）とからなる、積層構造とすることが好ましい。
After the opening is formed, a conductor to be the conductor 195 is formed. Here, the conductor 195 has a stacked structure including a conductor 195a (not shown) having a function of suppressing permeation of oxygen and a conductor 195b (not shown) having a higher conductivity than the conductor 195a. It is preferable that
導電体１９５ａとなる導電体は、酸素の透過を抑制する機能を有する導電性材料を含むことが好ましい。例えば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。又は、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体１９５ａとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
The conductor to be the conductor 195a preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 195a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体１９５ａとなる導電体として、スパッタリング法によって窒化タンタルを成膜する。
In this embodiment mode, tantalum nitride is formed by a sputtering method as a conductor to be the conductor 195a.
次に、導電体１９５ａとなる導電体上に、導電体１９５ｂとなる導電体を成膜する。当該導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
Next, a conductor to be the conductor 195b is formed on the conductor to be the conductor 195a. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体１９５ｂとなる導電体として、ＡＬＤ法によって窒化チタンを成膜し、当該窒化チタン上にＣＶＤ法によってタングステンを成膜する。
In this embodiment, as a conductor to be the conductor 195b, titanium nitride is formed by an ALD method, and tungsten is formed over the titanium nitride by a CVD method.
次に、ＣＭＰ処理を行うことで、導電体１９５ａとなる導電体、及び、導電体１９５ｂとなる導電体の一部を除去し、絶縁体１８０を露出する。その結果、開口部のみに、導電体１９５ａとなる導電体、及び、導電体１９５ｂとなる導電体が残存する。これにより、上面が平坦な、導電体１９５ａ及び導電体１９５ｂからなる導電体１９５を形成することができる。なお、当該ＣＭＰ処理により、絶縁体１８０の一部が除去される場合がある。
Next, by performing a CMP process, the conductor to be the conductor 195a and a part of the conductor to be the conductor 195b are removed, and the insulator 180 is exposed. As a result, the conductor to be the conductor 195a and the conductor to be the conductor 195b remain only in the opening. Accordingly, the conductor 195 including the conductor 195a and the conductor 195b having a flat upper surface can be formed. Note that part of the insulator 180 may be removed by the CMP treatment.
次に、絶縁体１８０及び導電体１９５上に、導電体２００となる導電体を成膜する。ここで、導電体２００は、酸素の透過を抑制する機能を有する導電体２００ａ（図示しない。）と、導電体２００ａよりも導電率の高い導電体２００ｂ（図示しない。）とからなる、積層構造とすることが好ましい。
Next, a conductor to be the conductor 200 is formed over the insulator 180 and the conductor 195. Here, the conductor 200 is a stacked structure including a conductor 200a (not shown) having a function of suppressing permeation of oxygen and a conductor 200b (not shown) having higher conductivity than the conductor 200a. It is preferable that
導電体２００ａとなる導電体は、酸素の透過を抑制する機能を有する導電性材料を含むことが好ましい。例えば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。又は、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体２００ａとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。
The conductor to be the conductor 200a preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 200a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体２００ａとなる導電体として、スパッタリング法によって窒化タンタル、又は窒化タンタルの上に窒化チタンを積層した膜を成膜する。導電体２００ａとなる導電体として、このような金属窒化物を用いることにより、後述する導電体２００ｂに銅など拡散しやすい金属を用いても、当該金属が導電体２００ａ及び導電体１９５を介して、トランジスタ１０中に拡散するのを防ぐことができる。
In this embodiment, as the conductor to be the conductor 200a, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the conductor to be the conductor 200a, even if a metal that easily diffuses, such as copper, is used for the conductor 200b described later, the metal is interposed through the conductor 200a and the conductor 195. , Diffusion into the transistor 10 can be prevented.
次に、導電体２００ａとなる導電体上に、導電体２００ｂとなる導電体を成膜する。導電体２００ｂとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、又はＡＬＤ法などを用いて行うことができる。本実施の形態では、導電体２００ｂとなる導電体として、銅などの低抵抗導電性材料を成膜する。
Next, a conductor to be the conductor 200b is formed on the conductor to be the conductor 200a. The conductor to be the conductor 200b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductor to be the conductor 200b.
次に、リソグラフィー法などを用いて、導電体１９５と重なる領域を有するように、導電体２００ｂとなる導電体、及び導電体２００ａとなる導電体を加工し、絶縁体１８０上に導電体２００ａ及び導電体２００ｂからなる導電体２００を形成することができる。なお、当該加工により、絶縁体１８０の一部が除去される場合がある。
Next, by using a lithography method or the like, the conductor to be the conductor 200b and the conductor to be the conductor 200a are processed so as to have a region overlapping with the conductor 195, and the conductor 200a and the conductor 200a are formed over the insulator 180. A conductor 200 made of the conductor 200b can be formed. Note that part of the insulator 180 may be removed by the processing.
以上により、本発明の一態様に係るトランジスタ１０を有する半導体装置を作製することができる（図１参照。）。
Through the above, a semiconductor device including the transistor 10 according to one embodiment of the present invention can be manufactured (see FIG. 1).
以上のように、本発明の一態様により、微細化又は高集積化が可能な半導体装置を提供することができる。又は、本発明の一態様により、リソグラフィー法では作製することが困難な数ｎｍ、あるいはそれ以下のチャネル長の複数のトランジスタを、基板面内において、精度良くかつ容易に作製することができる。又は、本発明の一態様により、チャネル長が微細でありながら、短チャネル効果の顕在化しにくい、良好な電気特性のトランジスタを有する半導体装置を作製することができる。また、本発明の一態様では、チャネル長だけでなく、配線やプラグも含めた素子サイズの微細なトランジスタを有する半導体装置を作製することができる。又は、本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。又は、本発明の一態様により、オフ電流の小さいトランジスタを有する半導体装置を提供することができる。又は、本発明の一態様により、オン電流の大きいトランジスタを有する半導体装置を提供することができる。又は、本発明の一態様により、基板面内において、素子間の電気特性ばらつきが小さい半導体装置を提供することができる。又は、本発明の一態様により、信頼性の高い半導体装置を提供することができる。又は、本発明の一態様により、消費電力が低減された半導体装置を提供することができる。又は、本発明の一態様により、生産性の高い半導体装置を提供することができる。
As described above, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a plurality of transistors with a channel length of several nanometers or less that are difficult to manufacture by a lithography method can be manufactured with high accuracy and easily in a substrate surface. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics in which a short channel effect is difficult to be realized while a channel length is fine can be manufactured. Further, according to one embodiment of the present invention, a semiconductor device including a minute transistor with an element size including not only a channel length but also a wiring and a plug can be manufactured. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device in which variation in electrical characteristics between elements is small in a substrate surface can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.
以上、本実施の形態に示す構成、方法などは、他の実施の形態に示す構成、方法などと適宜組み合わせて用いることができる。
As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.
（実施の形態２）
本実施の形態では、本発明の一態様に係る半導体装置の一形態を、図１１を用いて説明する。 (Embodiment 2)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
本実施の形態では、本発明の一態様に係る半導体装置の一形態を、図１１を用いて説明する。 (Embodiment 2)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
［記憶装置］
図１１に示す記憶装置は、トランジスタ３０００、トランジスタ２０００、及び容量素子１０００を有している。 [Storage device]
The memory device illustrated in FIG. 11 includes atransistor 3000, a transistor 2000, and a capacitor 1000.
図１１に示す記憶装置は、トランジスタ３０００、トランジスタ２０００、及び容量素子１０００を有している。 [Storage device]
The memory device illustrated in FIG. 11 includes a
トランジスタ２０００は、金属酸化物を有する半導体層にチャネルが形成されるトランジスタである。トランジスタ２０００は、オフ電流が小さいため、トランジスタ２０００を記憶装置に用いることにより、長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、あるいは、リフレッシュ動作の頻度が極めて少ないため、記憶装置の消費電力を十分に低減することができる。
The transistor 2000 is a transistor in which a channel is formed in a semiconductor layer including a metal oxide. Since the transistor 2000 has a low off-state current, stored data can be held for a long time by using the transistor 2000 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
図１１において、第１の配線３００１は、トランジスタ３０００のソースと電気的に接続され、第２の配線３００２は、トランジスタ３０００のドレインと電気的に接続されている。また、第３の配線３００３は、トランジスタ２０００のソース又はドレインの一方と電気的に接続され、第４の配線３００４は、トランジスタ２０００のゲートと電気的に接続されている。そして、トランジスタ３０００のゲート、及びトランジスタ２０００のソース又はドレインの他方は、容量素子１０００の電極の一方と電気的に接続され、第５の配線３００５は、容量素子１０００の電極の他方と電気的に接続されている。
In FIG. 11, the first wiring 3001 is electrically connected to the source of the transistor 3000, and the second wiring 3002 is electrically connected to the drain of the transistor 3000. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 2000, and the fourth wiring 3004 is electrically connected to the gate of the transistor 2000. The other of the gate of the transistor 3000 and the source or drain of the transistor 2000 is electrically connected to one of the electrodes of the capacitor 1000, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 1000. It is connected.
図１１に示す記憶装置は、トランジスタ３０００のゲートの電位が保持可能という特性を有することで、以下に示すように、情報の書き込み、保持、読み出しが可能である。
The memory device shown in FIG. 11 has a characteristic that the potential of the gate of the transistor 3000 can be held, so that information can be written, held, and read as described below.
情報の書き込み及び保持について説明する。まず、第４の配線３００４の電位を、トランジスタ２０００が導通状態となる電位にして、トランジスタ２０００を導通状態とする。これにより、第３の配線３００３の電位が、トランジスタ３０００のゲート、及び容量素子１０００の電極の一方と電気的に接続するノードＦＧに与えられる。すなわち、トランジスタ３０００のゲートには、所定の電荷が与えられる（書き込み）。ここでは、異なる二つの電位レベルを与える電荷（以下、Ｌｏｗレベル電荷、Ｈｉｇｈレベル電荷という。）のどちらかが与えられるものとする。その後、第４の配線３００４の電位を、トランジスタ２０００が非導通状態となる電位にして、トランジスタ２０００を非導通状態とすることにより、ノードＦＧに電荷が保持される（保持）。
Describes the writing and holding of information. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is turned on, so that the transistor 2000 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 3000 and the electrode of the capacitor 1000. That is, predetermined charge is given to the gate of the transistor 3000 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as a Low level charge and a High level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is turned off and the transistor 2000 is turned off, so that charge is held at the node FG (holding).
トランジスタ２０００のオフ電流が小さい場合、ノードＦＧの電荷は長期間にわたって保持される。
When the off-state current of the transistor 2000 is small, the charge of the node FG is held for a long time.
次に情報の読み出しについて説明する。第１の配線３００１に所定の電位（定電位）を与えた状態で、第５の配線３００５に適切な電位（読み出し電位）を与えると、第２の配線３００２は、ノードＦＧに保持された電荷量に応じた電位をとる。これは、トランジスタ３０００をｎチャネル型とすると、トランジスタ３０００のゲートにＨｉｇｈレベル電荷が与えられている場合の見かけ上の閾値電圧Ｖｔｈ＿Ｈは、トランジスタ３０００のゲートにＬｏｗレベル電荷が与えられている場合の見かけ上の閾値電圧Ｖｔｈ＿Ｌより低くなるためである。ここで、見かけ上の閾値電圧とは、トランジスタ３０００を導通状態とするために必要な第５の配線３００５の電位をいうものとする。したがって、第５の配線３００５の電位をＶｔｈ＿ＨとＶｔｈ＿Ｌの間の電位Ｖ０とすることにより、ノードＦＧに与えられた電荷を判別できる。例えば、書き込みにおいて、ノードＦＧにＨｉｇｈレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＞Ｖｔｈ＿Ｈ）となれば、トランジスタ３０００は導通状態となる。一方、ノードＦＧにＬｏｗレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＜Ｖｔｈ＿Ｌ）となっても、トランジスタ３０００は非導通状態のままである。このため、第２の配線３００２の電位を判別することで、ノードＦＧに保持されている情報を読み出すことができる。
Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3000 is an n-channel type, the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3000 is the case where a low level charge is applied to the gate of the transistor 3000 This is because it becomes lower than the apparent threshold voltage Vth_L . Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3000 into a conductive state. Therefore, by setting the potential of the fifth wiring 3005 to a potential V 0 between V th_H and V th_L , the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 3000 is turned on when the potential of the fifth wiring 3005 is V 0 (> V th_H ). On the other hand, in the case where a low-level charge is supplied to the node FG, the transistor 3000 is kept off even when the potential of the fifth wiring 3005 is V 0 (<V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
＜記憶装置の構造＞
本発明の一態様の記憶装置は、図１１に示すようにトランジスタ３０００、トランジスタ２０００、及び容量素子１０００を有する。トランジスタ２０００はトランジスタ３０００の上方に設けられ、容量素子１０００はトランジスタ３０００、及びトランジスタ２０００の上方に設けられている。 <Structure of storage device>
A memory device of one embodiment of the present invention includes atransistor 3000, a transistor 2000, and a capacitor 1000 as illustrated in FIG. The transistor 2000 is provided above the transistor 3000, and the capacitor 1000 is provided above the transistor 3000 and the transistor 2000.
本発明の一態様の記憶装置は、図１１に示すようにトランジスタ３０００、トランジスタ２０００、及び容量素子１０００を有する。トランジスタ２０００はトランジスタ３０００の上方に設けられ、容量素子１０００はトランジスタ３０００、及びトランジスタ２０００の上方に設けられている。 <Structure of storage device>
A memory device of one embodiment of the present invention includes a
トランジスタ３０００は、基板３１１上に設けられ、導電体３１６、絶縁体３１５、基板３１１の一部からなる半導体領域３１３、及び、ソース領域又はドレイン領域として機能する低抵抗領域３１４ａ及び低抵抗領域３１４ｂを有する。
The transistor 3000 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b which function as a source region or a drain region. Have.
トランジスタ３０００は、ｐチャネル型、あるいはｎチャネル型のいずれでもよい。
The transistor 3000 may be either a p-channel type or an n-channel type.
半導体領域３１３のチャネルが形成される領域、その近傍の領域、ソース領域、又はドレイン領域となる低抵抗領域３１４ａ、及び低抵抗領域３１４ｂなどにおいて、シリコン系半導体などの半導体を含むことが好ましく、単結晶シリコンを含むことが好ましい。又は、Ｇｅ（ゲルマニウム）、ＳｉＧｅ（シリコンゲルマニウム）、ＧａＡｓ（ガリウムヒ素）、ＧａＡｌＡｓ（ガリウムアルミニウムヒ素）などを有する材料で形成してもよい。結晶格子に応力を与え、格子間隔を変化させることで有効質量を制御したシリコンを用いた構成としてもよい。又はＧａＡｓとＧａＡｌＡｓ等を用いることで、トランジスタ３０００をＨＥＭＴ（Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ）としてもよい。
The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 3000 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
低抵抗領域３１４ａ、及び低抵抗領域３１４ｂは、半導体領域３１３に適用される半導体材料に加え、ヒ素、リンなどのｎ型の導電性を付与する元素、又はホウ素などのｐ型の導電性を付与する元素を含む。
The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
ゲート電極として機能する導電体３１６は、ヒ素、リンなどのｎ型の導電性を付与する元素、又はホウ素などのｐ型の導電性を付与する元素を含むシリコンなどの半導体材料、金属材料、合金材料、又は金属酸化物材料などの導電性材料を用いることができる。
The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.
なお、導電体の材料により、仕事関数が定まるため、導電体の材料を変更することで、トランジスタのＶｔｈを調整することができる。具体的には、導電体に窒化チタンや窒化タンタルなどの材料を用いることが好ましい。さらに、導電性と埋め込み性を両立するために、導電体にタングステンやアルミニウムなどの金属材料を積層として用いることが好ましく、特に、タングステンを用いることが耐熱性の点で好ましい。
Note that since the work function is determined by the material of the conductor, Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and in particular, tungsten is preferable from the viewpoint of heat resistance.
なお、図１１に示すトランジスタ３０００は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。
Note that the transistor 3000 illustrated in FIGS. 11A and 11B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
トランジスタ３０００を覆って、絶縁体３２０、絶縁体３２２、絶縁体３２４、及び絶縁体３２６が、順に積層して設けられている。
An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 3000.
絶縁体３２０、絶縁体３２２、絶縁体３２４、及び絶縁体３２６として、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、窒化アルミニウムなどを用いればよい。
As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
絶縁体３２２は、その下方に設けられるトランジスタ３０００などによって生じる段差を平坦化する平坦化膜としての機能を有していてもよい。例えば、絶縁体３２２の上面は、平坦性を高めるためにＣＭＰ処理等により平坦化されていてもよい。
The insulator 322 may have a function as a planarization film that planarizes a step generated by the transistor 3000 or the like provided below the insulator 322. For example, the top surface of the insulator 322 may be planarized by CMP treatment or the like to improve planarity.
また、絶縁体３２４には、基板３１１、又はトランジスタ３０００などから、トランジスタ２０００が設けられる領域に、水素や不純物が拡散しないようなバリア性を有する膜を用いることが好ましい。
The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 3000 to a region where the transistor 2000 is provided.
水素に対するバリア性を有する膜の一例として、例えば、ＣＶＤ法で形成した窒化シリコンを用いることができる。ここで、トランジスタ２０００等の金属酸化物を有する半導体素子に、水素が拡散することで、当該半導体素子の電気特性が劣化する場合がある。したがって、トランジスタ２０００と、トランジスタ３０００との間に、水素の拡散を抑制する膜を用いることが好ましい。水素の拡散を抑制する膜とは、具体的には、水素の脱離量が少ない膜とする。
As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having a metal oxide such as the transistor 2000, electrical characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 2000 and the transistor 3000. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
水素の脱離量は、例えば、昇温脱離ガス分析法（ＴＤＳ）などを用いて分析することができる。例えば、絶縁体３２４の水素の脱離量は、ＴＤＳ分析において、膜の表面温度が５０℃から５００℃の範囲において、水素原子に換算した脱離量が、絶縁体３２４の面積当たりに換算して、１０×１０１５ａｔｏｍｓ／ｃｍ２以下、好ましくは５×１０１５ａｔｏｍｓ／ｃｍ２以下であればよい。
The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is calculated by converting the amount of desorption converted to hydrogen atoms per area of the insulator 324 in the range of the surface temperature of the film from 50 ° C. to 500 ° C. in TDS analysis. 10 × 10 15 atoms / cm 2 or less, preferably 5 × 10 15 atoms / cm 2 or less.
なお、絶縁体３２６は、絶縁体３２４よりも誘電率が低いことが好ましい。例えば、絶縁体３２６の比誘電率は４未満が好ましく、３未満がより好ましい。また、例えば、絶縁体３２６の比誘電率は、絶縁体３２４の比誘電率の０．７倍以下が好ましく、０．６倍以下がより好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。
Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times that of the insulator 324, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.
また、絶縁体３２０、絶縁体３２２、絶縁体３２４、及び絶縁体３２６には、容量素子１０００、又はトランジスタ２０００と電気的に接続する導電体３２８、及び導電体３３０等が埋め込まれている。なお、導電体３２８、及び導電体３３０はプラグ、又は配線としての機能を有する。また、プラグ又は配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、及び導電体の一部がプラグとして機能する場合もある。
In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 that is electrically connected to the capacitor 1000 or the transistor 2000, the conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
各プラグ、及び配線（導電体３２８、及び導電体３３０等）の材料としては、金属材料、合金材料、金属窒化物材料、又は金属酸化物材料などの導電性材料を、単層又は積層して用いることができる。耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましく、タングステンを用いることが好ましい。又は、アルミニウムや銅などの低抵抗導電性材料で形成することが好ましい。低抵抗導電性材料を用いることで配線抵抗を低くすることができる。
As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is formed in a single layer or stacked layers. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Or it is preferable to form with low resistance conductive materials, such as aluminum and copper. Wiring resistance can be lowered by using a low-resistance conductive material.
絶縁体３２６、及び導電体３３０上に、配線層を設けてもよい。例えば、図１１において、絶縁体３５０、絶縁体３５２、及び絶縁体３５４が、順に積層して設けられている。また、絶縁体３５０、絶縁体３５２、及び絶縁体３５４には、導電体３５６が形成されている。導電体３５６は、プラグ、又は配線としての機能を有する。なお導電体３５６は、導電体３２８、及び導電体３３０と同様の材料を用いて設けることができる。
A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 11, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３５０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３５６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３５０が有する開口部に、水素に対するバリア性を有する導電体３５６を形成することが好ましい。当該構成により、トランジスタ３０００とトランジスタ２０００とを、バリア層により分離することができ、トランジスタ３０００からトランジスタ２０００への水素の拡散を抑制することができる。
Note that for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, the conductor 356 having a barrier property against hydrogen is preferably formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by the barrier layer, and hydrogen diffusion from the transistor 3000 to the transistor 2000 can be suppressed.
なお、水素に対するバリア性を有する導電体としては、例えば、窒化タンタル等を用いるとよい。また、窒化タンタルと導電性が高いタングステンを積層することで、配線としての導電性を保持したまま、トランジスタ３０００からの水素の拡散を抑制することができる。この場合、水素に対するバリア性を有する窒化タンタル層が、水素に対するバリア性を有する絶縁体３５０と接する構造であることが好ましい。
For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 3000 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
絶縁体３５４、及び導電体３５６上に、配線層を設けてもよい。例えば、図１１において、絶縁体３６０、絶縁体３６２、及び絶縁体３６４が、順に積層して設けられている。また、絶縁体３６０、絶縁体３６２、及び絶縁体３６４には、導電体３６６が形成されている。導電体３６６は、プラグ、又は配線としての機能を有する。なお導電体３６６は、導電体３２８、及び導電体３３０と同様の材料を用いて設けることができる。
A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 11, the insulator 360, the insulator 362, and the insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３６０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３６６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３６０が有する開口部に、水素に対するバリア性を有する導電体３６６を形成することが好ましい。当該構成により、トランジスタ３０００とトランジスタ２０００とを、バリア層により分離することができ、トランジスタ３０００からトランジスタ２０００への水素の拡散を抑制することができる。
Note that for example, as the insulator 360, an insulator having a barrier property against hydrogen is preferably used as the insulator 360. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, the conductor 366 having a barrier property against hydrogen is preferably formed in the opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by the barrier layer, and hydrogen diffusion from the transistor 3000 to the transistor 2000 can be suppressed.
絶縁体３６４、及び導電体３６６上に、配線層を設けてもよい。例えば、図１１において、絶縁体３７０、絶縁体３７２、及び絶縁体３７４が、順に積層して設けられている。また、絶縁体３７０、絶縁体３７２、及び絶縁体３７４には、導電体３７６が形成されている。導電体３７６は、プラグ、又は配線としての機能を有する。なお導電体３７６は、導電体３２８、及び導電体３３０と同様の材料を用いて設けることができる。
A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 11, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３７０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３７６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３７０が有する開口部に、水素に対するバリア性を有する導電体３７６を形成することが好ましい。当該構成により、トランジスタ３０００とトランジスタ２０００とを、バリア層により分離することができ、トランジスタ３０００からトランジスタ２０００への水素の拡散を抑制することができる。
Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, the conductor 376 having a barrier property against hydrogen is preferably formed in the opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by the barrier layer, and hydrogen diffusion from the transistor 3000 to the transistor 2000 can be suppressed.
絶縁体３７４、及び導電体３７６上に、配線層を設けてもよい。例えば、図１１において、絶縁体３８０、絶縁体３８２、及び絶縁体３８４が、順に積層して設けられている。また、絶縁体３８０、絶縁体３８２、及び絶縁体３８４には、導電体３８６が形成されている。導電体３８６は、プラグ、又は配線としての機能を有する。なお導電体３８６は、導電体３２８、及び導電体３３０と同様の材料を用いて設けることができる。
A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 11, the insulator 380, the insulator 382, and the insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３８０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３８６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３８０が有する開口部に、水素に対するバリア性を有する導電体３８６を形成することが好ましい。当該構成により、トランジスタ３０００とトランジスタ２０００とを、バリア層により分離することができ、トランジスタ３０００からトランジスタ２０００への水素の拡散を抑制することができる。
Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, the conductor 386 having a barrier property against hydrogen is preferably formed in the opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by the barrier layer, and hydrogen diffusion from the transistor 3000 to the transistor 2000 can be suppressed.
絶縁体３８４、及び導電体３８６上には、絶縁体２１０、絶縁体１００、絶縁体１０２、及び絶縁体１０５が、順に積層して設けられている。絶縁体２１０、絶縁体１００、絶縁体１０２、及び絶縁体１０５のいずれかは、酸素や水素に対してバリア性のある膜を用いることが好ましい。
The insulator 210, the insulator 100, the insulator 102, and the insulator 105 are sequentially stacked over the insulator 384 and the conductor 386. Any of the insulator 210, the insulator 100, the insulator 102, and the insulator 105 is preferably formed using a film having a barrier property against oxygen or hydrogen.
例えば、絶縁体２１０、及び絶縁体１０２には、基板３１１、又はトランジスタ３０００を設ける領域などから、トランジスタ２０００を設ける領域に、水素や不純物が拡散しないようなバリア性を有する膜を用いることが好ましい。したがって、絶縁体３２４と同様の材料を用いることができる。
For example, the insulator 210 and the insulator 102 are preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 3000 is provided to a region where the transistor 2000 is provided. . Therefore, a material similar to that of the insulator 324 can be used.
水素に対するバリア性を有する膜の一例として、ＣＶＤ法で形成した窒化シリコンを用いることができる。ここで、トランジスタ２０００等の金属酸化物を有する半導体素子に水素が拡散することで、当該半導体素子の電気特性が劣化する場合がある。したがって、トランジスタ２０００と、トランジスタ３０００との間に、水素の拡散を抑制する膜を用いることが好ましい。水素の拡散を抑制する膜とは、具体的には、水素の脱離量が少ない膜とする。
As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having a metal oxide such as the transistor 2000, electrical characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 2000 and the transistor 3000. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
また、水素に対するバリア性を有する膜として、例えば、絶縁体２１０、及び絶縁体１０２には、酸化アルミニウム、酸化ハフニウム、酸化タンタルなどの金属酸化物を用いることが好ましい。
As the film having a barrier property against hydrogen, for example, the insulator 210 and the insulator 102 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
特に、酸化アルミニウムは、酸素、及びトランジスタの電気特性の変動要因となる水素、水などの不純物、の両方に対して膜を透過させない遮断効果が高い。したがって、酸化アルミニウムは、トランジスタの作製工程中及び作製後において、水素、水などの不純物のトランジスタ２０００への混入を防止することができる。また、トランジスタ２０００を構成する酸化物からの酸素の放出を抑制することができる。そのため、トランジスタ２０００に対する保護膜として用いることに適している。
In particular, aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000.
また、例えば、絶縁体１００、及び絶縁体１０５には、絶縁体３２０と同様の材料を用いることができる。また、当該絶縁体に、比較的誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。例えば、絶縁体１００、及び絶縁体１０５として、酸化シリコンや酸化窒化シリコンなどを用いることができる。
For example, for the insulator 100 and the insulator 105, the same material as the insulator 320 can be used. In addition, by using a material having a relatively low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 100 and the insulator 105, silicon oxide, silicon oxynitride, or the like can be used.
また、絶縁体２１０、絶縁体１００、絶縁体１０２、及び絶縁体１０５には、導電体２１８、及びトランジスタ２０００と電気的に接続する導電体（導電体１８５）等が埋め込まれている。なお、導電体２１８は、容量素子１０００、又はトランジスタ３０００と電気的に接続するプラグ、又は配線としての機能を有する。導電体２１８は、導電体３２８、及び導電体３３０と同様の材料を用いて設けることができる。
The insulator 210, the insulator 100, the insulator 102, and the insulator 105 are embedded with a conductor 218, a conductor (conductor 185) that is electrically connected to the transistor 2000, and the like. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 1000 or the transistor 3000. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.
特に、絶縁体２１０、及び絶縁体１０２と接する領域の導電体２１８は、酸素、水素、及び水に対するバリア性を有する導電体であることが好ましい。当該構成により、トランジスタ３０００とトランジスタ２０００とを、酸素、水素、及び水に対するバリア性を有する層で確実に分離することができ、トランジスタ３０００からトランジスタ２０００への水素の拡散を抑制することができる。
In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 102 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 3000 and the transistor 2000 can be reliably separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.
絶縁体１０５の上方には、絶縁体１１０を介して、トランジスタ２０００が設けられている。なお、トランジスタ２０００の構造は、先の実施の形態で説明した半導体装置が有するトランジスタを用いればよい。また、図１１に示すトランジスタ２０００は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。
A transistor 2000 is provided above the insulator 105 with an insulator 110 interposed therebetween. Note that as the structure of the transistor 2000, a transistor included in the semiconductor device described in the above embodiment may be used. The transistor 2000 illustrated in FIGS. 11A and 11B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
トランジスタ２０００の上方には、絶縁体１７５、絶縁体１７６、及び絶縁体１７８を設ける。
An insulator 175, an insulator 176, and an insulator 178 are provided above the transistor 2000.
絶縁体１７８は、酸素や水素に対してバリア性のある膜を用いることが好ましい。したがって、絶縁体１７８には、絶縁体１０２と同様の材料を用いることができる。例えば、絶縁体１７８には、酸化アルミニウム、酸化ハフニウム、酸化タンタルなどの金属酸化物を用いることが好ましい。
The insulator 178 is preferably a film having a barrier property against oxygen or hydrogen. Therefore, the insulator 178 can be formed using a material similar to that of the insulator 102. For example, the insulator 178 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
特に、酸化アルミニウムは、酸素、及びトランジスタの電気特性の変動要因となる水素、水などの不純物、の両方に対して膜を透過させない遮断効果が高い。したがって、酸化アルミニウムは、トランジスタの作製工程中及び作製後において、水素、水などの不純物のトランジスタ２０００への混入を防止することができる。また、トランジスタ２０００を構成する酸化物からの酸素の放出を抑制することができる。そのため、トランジスタ２０００に対する保護膜として用いることに適している。
In particular, aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000.
また、絶縁体１７８上には、絶縁体１８０が設けられている。絶縁体１８０は、絶縁体３２０と同様の材料を用いることができる。また、当該絶縁体に、比較的誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。例えば、絶縁体１８０として、酸化シリコンや酸化窒化シリコンなどを用いることができる。
Further, an insulator 180 is provided on the insulator 178. The insulator 180 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 180, silicon oxide, silicon oxynitride, or the like can be used.
また、絶縁体１１０、絶縁体１７５、絶縁体１７６、絶縁体１７８、及び絶縁体１８０には、導電体２４６、及び導電体２４８等が埋め込まれている。
In addition, a conductor 246, a conductor 248, and the like are embedded in the insulator 110, the insulator 175, the insulator 176, the insulator 178, and the insulator 180.
導電体２４６、及び導電体２４８は、容量素子１０００、トランジスタ２０００、又はトランジスタ３０００と電気的に接続するプラグ、又は配線としての機能を有する。導電体２４６、及び導電体２４８は、導電体３２８、及び導電体３３０と同様の材料を用いて設けることができる。
The conductor 246 and the conductor 248 have a function as a plug or a wiring electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.
トランジスタ２０００の上方には、容量素子１０００が設けられている。容量素子１０００は、導電体１１００、導電体１２００、及び絶縁体１３００を有する。
A capacitor element 1000 is provided above the transistor 2000. The capacitor 1000 includes a conductor 1100, a conductor 1200, and an insulator 1300.
また、導電体２４６、及び導電体２４８上に、導電体１１２を設けてもよい。導電体１１２は、容量素子１０００、トランジスタ２０００、又はトランジスタ３０００と電気的に接続するプラグ、又は配線としての機能を有する。導電体１１００は、容量素子１０００の電極としての機能を有する。なお、導電体１１２、及び導電体１１００は、同時に形成することができる。
Alternatively, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000. The conductor 1100 functions as an electrode of the capacitor 1000. Note that the conductor 112 and the conductor 1100 can be formed at the same time.
導電体１１２、及び導電体１１００には、モリブデン、チタン、タンタル、タングステン、アルミニウム、銅、クロム、ネオジム、スカンジウムから選ばれた元素を含む金属、又は上述した元素を成分とする金属窒化物（窒化タンタル、窒化チタン、窒化モリブデン、窒化タングステン）等を用いることができる。又は、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、酸化ケイ素を添加したインジウム錫酸化物などの導電性材料を適用することもできる。
The conductor 112 and the conductor 1100 include a metal containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride containing any of the above elements as a component (nitriding) (Tantalum, titanium nitride, molybdenum nitride, tungsten nitride) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.
図１１では、導電体１１２、及び導電体１１００が単層構造である構成を示したが、当該構成に限定されず、２層以上の積層構造でもよい。例えば、バリア性を有する導電体と導電性が高い導電体との間に、バリア性を有する導電体、及び導電性が高い導電体に対して密着性が高い導電体を形成してもよい。
FIG. 11 illustrates a structure in which the conductor 112 and the conductor 1100 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
また、導電体１１２、及び導電体１１００上に、容量素子１０００の誘電体として、絶縁体１３００を設ける。絶縁体１３００は、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、窒化アルミニウム、酸化ハフニウム、酸化窒化ハフニウム、窒化酸化ハフニウム、窒化ハフニウムなどを用いればよく、積層又は単層で設けることができる。
Further, an insulator 1300 is provided as a dielectric of the capacitor 1000 over the conductor 112 and the conductor 1100. The insulator 1300 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like. What is necessary is just to use, and it can provide by lamination | stacking or single layer.
例えば、絶縁体１３００には、酸化窒化シリコンなどの絶縁耐圧の高い材料を用いるとよい。当該構成により、容量素子１０００の絶縁破壊耐性が向上し、容量素子１０００の静電破壊を抑制することができる。
For example, for the insulator 1300, a material with high withstand voltage such as silicon oxynitride may be used. With this configuration, the dielectric breakdown resistance of the capacitive element 1000 is improved, and electrostatic breakdown of the capacitive element 1000 can be suppressed.
絶縁体１３００上に、導電体１１００と重畳するように、導電体１２００を設ける。なお、導電体１２００は、金属材料、合金材料、又は金属酸化物材料などの導電性材料を用いることができる。耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましく、特に、タングステンを用いることが好ましい。また、導電体などの他の構造と同時に形成する場合は、低抵抗金属材料であるＣｕ（銅）やＡｌ（アルミニウム）等を用いればよい。
A conductor 1200 is provided on the insulator 1300 so as to overlap with the conductor 1100. Note that the conductor 1200 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.
導電体１２００、及び絶縁体１３００上には、絶縁体１５００が設けられている。絶縁体１５００は、絶縁体３２０と同様の材料を用いて設けることができる。また、絶縁体１５００は、その下方の凹凸形状を被覆する平坦化膜として機能してもよい。
An insulator 1500 is provided over the conductor 1200 and the insulator 1300. The insulator 1500 can be provided using a material similar to that of the insulator 320. The insulator 1500 may function as a planarization film that covers the concave and convex shapes below the insulator 1500.
以上が、本発明の一態様に係る半導体装置を適用した記憶装置の構成例についての説明である。本構成を用いることで、金属酸化物を有するトランジスタを用いた半導体装置において、電気特性の変動を抑制するとともに、信頼性を向上させることができる。又は、オン電流が大きい金属酸化物を有するトランジスタを提供することができる。又は、オフ電流が小さい金属酸化物を有するトランジスタを提供することができる。又は、消費電力が低減された半導体装置を提供することができる。
The above is the description of the structure example of the memory device to which the semiconductor device according to one embodiment of the present invention is applied. By using this structure, in a semiconductor device using a transistor including a metal oxide, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including a metal oxide with high on-state current can be provided. Alternatively, a transistor including a metal oxide with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.
以上、本実施の形態に示す構成、方法などは、他の実施の形態に示す構成、方法などと適宜組み合わせて用いることができる。
As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.
（実施の形態３）
本実施の形態では、図１２及び図１３を用いて、本発明の一態様に係る、金属酸化物をチャネル形成領域に用いたトランジスタ（以下、ＯＳトランジスタと呼ぶ。）、及び容量素子が適用されている記憶装置の一例として、ＮＯＳＲＡＭについて説明する。ＮＯＳＲＡＭ（登録商標）とは「Ｎｏｎｖｏｌａｔｉｌｅ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ＲＡＭ」の略称であり、ゲインセル型（２Ｔ型、３Ｔ型）のメモリセルを有するＲＡＭを指す。なお、以下において、ＮＯＳＲＡＭのようにＯＳトランジスタを用いたメモリ装置を、ＯＳメモリと呼ぶ場合がある。 (Embodiment 3)
In this embodiment, a transistor using a metal oxide for a channel formation region (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are used with reference to FIGS. As an example of the storage device, NOSRAM will be described. NOSRAM (registered trademark) is an abbreviation of “Nonvolatile Oxide Semiconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Hereinafter, a memory device using an OS transistor such as NOSRAM may be referred to as an OS memory.
本実施の形態では、図１２及び図１３を用いて、本発明の一態様に係る、金属酸化物をチャネル形成領域に用いたトランジスタ（以下、ＯＳトランジスタと呼ぶ。）、及び容量素子が適用されている記憶装置の一例として、ＮＯＳＲＡＭについて説明する。ＮＯＳＲＡＭ（登録商標）とは「Ｎｏｎｖｏｌａｔｉｌｅ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ＲＡＭ」の略称であり、ゲインセル型（２Ｔ型、３Ｔ型）のメモリセルを有するＲＡＭを指す。なお、以下において、ＮＯＳＲＡＭのようにＯＳトランジスタを用いたメモリ装置を、ＯＳメモリと呼ぶ場合がある。 (Embodiment 3)
In this embodiment, a transistor using a metal oxide for a channel formation region (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are used with reference to FIGS. As an example of the storage device, NOSRAM will be described. NOSRAM (registered trademark) is an abbreviation of “Nonvolatile Oxide Semiconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Hereinafter, a memory device using an OS transistor such as NOSRAM may be referred to as an OS memory.
ＮＯＳＲＡＭでは、メモリセルにＯＳトランジスタが用いられるメモリ装置（以下、「ＯＳメモリ」と呼ぶ。）が適用されている。ＯＳメモリは、少なくとも容量素子と、容量素子の充放電を制御するＯＳトランジスタを有するメモリである。ＯＳトランジスタが極小オフ電流のトランジスタであるので、ＯＳメモリは優れた保持特性をもち、不揮発性メモリとして機能させることができる。
In NOSRAM, a memory device using an OS transistor for a memory cell (hereinafter referred to as “OS memory”) is applied. The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
＜＜ＮＯＳＲＡＭ１６００＞＞
図１２にＮＯＳＲＡＭの構成例を示す。図１２に示すＮＯＳＲＡＭ１６００は、メモリセルアレイ１６１０、コントローラ１６４０、行ドライバ１６５０、列ドライバ１６６０、出力ドライバ１６７０を有する。なお、ＮＯＳＲＡＭ１６００は、１のメモリセルで多値データを記憶する多値ＮＯＳＲＡＭである。 <<NOSRAM 1600 >>
FIG. 12 shows a configuration example of NOSRAM. ANOSRAM 1600 illustrated in FIG. 12 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
図１２にＮＯＳＲＡＭの構成例を示す。図１２に示すＮＯＳＲＡＭ１６００は、メモリセルアレイ１６１０、コントローラ１６４０、行ドライバ１６５０、列ドライバ１６６０、出力ドライバ１６７０を有する。なお、ＮＯＳＲＡＭ１６００は、１のメモリセルで多値データを記憶する多値ＮＯＳＲＡＭである。 <<
FIG. 12 shows a configuration example of NOSRAM. A
メモリセルアレイ１６１０は複数のメモリセル１６１１、複数のワード線ＷＷＬ、複数のワード線ＲＷＬ、複数のビット線ＢＬ、複数のソース線ＳＬを有する。ワード線ＷＷＬは書き込みワード線であり、ワード線ＲＷＬは読み出しワード線である。ＮＯＳＲＡＭ１６００では、１のメモリセル１６１１で３ビット（８値）のデータを記憶する。
The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a plurality of bit lines BL, and a plurality of source lines SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (eight values) data.
コントローラ１６４０は、ＮＯＳＲＡＭ１６００全体を統括的に制御し、データＷＤＡ［３１：０］の書き込み、データＲＤＡ［３１：０］の読み出しを行う。コントローラ１６４０は、外部からのコマンド信号（例えば、チップイネーブル信号、書き込みイネーブル信号など）を処理して、行ドライバ１６５０、列ドライバ１６６０及び出力ドライバ１６７０の制御信号を生成する。
The controller 1640 comprehensively controls the entire NOSRAM 1600, and writes data WDA [31: 0] and reads data RDA [31: 0]. The controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
行ドライバ１６５０は、アクセスする行を選択する機能を有する。行ドライバ１６５０は、行デコーダ１６５１、及びワード線ドライバ１６５２を有する。
The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.
列ドライバ１６６０は、ソース線ＳＬ及びビット線ＢＬを駆動する。列ドライバ１６６０は、列デコーダ１６６１、書き込みドライバ１６６２、ＤＡＣ（デジタル−アナログ変換回路）１６６３を有する。
The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
ＤＡＣ１６６３は３ビットのデジタルデータをアナログ電圧に変換する。ＤＡＣ１６６３は３２ビットのデータＷＤＡ［３１：０］を３ビットごとに、アナログ電圧に変換する。
DAC 1663 converts 3-bit digital data into analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
書き込みドライバ１６６２は、ソース線ＳＬをプリチャージする機能、ソース線ＳＬを電気的に浮遊状態にする機能、ソース線ＳＬを選択する機能、選択されたソース線ＳＬにＤＡＣ１６６３で生成した書き込み電圧を入力する機能、ビット線ＢＬをプリチャージする機能、ビット線ＢＬを電気的に浮遊状態にする機能等を有する。
The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL. A function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.
出力ドライバ１６７０は、セレクタ１６７１、ＡＤＣ（アナログ−デジタル変換回路）１６７２、出力バッファ１６７３を有する。セレクタ１６７１は、アクセスするソース線ＳＬを選択し、選択されたソース線ＳＬの電圧をＡＤＣ１６７２に送信する。ＡＤＣ１６７２は、アナログ電圧を３ビットのデジタルデータに変換する機能を持つ。ソース線ＳＬの電圧はＡＤＣ１６７２において、３ビットのデータに変換され、出力バッファ１６７３はＡＤＣ１６７２から出力されるデータを保持する。
The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
＜メモリセル１６１１乃至メモリセル１６１４＞
図１３（Ａ）は、メモリセル１６１１の構成例を示す回路図である。メモリセル１６１１は２Ｔ型のゲインセルであり、メモリセル１６１１はワード線ＷＷＬ、ワード線ＲＷＬ、ビット線ＢＬ、ソース線ＳＬに電気的に接続されている。メモリセル１６１１は、ノードＳＮ、ＯＳトランジスタＭＯ６１、トランジスタＭＰ６１、容量素子Ｃ６１を有する。ＯＳトランジスタＭＯ６１は書き込みトランジスタである。トランジスタＭＰ６１は読み出しトランジスタであり、例えば、ｐチャネル型Ｓｉトランジスタで構成される。容量素子Ｃ６１はノードＳＮの電圧を保持するための保持容量である。ノードＳＮはデータの保持ノードであり、ここではトランジスタＭＰ６１のゲートに相当する。 <Memory cells 1611 to 1614>
FIG. 13A is a circuit diagram illustrating a structural example of thememory cell 1611. The memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, the word line RWL, the bit line BL, and the source line SL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor. The capacitive element C61 is a holding capacitor for holding the voltage of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
図１３（Ａ）は、メモリセル１６１１の構成例を示す回路図である。メモリセル１６１１は２Ｔ型のゲインセルであり、メモリセル１６１１はワード線ＷＷＬ、ワード線ＲＷＬ、ビット線ＢＬ、ソース線ＳＬに電気的に接続されている。メモリセル１６１１は、ノードＳＮ、ＯＳトランジスタＭＯ６１、トランジスタＭＰ６１、容量素子Ｃ６１を有する。ＯＳトランジスタＭＯ６１は書き込みトランジスタである。トランジスタＭＰ６１は読み出しトランジスタであり、例えば、ｐチャネル型Ｓｉトランジスタで構成される。容量素子Ｃ６１はノードＳＮの電圧を保持するための保持容量である。ノードＳＮはデータの保持ノードであり、ここではトランジスタＭＰ６１のゲートに相当する。 <
FIG. 13A is a circuit diagram illustrating a structural example of the
メモリセル１６１１の書き込みトランジスタがＯＳトランジスタＭＯ６１で構成されているため、ＮＯＳＲＡＭ１６００は長時間データを保持することが可能である。
Since the write transistor of the memory cell 1611 includes the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.
図１３（Ａ）の例では、ビット線は、書き込みと読み出しで共通のビット線であるが、図１３（Ｂ）に示すように、書き込みビット線ＷＢＬと、読み出しビット線ＲＢＬとを設けてもよい。
In the example of FIG. 13A, the bit line is a common bit line for writing and reading. However, as shown in FIG. 13B, a writing bit line WBL and a reading bit line RBL may be provided. Good.
図１３（Ｃ）乃至図１３（Ｅ）にメモリセルの他の構成例を示す。図１３（Ｃ）乃至図１３（Ｅ）には、書き込み用ビット線と読み出し用ビット線を設けた例を示しているが、図１３（Ａ）のように書き込みと読み出しで共有されるビット線を設けてもよい。
FIGS. 13C to 13E show other configuration examples of the memory cell. FIGS. 13C to 13E show an example in which a write bit line and a read bit line are provided. As shown in FIG. 13A, a bit line shared by writing and reading is used. May be provided.
図１３（Ｃ）に示すメモリセル１６１２は、メモリセル１６１１の変形例であり、読み出しトランジスタをｎチャネル型トランジスタ（ＭＮ６１）に変更したものである。トランジスタＭＮ６１はＯＳトランジスタであってもよいし、Ｓｉトランジスタであってもよい。
A memory cell 1612 shown in FIG. 13C is a modified example of the memory cell 1611 in which a read transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.
図１３（Ｄ）に示すメモリセル１６１３は、３Ｔ型ゲインセルであり、ワード線ＷＷＬ、ワード線ＲＷＬ、ビット線ＷＢＬ、ビット線ＲＢＬ、ソース線ＳＬ、配線ＰＣＬに電気的に接続されている。メモリセル１６１３は、ノードＳＮ、ＯＳトランジスタＭＯ６２、トランジスタＭＰ６２、トランジスタＭＰ６３、容量素子Ｃ６２を有する。ＯＳトランジスタＭＯ６２は書き込みトランジスタである。トランジスタＭＰ６２は読み出しトランジスタであり、トランジスタＭＰ６３は選択トランジスタである。
A memory cell 1613 shown in FIG. 13D is a 3T type gain cell, and is electrically connected to the word line WWL, the word line RWL, the bit line WBL, the bit line RBL, the source line SL, and the wiring PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
図１３（Ｅ）に示すメモリセル１６１４は、メモリセル１６１３の変形例であり、読み出しトランジスタ及び選択トランジスタをｎチャネル型トランジスタ（ＭＮ６２、ＭＮ６３）に変更したものである。トランジスタＭＮ６２、トランジスタＭＮ６３はＯＳトランジスタであってもよいし、Ｓｉトランジスタであってもよい。
A memory cell 1614 shown in FIG. 13E is a modified example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (MN62 and MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.
メモリセル１６１１乃至メモリセル１６１４に設けられるＯＳトランジスタは、ボトムゲートの無いトランジスタでもよいし、ボトムゲートが有るトランジスタであってもよい。
The OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a bottom gate or a transistor with a bottom gate.
容量素子Ｃ６１の充放電によってデータを書き換えるため、ＮＯＳＲＡＭ１６００は原理的には書き換え回数に制約はなく、かつ、低エネルギーで、データの書き込み及び読み出しが可能である。また、長時間データを保持することが可能であるので、リフレッシュ頻度を低減できる。
Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no limitation on the number of rewrites in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
上記実施の形態に示す半導体装置をメモリセル１６１１、メモリセル１６１２、メモリセル１６１３、メモリセル１６１４に用いる場合、ＯＳトランジスタＭＯ６１、ＯＳトランジスタＭＯ６２としてトランジスタ２０００を用い、トランジスタＭＰ６１、トランジスタＭＮ６２としてトランジスタ３０００を用いることができる。これにより、トランジスタの上面視における占有面積を低減することができるので、本実施の形態に係る記憶装置をさらに高集積化させることができる。よって、本実施の形態に係る記憶装置の単位面積当たりの記憶容量を増加させることができる。
When the semiconductor device described in any of the above embodiments is used for the memory cell 1611, the memory cell 1612, the memory cell 1613, and the memory cell 1614, the transistor 2000 is used as the OS transistor MO61 and the OS transistor MO62, and the transistor 3000 is used as the transistor MP61 and the transistor MN62. Can be used. Accordingly, the area occupied by the transistor in a top view can be reduced, so that the memory device according to this embodiment can be further highly integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。
The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態４）
本実施の形態では、図１４及び図１５を用いて、本発明の一態様に係る、ＯＳトランジスタが適用されている記憶装置の一例として、ＤＯＳＲＡＭについて説明する。ＤＯＳＲＡＭ（登録商標）とは、「Ｄｙｎａｍｉｃ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ＲＡＭ」の略称であり、１Ｔ（トランジスタ）１Ｃ（容量）型のメモリセルを有するＲＡＭを指す。ＤＯＳＲＡＭも、ＮＯＳＲＡＭと同様に、ＯＳメモリが適用されている。 (Embodiment 4)
In this embodiment, DOSRAM is described as an example of a memory device to which an OS transistor is applied according to one embodiment of the present invention, with reference to FIGS. DOSRAM (registered trademark) is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells. OS memory is applied to DOSRAM as well as NOSRAM.
本実施の形態では、図１４及び図１５を用いて、本発明の一態様に係る、ＯＳトランジスタが適用されている記憶装置の一例として、ＤＯＳＲＡＭについて説明する。ＤＯＳＲＡＭ（登録商標）とは、「Ｄｙｎａｍｉｃ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ＲＡＭ」の略称であり、１Ｔ（トランジスタ）１Ｃ（容量）型のメモリセルを有するＲＡＭを指す。ＤＯＳＲＡＭも、ＮＯＳＲＡＭと同様に、ＯＳメモリが適用されている。 (Embodiment 4)
In this embodiment, DOSRAM is described as an example of a memory device to which an OS transistor is applied according to one embodiment of the present invention, with reference to FIGS. DOSRAM (registered trademark) is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells. OS memory is applied to DOSRAM as well as NOSRAM.
＜＜ＤＯＳＲＡＭ１４００＞＞
図１４にＤＯＳＲＡＭの構成例を示す。図１４に示すＤＯＳＲＡＭ１４００は、コントローラ１４０５、行回路１４１０、列回路１４１５、メモリセル及びセンスアンプアレイ１４２０（以下、「ＭＣ−ＳＡアレイ１４２０」と呼ぶ。）を有する。 <<DOSRAM 1400 >>
FIG. 14 shows a configuration example of the DOSRAM. ADOSRAM 1400 illustrated in FIG. 14 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
図１４にＤＯＳＲＡＭの構成例を示す。図１４に示すＤＯＳＲＡＭ１４００は、コントローラ１４０５、行回路１４１０、列回路１４１５、メモリセル及びセンスアンプアレイ１４２０（以下、「ＭＣ−ＳＡアレイ１４２０」と呼ぶ。）を有する。 <<
FIG. 14 shows a configuration example of the DOSRAM. A
行回路１４１０は、デコーダ１４１１、ワード線ドライバ回路１４１２、列セレクタ１４１３、センスアンプドライバ回路１４１４を有する。列回路１４１５は、グローバルセンスアンプアレイ１４１６、入出力回路１４１７を有する。グローバルセンスアンプアレイ１４１６は、複数のグローバルセンスアンプ１４４７を有する。ＭＣ−ＳＡアレイ１４２０は、メモリセルアレイ１４２２、センスアンプアレイ１４２３、グローバルビット線ＧＢＬＬ、グローバルビット線ＧＢＬＲを有する。
The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and a global bit line GBLR.
（ＭＣ−ＳＡアレイ１４２０）
ＭＣ−ＳＡアレイ１４２０は、メモリセルアレイ１４２２をセンスアンプアレイ１４２３上に積層した積層構造を有する。グローバルビット線ＧＢＬＬ、グローバルビット線ＧＢＬＲは、メモリセルアレイ１４２２上に積層されている。ＤＯＳＲＡＭ１４００では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。 (MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. The global bit line GBLL and the global bit line GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
ＭＣ−ＳＡアレイ１４２０は、メモリセルアレイ１４２２をセンスアンプアレイ１４２３上に積層した積層構造を有する。グローバルビット線ＧＢＬＬ、グローバルビット線ＧＢＬＲは、メモリセルアレイ１４２２上に積層されている。ＤＯＳＲＡＭ１４００では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。 (MC-SA array 1420)
The MC-
メモリセルアレイ１４２２は、Ｎ個（Ｎは２以上の整数）のローカルメモリセルアレイ１４２５＜０＞乃至ローカルメモリセルアレイ１４２５＜Ｎ−１＞を有する。図１５（Ａ）に、ローカルメモリセルアレイ１４２５の構成例を示す。ローカルメモリセルアレイ１４２５は、複数のメモリセル１４４５、複数のワード線ＷＬ、複数のビット線ＢＬＬ、複数のビット線ＢＬＲを有する。図１５（Ａ）の例では、ローカルメモリセルアレイ１４２５の構造はオープンビット線型であるが、フォールデッドビット線型であってもよい。
The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to 1425 <N-1>. FIG. 15A illustrates a configuration example of the local memory cell array 1425. The local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a plurality of bit lines BLR. In the example of FIG. 15A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
図１５（Ｂ）に、メモリセル１４４５の回路構成例を示す。メモリセル１４４５は、トランジスタＭＷ１、容量素子ＣＳ１、端子Ｂ１を有する。トランジスタＭＷ１は、容量素子ＣＳ１の充放電を制御する機能を有する。トランジスタＭＷ１のゲートはワード線に電気的に接続され、第１端子はビット線に電気的に接続され、第２端子は容量素子ＣＳ１の第１端子に電気的に接続されている。容量素子ＣＳ１の第２端子は、端子Ｂ１に電気的に接続されている。端子Ｂ１には、定電位（例えば、低電源電位）が入力される。
FIG. 15B shows a circuit configuration example of the memory cell 1445. The memory cell 1445 includes a transistor MW1, a capacitor CS1, and a terminal B1. The transistor MW1 has a function of controlling charging / discharging of the capacitor CS1. The gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitor CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B1. A constant potential (for example, a low power supply potential) is input to the terminal B1.
トランジスタＭＷ１は、ボトムゲートを有するトランジスタであってもよい。トランジスタＭＷ１が、ボトムゲートを有するトランジスタである場合、例えば、トランジスタＭＷ１のボトムゲートを、トランジスタＭＷ１のゲート、ソース、又はドレインに電気的に接続する構成としてもよい。
The transistor MW1 may be a transistor having a bottom gate. In the case where the transistor MW1 is a transistor having a bottom gate, for example, the bottom gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1.
センスアンプアレイ１４２３は、Ｎ個のローカルセンスアンプアレイ１４２６＜０＞乃至ローカルセンスアンプアレイ１４２６＜Ｎ−１＞を有する。ローカルセンスアンプアレイ１４２６は、１のスイッチアレイ１４４４、複数のセンスアンプ１４４６を有する。センスアンプ１４４６には、ビット線対が電気的に接続されている。センスアンプ１４４６は、ビット線対をプリチャージする機能、ビット線対の電位差を増幅する機能、この電位差を保持する機能を有する。スイッチアレイ１４４４は、ビット線対を選択し、選択したビット線対とグローバルビット線対との間を導通状態にする機能を有する。
The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> to 1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference between the bit line pair, and a function of holding this potential difference. The switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
ここで、ビット線対とは、センスアンプによって、同時に比較される２本のビット線のことをいう。グローバルビット線対とは、グローバルセンスアンプによって、同時に比較される２本のグローバルビット線のことをいう。ビット線対を一対のビット線と呼ぶことができ、グローバルビット線対を一対のグローバルビット線と呼ぶことができる。ここでは、ビット線ＢＬＬとビット線ＢＬＲが１組のビット線対を成す。グローバルビット線ＧＢＬＬとグローバルビット線ＧＢＬＲとが１組のグローバルビット線対をなす。以下、ビット線対（ＢＬＬ，ＢＬＲ）、グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）とも表す。
Here, the bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
（コントローラ１４０５）
コントローラ１４０５は、ＤＯＳＲＡＭ１４００の動作全般を制御する機能を有する。コントローラ１４０５は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路１４１０、列回路１４１５の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。 (Controller 1405)
Thecontroller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.
コントローラ１４０５は、ＤＯＳＲＡＭ１４００の動作全般を制御する機能を有する。コントローラ１４０５は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路１４１０、列回路１４１５の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。 (Controller 1405)
The
（行回路１４１０）
行回路１４１０は、ＭＣ−ＳＡアレイ１４２０を駆動する機能を有する。デコーダ１４１１は、アドレス信号をデコードする機能を有する。ワード線ドライバ回路１４１２は、アクセス対象行のワード線ＷＬを選択する選択信号を生成する。 (Row circuit 1410)
Therow circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
行回路１４１０は、ＭＣ−ＳＡアレイ１４２０を駆動する機能を有する。デコーダ１４１１は、アドレス信号をデコードする機能を有する。ワード線ドライバ回路１４１２は、アクセス対象行のワード線ＷＬを選択する選択信号を生成する。 (Row circuit 1410)
The
列セレクタ１４１３、センスアンプドライバ回路１４１４は、センスアンプアレイ１４２３を駆動するための回路である。列セレクタ１４１３は、アクセス対象列のビット線を選択するための選択信号を生成する機能を有する。列セレクタ１４１３の選択信号によって、各ローカルセンスアンプアレイ１４２６のスイッチアレイ１４４４が制御される。センスアンプドライバ回路１４１４の制御信号によって、複数のローカルセンスアンプアレイ１４２６は独立して駆動される。
The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413. The plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
（列回路１４１５）
列回路１４１５は、データ信号ＷＤＡ［３１：０］の入力を制御する機能、データ信号ＲＤＡ［３１：０］の出力を制御する機能を有する。データ信号ＷＤＡ［３１：０］は書き込みデータ信号であり、データ信号ＲＤＡ［３１：０］は読み出しデータ信号である。 (Column circuit 1415)
Thecolumn circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.
列回路１４１５は、データ信号ＷＤＡ［３１：０］の入力を制御する機能、データ信号ＲＤＡ［３１：０］の出力を制御する機能を有する。データ信号ＷＤＡ［３１：０］は書き込みデータ信号であり、データ信号ＲＤＡ［３１：０］は読み出しデータ信号である。 (Column circuit 1415)
The
グローバルセンスアンプ１４４７は、グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）に電気的に接続されている。グローバルセンスアンプ１４４７は、グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）間の電位差を増幅する機能、この電位差を保持する機能を有する。グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）へのデータの書き込み、及び読み出しは、入出力回路１４１７によって行われる。
The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Data is written to and read from the global bit line pair (GBLL, GBLR) by an input / output circuit 1417.
ＤＯＳＲＡＭ１４００の書き込み動作の概要を説明する。入出力回路１４１７によって、データがグローバルビット線対に書き込まれる。グローバルビット線対のデータは、グローバルセンスアンプアレイ１４１６によって保持される。アドレスが指定するローカルセンスアンプアレイ１４２６のスイッチアレイ１４４４によって、グローバルビット線対のデータが、対象列のビット線対に書き込まれる。ローカルセンスアンプアレイ１４２６は、書き込まれたデータを増幅し、保持する。指定されたローカルメモリセルアレイ１４２５において、行回路１４１０によって、対象行のワード線ＷＬが選択され、選択行のメモリセル１４４５にローカルセンスアンプアレイ１４２６の保持データが書き込まれる。
An outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the specified local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
ＤＯＳＲＡＭ１４００の読み出し動作の概要を説明する。アドレス信号によって、ローカルメモリセルアレイ１４２５の１行が指定される。指定されたローカルメモリセルアレイ１４２５において、対象行のワード線ＷＬが選択状態となり、メモリセル１４４５のデータがビット線に書き込まれる。ローカルセンスアンプアレイ１４２６によって、各列のビット線対の電位差がデータとして検出され、かつ保持される。スイッチアレイ１４４４によって、ローカルセンスアンプアレイ１４２６の保持データのうち、アドレスが指定する列のデータが、グローバルビット線対に書き込まれる。グローバルセンスアンプアレイ１４１６は、グローバルビット線対のデータを検出し、保持する。グローバルセンスアンプアレイ１４１６の保持データは入出力回路１４１７に出力される。以上で、読み出し動作が完了する。
An outline of the reading operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data. The switch array 1444 writes the data in the column specified by the address among the data held in the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.
容量素子ＣＳ１の充放電によってデータを書き換えるため、ＤＯＳＲＡＭ１４００は、原理的には書き換え回数に制約はなく、かつ、低エネルギーで、データの書き込み及び読み出しが可能である。また、メモリセル１４４５の回路構成が単純であるため、大容量化が容易である。
In order to rewrite data by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of rewrites in principle, and can write and read data with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
トランジスタＭＷ１は、ＯＳトランジスタである。ＯＳトランジスタはオフ電流が極めて小さいため、容量素子ＣＳ１から電荷がリークすることを抑えることができる。したがって、ＤＯＳＲＡＭ１４００の保持時間は、Ｓｉトランジスタを用いたＤＲＡＭに比べて非常に長い。したがって、リフレッシュの頻度を低減できるため、リフレッシュ動作に要する電力を削減できる。そのため、ＤＯＳＲＡＭ１４００をフレームメモリとして用いることで、表示コントローラＩＣ、及びソースドライバＩＣの消費電力を削減することができる。
The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is much longer than that of a DRAM using a Si transistor. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the power consumption of the display controller IC and the source driver IC can be reduced by using the DOSRAM 1400 as a frame memory.
ＭＣ−ＳＡアレイ１４２０が積層構造であることよって、ローカルセンスアンプアレイ１４２６の長さと同程度の長さにビット線を短くすることができる。ビット線を短くすることで、ビット線容量が小さくなり、メモリセル１４４５の保持容量を低減することができる。また、ローカルセンスアンプアレイ１４２６にスイッチアレイ１４４４を設けることで、長いビット線の本数を減らすことができる。以上の理由から、ＤＯＳＲＡＭ１４００のアクセス時に駆動する負荷が低減されるので、表示コントローラＩＣ、及びソースドライバＩＣの消費エネルギーを低減できる。
Since the MC-SA array 1420 has a laminated structure, the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reason, the load that is driven when accessing the DOSRAM 1400 is reduced, so that the energy consumption of the display controller IC and the source driver IC can be reduced.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。
The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態５）
本実施の形態では、本発明の一態様に係る、金属酸化物をチャネル形成領域に用いたトランジスタ（ＯＳトランジスタ）が適用されている半導体装置の一例として、ＦＰＧＡ（フィールドプログラマブルゲートアレイ）について説明する。本実施の形態のＦＰＧＡは、コンフィギュレーションメモリ、及びレジスタにＯＳメモリが適用されている。ここでは、このようなＦＰＧＡを「ＯＳ−ＦＰＧＡ」と呼ぶ。 (Embodiment 5)
In this embodiment, a field programmable gate array (FPGA) is described as an example of a semiconductor device to which a transistor using a metal oxide in a channel formation region (OS transistor) according to one embodiment of the present invention is applied. . In the FPGA of this embodiment, an OS memory is applied to the configuration memory and the register. Here, such FPGA is referred to as “OS-FPGA”.
本実施の形態では、本発明の一態様に係る、金属酸化物をチャネル形成領域に用いたトランジスタ（ＯＳトランジスタ）が適用されている半導体装置の一例として、ＦＰＧＡ（フィールドプログラマブルゲートアレイ）について説明する。本実施の形態のＦＰＧＡは、コンフィギュレーションメモリ、及びレジスタにＯＳメモリが適用されている。ここでは、このようなＦＰＧＡを「ＯＳ−ＦＰＧＡ」と呼ぶ。 (Embodiment 5)
In this embodiment, a field programmable gate array (FPGA) is described as an example of a semiconductor device to which a transistor using a metal oxide in a channel formation region (OS transistor) according to one embodiment of the present invention is applied. . In the FPGA of this embodiment, an OS memory is applied to the configuration memory and the register. Here, such FPGA is referred to as “OS-FPGA”.
ＯＳメモリは、少なくとも容量素子と、容量素子の充放電を制御するＯＳトランジスタを有するメモリである。ＯＳトランジスタが極小オフ電流のトランジスタであるので、ＯＳメモリは優れた保持特性を有し、不揮発性メモリとして機能させることができる。
The OS memory is a memory having at least a capacitive element and an OS transistor that controls charging / discharging of the capacitive element. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
図１６（Ａ）に、ＯＳ−ＦＰＧＡの構成例を示す。図１６（Ａ）に示すＯＳ−ＦＰＧＡ３１１０は、マルチコンテキスト構造によるコンテキスト切り替えとＰＬＥ毎の細粒度パワーゲーティングを実行するＮＯＦＦ（ノーマリオフ）コンピューティングが可能である。ＯＳ−ＦＰＧＡ３１１０は、コントローラ（Ｃｏｎｔｒｏｌｌｅｒ）３１１１、ワードドライバ（Ｗｏｒｄ ｄｒｉｖｅｒ）３１１２、データドライバ（Ｄａｔａ ｄｒｉｖｅｒ）３１１３、プログラマブルエリア（Ｐｒｏｇｒａｍｍａｂｌｅ ａｒｅａ）３１１５を有する。
FIG. 16A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 16A is capable of NOFF (normally off) computing that performs context switching by a multi-context structure and fine-grain power gating for each PLE. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.
プログラマブルエリア３１１５は、２個の入出力ブロック（ＩＯＢ）３１１７、コア（Ｃｏｒｅ）３１１９を有する。ＩＯＢ３１１７は、複数のプログラマブル入出力回路を有する。コア３１１９は、複数のロジックアレイブロック（ＬＡＢ）３１２０、複数のスイッチアレイブロック（ＳＡＢ）３１３０を有する。ＬＡＢ３１２０は、複数のＰＬＥ３１２１を有する。図１６（Ｂ）には、ＬＡＢ３１２０を５個のＰＬＥ３１２１で構成する例を示す。図１６（Ｃ）に示すように、ＳＡＢ３１３０は、アレイ状に配列された複数のスイッチブロック（ＳＢ）３１３１を有する。ＬＡＢ３１２０は自身の入力端子と、ＳＡＢ３１３０を介して４（上下左右）方向のＬＡＢ３１２０に接続される。
The programmable area 3115 has two input / output blocks (IOB) 3117 and a core (Core) 3119. The IOB 3117 has a plurality of programmable input / output circuits. The core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. The LAB 3120 includes a plurality of PLE 3121s. FIG. 16B shows an example in which the LAB 3120 is composed of five PLE 3121s. As shown in FIG. 16C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.
図１７（Ａ）乃至図１７（Ｃ）を参照して、ＳＢ３１３１について説明する。図１７（Ａ）に示すＳＢ３１３１には、ｄａｔａ、ｄａｔａｂ、信号ｃｏｎｔｅｘｔ［１：０］、ｗｏｒｄ［１：０］が入力される。ｄａｔａ、ｄａｔａｂはコンフィギュレーションデータであり、ｄａｔａとｄａｔａｂは論理が相補的な関係にある。ＯＳ−ＦＰＧＡ３１１０のコンテキスト数は２であり、信号ｃｏｎｔｅｘｔ［１：０］はコンテキスト選択信号である。信号ｗｏｒｄ［１：０］はワード線選択信号であり、信号ｗｏｒｄ［１：０］が入力される配線がそれぞれワード線である。
SB3131 will be described with reference to FIGS. 17 (A) to 17 (C). Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.
ＳＢ３１３１は、ＰＲＳ（プログラマブルルーティングスイッチ）３１３３［０］、ＰＲＳ３１３３［１］を有する。ＰＲＳ３１３３［０］、ＰＲＳ３１３３［１］は、相補データを格納できるコンフィギュレーションメモリ（ＣＭ）を有する。なお、ＰＲＳ３１３３［０］とＰＲＳ３１３３［１］とを区別しない場合、ＰＲＳ３１３３と呼ぶ。他の要素についても同様である。
The SB 3131 includes a PRS (programmable routing switch) 3133 [0] and a PRS 3133 [1]. The PRS 3133 [0] and the PRS 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.
図１７（Ｂ）に、ＰＲＳ３１３３［０］の回路構成例を示す。ＰＲＳ３１３３［０］とＰＲＳ３１３３［１］とは、同じ回路構成を有する。ＰＲＳ３１３３［０］とＰＲＳ３１３３［１］とは、入力されるコンテキスト選択信号、ワード線選択信号が異なる。信号ｃｏｎｔｅｘｔ［０］、信号ｗｏｒｄ［０］はＰＲＳ３１３３［０］に入力され、信号ｃｏｎｔｅｘｔ［１］、信号ｗｏｒｄ［１］はＰＲＳ３１３３［１］に入力される。例えば、ＳＢ３１３１において、信号ｃｏｎｔｅｘｔ［０］が“Ｈ”になることで、ＰＲＳ３１３３［０］がアクティブになる。
FIG. 17B illustrates a circuit configuration example of PRS3133 [0]. PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration. PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal. The signal context [0] and the signal word [0] are input to the PRS 3133 [0], and the signal context [1] and the signal word [1] are input to the PRS 3133 [1]. For example, in the SB 3131, when the signal context [0] becomes “H”, the PRS 3133 [0] becomes active.
ＰＲＳ３１３３［０］は、ＣＭ３１３５、ＳｉトランジスタＭ３１を有する。ＳｉトランジスタＭ３１は、ＣＭ３１３５により制御されるパストランジスタである。ＣＭ３１３５は、メモリ回路３１３７、メモリ回路３１３７Ｂを有する。メモリ回路３１３７、メモリ回路３１３７Ｂは同じ回路構成である。メモリ回路３１３７は、容量素子Ｃ３１、ＯＳトランジスタＭＯ３１、ＯＳトランジスタＭＯ３２を有する。メモリ回路３１３７Ｂは、容量素子ＣＢ３１、ＯＳトランジスタＭＯＢ３１、ＯＳトランジスタＭＯＢ３２を有する。
PRS3133 [0] has CM3135 and Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM 3135. The CM 3135 includes a memory circuit 3137 and a memory circuit 3137B. The memory circuit 3137 and the memory circuit 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit 3137B includes a capacitor CB31, an OS transistor MOB31, and an OS transistor MOB32.
ＯＳトランジスタＭＯ３１、ＯＳトランジスタＭＯ３２、ＯＳトランジスタＭＯＢ３１、及びＯＳトランジスタＭＯＢ３２はボトムゲートを有していてもよい。例えば、ＯＳトランジスタＭＯ３１、ＯＳトランジスタＭＯ３２、ＯＳトランジスタＭＯＢ３１、及びＯＳトランジスタＭＯＢ３２がボトムゲートを有している場合、これらボトムゲートはそれぞれ固定電位を供給する電源線と電気的に接続されていてもよい。
The OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 may have a bottom gate. For example, in the case where the OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 have bottom gates, the bottom gates may be electrically connected to power supply lines that supply a fixed potential. .
ＳｉトランジスタＭ３１のゲートがノードＮ３１であり、ＯＳトランジスタＭＯ３２のゲートがノードＮ３２であり、ＯＳトランジスタＭＯＢ３２のゲートがノードＮＢ３２である。ノードＮ３２、ノードＮＢ３２はＣＭ３１３５の電荷保持ノードである。ＯＳトランジスタＭＯ３２は、ノードＮ３１と信号ｃｏｎｔｅｘｔ［０］用の信号線との間の導通状態を制御する。ＯＳトランジスタＭＯＢ３２は、ノードＮ３１と低電位電源線ＶＳＳとの間の導通状態を制御する。
The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. The nodes N32 and NB32 are charge holding nodes of the CM 3135. The OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls the conduction state between the node N31 and the low potential power supply line VSS.
メモリ回路３１３７、メモリ回路３１３７Ｂが保持するデータの論理は相補的な関係にある。したがって、ＯＳトランジスタＭＯ３２又はＯＳトランジスタＭＯＢ３２のいずれか一方が導通する。
The logic of data held in the memory circuit 3137 and the memory circuit 3137B has a complementary relationship. Therefore, either the OS transistor MO32 or the OS transistor MOB32 becomes conductive.
図１７（Ｃ）を参照して、ＰＲＳ３１３３［０］の動作例を説明する。ＰＲＳ３１３３［０］にコンフィギュレーションデータが既に書き込まれており、ＰＲＳ３１３３［０］のノードＮ３２は“Ｈ”であり、ノードＮＢ３２は“Ｌ”である。
An example of the operation of PRS 3133 [0] will be described with reference to FIG. Configuration data has already been written in the PRS 3133 [0], the node N32 of the PRS 3133 [0] is “H”, and the node NB32 is “L”.
信号ｃｏｎｔｅｘｔ［０］が“Ｌ”である間は、ＰＲＳ３１３３［０］は非アクティブである。この期間に、ＰＲＳ３１３３［０］の入力端子が“Ｈ”に遷移しても、ＳｉトランジスタＭ３１のゲートは“Ｌ”が維持され、ＰＲＳ３１３３［０］の出力端子も“Ｌ”が維持される。
While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.
信号ｃｏｎｔｅｘｔ［０］が“Ｈ”である間は、ＰＲＳ３１３３［０］はアクティブである。信号ｃｏｎｔｅｘｔ［０］が“Ｈ”に遷移すると、ＣＭ３１３５が記憶するコンフィギュレーションデータによって、ＳｉトランジスタＭ３１のゲートは“Ｈ”に遷移する。
While the signal context [0] is “H”, the PRS 3133 [0] is active. When the signal context [0] changes to “H”, the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
ＰＲＳ３１３３［０］がアクティブである期間に、入力端子が“Ｈ”に遷移すると、メモリ回路３１３７のＯＳトランジスタＭＯ３２がソースフォロアであるために、ブースティング（ｂｏｏｓｔｉｎｇ）によってＳｉトランジスタＭ３１のゲート電位は上昇する。その結果、メモリ回路３１３７のＯＳトランジスタＭＯ３２は駆動能力を失い、ＳｉトランジスタＭ３１のゲートは浮遊状態となる。
When the input terminal changes to “H” during a period in which PRS 3133 [0] is active, the OS transistor MO32 of the memory circuit 3137 is a source follower, and therefore the gate potential of the Si transistor M31 is increased by boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
マルチコンテキスト機能を備えるＰＲＳ３１３３において、ＣＭ３１３５はマルチプレクサの機能を併せ持つ。
In the PRS 3133 having a multi-context function, the CM 3135 also has a multiplexer function.
図１８に、ＰＬＥ３１２１の構成例を示す。ＰＬＥ３１２１は、ＬＵＴ（ルックアップテーブル）ブロック３１２３、レジスタブロック３１２４、セレクタ３１２５、ＣＭ３１２６を有する。ＬＵＴブロック（ＬＵＴ ｂｌｏｃｋ）３１２３は、入力ｉｎＡ−ｉｎＤに従ってデータを選択し、出力する構成である。セレクタ３１２５は、ＣＭ３１２６が格納するコンフィギュレーションデータに従って、ＬＵＴブロック３１２３の出力又はレジスタブロック３１２４の出力を選択する。
FIG. 18 shows a configuration example of the PLE 3121. The PLE 3121 includes an LUT (look-up table) block 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block (LUT block) 3123 is configured to select and output data according to input inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.
ＰＬＥ３１２１は、パワースイッチ３１２７を介して電位ＶＤＤ用の電源線に電気的に接続されている。パワースイッチ３１２７のオンオフは、ＣＭ３１２８が格納するコンフィギュレーションデータによって設定される。各ＰＬＥ３１２１にパワースイッチ３１２７を設けることで、細粒度パワーゲーティングが可能である。細粒度パワーゲーティング機能により、コンテキストの切り替え後に使用されないＰＬＥ３１２１をパワーゲーティングすることができるので、待機電力を効果的に低減できる。
The PLE 3121 is electrically connected to the power line for the potential VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
ＮＯＦＦコンピューティングを実現するため、レジスタブロック３１２４は、不揮発性レジスタで構成される。ＰＬＥ３１２１内の不揮発性レジスタは、ＯＳメモリを備えるフリップフロップ（以下「ＯＳ−ＦＦ」と呼ぶ。）である。
In order to realize NOFF computing, the register block 3124 is composed of a nonvolatile register. The nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as “OS-FF”) including an OS memory.
レジスタブロック３１２４は、ＯＳ−ＦＦ３１４０［１］、ＯＳ−ＦＦ３１４０［２］を有する。信号ｕｓｅｒ＿ｒｅｓ、信号ｌｏａｄ、信号ｓｔｏｒｅがＯＳ−ＦＦ３１４０［１］、ＯＳ−ＦＦ３１４０［２］に入力される。クロック信号ＣＬＫ１はＯＳ−ＦＦ３１４０［１］に入力され、クロック信号ＣＬＫ２はＯＳ−ＦＦ３１４０［２］に入力される。図１９（Ａ）に、ＯＳ−ＦＦ３１４０の構成例を示す。
The register block 3124 includes OS-FF 3140 [1] and OS-FF 3140 [2]. The signal user_res, the signal load, and the signal store are input to the OS-FF 3140 [1] and the OS-FF 3140 [2]. The clock signal CLK1 is input to the OS-FF 3140 [1], and the clock signal CLK2 is input to the OS-FF 3140 [2]. FIG. 19A illustrates a configuration example of the OS-FF 3140.
ＯＳ−ＦＦ３１４０は、ＦＦ３１４１、シャドウレジスタ３１４２を有する。ＦＦ３１４１は、ノードＣＫ、ノードＲ、ノードＤ、ノードＱ、及びノードＱＢを有する。ノードＣＫにはクロック信号が入力される。ノードＲには信号ｕｓｅｒ＿ｒｅｓが入力される。信号ｕｓｅｒ＿ｒｅｓはリセット信号である。ノードＤはデータ入力ノードであり、ノードＱはデータ出力ノードである。ノードＱとノードＱＢとは、論理が相補関係にある。
The OS-FF 3140 includes an FF 3141 and a shadow register 3142. The FF 3141 includes a node CK, a node R, a node D, a node Q, and a node QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. The node Q and the node QB have a complementary logic relationship.
シャドウレジスタ３１４２は、ＦＦ３１４１のバックアップ回路として機能する。シャドウレジスタ３１４２は、信号ｓｔｏｒｅに従い、ノードＱ、ノードＱＢのデータをそれぞれバックアップし、また、信号ｌｏａｄに従い、バックアップしたデータをノードＱ、ノードＱＢに書き戻す。
The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
シャドウレジスタ３１４２は、インバータ回路３１８８、インバータ回路３１８９、ＳｉトランジスタＭ３７、ＳｉトランジスタＭＢ３７、メモリ回路３１４３、メモリ回路３１４３Ｂを有する。メモリ回路３１４３、メモリ回路３１４３Ｂは、ＰＲＳ３１３３のメモリ回路３１３７と同じ回路構成である。メモリ回路３１４３は、容量素子Ｃ３６、ＯＳトランジスタＭＯ３５、ＯＳトランジスタＭＯ３６を有する。メモリ回路３１４３Ｂは、容量素子ＣＢ３６、ＯＳトランジスタＭＯＢ３５、ＯＳトランジスタＭＯＢ３６を有する。ノードＮ３６、ノードＮＢ３６は、ＯＳトランジスタＭＯ３６、ＯＳトランジスタＭＯＢ３６のゲートであり、それぞれ電荷保持ノードである。ノードＮ３７、ノードＮＢ３７は、ＳｉトランジスタＭ３７、ＳｉトランジスタＭＢ３７のゲートである。
The shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, an Si transistor M37, an Si transistor MB37, a memory circuit 3143, and a memory circuit 3143B. The memory circuit 3143 and the memory circuit 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. The node N36 and the node NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes. The nodes N37 and NB37 are the gates of the Si transistor M37 and the Si transistor MB37.
ＯＳトランジスタＭＯ３５、ＯＳトランジスタＭＯ３６、ＯＳトランジスタＭＯＢ３５、及びＯＳトランジスタＭＯＢ３６はボトムゲートを有していてもよい。例えば、ＯＳトランジスタＭＯ３５、ＯＳトランジスタＭＯ３６、ＯＳトランジスタＭＯＢ３５、及びＯＳトランジスタＭＯＢ３６がボトムゲートを有している場合、これらボトムゲートはそれぞれ固定電位を供給する電源線と電気的に接続されていてもよい。
The OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 may have a bottom gate. For example, in the case where the OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 have bottom gates, the bottom gates may be electrically connected to power supply lines that supply fixed potentials. .
図１９（Ｂ）を参照して、ＯＳ−ＦＦ３１４０の動作方法例を説明する。
An example of an operating method of the OS-FF 3140 will be described with reference to FIG.
（バックアップ（Ｂａｃｋｕｐ））
“Ｈ”の信号ｓｔｏｒｅがＯＳ−ＦＦ３１４０に入力されると、シャドウレジスタ３１４２はＦＦ３１４１のデータをバックアップする。ノードＮ３６は、ノードＱのデータが書き込まれることで、“Ｌ”となり、ノードＮＢ３６は、ノードＱＢのデータが書き込まれることで、“Ｈ”となる。しかる後、パワーゲーティングが実行され、パワースイッチ３１２７をオフにする。ＦＦ３１４１のノードＱ、ノードＱＢのデータは消失するが、電源オフであっても、シャドウレジスタ３１４２はバックアップしたデータを保持する。 (Backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data in the FF 3141. The node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. The data of the node Q and the node QB of the FF 3141 is lost, but the shadow register 3142 holds the backed up data even when the power is turned off.
“Ｈ”の信号ｓｔｏｒｅがＯＳ−ＦＦ３１４０に入力されると、シャドウレジスタ３１４２はＦＦ３１４１のデータをバックアップする。ノードＮ３６は、ノードＱのデータが書き込まれることで、“Ｌ”となり、ノードＮＢ３６は、ノードＱＢのデータが書き込まれることで、“Ｈ”となる。しかる後、パワーゲーティングが実行され、パワースイッチ３１２７をオフにする。ＦＦ３１４１のノードＱ、ノードＱＢのデータは消失するが、電源オフであっても、シャドウレジスタ３１４２はバックアップしたデータを保持する。 (Backup)
When the “H” signal store is input to the OS-
（リカバリ（Ｒｅｃｏｖｅｒｙ））
パワースイッチ３１２７をオンにし、ＰＬＥ３１２１に電源を供給する。しかる後、“Ｈ”の信号ｌｏａｄがＯＳ−ＦＦ３１４０に入力されると、シャドウレジスタ３１４２はバックアップしているデータをＦＦ３１４１に書き戻す。ノードＮ３６は“Ｌ”であるので、ノードＮ３７は“Ｌ”が維持され、ノードＮＢ３６は“Ｈ”であるので、ノードＮＢ３７は“Ｈ”となる。よって、ノードＱは“Ｈ”になり、ノードＱＢは“Ｌ”になる。つまり、ＯＳ−ＦＦ３１４０はバックアップ動作時の状態に復帰する。 (Recovery)
Thepower switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.
パワースイッチ３１２７をオンにし、ＰＬＥ３１２１に電源を供給する。しかる後、“Ｈ”の信号ｌｏａｄがＯＳ−ＦＦ３１４０に入力されると、シャドウレジスタ３１４２はバックアップしているデータをＦＦ３１４１に書き戻す。ノードＮ３６は“Ｌ”であるので、ノードＮ３７は“Ｌ”が維持され、ノードＮＢ３６は“Ｈ”であるので、ノードＮＢ３７は“Ｈ”となる。よって、ノードＱは“Ｈ”になり、ノードＱＢは“Ｌ”になる。つまり、ＯＳ−ＦＦ３１４０はバックアップ動作時の状態に復帰する。 (Recovery)
The
細粒度パワーゲーティングと、ＯＳ−ＦＦ３１４０のバックアップ／リカバリ動作とを組み合わせることで、ＯＳ−ＦＰＧＡ３１１０の消費電力を効果的に低減できる。
By combining the fine-grain power gating and the backup / recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.
メモリ回路において発生し得るエラーとして、放射線の入射によるソフトエラーが挙げられる。ソフトエラーは、メモリやパッケージを構成する材料などから放出されるα線や、宇宙から大気に入射した一次宇宙線が大気中に存在する原子の原子核と核反応を起こすことにより発生する二次宇宙線中性子などがトランジスタに照射され、電子正孔対が生成されることにより、メモリに保持されたデータが反転するなどの誤作動が生じる現象である。ＯＳトランジスタを用いたＯＳメモリはソフトエラー耐性が高い。そのため、ＯＳメモリを搭載することで、信頼性の高いＯＳ−ＦＰＧＡ３１１０を提供することができる。
An error that can occur in a memory circuit is a soft error due to the incidence of radiation. A soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair. An OS memory using an OS transistor has high soft error resistance. Therefore, the OS-FPGA 3110 with high reliability can be provided by installing the OS memory.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。
The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態６）
本実施の形態においては、上述した記憶装置など、本発明の一態様に係る半導体装置を含むＣＰＵの一例について説明する。 (Embodiment 6)
In this embodiment, an example of a CPU including a semiconductor device according to one embodiment of the present invention, such as the memory device described above, will be described.
本実施の形態においては、上述した記憶装置など、本発明の一態様に係る半導体装置を含むＣＰＵの一例について説明する。 (Embodiment 6)
In this embodiment, an example of a CPU including a semiconductor device according to one embodiment of the present invention, such as the memory device described above, will be described.
＜ＣＰＵの構成＞
図２０に示す半導体装置５４００は、ＣＰＵコア５４０１、パワーマネージメントユニット５４２１、及び周辺回路５４２２を有する。パワーマネージメントユニット５４２１は、パワーコントローラ（Ｐｏｗｅｒ Ｃｏｎｔｒｏｌｌｅｒ）５４０２、及びパワースイッチ（Ｐｏｗｅｒ Ｓｗｉｔｃｈ）５４０３を有する。周辺回路５４２２は、キャッシュメモリを有するキャッシュ（Ｃａｃｈｅ）５４０４、バスインターフェース（ＢＵＳ Ｉ／Ｆ）５４０５、及びデバッグインターフェース（Ｄｅｂｕｇ Ｉ／Ｆ）５４０６を有する。ＣＰＵコア５４０１は、データバス５４２３、制御装置（Ｃｏｎｔｒｏｌ Ｕｎｉｔ）５４０７、ＰＣ（プログラムカウンタ）５４０８、パイプラインレジスタ（Ｐｉｐｅｌｉｎｅ Ｒｅｇｉｓｔｅｒ）５４０９、パイプラインレジスタ５４１０、ＡＬＵ（Ａｒｉｔｈｍｅｔｉｃ ｌｏｇｉｃ ｕｎｉｔ）５４１１、及びレジスタファイル（Ｒｅｇｉｓｔｅｒ Ｆｉｌｅ）５４１２を有する。ＣＰＵコア５４０１と、キャッシュ５４０４等の周辺回路５４２２とのデータのやり取りは、データバス５４２３を介して行われる。 <Configuration of CPU>
Asemiconductor device 5400 illustrated in FIG. 20 includes a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422. The power management unit 5421 includes a power controller (Power Controller) 5402 and a power switch (Power Switch) 5403. The peripheral circuit 5422 includes a cache 5404 having a cache memory, a bus interface (BUS I / F) 5405, and a debug interface (Debug I / F) 5406. The CPU core 5401 includes a data bus 5423, a control unit (Control Unit) 5407, a PC (Program Counter) 5408, a pipeline register (Pipeline Register) 5409, a pipeline register 5410, an ALU (Arithmetic logic unit) 5411, and a register file ( (Register File) 5412. Data exchange between the CPU core 5401 and the peripheral circuit 5422 such as the cache 5404 is performed via the data bus 5423.
図２０に示す半導体装置５４００は、ＣＰＵコア５４０１、パワーマネージメントユニット５４２１、及び周辺回路５４２２を有する。パワーマネージメントユニット５４２１は、パワーコントローラ（Ｐｏｗｅｒ Ｃｏｎｔｒｏｌｌｅｒ）５４０２、及びパワースイッチ（Ｐｏｗｅｒ Ｓｗｉｔｃｈ）５４０３を有する。周辺回路５４２２は、キャッシュメモリを有するキャッシュ（Ｃａｃｈｅ）５４０４、バスインターフェース（ＢＵＳ Ｉ／Ｆ）５４０５、及びデバッグインターフェース（Ｄｅｂｕｇ Ｉ／Ｆ）５４０６を有する。ＣＰＵコア５４０１は、データバス５４２３、制御装置（Ｃｏｎｔｒｏｌ Ｕｎｉｔ）５４０７、ＰＣ（プログラムカウンタ）５４０８、パイプラインレジスタ（Ｐｉｐｅｌｉｎｅ Ｒｅｇｉｓｔｅｒ）５４０９、パイプラインレジスタ５４１０、ＡＬＵ（Ａｒｉｔｈｍｅｔｉｃ ｌｏｇｉｃ ｕｎｉｔ）５４１１、及びレジスタファイル（Ｒｅｇｉｓｔｅｒ Ｆｉｌｅ）５４１２を有する。ＣＰＵコア５４０１と、キャッシュ５４０４等の周辺回路５４２２とのデータのやり取りは、データバス５４２３を介して行われる。 <Configuration of CPU>
A
半導体装置（セル）は、パワーコントローラ５４０２、制御装置５４０７をはじめ、多くの論理回路に適用することができる。特に、スタンダードセルを用いて構成することができる全ての論理回路に適用することができる。その結果、小型の半導体装置５４００を提供できる。また、消費電力を低減することが可能な半導体装置５４００を提供できる。また、動作速度を向上することが可能な半導体装置５４００を提供できる。また、電源電圧の変動を低減することが可能な半導体装置５４００を提供できる。
The semiconductor device (cell) can be applied to many logic circuits including the power controller 5402 and the control device 5407. In particular, the present invention can be applied to all logic circuits that can be configured using standard cells. As a result, a small semiconductor device 5400 can be provided. In addition, a semiconductor device 5400 that can reduce power consumption can be provided. In addition, a semiconductor device 5400 that can increase the operation speed can be provided. In addition, a semiconductor device 5400 that can reduce fluctuations in power supply voltage can be provided.
半導体装置（セル）に、ｐチャネル型Ｓｉトランジスタと、先の実施の形態に記載の金属酸化物（好ましくは、Ｉｎ、Ｇａ、及びＺｎを含む酸化物）をチャネル形成領域に含むトランジスタとを用い、当該半導体装置（セル）を半導体装置５４００に適用することで、小型の半導体装置５４００を提供できる。また、消費電力を低減することが可能な半導体装置５４００を提供できる。また、動作速度を向上することが可能な半導体装置５４００を提供できる。特に、Ｓｉトランジスタをｐチャネル型のみとすることで、製造コストを低く抑えることができる。
A p-channel Si transistor and a transistor including the metal oxide described in the above embodiment (preferably, an oxide containing In, Ga, and Zn) in a channel formation region are used for a semiconductor device (cell). By applying the semiconductor device (cell) to the semiconductor device 5400, a small semiconductor device 5400 can be provided. In addition, a semiconductor device 5400 that can reduce power consumption can be provided. In addition, a semiconductor device 5400 that can increase the operation speed can be provided. In particular, manufacturing costs can be reduced by using only p-channel Si transistors.
制御装置５４０７は、ＰＣ５４０８、パイプラインレジスタ５４０９、パイプラインレジスタ５４１０、ＡＬＵ５４１１、レジスタファイル５４１２、キャッシュ５４０４、バスインターフェース５４０５、デバッグインターフェース５４０６、及びパワーコントローラ５４０２の動作を統括的に制御することで、入力されたアプリケーションなどのプログラムに含まれる命令をデコードし、実行する機能を有する。
The control device 5407 controls the operations of the PC 5408, the pipeline register 5409, the pipeline register 5410, the ALU 5411, the register file 5412, the cache 5404, the bus interface 5405, the debug interface 5406, and the power controller 5402 so that the input is performed. A function of decoding and executing an instruction included in a program such as an executed application.
ＡＬＵ５４１１は、四則演算、論理演算などの各種演算処理を行う機能を有する。
The ALU 5411 has a function of performing various arithmetic processes such as four arithmetic operations and logical operations.
キャッシュ５４０４は、使用頻度の高いデータを一時的に記憶しておく機能を有する。ＰＣ５４０８は、次に実行する命令のアドレスを記憶する機能を有するレジスタである。なお、図２０では図示していないが、キャッシュ５４０４には、キャッシュメモリの動作を制御するキャッシュコントローラが設けられている。
The cache 5404 has a function of temporarily storing frequently used data. The PC 5408 is a register having a function of storing an address of an instruction to be executed next. Although not shown in FIG. 20, the cache 5404 is provided with a cache controller that controls the operation of the cache memory.
パイプラインレジスタ５４０９は、命令データを一時的に記憶する機能を有するレジスタである。
Pipeline register 5409 is a register having a function of temporarily storing instruction data.
レジスタファイル５４１２は、汎用レジスタを含む複数のレジスタを有しており、メインメモリから読み出されたデータ、又はＡＬＵ５４１１の演算処理の結果得られたデータなどを記憶することができる。
The register file 5412 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 5411, and the like.
パイプラインレジスタ５４１０は、ＡＬＵ５４１１の演算処理に利用するデータ、又はＡＬＵ５４１１の演算処理の結果、得られたデータなどを一時的に記憶する機能を有するレジスタである。
The pipeline register 5410 is a register having a function of temporarily storing data used for the arithmetic processing of the ALU 5411 or data obtained as a result of the arithmetic processing of the ALU 5411.
バスインターフェース５４０５は、半導体装置５４００と半導体装置５４００の外部にある各種装置との間におけるデータの経路としての機能を有する。デバッグインターフェース５４０６は、デバッグの制御を行うための命令を半導体装置５４００に入力するための信号の経路としての機能を有する。
The bus interface 5405 has a function as a data path between the semiconductor device 5400 and various devices outside the semiconductor device 5400. The debug interface 5406 has a function as a signal path for inputting an instruction for controlling debugging to the semiconductor device 5400.
パワースイッチ５４０３は、半導体装置５４００が有するパワーコントローラ５４０２以外の各種回路への、電源電圧の供給を制御する機能を有する。上記各種回路は、いくつかのパワードメインにそれぞれ属しており、同一のパワードメインに属する各種回路は、パワースイッチ５４０３によって電源電圧の供給の有無が制御される。また、パワーコントローラ５４０２は、パワースイッチ５４０３の動作を制御する機能を有する。
The power switch 5403 has a function of controlling supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400. The various circuits belong to several power domains, and the power switches 5403 control whether the various circuits belonging to the same power domain are supplied with a power supply voltage. The power controller 5402 has a function of controlling the operation of the power switch 5403.
上記構成を有する半導体装置５４００は、パワーゲーティングを行うことが可能である。パワーゲーティングの動作の流れについて、一例を挙げて説明する。
The semiconductor device 5400 having the above structure can perform power gating. The flow of power gating operation will be described with an example.
まず、ＣＰＵコア５４０１が、電源電圧の供給を停止するタイミングを、パワーコントローラ５４０２のレジスタに設定する。次いで、ＣＰＵコア５４０１からパワーコントローラ５４０２へ、パワーゲーティングを開始する旨の命令を送る。次いで、半導体装置５４００内に含まれる各種レジスタとキャッシュ５４０４が、データの退避を開始する。次いで、半導体装置５４００が有するパワーコントローラ５４０２以外の各種回路への電源電圧の供給が、パワースイッチ５４０３により停止される。次いで、割り込み信号がパワーコントローラ５４０２に入力されることで、半導体装置５４００が有する各種回路への電源電圧の供給が開始される。なお、パワーコントローラ５４０２にカウンタを設けておき、電源電圧の供給が開始されるタイミングを、割り込み信号の入力によらずに、当該カウンタを用いて決めるようにしてもよい。次いで、各種レジスタとキャッシュ５４０４が、データの復帰を開始する。次いで、制御装置５４０７における命令の実行が再開される。
First, the CPU core 5401 sets the timing of stopping the supply of the power supply voltage in the register of the power controller 5402. Next, an instruction to start power gating is sent from the CPU core 5401 to the power controller 5402. Next, various registers and the cache 5404 included in the semiconductor device 5400 start data saving. Next, supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 is stopped by the power switch 5403. Next, when an interrupt signal is input to the power controller 5402, supply of power supply voltage to various circuits included in the semiconductor device 5400 is started. Note that a counter may be provided in the power controller 5402 so that the timing at which the supply of the power supply voltage is started is determined using the counter regardless of the input of the interrupt signal. Next, the various registers and the cache 5404 start data restoration. Next, the execution of the instruction in the control device 5407 is resumed.
このようなパワーゲーティングは、プロセッサ全体、又はプロセッサを構成する一つ、若しくは複数の論理回路において行うことができる。また、短い時間でも電源の供給を停止することができる。このため、空間的に、あるいは時間的に細かい粒度で消費電力の削減を行うことができる。
Such power gating can be performed in the entire processor or in one or a plurality of logic circuits constituting the processor. Further, power supply can be stopped even in a short time. For this reason, power consumption can be reduced with fine granularity spatially or temporally.
パワーゲーティングを行う場合、ＣＰＵコア５４０１や周辺回路５４２２が保持する情報を短期間に退避できることが好ましい。そうすることで、短期間に電源のオンオフが可能となり、省電力の効果が大きくなる。
When performing power gating, it is preferable that information held by the CPU core 5401 and the peripheral circuit 5422 can be saved in a short time. By doing so, the power can be turned on and off in a short time, and the power saving effect is increased.
ＣＰＵコア５４０１や周辺回路５４２２が保持する情報を短期間に退避するためには、フリップフロップ回路がその回路内でデータ退避できることが好ましい（バックアップ可能なフリップフロップ回路と呼ぶ。）。また、ＳＲＡＭセルがセル内でデータ退避できることが好ましい（バックアップ可能なＳＲＡＭセルと呼ぶ。）。バックアップ可能なフリップフロップ回路やＳＲＡＭセルは、金属酸化物（好ましくは、Ｉｎ、Ｇａ、及びＺｎを含む酸化物）をチャネル形成領域に含むトランジスタを有することが好ましい。その結果、トランジスタが低いオフ電流を有することで、バックアップ可能なフリップフロップ回路やＳＲＡＭセルは、長期間電源供給無しでも情報を保持することができる。また、トランジスタが高速なスイッチング速度を有することで、バックアップ可能なフリップフロップ回路やＳＲＡＭセルは、短期間のデータ退避及び復帰が可能となる場合がある。
In order to save the information held by the CPU core 5401 and the peripheral circuit 5422 in a short time, it is preferable that the flip-flop circuit can save data in the circuit (referred to as a backupable flip-flop circuit). In addition, it is preferable that the SRAM cell can save data in the cell (referred to as a backupable SRAM cell). A flip-flop circuit or SRAM cell that can be backed up preferably includes a transistor including a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, when the transistor has a low off-state current, a flip-flop circuit or an SRAM cell that can be backed up can hold information without power supply for a long time. In addition, when a transistor has a high switching speed, a flip-flop circuit or an SRAM cell that can be backed up may be able to save and restore data in a short time.
バックアップ可能なフリップフロップ回路の例について、図２１を用いて説明する。
An example of a flip-flop circuit that can be backed up will be described with reference to FIG.
図２１に示す半導体装置５５００は、バックアップ可能なフリップフロップ回路の一例である。半導体装置５５００は、第１の記憶回路５５０１と、第２の記憶回路５５０２と、第３の記憶回路５５０３と、読み出し回路５５０４と、を有する。半導体装置５５００には、電位Ｖ１と電位Ｖ２の電位差が、電源電圧として供給される。電位Ｖ１と電位Ｖ２は一方がハイレベルであり、他方がローレベルである。以下、電位Ｖ１がローレベル、電位Ｖ２がハイレベルの場合を例に挙げて、半導体装置５５００の構成例について説明するものとする。
The semiconductor device 5500 shown in FIG. 21 is an example of a flip-flop circuit that can be backed up. The semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, a third memory circuit 5503, and a reading circuit 5504. A potential difference between the potential V1 and the potential V2 is supplied to the semiconductor device 5500 as a power supply voltage. One of the potential V1 and the potential V2 is at a high level, and the other is at a low level. Hereinafter, a configuration example of the semiconductor device 5500 will be described by using as an example the case where the potential V1 is low level and the potential V2 is high level.
第１の記憶回路５５０１は、半導体装置５５００に電源電圧が供給されている期間において、データを含む信号Ｄが入力されると、当該データを保持する機能を有する。そして、半導体装置５５００に電源電圧が供給されている期間において、第１の記憶回路５５０１からは、保持されているデータを含む信号Ｑが出力される。一方、第１の記憶回路５５０１は、半導体装置５５００に電源電圧が供給されていない期間においては、データを保持することができない。すなわち、第１の記憶回路５５０１は、揮発性の記憶回路と呼ぶことができる。
The first memory circuit 5501 has a function of holding data when a signal D including data is input in a period in which the power supply voltage is supplied to the semiconductor device 5500. In the period when the power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 5501 outputs a signal Q including retained data. On the other hand, the first memory circuit 5501 cannot hold data in a period in which the power supply voltage is not supplied to the semiconductor device 5500. That is, the first memory circuit 5501 can be called a volatile memory circuit.
第２の記憶回路５５０２は、第１の記憶回路５５０１に保持されているデータを読み込んで記憶する（あるいは退避する。）機能を有する。第３の記憶回路５５０３は、第２の記憶回路５５０２に保持されているデータを読み込んで記憶する（あるいは退避する。）機能を有する。読み出し回路５５０４は、第２の記憶回路５５０２又は第３の記憶回路５５０３に保持されたデータを読み出して第１の記憶回路５５０１に記憶する（あるいは復帰する。）機能を有する。
The second memory circuit 5502 has a function of reading and storing (or saving) data held in the first memory circuit 5501. The third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502. The reading circuit 5504 has a function of reading data stored in the second memory circuit 5502 or the third memory circuit 5503 and storing (or returning) the data in the first memory circuit 5501.
特に、第３の記憶回路５５０３は、半導体装置５５００に電源電圧が供給されてない期間においても、第２の記憶回路５５０２に保持されているデータを読み込んで記憶する（あるいは退避する。）機能を有する。
In particular, the third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502 even during a period in which the power supply voltage is not supplied to the semiconductor device 5500. Have.
図２１に示すように、第２の記憶回路５５０２は、トランジスタ５５１２と、容量素子５５１９とを有する。第３の記憶回路５５０３は、トランジスタ５５１３と、トランジスタ５５１５と、容量素子５５２０とを有する。読み出し回路５５０４は、トランジスタ５５１０と、トランジスタ５５１８と、トランジスタ５５０９と、トランジスタ５５１７と、を有する。
As shown in FIG. 21, the second memory circuit 5502 includes a transistor 5512 and a capacitor 5519. The third memory circuit 5503 includes a transistor 5513, a transistor 5515, and a capacitor 5520. The reading circuit 5504 includes a transistor 5510, a transistor 5518, a transistor 5509, and a transistor 5517.
トランジスタ５５１２は、第１の記憶回路５５０１に保持されているデータに応じた電荷を、容量素子５５１９に充放電する機能を有する。トランジスタ５５１２は、第１の記憶回路５５０１に保持されているデータに応じた電荷を容量素子５５１９に対して高速に充放電できることが好ましい。具体的には、トランジスタ５５１２が、結晶性を有するシリコン（好ましくは、多結晶シリコン、さらに好ましくは、単結晶シリコン）をチャネル形成領域に含むことが好ましい。
The transistor 5512 has a function of charging and discharging the capacitor 5519 with electric charge corresponding to data stored in the first memory circuit 5501. The transistor 5512 can charge and discharge the capacitor 5519 with charge according to data stored in the first memory circuit 5501 at high speed. Specifically, the transistor 5512 preferably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in a channel formation region.
トランジスタ５５１３は、容量素子５５１９に保持されている電荷に従って導通状態又は非導通状態が選択される。トランジスタ５５１５は、トランジスタ５５１３が導通状態であるときに、配線５５４４の電位に応じた電荷を容量素子５５２０に充放電する機能を有する。トランジスタ５５１５は、オフ電流が著しく小さいことが好ましい。具体的には、トランジスタ５５１５が、金属酸化物（好ましくは、Ｉｎ、Ｇａ、及びＺｎを含む酸化物）をチャネル形成領域に含むことが好ましい。
The transistor 5513 is selected to be in a conductive state or a non-conductive state in accordance with the charge held in the capacitor 5519. The transistor 5515 has a function of charging and discharging the capacitor 5520 with a charge corresponding to the potential of the wiring 5544 when the transistor 5513 is in a conductive state. The transistor 5515 preferably has extremely low off-state current. Specifically, the transistor 5515 preferably includes a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region.
各素子の接続関係を具体的に説明すると、トランジスタ５５１２のソース及びドレインの一方は、第１の記憶回路５５０１に接続されている。トランジスタ５５１２のソース及びドレインの他方は、容量素子５５１９の一方の電極、トランジスタ５５１３のゲート、及びトランジスタ５５１８のゲートに接続されている。容量素子５５１９の他方の電極は、配線５５４２に接続されている。トランジスタ５５１３のソース及びドレインの一方は、配線５５４４に接続されている。トランジスタ５５１３のソース及びドレインの他方は、トランジスタ５５１５のソース及びドレインの一方に接続されている。トランジスタ５５１５のソース及びドレインの他方は、容量素子５５２０の一方の電極、及びトランジスタ５５１０のゲートに接続されている。容量素子５５２０の他方の電極は、配線５５４３に接続されている。トランジスタ５５１０のソース及びドレインの一方は、配線５５４１に接続されている。トランジスタ５５１０のソース及びドレインの他方は、トランジスタ５５１８のソース及びドレインの一方に接続されている。トランジスタ５５１８のソース及びドレインの他方は、トランジスタ５５０９のソース及びドレインの一方に接続されている。トランジスタ５５０９のソース及びドレインの他方は、トランジスタ５５１７のソース及びドレインの一方、及び第１の記憶回路５５０１に接続されている。トランジスタ５５１７のソース及びドレインの他方は、配線５５４０に接続されている。また、図２１においては、トランジスタ５５０９のゲートは、トランジスタ５５１７のゲートと接続されているが、トランジスタ５５０９のゲートは、必ずしもトランジスタ５５１７のゲートと接続されていなくてもよい。
Specifically, the connection relationship between the elements is described. One of the source and the drain of the transistor 5512 is connected to the first memory circuit 5501. The other of the source and the drain of the transistor 5512 is connected to one electrode of the capacitor 5519, the gate of the transistor 5513, and the gate of the transistor 5518. The other electrode of the capacitor 5519 is connected to the wiring 5542. One of a source and a drain of the transistor 5513 is connected to the wiring 5544. The other of the source and the drain of the transistor 5513 is connected to one of the source and the drain of the transistor 5515. The other of the source and the drain of the transistor 5515 is connected to one electrode of the capacitor 5520 and the gate of the transistor 5510. The other electrode of the capacitor 5520 is connected to the wiring 5543. One of a source and a drain of the transistor 5510 is connected to the wiring 5541. The other of the source and the drain of the transistor 5510 is connected to one of the source and the drain of the transistor 5518. The other of the source and the drain of the transistor 5518 is connected to one of the source and the drain of the transistor 5509. The other of the source and the drain of the transistor 5509 is connected to one of the source and the drain of the transistor 5517 and the first memory circuit 5501. The other of the source and the drain of the transistor 5517 is connected to the wiring 5540. In FIG. 21, the gate of the transistor 5509 is connected to the gate of the transistor 5517; however, the gate of the transistor 5509 is not necessarily connected to the gate of the transistor 5517.
トランジスタ５５１５に、先の実施の形態で例示したトランジスタを適用することができる。トランジスタ５５１５のオフ電流が小さいために、半導体装置５５００は、長期間電源供給無しに情報を保持することができる。トランジスタ５５１５のスイッチング特性が良好であるために、半導体装置５５００は、高速のバックアップとリカバリを行うことができる。
The transistor illustrated in the above embodiment can be used as the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can hold information without supplying power for a long time. Since the switching characteristics of the transistor 5515 are favorable, the semiconductor device 5500 can perform high-speed backup and recovery.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。
The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態７）
本実施の形態では、本発明の一態様に係る半導体装置の一形態を、図２２及び図２３を用いて説明する。 (Embodiment 7)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
本実施の形態では、本発明の一態様に係る半導体装置の一形態を、図２２及び図２３を用いて説明する。 (Embodiment 7)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
＜半導体ウエハ、チップ＞
図２２（Ａ）は、ダイシング処理が行われる前の基板７１１の上面図を示している。基板７１１としては、例えば、半導体基板（「半導体ウエハ」ともいう。）を用いることができる。基板７１１上には、複数の回路領域７１２が設けられている。回路領域７１２には、本発明の一態様に係る半導体装置などを設けることができる。 <Semiconductor wafer, chip>
FIG. 22A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality ofcircuit regions 712 are provided on the substrate 711. The circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.
図２２（Ａ）は、ダイシング処理が行われる前の基板７１１の上面図を示している。基板７１１としては、例えば、半導体基板（「半導体ウエハ」ともいう。）を用いることができる。基板７１１上には、複数の回路領域７１２が設けられている。回路領域７１２には、本発明の一態様に係る半導体装置などを設けることができる。 <Semiconductor wafer, chip>
FIG. 22A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of
複数の回路領域７１２は、それぞれが分離領域７１３に囲まれている。分離領域７１３と重なる位置に分離線（「ダイシングライン」ともいう。）７１４が設定される。分離線７１４に沿って基板７１１を切断することで、回路領域７１２を含むチップ７１５を、基板７１１から切り出すことができる。図２２（Ｂ）に、チップ７１５の拡大図を示す。
The plurality of circuit regions 712 are each surrounded by a separation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 22B shows an enlarged view of the chip 715.
また、分離領域７１３に導電層、半導体層などを設けてもよい。分離領域７１３に導電層、半導体層などを設けることで、ダイシング工程時に生じ得るＥＳＤ（Ｅｒｅｃｔｒｏ−Ｓｔａｔｉｃ Ｄｉｓｃｈａｒｇｅ：静電気放電）を緩和し、ダイシング工程に起因する歩留まりの低下を防ぐことができる。また、一般にダイシング工程は、基板の冷却、削りくずの除去、帯電防止などを目的として、炭酸ガスなどを溶解させて比抵抗を下げた純水を切削部に供給しながら行う。分離領域７１３に導電層、半導体層などを設けることで、当該純水の使用量を削減することができる。よって、半導体装置の生産コストを低減することができる。また、半導体装置の生産性を高めることができる。
Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD (Electro-Static Discharge) that can occur in the dicing process can be reduced, and a decrease in yield due to the dicing process can be prevented. In general, the dicing process is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, preventing charging, and the like. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, the productivity of the semiconductor device can be increased.
＜電子部品＞
チップ７１５を用いた電子部品の一例について、図２３（Ａ）及び図２３（Ｂ）を用いて説明する。なお、電子部品は、半導体パッケージ、又はＩＣ用パッケージともいう。電子部品は、端子取り出し方向、端子の形状などに応じて、複数の規格、名称などが存在する。 <Electronic parts>
An example of an electronic component using thechip 715 will be described with reference to FIGS. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.
チップ７１５を用いた電子部品の一例について、図２３（Ａ）及び図２３（Ｂ）を用いて説明する。なお、電子部品は、半導体パッケージ、又はＩＣ用パッケージともいう。電子部品は、端子取り出し方向、端子の形状などに応じて、複数の規格、名称などが存在する。 <Electronic parts>
An example of an electronic component using the
電子部品は、組み立て工程（後工程）において、上記実施の形態に示した半導体装置と当該半導体装置以外の部品が組み合わされて完成する。
The electronic component is completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).
図２３（Ａ）に示すフローチャートを用いて、後工程について説明する。前工程において、基板７１１に本発明の一態様に係る半導体装置などを形成した後、基板７１１の裏面（半導体装置などが形成されていない面）を研削する「裏面研削工程」を行う（ステップＳ７２１）。研削により基板７１１を薄くすることで、電子部品の小型化を図ることができる。
The post-process will be described with reference to the flowchart shown in FIG. In the previous step, after a semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711, a “back surface grinding step” of grinding the back surface of the substrate 711 (a surface where the semiconductor device or the like is not formed) is performed (step S721). ). By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.
次に、基板７１１を複数のチップ７１５に分離する「ダイシング工程」を行う（ステップＳ７２２）。そして、分離したチップ７１５を個々のリードフレーム上に接合する「ダイボンディング工程」を行う（ステップＳ７２３）。ダイボンディング工程におけるチップ７１５とリードフレームとの接合は、樹脂による接合、又はテープによる接合など、適宜製品に応じて適した方法を選択する。なお、リードフレームに代えてインターポーザ基板上にチップ７１５を接合してもよい。
Next, a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.
次いで、リードフレームのリードとチップ７１５上の電極とを、金属の細線（ワイヤー）で電気的に接続する「ワイヤーボンディング工程」を行う（ステップＳ７２４）。金属の細線には、銀線、金線などを用いることができる。また、ワイヤーボンディングは、例えば、ボールボンディング、又はウェッジボンディングを用いることができる。
Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.
ワイヤーボンディングされたチップ７１５は、エポキシ樹脂などで封止される「封止工程（モールド工程）」が施される（ステップＳ７２５）。封止工程を行うことで、電子部品の内部が樹脂で充填され、チップ７１５とリードを接続するワイヤーを機械的な外力から保護することができ、また、水分、埃などによる電気特性の劣化（信頼性の低下）を低減させることができる。
The wire-bonded chip 715 is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and the electrical characteristics are degraded by moisture, dust, etc. ( (Decrease in reliability) can be reduced.
次いで、リードフレームのリードをめっき処理する「リードめっき工程」を行う（ステップＳ７２６）。めっき処理によりリードの錆を防止し、後にプリント基板に実装する際のはんだ付けをより確実に行うことができる。次いで、リードを切断及び成形加工する「成形加工工程」を行う（ステップＳ７２７）。
Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).
次いで、パッケージの表面に印字処理（マーキング）を施す「マーキング工程」を行う（ステップＳ７２８）。そして、外観形状の良否、動作不良の有無などを調べる「検査工程」（ステップＳ７２９）を経て、電子部品が完成する。
Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection step” (step S729) for checking the appearance shape and the presence / absence of operation failure.
また、完成した電子部品の斜視模式図を図２３（Ｂ）に示す。図２３（Ｂ）では、電子部品の一例として、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）の斜視模式図を示している。図２３（Ｂ）に示す電子部品７５０は、リード７５５及びチップ７１５を有する。電子部品７５０は、チップ７１５を複数有していてもよい。
Further, FIG. 23B shows a schematic perspective view of the completed electronic component. FIG. 23B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 23B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.
図２３（Ｂ）に示す電子部品７５０は、例えば、プリント基板７５２に実装される。このような電子部品７５０が複数組み合わされて、それぞれがプリント基板７５２上で電気的に接続されることで、電子部品が実装された基板（実装基板７５４）が完成する。完成した実装基板７５４は、電子機器などに用いられる。
23B is mounted on a printed board 752, for example. A plurality of such electronic components 750 are combined and electrically connected to each other on the printed circuit board 752, whereby a substrate (mounting substrate 754) on which the electronic components are mounted is completed. The completed mounting board 754 is used for an electronic device or the like.
本実施の形態は、他の実施の形態に記載した構成と適宜組み合わせて実施することが可能である。
This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.
（実施の形態８）
＜電子機器＞
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図２４に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。 (Embodiment 8)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 24 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
＜電子機器＞
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図２４に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。 (Embodiment 8)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 24 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
図２４（Ａ）は、自動車の一例を示す外観図である。自動車２９８０は、車体２９８１、車輪２９８２、ダッシュボード２９８３、及びライト２９８４等を有する。また、自動車２９８０は、アンテナ、バッテリなどを備える。
FIG. 24A is an external view showing an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.
図２４（Ｂ）に示す情報端末２９１０は、筐体２９１１、表示部２９１２、マイク２９１７、スピーカ部２９１４、カメラ２９１３、外部接続部２９１６、及び操作スイッチ２９１５等を有する。表示部２９１２には、可撓性基板が用いられた表示パネル及びタッチスクリーンを備える。また、情報端末２９１０は、筐体２９１１の内側にアンテナ、バッテリなどを備える。情報端末２９１０は、例えば、スマートフォン、携帯電話、タブレット型情報端末、タブレット型パーソナルコンピュータ、電子書籍端末等として用いることができる。
An information terminal 2910 illustrated in FIG. 24B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
図２４（Ｃ）に示すノート型パーソナルコンピュータ２９２０は、筐体２９２１、表示部２９２２、キーボード２９２３、及びポインティングデバイス２９２４等を有する。また、ノート型パーソナルコンピュータ２９２０は、筐体２９２１の内側にアンテナ、バッテリなどを備える。
A laptop personal computer 2920 shown in FIG. 24C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
図２４（Ｄ）に示すビデオカメラ２９４０は、筐体２９４１、筐体２９４２、表示部２９４３、操作スイッチ２９４４、レンズ２９４５、及び接続部２９４６等を有する。操作スイッチ２９４４及びレンズ２９４５は筐体２９４１に設けられており、表示部２９４３は筐体２９４２に設けられている。また、ビデオカメラ２９４０は、筐体２９４１の内側にアンテナ、バッテリなどを備える。そして、筐体２９４１と筐体２９４２は、接続部２９４６により接続されており、筐体２９４１と筐体２９４２の間の角度は、接続部２９４６により変えることが可能な構造となっている。筐体２９４１に対する筐体２９４２の角度によって、表示部２９４３に表示される画像の向きの変更や、画像の表示／非表示の切り換えを行うことができる。
A video camera 2940 illustrated in FIG. 24D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the housing 2941, and the display portion 2944 is provided in the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.
図２４（Ｅ）にバングル型の情報端末の一例を示す。情報端末２９５０は、筐体２９５１、及び表示部２９５２等を有する。また、情報端末２９５０は、筐体２９５１の内側にアンテナ、バッテリなどを備える。表示部２９５２は、曲面を有する筐体２９５１に支持されている。表示部２９５２には、可撓性基板を用いた表示パネルを備えているため、フレキシブルかつ軽くて使い勝手の良い情報端末２９５０を提供することができる。
FIG. 24E illustrates an example of a bangle type information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.
図２４（Ｆ）に腕時計型の情報端末の一例を示す。情報端末２９６０は、筐体２９６１、表示部２９６２、バンド２９６３、バックル２９６４、操作スイッチ２９６５、入出力端子２９６６などを備える。また、情報端末２９６０は、筐体２９６１の内側にアンテナ、バッテリなどを備える。情報端末２９６０は、移動電話、電子メール、文章閲覧及び作成、音楽再生、インターネット通信、コンピュータゲームなどの種々のアプリケーションを実行することができる。
FIG. 24F shows an example of a wristwatch type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. The information terminal 2960 includes an antenna, a battery, and the like inside the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.
表示部２９６２の表示面は湾曲しており、湾曲した表示面に沿って表示を行うことができる。また、表示部２９６２はタッチセンサを備え、指やスタイラスなどで画面に触れることで操作することができる。例えば、表示部２９６２に表示されたアイコン２９６７に触れることで、アプリケーションを起動することができる。操作スイッチ２９６５は、時刻設定の他、電源のオン、オフ動作、無線通信のオン、オフ動作、マナーモードの実行及び解除、省電力モードの実行及び解除など、様々な機能を持たせることができる。例えば、情報端末２９６０に組み込まれたオペレーティングシステムにより、操作スイッチ２９６５の機能を設定することもできる。
The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and cancellation, and power saving mode execution and cancellation. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.
また、情報端末２９６０は、通信規格された近距離無線通信を実行することが可能である。例えば、無線通信可能なヘッドセットと相互通信することによって、ハンズフリーで通話することもできる。また、情報端末２９６０は入出力端子２９６６を備え、他の情報端末とコネクターを介して直接データのやり取りを行うことができる。また、入出力端子２９６６を介して充電を行うこともできる。なお、充電動作は入出力端子２９６６を介さずに無線給電により行ってもよい。
In addition, the information terminal 2960 can execute short-range wireless communication with a communication standard. For example, a hands-free call can be made by communicating with a headset capable of wireless communication. In addition, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. In addition, charging can be performed through the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.
例えば、本発明の一態様の半導体装置を用いた記憶装置は、上述した電子機器の制御情報や、制御プログラムなどを長期間保持することができる。本発明の一態様に係る半導体装置を用いることで、信頼性の高い電子機器を実現することができる。
For example, a memory device using the semiconductor device of one embodiment of the present invention can hold the above-described control information of an electronic device, a control program, and the like for a long time. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.
本実施の形態は、他の実施の形態に記載した構成と適宜組み合わせて実施することが可能である。
This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.
１０：トランジスタ、１１：トランジスタ、１２：トランジスタ、１３：トランジスタ、１００：絶縁体、１０２：絶縁体、１０５：絶縁体、１１０：絶縁体、１１２：導電体、１２０：導電体、１２０＿１：導電体、１２０＿２：導電体、１２０ａ：導電体、１２０ｂ：導電体、１３０：絶縁体、１３０＿１：絶縁体、１３０＿２：絶縁体、１３０ａ：絶縁体、１３０ｂ：絶縁体、１４０：導電体、１４０＿１：導電体、１４０＿２：導電体、１４０ａ：導電体、１４０ｂ：導電体、１４５：開口、１５０：酸化物、１５０＿１：酸化物、１５０＿２：酸化物、１５０ａ：酸化物、１５０ｂ：酸化物、１５０ｃ：酸化物、１５１：酸化物、１６０：絶縁体、１６１：絶縁体、１７０：導電体、１７１：導電体、１７５：絶縁体、１７６：絶縁体、１７８：絶縁体、１８０：絶縁体、１８５：導電体、１８５＿１：導電体、１８５＿２：導電体、１８５ａ：導電体、１８５ｂ：導電体、１９０：導電体、１９０＿１：導電体、１９０＿２：導電体、１９０ａ：導電体、１９０ｂ：導電体、１９５：導電体、１９５＿１：導電体、１９５＿２：導電体、１９５ａ：導電体、１９５ｂ：導電体、２００：導電体、２００＿１：導電体、２００＿２：導電体、２００ａ：導電体、２００ｂ：導電体、２１０：絶縁体、２１８：導電体、２４６：導電体、２４８：導電体、３１１：基板、３１３：半導体領域、３１４ａ：低抵抗領域、３１４ｂ：低抵抗領域、３１５：絶縁体、３１６：導電体、３２０：絶縁体、３２２：絶縁体、３２４：絶縁体、３２６：絶縁体、３２８：導電体、３３０：導電体、３５０：絶縁体、３５２：絶縁体、３５４：絶縁体、３５６：導電体、３６０：絶縁体、３６２：絶縁体、３６４：絶縁体、３６６：導電体、３７０：絶縁体、３７２：絶縁体、３７４：絶縁体、３７６：導電体、３８０：絶縁体、３８２：絶縁体、３８４：絶縁体、３８６：導電体、７１１：基板、７１２：回路領域、７１３：分離領域、７１４：分離線、７１５：チップ、７５０：電子部品、７５２：プリント基板、７５４：実装基板、７５５：リード、１０００：容量素子、１１００：導電体、１２００：導電体、１３００：絶縁体、１４００：ＤＯＳＲＡＭ、１４０５：コントローラ、１４１０：行回路、１４１１：デコーダ、１４１２：ワード線ドライバ回路、１４１３：列セレクタ、１４１４：センスアンプドライバ回路、１４１５：列回路、１４１６：グローバルセンスアンプアレイ、１４１７：入出力回路、１４２０：メモリセル及びセンスアンプアレイ、１４２２：メモリセルアレイ、１４２３：センスアンプアレイ、１４２５：ローカルメモリセルアレイ、１４２６：ローカルセンスアンプアレイ、１４４４：スイッチアレイ、１４４５：メモリセル、１４４６：センスアンプ、１４４７：グローバルセンスアンプ、１５００：絶縁体、１６００：ＮＯＳＲＡＭ、１６１０：メモリセルアレイ、１６１１：メモリセル、１６１２：メモリセル、１６１３：メモリセル、１６１４：メモリセル、１６４０：コントローラ、１６５０：行ドライバ、１６５１：行デコーダ、１６５２：ワード線ドライバ、１６６０：列ドライバ、１６６１：列デコーダ、１６６２：書き込みドライバ、１６６３：ＤＡＣ、１６７０：出力ドライバ、１６７１：セレクタ、１６７２：ＡＤＣ、１６７３：出力バッファ、２０００：トランジスタ、２９１０：情報端末、２９１１：筐体、２９１２：表示部、２９１３：カメラ、２９１４：スピーカ部、２９１５：操作スイッチ、２９１６：外部接続部、２９１７：マイク、２９２０：ノート型パーソナルコンピュータ、２９２１：筐体、２９２２：表示部、２９２３：キーボード、２９２４：ポインティングデバイス、２９４０：ビデオカメラ、２９４１：筐体、２９４２：筐体、２９４３：表示部、２９４４：操作スイッチ、２９４５：レンズ、２９４６：接続部、２９５０：情報端末、２９５１：筐体、２９５２：表示部、２９６０：情報端末、２９６１：筐体、２９６２：表示部、２９６３：バンド、２９６４：バックル、２９６５：操作スイッチ、２９６６：入出力端子、２９６７：アイコン、２９８０：自動車、２９８１：車体、２９８２：車輪、２９８３：ダッシュボード、２９８４：ライト、３０００：トランジスタ、３００１：配線、３００２：配線、３００３：配線、３００４：配線、３００５：配線、３１１０：ＯＳ−ＦＰＧＡ、３１１１：コントローラ、３１１２：ワードドライバ、３１１３：データドライバ、３１１５：プログラマブルエリア、３１１７：ＩＯＢ、３１１９：コア、３１２０：ＬＡＢ、３１２１：ＰＬＥ、３１２３：ＬＵＴブロック、３１２４：レジスタブロック、３１２５：セレクタ、３１２６：ＣＭ、３１２７：パワースイッチ、３１２８：ＣＭ、３１３０：ＳＡＢ、３１３１：ＳＢ、３１３３：ＰＲＳ、３１３３［０］：ＰＲＳ、３１３３［１］：ＰＲＳ、３１３５：ＣＭ、３１３７：メモリ回路、３１３７Ｂ：メモリ回路、３１４０：ＯＳ−ＦＦ、３１４０［１］：ＯＳ−ＦＦ、３１４０［２］：ＯＳ−ＦＦ、３１４１：ＦＦ、３１４２：シャドウレジスタ、３１４３：メモリ回路、３１４３Ｂ：メモリ回路、３１８８：インバータ回路、３１８９：インバータ回路、５４００：半導体装置、５４０１：ＣＰＵコア、５４０２：パワーコントローラ、５４０３：パワースイッチ、５４０４：キャッシュ、５４０５：バスインターフェース、５４０６：デバッグインターフェース、５４０７：制御装置、５４０８：ＰＣ、５４０９：パイプラインレジスタ５４１０：パイプラインレジスタ、５４１１：ＡＬＵ、５４１２：レジスタファイル、５４２１：パワーマネージメントユニット、５４２２：周辺回路、５４２３：データバス、５５００：半導体装置、５５０１：記憶回路、５５０２：記憶回路、５５０３：記憶回路、５５０４：読み出し回路、５５０９：トランジスタ、５５１０：トランジスタ、５５１２：トランジスタ、５５１３：トランジスタ、５５１５：トランジスタ、５５１７：トランジスタ、５５１８：トランジスタ、５５１９：容量素子、５５２０：容量素子、５５４０：配線、５５４１：配線、５５４２：配線、５５４３：配線
５５４４ 配線 10: transistor, 11: transistor, 12: transistor, 13: transistor, 100: insulator, 102: insulator, 105: insulator, 110: insulator, 112: conductor, 120: conductor, 120_1: conductor 120_2: conductor, 120a: conductor, 120b: conductor, 130: insulator, 130_1: insulator, 130_2: insulator, 130a: insulator, 130b: insulator, 140: conductor, 140_1: conductor 140_2: conductor, 140a: conductor, 140b: conductor, 145: opening, 150: oxide, 150_1: oxide, 150_2: oxide, 150a: oxide, 150b: oxide, 150c: oxide, 151: oxide, 160: insulator, 161: insulator, 170: conductor, 171: conductor, 175: insulator, 176: absolute 178: insulator, 185: conductor, 185_1: conductor, 185_2: conductor, 185a: conductor, 185b: conductor, 190: conductor, 190_1: conductor, 190_2: conductor Body, 190a: conductor, 190b: conductor, 195: conductor, 195_1: conductor, 195_2: conductor, 195a: conductor, 195b: conductor, 200: conductor, 200_1: conductor, 200_2: conductor 200a: conductor, 200b: conductor, 210: insulator, 218: conductor, 246: conductor, 248: conductor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low Resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330 Conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 711: Substrate, 712: Circuit region, 713: Separation region, 714: Minute Separation line, 715: chip, 750: electronic component, 752: printed circuit board, 754: mounting board, 755: lead, 1000: capacitive element, 1100: conductor, 1200: conductor, 1300: insulator, 1400: DOSRAM, 1405 : Controller, 1410: Row circuit, 1411: Decoder, 1412: Word line driver circuit, 1413: Column selector, 1414: Sense amplifier driver circuit Path, 1415: column circuit, 1416: global sense amplifier array, 1417: input / output circuit, 1420: memory cell and sense amplifier array, 1422: memory cell array, 1423: sense amplifier array, 1425: local memory cell array, 1426: local sense Amplifier array, 1444: switch array, 1445: memory cell, 1446: sense amplifier, 1447: global sense amplifier, 1500: insulator, 1600: NOSRAM, 1610: memory cell array, 1611: memory cell, 1612: memory cell, 1613: Memory cell, 1614: memory cell, 1640: controller, 1650: row driver, 1651: row decoder, 1652: word line driver, 1660: column driver, 1661: column decoder, 1 62: Write driver, 1663: DAC, 1670: Output driver, 1671: Selector, 1672: ADC, 1673: Output buffer, 2000: Transistor, 2910: Information terminal, 2911: Housing, 2912: Display unit, 2913: Camera, 2914: Speaker unit, 2915: Operation switch, 2916: External connection unit, 2917: Microphone, 2920: Notebook personal computer, 2921: Case, 2922: Display unit, 2923: Keyboard, 2924: Pointing device, 2940: Video camera , 2941: casing, 2942: casing, 2944: display unit, 2944: operation switch, 2945: lens, 2946: connection unit, 2950: information terminal, 2951: casing, 2952: display unit, 2960: information terminal, 2961: Housing 2962: Display, 2963: Band, 2964: Buckle, 2965: Operation switch, 2966: Input / output terminal, 2967: Icon, 2980: Automobile, 2981: Car body, 2982: Wheel, 2983: Dashboard, 2984: Light, 3000 : Transistor, 3001: wiring, 3002: wiring, 3003: wiring, 3004: wiring, 3005: wiring, 3110: OS-FPGA, 3111: controller, 3112: word driver, 3113: data driver, 3115: programmable area, 3117: IOB, 3119: Core, 3120: LAB, 3121: PLE, 3123: LUT block, 3124: Register block, 3125: Selector, 3126: CM, 3127: Power switch, 3128: CM, 3130: SAB, 3131: SB, 3133: PRS, 3133 [0]: PRS, 3133 [1]: PRS, 3135: CM, 3137: memory circuit, 3137B: memory circuit, 3140: OS-FF, 3140 [1]: OS -FF, 3140 [2]: OS-FF, 3141: FF, 3142: Shadow register, 3143: Memory circuit, 3143B: Memory circuit, 3188: Inverter circuit, 3189: Inverter circuit, 5400: Semiconductor device, 5401: CPU core 5402: Power controller 5403: Power switch 5404: Cache 5405: Bus interface 5406: Debug interface 5407: Control device 5408: PC 5409: Pipeline register 5410: Pipeline register 541 : ALU, 5412: Register file, 5421: Power management unit, 5422: Peripheral circuit, 5423: Data bus, 5500: Semiconductor device, 5501: Memory circuit, 5502: Memory circuit, 5503: Memory circuit, 5504: Read circuit, 5509 : Transistor, 5510: transistor, 5512: transistor, 5513: transistor, 5515: transistor, 5517: transistor, 5518: transistor, 5519: capacitor, 5520: capacitor, 5540: wiring, 5541: wiring, 5542: wiring, 5543 : Wiring 5544 Wiring
５５４４ 配線 10: transistor, 11: transistor, 12: transistor, 13: transistor, 100: insulator, 102: insulator, 105: insulator, 110: insulator, 112: conductor, 120: conductor, 120_1: conductor 120_2: conductor, 120a: conductor, 120b: conductor, 130: insulator, 130_1: insulator, 130_2: insulator, 130a: insulator, 130b: insulator, 140: conductor, 140_1: conductor 140_2: conductor, 140a: conductor, 140b: conductor, 145: opening, 150: oxide, 150_1: oxide, 150_2: oxide, 150a: oxide, 150b: oxide, 150c: oxide, 151: oxide, 160: insulator, 161: insulator, 170: conductor, 171: conductor, 175: insulator, 176: absolute 178: insulator, 185: conductor, 185_1: conductor, 185_2: conductor, 185a: conductor, 185b: conductor, 190: conductor, 190_1: conductor, 190_2: conductor Body, 190a: conductor, 190b: conductor, 195: conductor, 195_1: conductor, 195_2: conductor, 195a: conductor, 195b: conductor, 200: conductor, 200_1: conductor, 200_2: conductor 200a: conductor, 200b: conductor, 210: insulator, 218: conductor, 246: conductor, 248: conductor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low Resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330 Conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 711: Substrate, 712: Circuit region, 713: Separation region, 714: Minute Separation line, 715: chip, 750: electronic component, 752: printed circuit board, 754: mounting board, 755: lead, 1000: capacitive element, 1100: conductor, 1200: conductor, 1300: insulator, 1400: DOSRAM, 1405 : Controller, 1410: Row circuit, 1411: Decoder, 1412: Word line driver circuit, 1413: Column selector, 1414: Sense amplifier driver circuit Path, 1415: column circuit, 1416: global sense amplifier array, 1417: input / output circuit, 1420: memory cell and sense amplifier array, 1422: memory cell array, 1423: sense amplifier array, 1425: local memory cell array, 1426: local sense Amplifier array, 1444: switch array, 1445: memory cell, 1446: sense amplifier, 1447: global sense amplifier, 1500: insulator, 1600: NOSRAM, 1610: memory cell array, 1611: memory cell, 1612: memory cell, 1613: Memory cell, 1614: memory cell, 1640: controller, 1650: row driver, 1651: row decoder, 1652: word line driver, 1660: column driver, 1661: column decoder, 1 62: Write driver, 1663: DAC, 1670: Output driver, 1671: Selector, 1672: ADC, 1673: Output buffer, 2000: Transistor, 2910: Information terminal, 2911: Housing, 2912: Display unit, 2913: Camera, 2914: Speaker unit, 2915: Operation switch, 2916: External connection unit, 2917: Microphone, 2920: Notebook personal computer, 2921: Case, 2922: Display unit, 2923: Keyboard, 2924: Pointing device, 2940: Video camera , 2941: casing, 2942: casing, 2944: display unit, 2944: operation switch, 2945: lens, 2946: connection unit, 2950: information terminal, 2951: casing, 2952: display unit, 2960: information terminal, 2961: Housing 2962: Display, 2963: Band, 2964: Buckle, 2965: Operation switch, 2966: Input / output terminal, 2967: Icon, 2980: Automobile, 2981: Car body, 2982: Wheel, 2983: Dashboard, 2984: Light, 3000 : Transistor, 3001: wiring, 3002: wiring, 3003: wiring, 3004: wiring, 3005: wiring, 3110: OS-FPGA, 3111: controller, 3112: word driver, 3113: data driver, 3115: programmable area, 3117: IOB, 3119: Core, 3120: LAB, 3121: PLE, 3123: LUT block, 3124: Register block, 3125: Selector, 3126: CM, 3127: Power switch, 3128: CM, 3130: SAB, 3131: SB, 3133: PRS, 3133 [0]: PRS, 3133 [1]: PRS, 3135: CM, 3137: memory circuit, 3137B: memory circuit, 3140: OS-FF, 3140 [1]: OS -FF, 3140 [2]: OS-FF, 3141: FF, 3142: Shadow register, 3143: Memory circuit, 3143B: Memory circuit, 3188: Inverter circuit, 3189: Inverter circuit, 5400: Semiconductor device, 5401: CPU core 5402: Power controller 5403: Power switch 5404: Cache 5405: Bus interface 5406: Debug interface 5407: Control device 5408: PC 5409: Pipeline register 5410: Pipeline register 541 : ALU, 5412: Register file, 5421: Power management unit, 5422: Peripheral circuit, 5423: Data bus, 5500: Semiconductor device, 5501: Memory circuit, 5502: Memory circuit, 5503: Memory circuit, 5504: Read circuit, 5509 : Transistor, 5510: transistor, 5512: transistor, 5513: transistor, 5515: transistor, 5517: transistor, 5518: transistor, 5519: capacitor, 5520: capacitor, 5540: wiring, 5541: wiring, 5542: wiring, 5543 : Wiring 5544 Wiring
Claims (5)
- 第１の導電体と、
前記第１の導電体上の第１の絶縁体と、
前記第１の絶縁体上の第２の導電体と、
前記第１の導電体、前記第１の絶縁体、及び前記第２の導電体の側面と接する領域を有する酸化物と、
前記酸化物上の第２の絶縁体と、
前記第２の絶縁体上の第３の導電体と、を有し、
前記第２の絶縁体は、前記酸化物を介して、前記第１の導電体、前記第１の絶縁体、及び前記第２の導電体の側面と向かい合う領域を有し、
前記第３の導電体は、前記酸化物及び前記第２の絶縁体を介して、前記第１の導電体、前記第１の絶縁体、及び前記第２の導電体の側面と向かい合う領域を有する、ことを特徴とする半導体装置。 A first conductor;
A first insulator on the first conductor;
A second conductor on the first insulator;
An oxide having a region in contact with a side surface of the first conductor, the first insulator, and the second conductor;
A second insulator on the oxide;
A third conductor on the second insulator;
The second insulator has a region facing a side surface of the first conductor, the first insulator, and the second conductor via the oxide,
The third conductor has a region facing a side surface of the first conductor, the first insulator, and the second conductor through the oxide and the second insulator. A semiconductor device characterized by that. - 請求項１において、
前記第１の導電体、前記第１の絶縁体、及び前記第２の導電体は、第３の絶縁体で覆われ、
前記第３の絶縁体は、開口を有し、
前記酸化物、前記第２の絶縁体、及び前記第３の導電体は、前記開口を埋め込むように形成される、ことを特徴とする半導体装置。 In claim 1,
The first conductor, the first insulator, and the second conductor are covered with a third insulator;
The third insulator has an opening;
The semiconductor device, wherein the oxide, the second insulator, and the third conductor are formed so as to fill the opening. - 請求項１において、
前記酸化物は、前記第２の導電体の上面と接する領域を有し、
前記第２の絶縁体は、前記酸化物を介して、前記第２の導電体の上面と重なる領域を有し、
前記第３の導電体は、前記酸化物及び前記第２の絶縁体を介して、前記第２の導電体の上面と重なる領域を有する、ことを特徴とする半導体装置。 In claim 1,
The oxide has a region in contact with the upper surface of the second conductor,
The second insulator has a region overlapping the upper surface of the second conductor via the oxide,
The semiconductor device, wherein the third conductor has a region overlapping with an upper surface of the second conductor with the oxide and the second insulator interposed therebetween. - 請求項１において、
前記第１の絶縁体の膜厚は、１ｎｍ以上１００ｎｍ以下である、ことを特徴とする半導体装置。 In claim 1,
The semiconductor device is characterized in that the thickness of the first insulator is not less than 1 nm and not more than 100 nm. - 請求項１において、
前記酸化物は、金属酸化物を含む、ことを特徴とする半導体装置。 In claim 1,
The semiconductor device, wherein the oxide includes a metal oxide.
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023066365A (en) * | 2021-10-28 | 2023-05-15 | 台湾積體電路製造股▲ふん▼有限公司 | Vertical field effect transistor and formation method for the same |
| WO2023157048A1 (en) * | 2022-02-15 | 2023-08-24 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and method for manufacturing same |
| WO2023166378A1 (en) * | 2022-03-04 | 2023-09-07 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2023175436A1 (en) * | 2022-03-18 | 2023-09-21 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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| WO2023199153A1 (en) * | 2022-04-15 | 2023-10-19 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2023203426A1 (en) * | 2022-04-19 | 2023-10-26 | 株式会社半導体エネルギー研究所 | Semiconductor device and storage device |
| WO2024057168A1 (en) * | 2022-09-16 | 2024-03-21 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2024069340A1 (en) * | 2022-09-30 | 2024-04-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for producing semiconductor device |
| WO2024095110A1 (en) * | 2022-11-03 | 2024-05-10 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for producing semiconductor device |
| WO2024105516A1 (en) * | 2022-11-17 | 2024-05-23 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for manufacturing same |
| WO2024105497A1 (en) * | 2022-11-15 | 2024-05-23 | 株式会社半導体エネルギー研究所 | Storage device |
| WO2024141865A1 (en) * | 2022-12-27 | 2024-07-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and semiconductor device manufacturing method |
| WO2024141887A1 (en) * | 2022-12-28 | 2024-07-04 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2024157122A1 (en) * | 2023-01-25 | 2024-08-02 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023066365A (en) * | 2021-10-28 | 2023-05-15 | 台湾積體電路製造股▲ふん▼有限公司 | Vertical field effect transistor and formation method for the same |
| JP7444933B2 (en) | 2021-10-28 | 2024-03-06 | 台湾積體電路製造股▲ふん▼有限公司 | Vertical field effect transistor and its formation method |
| WO2023157048A1 (en) * | 2022-02-15 | 2023-08-24 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and method for manufacturing same |
| WO2023166378A1 (en) * | 2022-03-04 | 2023-09-07 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2023175436A1 (en) * | 2022-03-18 | 2023-09-21 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2023187543A1 (en) * | 2022-03-31 | 2023-10-05 | 株式会社半導体エネルギー研究所 | Display device |
| WO2023199153A1 (en) * | 2022-04-15 | 2023-10-19 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2023203426A1 (en) * | 2022-04-19 | 2023-10-26 | 株式会社半導体エネルギー研究所 | Semiconductor device and storage device |
| WO2024057168A1 (en) * | 2022-09-16 | 2024-03-21 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2024069340A1 (en) * | 2022-09-30 | 2024-04-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for producing semiconductor device |
| WO2024095110A1 (en) * | 2022-11-03 | 2024-05-10 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for producing semiconductor device |
| WO2024105497A1 (en) * | 2022-11-15 | 2024-05-23 | 株式会社半導体エネルギー研究所 | Storage device |
| WO2024105516A1 (en) * | 2022-11-17 | 2024-05-23 | 株式会社半導体エネルギー研究所 | Semiconductor device and method for manufacturing same |
| WO2024141865A1 (en) * | 2022-12-27 | 2024-07-04 | 株式会社半導体エネルギー研究所 | Semiconductor device and semiconductor device manufacturing method |
| WO2024141887A1 (en) * | 2022-12-28 | 2024-07-04 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2024157122A1 (en) * | 2023-01-25 | 2024-08-02 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2018203181A1 (en) | 2020-03-12 |
| JP2022159517A (en) | 2022-10-17 |
| JP7128809B2 (en) | 2022-08-31 |
| JP2024050930A (en) | 2024-04-10 |
| JP7441282B2 (en) | 2024-02-29 |
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