WO2023157048A1

WO2023157048A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2023157048A1
Application number: PCT/JP2022/005810
Authority: WO
Inventors: 正一各務; 望原田
Original assignee: ユニサンティスエレクトロニクスシンガポールプライベートリミテッド; 正一各務; 望原田
Priority date: 2022-02-15
Filing date: 2022-02-15
Publication date: 2023-08-24

Abstract

In the present invention, a first insulating layer 1 is on a substrate 40, a first metal wiring layer 2 and a fourth metal wiring layer 3 are embedded in the insulating layer, a second metal wiring layer 4 abuts the metal wiring layer 2 and extends perpendicularly thereto, a first impurity layer (n+ layer) 5a abuts the second metal wiring layer 4 and extends perpendicularly thereto, a semiconductor p layer 6 and a second impurity layer (n+ layer) 5b abut the first impurity layer 5a and extend perpendicularly thereto, side surfaces of the first impurity layer 5a, the semiconductor p layer 6, and the second impurity layer 5b are partially covered by a first gate insulating layer 7, a first gate conductor layer 8 abuts the first gate insulating layer 7, the second impurity layer 5b is covered by a second insulating layer 9, and the n+ layer 5b is connected with a third metal wiring layer 10 via a contact hole 33. The fourth metal wiring layer 3 is connected to the gate conductor layer 8.

Description

Semiconductor device and its manufacturing method

The present invention relates to a semiconductor device and its manufacturing method.

In recent years, in the development of LSI (Large Scale Integration) technology, there is a demand for higher integration and higher performance of semiconductor devices.

In a normal planar MOS transistor, the channel extends horizontally along the surface of the semiconductor substrate. In contrast, the SGT channel extends in a direction perpendicular to the surface of the semiconductor substrate (see Non-Patent Document 1, for example). For this reason, the SGT enables a higher density semiconductor device compared to a planar MOS transistor. When configuring an integrated circuit using this SGT, there is a method of connecting the semiconductor elements respectively. An example of using a partial semiconductor portion of the substrate for connecting n+ and p+ is shown (see, for example, Non-Patent Document 2). Also, in an example of using SGTs in a DRAM, an example is shown in which the electrodes on the bottom of the SGT are connected by metal wiring from above (see, for example, Non-Patent Document 3). In addition, although the transistor structure is not SGT, an example of embedding a metal layer in a semiconductor substrate has been announced (see, for example, Non-Patent Document 4). The present application relates to a semiconductor device that uses an SGT structure and has conventional wiring structures on both sides of a semiconductor element to provide a high-density, high-speed MOS circuit.

When wiring MOSFETs with an SGT structure in an integrated circuit, a problem arises when wiring the electrodes of the MOSFETs arranged on the substrate side. When a part of the semiconductor substrate is used for wiring, a large wiring delay due to the parasitic capacitance caused by the relative dielectric constant of silicon, which is about three times as large as that of the resistance and silicon oxide film, becomes a problem. Furthermore, a depletion layer is formed in the substrate due to the voltage applied to the wiring, and the parasitic capacitance of the wiring is greatly changed due to the dependency of the depletion layer on the applied voltage, which greatly hinders the design of LSI. Furthermore, focusing on the parasitic resistance of the SGT transistor, the large difference in the balance between the parasitic resistance on the source side and the drain side imposes significant restrictions on the design (see, for example, Non-Patent Document 5). Of course, it is also possible to open contact holes from the surface of the wafer and make direct contact with the metal layer. At the same time as the sparseness, the contact holes become very deep, increasing the difficulty of the process. Also, a structure in which a metal layer is embedded instead of a semiconductor has been proposed for the wiring resistance on the substrate side (see, for example, Non-Patent Document 6), but the process after once forming the metal wiring is complicated. There is also a limit to the wiring material that can be used due to the thermal history of . In addition to solving the above problems, it is necessary to wire transistors using SGTs with low resistance and increase the density.

In order to solve the above problems, a semiconductor device according to the present invention includes:
a first insulating layer overlying the substrate;
a first metal wiring layer embedded in the first insulating layer and extending horizontally with respect to the substrate;
a second metal wiring layer that is in contact with the first metal wiring layer, extends in a direction perpendicular to the substrate, and has an upper surface positioned at the upper surface of the first insulating layer;
a first impurity layer in contact with the second metal wiring layer and extending upward;
a first semiconductor pillar in contact with the first impurity layer and extending upward;
a second impurity layer connected to the top of the first semiconductor pillar and extending upward; the first semiconductor pillar, a portion of the first impurity layer, and a portion of a side surface of the second impurity layer; a gate insulating layer covering the
a gate conductor layer covering side surfaces of the first gate insulating layer;
a second insulating layer covering the top of the second impurity layer;
a third metal wiring layer horizontally extending on or inside the second insulating layer through a contact hole connected to the second impurity layer;
a fourth metal wiring layer connected to the gate conductor layer and in the first insulating layer or in the second insulating layer and connected in or above it;
(first invention).

In the above first invention, the majority carriers in the first and second impurity layers are electrons, and the majority carriers in the first semiconductor pillar are holes (second invention).

In the above first invention, majority carriers in the first and second impurity layers are holes, and majority carriers in the first semiconductor pillar are electrons (third invention).

The first invention is characterized in that the gate conductor layer is divided into two or more pieces in plan view (fourth invention).

In the above first invention, the gate conductor layer is vertically divided into two or more,
(Fifth invention).

In the above-described first invention, the first metal wiring layer and the third metal wiring layer are provided in a direction perpendicular to the interface between the contact hole and the second impurity layer, and the first metal wiring layer and the third metal wiring layer are arranged in a vertical direction. A first semiconductor column is present between three metal wiring layers (sixth invention).

In the above-described first invention, a part or all of the surface of at least one of the first impurity layer and the second impurity layer is covered with a first metal film. (seventh invention).

In the above-described first invention, a first channel-type MOSFET in which majority carriers in the first impurity layer and the second impurity layer are electrons, and a plurality of the first impurity layer and the second impurity layer. A second channel-type MOSFET whose carriers are holes exists on the same substrate, and the first metal wiring layer, the second metal wiring layer, the third metal wiring layer, and the fourth metal wiring. A part of constituent elements of the first channel-type MOSFET and the second channel-type MOSFET are electrically connected in at least one metal wiring layer among the layers (eighth invention).

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes:
After forming a first insulating film and a first semiconductor layer containing an impurity in an element region of the semiconductor substrate on a first semiconductor substrate, a second insulating film, a gate material layer, and a third insulating film are formed. forming a film, and forming a mask material thereon so as to cover part of the first insulating film and part of the element region in plan view;
etching and removing the third insulating film and the gate material layer using the mask material as a mask;
forming a fourth insulating film over the entire surface, flattening the fourth insulating film until the mask material appears, and then removing the mask material; removing the second insulating film and the gate material layer to form an opening, forming a gate insulating layer on sidewalls thereof, and further on the first semiconductor layer inside the gate insulating layer; filling a second semiconductor layer into the second semiconductor layer, forming a third semiconductor layer containing impurities on the second semiconductor layer, and forming a fifth insulating film on the whole;
A first contact hole is formed in the fifth insulating film above the gate material layer to form a first metal wiring, a sixth insulating film is formed thereon, and the second impurity layer is formed. a step of forming a seventh insulating film on the entire surface after forming a second metal wiring by forming a second contact hole in the sixth insulating film on the upper portion of the
A second substrate is adhered to the seventh insulating film, the first substrate is turned over so that the bottom surface of the semiconductor substrate, and then the first semiconductor substrate is polished until the first insulating film is exposed. process and
a step of forming a seventh insulating film on the entire surface, opening a third contact hole, and forming a third metal wiring;
(9th invention).

In the above ninth invention, the step of further forming an eighth insulating film on the entire surface before forming the seventh insulating film, forming a fourth contact hole, and forming a fourth metal wiring. and then forming the seventh insulating film on the entire surface (tenth invention).

[Correction under Rule 91 11.05.2022]
It is a figure which shows the cross-section of the semiconductor element which concerns on 1st Embodiment. FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a sectional structure of a semiconductor element according to a second embodiment in which a part of an electrode is covered with a metal film; FIG. FIG. 10 is a sectional structure of a semiconductor element according to a second embodiment in which a part of an electrode is covered with a metal film; FIG. It is a cross-sectional structure of a CMOS device using the semiconductor device according to the third embodiment.

A semiconductor device according to the present invention will be described below with reference to the drawings.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a cross section of a semiconductor device structure according to a first embodiment of the present invention.
An insulating layer 1 (which is an example of a "first insulating layer" in the claims) is provided on a substrate 40 (which is an example of a "substrate" in the claims). There is a metal wiring layer 2 (which is an example of the “first metal wiring layer” in the claims) embedded in the insulating layer 1 and extending horizontally with respect to the substrate 40 . A metal wiring layer 4 that is in contact with the upper surface of the metal wiring layer 2, extends in a direction perpendicular to the substrate 40, and has an upper surface position at the upper surface position of the insulating layer 1 ("second metal wiring layer" in the scope of claims). is an example). An n+ layer 5a which is in contact with the upper surface of the metal wiring layer 4 and contains a high concentration of donor impurities (hereinafter, a semiconductor region containing a high concentration of donor impurities is referred to as an "n+ layer"). is an example of "impurity layer"). In contact with the upper surface of n+ layer 5a, there is a columnar silicon p layer 6 (an example of a "first semiconductor column" in the claims) having p-type conductivity containing acceptor impurities. In contact with the upper surface of the p-layer 6, there is an n+ layer 5b (which is an example of the "second impurity layer" in the scope of claims) containing columnar donor impurities. There is a gate insulating layer 7 (which is an example of the "first gate insulating layer" in the claims) covering the side surfaces of the p layer 6, the side surfaces of the n+ layer 5a, and the side surfaces of the n+ layer 5b. Also, the gate conductor layer 8 (which is an example of the “first gate conductor layer” in the claims) is in contact with the side surface of the gate insulating layer 7 . An insulating layer 9 covering the n+ layer 5b (an example of a “second insulating layer” in the claims), and a contact hole 33 in the insulating layer 9 and connected to the n+ layer 5b (an example of the “second insulating layer” in the claims). There is a metal wiring layer 10 (which is an example of the "third metal wiring layer" in the claims) extending horizontally in the insulating layer 9 via the "contact hole"). A metal wiring layer 3 (which is an example of the "fourth metal wiring layer" in the scope of claims) is connected to the gate conductor layer 8 buried in the insulating layer 1 . In this manner, a semiconductor element comprising p layer 6, n+ layer 5a, n+ layer 5b, gate insulating layer 7 and gate conductor layer 8 is formed.

In an integrated circuit to which the semiconductor device of this embodiment is applied, one or a plurality of the semiconductor devices described above are arranged two-dimensionally on the substrate 40 .

Also, each of the

metal wiring layers

2, 3, 4, and 10 may be made of any material, such as a single metal material, a metal compound, or a multi-layered structure of a plurality of materials, as long as it has the properties of a conductor.

Also, in FIG. 1, the metal wiring layer 2 penetrates the insulating layer 1 and is connected to the n+ layer 5a. Moreover, the metal wiring layer 2 and the metal wiring layer 4 may be formed of the same conductor layer or different conductor layers.

In addition, although the metal wiring layer 3 connected to the gate conductor layer 8 is embedded in the insulating layer 1 in FIG. 1, the metal wiring layer 3 is embedded in the insulating layer 9 and connected to the gate conductor layer 8 from above. You may In this case, the metal wiring layer 3 and the metal wiring layer 10 have different heights in the vertical direction.

In addition, although the

metal wiring layers

2, 3, 4 and 10 are shown independently in FIG. may

In addition, although the p-layer 6 is a p-type semiconductor in FIG. 1, the impurity concentration may have a profile. Also, the p-layer 6 may be an n-type or i-type semiconductor.

Further, when the n+ layer 5a and the n+ layer 5b are formed of a p+ layer in which holes are majority carriers (hereinafter, a semiconductor region containing a high concentration of acceptor impurities is referred to as a "p+ layer"), the p layer 6 is an n-type semiconductor, it functions as a p-type semiconductor element.

Also, the substrate 40 can be made of any material, whether it is an insulator or a semiconductor, as long as it can adhere to the insulating layer 1 and support the SGT structure MOSFET.

In addition, the gate conductor layer 8 can change the potential of the p-layer 6 through the gate insulating layer 7, and may be a highly doped semiconductor layer or a conductor layer.

Also, in FIG. 1, the gate conductor layer 8 is shown as one piece, but it may be divided horizontally or vertically with respect to the substrate 40 .

When wiring is to be connected to the gate conductor layer, the connection is made from the metal wiring layer 2 side in FIG. to connect.

In addition, in FIG. 1, the insulating layer 1 and the insulating layer 9 are illustrated as being integrated, but they may be formed by combining the same material or multiple materials in multiple layers.

[Correction under Rule 91 11.05.2022]
2A to 2M (2I is omitted because it is easy to confuse the notation) (hereinafter collectively referred to as "FIG. 2"), the manufacturing method of the semiconductor device according to the present embodiment is shown. In each figure, (a) is a plan view, and (b) is a vertical sectional view taken along line XX' of (a).

As shown in FIG. 2A, an insulating film 30 for element isolation is formed on the p-type semiconductor substrate 11 . Next, an n+ layer 12a is formed in a region where a transistor is to be formed. Any material may be used for the insulating film 30 as long as it has an etching selectivity with respect to the semiconductor substrate when the substrate is later polished from the back side and is an insulator. The p-type substrate 11 may be a p-well layer formed on an n-type semiconductor substrate.

Next, as shown in FIG. 2B, a silicon oxide film 13 is formed on the p-type substrate 11, and a phosphorus-doped polysilicon 14, a silicon oxide film 41, and a silicon nitride film 42 are formed thereon. The silicon nitride film 42 can be used as a mask material in an etching process such as RIE (Reactive Ion Etching), and any material can be used as long as it has an etching selectivity with respect to the silicon oxide film. Also, the polysilicon 14 will be the material of the gate electrode in the future, but any material can be used as long as it can withstand the thermal hysteresis of subsequent processes and is a conductor.

Next, as shown in FIG. 2C, using the silicon nitride film 42 as a mask material, the silicon oxide film 41 and the polysilicon 14 are etched by RIE so that the gate electrode portion remains.

Next, as shown in FIG. 2D, an insulating layer 15 is formed on the entire surface by, for example, a CVD (Chemical Vapor Deposition) method, and then a CMP (Chemical Mechanical Polishing) method is used to form the insulating layer 15 until the surface of the mask material 42 is exposed. is polished, and the mask material 42 is selectively removed. Further, etching is performed by CMP so that the insulating layer 15 and the silicon oxide film 41 are flattened. Although the insulating layer 15 and the silicon oxide film 41 are separately shown in FIG. 2D, they are collectively shown as the insulating layer 15 hereinafter.

Next, as shown in FIG. 2E, the insulating layer 15, the polysilicon 14, and the silicon oxide film 13 in the portion where the SGT will be formed in the future are etched by RIE until the surface of the n+ layer 12a is exposed.

Next, as shown in FIG. 2F, an oxide film (not shown) is formed on the entire surface using, for example, ALD (Atomic Layer Deposition) technology, and etched back to form the oxide film shown in FIG. 2E. A gate insulating film 16 is formed leaving this oxide film only on the sidewalls of the trench.

Next, as shown in FIG. 2G, the p-layer 17 is grown by, for example, selective CVD under the condition that it is continuous as a crystal layer from the n+ layer 12a, and then the layers required to operate as a MOSFET in the memory cell are grown. Remove the rest. Note that p-layer 17 may be formed using other methods such as selective epitaxial crystal growth.

Next, an n+ layer 12b is formed on the p layer 17 as shown in FIG. 2H. Further, the n+ layer 12a diffuses upward from the lower portion of the p layer 17 due to the thermal history in the processes shown in FIGS. 2G and 2H.

[Correction under Rule 91 11.05.2022]
Next, as shown in FIG. 2I, after forming an insulating layer 19-1 on the entire surface, a contact hole 31 is formed. After that, a metal wiring layer 21 is formed. Further, after forming an insulating layer 19-2 on the entire surface, a contact hole 32 is opened and a metal wiring layer 22 is formed. After that, an insulating layer 19-3 is formed on the entire surface. Although the insulating layers 19-1, 19-2, and 19-3 are shown separately in FIG. 2I, they will be collectively shown as the insulating layer 19 hereinafter. Although FIG. 2I shows a method of directly connecting the wiring layer of the n+ layer 12b by opening the contact hole 32, a method of connecting the metal wiring layer 22 via the contact hole 31 and the metal wiring layer 21 is also possible. Also, although the contact holes and metal wiring layers cannot actually be seen in the plan view, the metal wiring layers are indicated by dotted lines for easy understanding.

[Correction under Rule 91 11.05.2022]
Next, as shown in FIG. 2J, a substrate 40 is attached onto the insulating layer 19 by room temperature bonding. This substrate will be the base of the semiconductor device in the future, and may be made of metal, semiconductor, or insulator as long as it can withstand the subsequent wiring process.

[Correction under Rule 91 11.05.2022]
Next, the above-illustrated structure is turned upside down so that the substrate 40 is the bottom surface and the p-layer 11 is the surface. This is shown in FIG. 2K. Then, the p-layer 11 is polished by the CMP technique until the surface of the insulating layer 30 is exposed.

[Correction under Rule 91 11.05.2022]
Next, as shown in FIG. 2L, after forming an insulating layer 29-1 on the entire surface, a contact hole 33 is formed. After that, a metal wiring layer 23 is formed.

[Correction under Rule 91 11.05.2022]
Next, as shown in FIG. 2M, after forming an insulating layer 29-2 on the entire surface, a contact hole 34 is opened. After that, a metal wiring layer 24 is formed. Thereby, a MOS transistor element is formed on the substrate 40 . Although FIG. 2M shows a method of directly connecting the wiring layer of the n+ layer 12a by opening the contact hole 34, a method of connecting the metal wiring layer 24 via the contact hole 33 and the metal wiring layer 23 is also possible. . Although the contact holes 33 and 34 and the metal wiring layer 23 cannot actually be seen in the plan view, they are illustrated for easy understanding.

In the present embodiment, the p-layer 17 and the impurity layers 12a and 12b are shown to have square columnar bottoms, but they may have other polygonal, rectangular, elliptical or circular bottoms.

In addition, although the gate conductor layer 14 is a polysilicon layer doped with phosphorus, it should be able to withstand the heat process after the formation of the gate conductor layer 14 and exhibit the properties of a conductor such as a metal, an alloy, or a metal compound. Any material can be used as long as it is used.

Any insulating film used in a normal MOS process can be used for the gate insulating film 16, such as a SiO2 film, a SiON film, an HfSiON film, or a laminated film of SiO2/SiN.

In addition, in FIG. 2 of the present embodiment, all metal wiring layers are shown extending in the direction perpendicular to the XX' axis, but they extend in the direction parallel to the XX' axis. It may be extended in an oblique direction or in an oblique direction.

The insulating films 19-1, 19-2, 19-3, 29-1, and 29-2 described with reference to FIG. Any combination is acceptable.

This embodiment has the following features.
(Feature 1)
In the semiconductor device according to the first embodiment of the present invention, low-resistance metal wiring can be provided on either side of the source or drain of the MOSFET having the SGT structure. can reduce the parasitic resistance related to , and solve the imbalance between the parasitic resistances of the source and the drain.

(Feature 2)
In the semiconductor device according to the first embodiment of the present invention, since the wirings connected to the source side and the drain side of the SGT structure MOSFET can be arranged with the semiconductor portion sandwiched therebetween, from the viewpoint of the planar layout, contact holes and Wiring can be arranged in an overlapping manner, and the degree of freedom in wiring layout is greatly improved as compared with the conventional example. Furthermore, connections to other electrodes and interconnections of wiring can be freely wired in both directions. Therefore, it is possible to form metal wiring with a higher degree of freedom than in the prior art, and to provide a semiconductor device with a higher density.

(Second embodiment)
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 3A and 3B. 3A and 3B, the same or similar components as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, part of the n+ layers 5a and 5b in FIG. 1 is covered with a metal film 20a (an example of the "first metal film" in the claims). This makes it possible to provide a semiconductor device in which the parasitic resistance is further reduced from that of the first embodiment.

Note that in FIG. 3A, the metal film 20a was formed only on the surfaces of the n+ layers 5a and 5b. On the other hand, FIG. 3B shows the case where the metal film 20b is also formed partially on the side surfaces of the n+ layers 5a and 5b. This makes it possible to provide a semiconductor device in which the parasitic resistance is further reduced from that of the first embodiment.

It should be noted that the

metal films

20a and 20b may be made of metal or silicide as long as they have metallic properties. Alternatively, a multilayer structure of metal films may be used.

Also, in FIGS. 3A and 3B, both the impurity layers (n+ layers) 5a and 5b are partially coated with the metal film 20, but the metal film may be formed on the surface of only one of them.

Embodiments of the invention have the following features.
(Feature 1)
In the semiconductor device according to the second embodiment of the present invention, the effective contact resistance between the metal wiring layer 22 and the impurity layer 7b is reduced by forming the

metal layers

20a and 20b on the surfaces of the impurity layers (n+ layers) 5a and 5b. Thus, in addition to the first embodiment, a semiconductor device with even smaller parasitic resistance can be provided.

(Third embodiment)
A semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. In FIG. 4, components identical or similar to those in FIG. 2 are denoted by the same reference numerals.

As shown in FIG. 4, an n-channel MOSFET having an SGT structure formed of the p-layer 17, n+ layers 12a and 12b, gate insulating layer 16, and gate conductor layer 14 in FIG. 1 channel type MOSFET"), an SGT structure p-channel type MOSFET (claimed , which is an example of a "second channel type MOSFET" in the range of . The metal wiring layer 21 is connected to the n+ layer 12b, the metal wiring layer 22 is connected to the p+ layer 25b, and the metal wiring layer 23 (which is an example of the "fourth metal wiring" in the claims) is connected to the gate conductor layer 14. , the metal wiring layer 24 (which is an example of the "third metal wiring" in the claims) connects the n+ layer 12a and the p+ layer 25a. If the metal wiring layer 22 is used as a power source and the metal wiring layer 21 is used as a grounded source, it can be operated as an inverter circuit using the metal wiring layer 23 as a signal input line and the metal wiring layer 24 as a signal output line.

In the conventional example, no matter how many multilayer wiring techniques are used, the metal wiring layer 24 connected to the n+ layer 12a and the metal wiring layer 21 connected to the n+ layer 12b in FIG. Similarly, the metal wiring layer 24 connected to the p+ layer 25a and the metal wiring layer 22 connected to the p+ layer 25b cannot be laid out two-dimensionally. According to the present invention, the combination of the metal wiring layer 22 serving as the power line and the metal wiring layer 21 serving as the ground line, and the combination of the metal wiring layer 23 serving as the signal input line and the metal wiring layer 24 serving as the signal output line are semiconductor layers. 17 and 27 can be designed independently, so that the degree of freedom in wiring layout is increased compared to the conventional example, so that higher density wiring can be achieved and the degree of integration is improved.

This embodiment has the following features.
(Feature 1)
As in the first embodiment, the MOSFET circuit of the CMOS type SGT structure having both channels can be laid out above and below the semiconductor layer. , the degree of freedom of the wiring increases. Furthermore, connections to other electrodes and interconnections of wiring can be freely wired in both directions. Therefore, a CMOS structure having wiring with a higher degree of freedom than the conventional example can be provided, and as a result, a high-density semiconductor device can be provided.

In addition, the present invention enables various embodiments and modifications without departing from the broad spirit and scope of the present invention. Moreover, each embodiment described above is for describing one example of the present invention, and does not limit the scope of the present invention. The above embodiments and modifications can be combined arbitrarily. Furthermore, it is within the scope of the technical idea of the present invention even if some of the constituent elements of the above embodiments are removed as necessary.

By using the semiconductor element according to the present invention, it is possible to provide a semiconductor circuit using an SGT structure with a higher density than before.

1 first insulating layer 2 first metal wiring layer 3 fourth metal wiring layer 4 second

metal wiring layers

5a, 5b n+ layer 6 p layer 7 gate insulating layer 8 gate conductor layer 9 second insulating layer 10 third metal wiring layer 11 p-

type semiconductor substrates

12a, 12b n+ layer 13 insulating layer
14 Phosphorus-doped silicon film (gate conductor layer)
15 insulating layer (collective term for insulating layer 15 and insulating layer 41)
16 first gate insulating layer 17 p-layer 19 insulating layer (collective term for insulating layers 19-1, 19-2 and 19-3)
19-1, 19-2, 19-3

insulating layers

20a, 20b metal layer 21 metal wiring layer 22 metal wiring layer 23 metal wiring layer 24

metal wiring layers

25a, 25b p+ layer 27 n layer 30 insulating film 29 insulating layer (insulating General term for layers 29-1 and 29-2)
29-1, 29-2 insulating layer 31 contact hole 32 contact hole 33 contact hole 34 contact hole 40 substrate 41 insulating layer 42 mask material

Claims

a first insulating layer overlying the substrate;
a first metal wiring layer embedded in the first insulating layer and extending horizontally with respect to the substrate;
a second metal wiring layer that is in contact with the first metal wiring layer, extends in a direction perpendicular to the substrate, and has an upper surface positioned at the upper surface of the first insulating layer;
a first impurity layer in contact with the second metal wiring layer and extending upward;
a first semiconductor pillar in contact with the first impurity layer and extending upward;
a second impurity layer connected to the top of the first semiconductor pillar and extending upward; the first semiconductor pillar, a portion of the first impurity layer, and a portion of a side surface of the second impurity layer; a gate insulating layer covering the
a gate conductor layer covering side surfaces of the first gate insulating layer;
a second insulating layer covering the top of the second impurity layer;
a third metal wiring layer horizontally extending on or inside the second insulating layer through a contact hole connected to the second impurity layer;
a fourth metal wiring layer connected to the gate conductor layer and in the first insulating layer or in the second insulating layer and connected in or on top of it;
A semiconductor device characterized by:
majority carriers of the first and second impurity layers are electrons, and majority carriers of the first semiconductor pillar are holes;
2. The semiconductor device according to claim 1, wherein:
majority carriers of the first and second impurity layers are holes, and majority carriers of the first semiconductor pillar are electrons;
2. The semiconductor device according to claim 1, wherein:
In plan view, the gate conductor layer is divided into two or more,
2. The semiconductor device according to claim 1, wherein:
the gate conductor layer is divided vertically into two or more;
2. The semiconductor device according to claim 1, wherein:
The first metal wiring layer and the third metal wiring layer are provided in a direction perpendicular to the interface between the contact hole and the second impurity layer, and between the first metal wiring layer and the third metal wiring layer. there is a first semiconductor pillar at
2. The semiconductor device according to claim 1, wherein:
part or all of the surface of at least one of the first impurity layer and the second impurity layer is covered with a first metal film;
2. The semiconductor device according to claim 1, wherein:
A first channel-type MOSFET in which majority carriers in the first impurity layer and the second impurity layer are electrons, and a second impurity layer in which the majority carriers in the first impurity layer and the second impurity layer are holes. Two channel-type MOSFETs are present on the same substrate, and at least one of the first metal wiring layer, the second metal wiring layer, the third metal wiring layer, and the fourth metal wiring layer is metal. part of the components of the first channel-type MOSFET and the second channel-type MOSFET are electrically connected in a wiring layer;
2. The semiconductor device according to claim 1, wherein:
After forming a first insulating film and a first semiconductor layer containing an impurity in an element region of the semiconductor substrate on a first semiconductor substrate, a second insulating film, a gate material layer, and a third insulating film are formed. forming a film, and forming a mask material thereon so as to cover part of the first insulating film and part of the element region in plan view;
etching and removing the third insulating film and the gate material layer using the mask material as a mask;
forming a fourth insulating film over the entire surface, flattening the fourth insulating film until the mask material appears, and then removing the mask material; removing the second insulating film and the gate material layer to form an opening, forming a gate insulating layer on sidewalls thereof, and further on the first semiconductor layer inside the gate insulating layer; filling a second semiconductor layer into the second semiconductor layer, forming a third semiconductor layer containing impurities on the second semiconductor layer, and forming a fifth insulating film on the whole;
A first contact hole is formed in the fifth insulating film above the gate material layer to form a first metal wiring, a sixth insulating film is formed thereon, and the second impurity layer is formed. a step of forming a seventh insulating film on the entire surface after forming a second metal wiring by opening a second contact hole in the sixth insulating film on the upper portion of the
A second substrate is adhered to the seventh insulating film, the first substrate is turned over so that the bottom surface of the semiconductor substrate, and then the first semiconductor substrate is polished until the first insulating film is exposed. process and
a step of forming a seventh insulating film on the entire surface, opening a third contact hole, and forming a third metal wiring;
A method of manufacturing a semiconductor device, comprising:
Furthermore, before forming the seventh insulating film, a step of forming an eighth insulating film on the entire surface, forming a fourth contact hole, and forming a fourth metal wiring is provided. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the seventh insulating film is formed on the .